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    AST RESEARCH, INC.        TECHNICAL BULLETIN # 1103                  3-9-95

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    			   AST'S RESPONSE TO INTEL'S PUBLISHED ERRATA

    This is an informational bulletin.  This document provides information about
    Intel's Errata disclosure and AST's position in the matter.

    PART I PENTIUM 60/90 MHz DESKTOPS AND MANHATTAN G560 SERVERS

    REF. #         STEPS                    ERRATA

    	B1   C1   D1   PLANS

    1.   X              Fixed     BOFF# Hold Timing.
    						Response: Hold time is conditioned properly by
    						VLSI chipset.

    2.   X              Fixed     Incomplete initialization may Flush the internal
    						Pipeline.
    						Response: No work around necessary.  If errors
    						occur, pipeline is flushed and the instruction
    						is refetched until successful.

    12.  X    X         Fixed     Internal snoop problem due to reflection on
    						address bus.
    						Response: AST conditioned CLK for no reflection.

    13.  X    X         Fixed     Internal Parity Error on un-initialized data
    						cache entry.
    						Response: AST doesn't enable internal parity
    						checking.

    14.  X    X         Fixed     Missing shutdown after an IERR#.
    						Response: AST doesn't enable internal parity
    						checking.

    15.  X    X         Fixed     Processor core may not serialize on bus idle.
    						Response: This errata applies only to B1.  AST
    						has been shipping B3 on most of our products for
    						some time.  If one of the conditions were to
    						occur on B1 parts then this could cause the
    						system to crash.  There is no work around in
    						place for this error.

    16.  X    X         Fixed     SMIACT# assertion during replacement writeback
    						cycle.
    						Response: AST does not cache SMM memory space
    						which avoids the problem.

    PART I PENTIUM 60 MHz PREMMIA SERVERS

    REF. #         STEPS                    ERRATA

    	B1   C1   D1   PLANS

    1.   X              Fixed     BOFF# Hold Timing.
    						Response specification does not list a minimum
    						delay for BOFF#; it specifies a typical of 5 ns
    						and a maximum of 8ns.

    2.   X              Fixed     Incomplete initialization may Flush the internal
    						Pipeline.
    						Response: This errata will not occur, because
    						followingRESET, a branch instruction is executed
    						before a memory write.

    12.  X    X         Fixed     Internal snoop problem due to reflection on
    						address bus.
    						Response: Signal quality has not been
    						investigated as it pertains to this errata. There
    						could be an issue.

    13.  X    X         Fixed     Internal Parity Error on uninitialized data cache
    						entry.
    						Response: The internal parity error in question,
    						will not occur in the Premmia SE because the CPU
    						performs a BIST at reset

    14.  X    X         Fixed     Missing shutdown after an IERR#.
    						Response: AST disabled internal parity checking,
    						but it is believed an internal parity error, due
    						to defective CPU, can occur without any detection
    						of  the error.

    15.  X    X         Fixed     Processor core may not serialize on bus idle.
    						Response: This errata is fixed on D-stepping and
    						subsequent steppings. Of the 4 possible
    						implications of this errata, only one applies to
    						Premmia: invalidation during cache fill. There is
    						no workaround.

    16.  X    X         Fixed     SMIACT# assertion during replacement writeback
    						cycle.
    						Response: This errata cannot occur on Premmia
    						SE because SMI# is never asserted.

    PART II PENTIUM 75/90/100 MHz DESKTOPS AND MANHATTAN G590 SERVERS

    REF. #         STEPS               ERRATA

    	B1   B3   B5   C2   PLANS

    5.   X    X    X         Fixed     SMI# and FLUSH# during shutdown.
    							Response: None of the AST designs assert
    							Flush; this avoids the problem.

    6.   X    X    X         Fixed     No Shutdown after IERR#.
    							Response: AST doesn't enable internal
    							parity checking.

    8.   X                   Fixed     Processor core may not serialize on bus
    							idle.
    							Response: This errata applies only to B1.
    							AST has been shipping B3 on most of our
    							products for some time.  If one of the
    							conditions were to occur on B1 parts then
    							this could cause the system to crash.
    							There is no work around in place for this
    							error.

    10.  X    X    X    X    Doc       STPCLK# de-assertion not recognized for 5
    							CLKs after BRDY# returned.
    							Response: AST does not assert STPCLK, this
    							avoids the problem.

    11.  X    X    X         Fixed     Future Pentium OverDrive processor FERR#
    							Contention in Two Socket Systems:
    							Response: Intel provided several methods of
    							working around this errata. AST chose to
    							implement work around #1 as listed by Intel.

    16.  X    X    X    X    Doc       FRC Mode miscompare due to uninitialized
    							register.
    							Response: This mode not used, therefore
    							problem is avoided.

    17.  X    X    X    X    Doc       STPCLK# restrictions during EWBE#.
    							Response: Premmia GX' does not use STPCLK,
    							Bravo MSand Manhattan G590 do not de-assert
    							EWEB.  This avoids the problem.

    19.  X    X    X         Fixed     100 MHz REP MOVS Speed Path.
    							Response: At 100MHz AST is only shipping
    							rev C2, this errata is fixed in C2.

    1DP  X    X    X         Fixed     Problem with external snooping while two
    							cycles are pending on the bus.
    							Response: This errata does not apply to
    							Neptune-based systems such as the
    							Premmia GX and Manhattan G560/G590.

    2DP  X    X    X         Fixed     STPCLK# assertion and the Stop Grant bus
    							cycle.
    							Response: Not using STPCLK so this problem
    							does not apply.

    3DP  X    X    X         Fixed     External snoops with AHOLD asserted may
    							cause processor to hang.
    							Response: This errata does not apply to
    							Neptune-based systems such as the
    							Premmia GX and Manhattan G560/G590.

    5DP  X    X              Fixed     Inconsistent cache state may result from
    							interprocessor pipelined READ into a WRITE.
    							Response: AST using workaround by disabling
    							pipelining in dual CPU mode.

    6DP  X    X    X         Fixed     Processors hang during Zero WS, pipelined
    							bus cycles.
    							Response: AST using workaround by disabling
    							pipelining in dual CPU mode.

    7DP  X    X    X         Fixed     Bus Lock up problem in a specific DP mode
    							sequence.
    							Response: There is no work around in place
    							for this.  The occurrence of this error
    							with a Premmia GX and Manhattan G590 have
    							been made less likely by:
    							(1) Disabling of address pipeline.
    							(2) Processor bus cycles not running in 0
    							or 1 wait states.

    2AP  X    X    X         Fixed     Chance of clearing an unread error in the
    							Error Register.
    							Response: No workaround. No functional or
    							performance impact.

    6AP  X    X    X         Fixed     HOLD During a READ from Local APIC Register
    							May Cause Incorrect PCHK#.
    							Response: Parity not enabled.

    7AP  X    X    X         Fixed     HOLD during an outstanding interprocessor
    							pipelined APIC cycle hangs processor.
    							Response: AST using workaround by disabling
    							pipelining in dual CPU mode.

    8AP  X    X    X         Fixed     PICCLK reflection may cause an APIC checksum
    							error.
    							Response: Conditioned APIC CLK to avoid the
    							problem.

    9AP  X    X    X    X    Fixed     Spurious interrupt in APIC through local
    							mode.
    							Response: AST does not use "Virtual wire
    							mode".

    10AP X    X    X         Fixed     Potential for a lost interrupts while using
    							APIC in through local mode.
    							Response: AST does not use "Virtual wire
    							mode".

    2TCP X                             BRDY# does not have buffer selection
    							capability.
    							Response: Feature not used. No functional
    							or performance impact.

    PART II - MANHATTAN P5090/5100, V5090/V5100

    REF. #         STEPS               ERRATA

    	B1   B3   B5   C2   PLANS

    5.   X    X    X         Fixed     SMI# and FLUSH# during shutdown.
    							Response: None of the AST designs assert
    							Flush; this avoids the problem.

    6.   X    X    X         Fixed     No Shutdown after IERR#.
    							Response: No specific hardware workaround
    							has been implemented or recommended by
    							Intel at this date.  The odds of getting
    							an IERR# (CPU IC Internal error) indication
    							are extremely remote, and if you get one,
    							it's fatal or will be fatal shortly
    							thereafter.

    8.   X                   Fixed     Processor core may not serialize on bus
    							idle.
    							Response: This errata applies only to B1.
    							AST has been shipping B3 on most of our
    							products for some time.  If one of the
    							conditions were to occur on B1 parts then
    							this could cause the system to crash.
    							However, this is minimized since AST does
    							not [1] shadow SMRAM memory over standard
    							memory, nor [2] use STPCLK# functionality
    							(part of System Power Management).

    10.  X    X    X    X    Doc       STPCLK# de-assertion not recognized for 5
    							CLKs after BRDY# returned.
    							Response: AST doesn't use STPCLK#
    							functionality (part of System Power
    							Management).  In addition, the Neptune ESC
    							IC guarantees the deassertion of STPCLK#
    							for 5 CLKs, thereby implementing
    							Workaround #2 and avoiding the problem.

    11.  X    X    X         Fixed     Future Pentium OverDrive processor FERR#
    							Contention in Two Socket Systems:
    							Response: AST implemented work around #1.

    16.  X    X    X    X    Doc       FRC Mode miscompare due to uninitialized
    							register.
    							Response: This mode not used, therefore
    							problem is avoided.

    17.  X    X    X    X    Doc       STPCLK# restrictions during EWBE#.
    							Response: We do not use STPCLK#
    							functionality (part of System Power
    							Management).  In addition, the Neptune-based
    							L2 cache design does not use the EWBE#
    							signal of the CPU, always leaving it
    							asserted so that this error condition
    							cannot occur.

    19.  X    X    X         Fixed     100 MHz REP MOVS Speed Path.
    							Response: P5090 CPU boards may use B1 or B5
    							parts. However, since they only run at
    							90MHz, this error condition will never
    							happen.  At 100MHz AST is only shipping
    							rev C2, this errata is fixed in C2.

    1DP  X    X    X         Fixed     Problem with external snooping while two
    							cycles are pending on the bus.
    							Response 90MHz CPU boards may use B1 or B5
    							parts.  However, they have pipelining
    							disabled so this error cannot happen.
    							100MHz boards use only C2.

    2DP  X    X    X         Fixed     STPCLK# assertion and the Stop Grant bus
    							cycle.
    							Response: Not using STPCLK# functionality
    							(part of System Power Management).

    3DP  X    X    X         Fixed     External snoops with AHOLD asserted may
    							cause processor to hang.
    							Response: None.  The Intel Neptune chipset
    							used on our CPUs assures that the conditions
    							for Workaround #2 are always met for cache
    							snoop cycles.

    5DP  X    X              Fixed     Inconsistent cache state may result from
    							interprocessor pipelined READ into a WRITE.
    							Response: AST's 90MHz workaround disables
    							pipelining in dual CPU mode.  100MHz boards
    							use C2 CPU with pipelining enabled.

    6DP  X    X    X         Fixed     Processors hang during Zero WS, pipelined
    							bus cycles.
    							Response: None.  Because our CPU board's
    							bus runs at either 60MHz (5090) or 66MHz
    							(5100); they cannot be run with zero wait
    							states.  They always run with 1 wait state
    							(3-1-1-1 cache timing).

    7DP  X    X    X         Fixed     Bus Lock up problem in a specific DP mode
    							sequence.
    							Response: There is no 90MHz workaround for
    							this. Theoccurrence of this error in a
    							5090 Manhattan has been made less likely
    							by disabling the address pipeline.
    							The 5100 MHz Manhattan uses C2 CPU with the
    							problem fixed.

    2AP  X    X    X         Fixed     Chance of clearing an unread error in the
    							Error Register.
    							Response: No workaround for 5090's. 5100's
    							use C2 CPU - fixed.

    6AP  X    X    X         Fixed     HOLD During a READ from Local APIC Register
    							May Cause Incorrect PCHK#.
    							Response: Hold is not used on Manhattan
    							P & V.

    7AP  X    X    X         Fixed     HOLD during an outstanding interprocessor
    							pipelined APIC cycle hangs processor.
    							Response: None. CPU boards do not use the
    							CPU HOLD function for snoop cycles.

    8AP  X    X    X         Fixed     PICCLK reflection may cause an APIC
    							checksum error.
    							Response: None.  Our CPU boards where
    							designed with great care and attention to
    							the PCICLK drive circuitry.

    9AP  X    X    X    X    Fixed     Spurious interrupt in APIC through local
    							mode.
    							Response: Our CPU boards force hardware
    							disable of the APIC when used as single
    							CPU systems.  Dual CPU systems, by
    							definition, must have the APIC enabled on
    							reset, and thus software must take the
    							appropriate steps described in the
    							workaround section above.

    10AP X    X    X         Fixed     Potential for a lost interrupts while
    							using APIC in through local mode.
    							Response:  Our CPU boards force hardware
    							disable of the APIC when used as single CPU
    							systems.  Dual CPU systems, by definition,
    							must have the APIC enabled on reset, and
    							thus software must take the appropriate
    							steps described in the workaround section
    							above.

    2TCP X                             BRDY# does not have buffer selection
    							capability.
    							Response: None.  Our CPU boards do not use
    							the 75MHz P54C IC.

    For additional information, call Intel at 1-800-548-4725.

    SYSTEMS AFFECTED
    AST PART NUMBER AND DESCRIPTION

    All AST systems with Pentium 60/66/75/90/100 MHz processors.