*
*   Hardware equates for SBC board
*
DATBOX equ $FFF0 memory mapper regs
DATRW equ $E840 r/w memory mapper regs
CLKSEL equ IFR29 clock select and status register
BASACI equ $E800
INITBR equ $ee initial baud rates (9600 baud)
BAUDRG     equ     $E820      baud rate generator (tty01=MS half; tty02=LS)
wd_reset   equ     $E820               read to reset wdxx controller
           pag
*
*                      Interrupt Flag/Enable Register
*                   _________________________________
*                   | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
*                   ---------------------------------
*  0 clr/set 1 _______/   /   /   /   \   \   \   \_______  CA2 (WDxx)
*  Timer 1     __________/   /   /     \   \   \__________  CA1 (FD time)
*  Timer 2     _____________/   /       \   \_____________  Shift reg
*  CB1 (timer) ________________/         \________________  CB2 (1797)
*
*
           pag


VIA29      equ     $E8A0               via base address

ORB29      equ     VIA29+0             output register B
ORA29      equ     VIA29+1             output register A
DDRB29     equ     VIA29+2             data dir reg A side
DDRA29     equ     VIA29+3             data dir reg B side
SHT29      equ     VIA29+10            shift register for timer
AUX29      equ     VIA29+11            aux ctrl register
PCR29      equ     VIA29+12            periph control register
IFR29      equ     VIA29+13            interrupt flag register
IER29      equ     VIA29+14            interrupt enable register


*
*   interrupt flag and enble bits for VIA29
*
i_via      equ     %10000000           any part of via interrupt bit
i_time     equ     %00010000           clock timer bit (unshifted)
i_shift    equ     %00000100           shift register interr bit

*
*   Equates for via8 - character input/output port
*
VIA08      equ     $E890               via base address

ORB08      equ     VIA08+0             output register B
ORA08      equ     VIA08+1             output register A
DDRB08     equ     VIA08+2             data dir reg A side
DDRA08     equ     VIA08+3             data dir reg B side
T1CNTR     equ     VIA08+4             timer 1 count regs
T2CNTR     equ     VIA08+8             timer 2 count regs
SHT08      equ     VIA08+10            shift register for timer
AUX08      equ     VIA08+11            aux ctrl register
PCR08      equ     VIA08+12            periph control register
IFR08      equ     VIA08+13            interrupt flag register
IER08      equ     VIA08+14            interrupt enable register

IFRPPR     equ     $F001               PPR on X-12
IFRSPR     equ     $F002               SPR on X-12
IFRCOM     equ     $F003               COM on X-12

CA1        equ     %00000010
CB1        equ     %00010000
i_t1cnt    equ     %01000000           timer 1 count down
i_t2cnt    equ     %00100000           timer2 count down

*
*   bit assignments for the via protocol
*   status bytes
*
TTYOFF     equ     4
TTYON      equ     8
PPROFF     equ     5
PPRON      equ     9
SPROFF     equ     6
SPRON      equ     10
TTYCBRK    equ     7
TTYBRK     equ     11
COMOFF     equ     13
COMON      equ     12
COMBRK     equ     14
SPRBRK     equ     15
