 sttl FIO Simulation Structure
 pag

*
* Control structure used to simulate Z8038 FIO
* -- As seen by Main 6809 CPU (UniFLEX)
*

FIFO_SIZE equ 128 Size of FIFO buffer

IOP_MAP  equ $F8 -- IOP Mapping at $E000
ROM_MAP  equ $FF -- Normal I/O at $E000
*
IO_DAT   equ $F40E

         org $E000 -- Shared Dual Port RAM
irq_gen  rmb 1 IRQ generator cell
iop_cpu  rmb 1 IOP -> CPU Mailbox cell
iop_cpu1 rmb 1            -- Additional cell
iop_cpu2 rmb 1            --
iop_cpu3 rmb 1            --
iop_cpuF rmb 1 Non-zero when mailbox has data
cpu_iop  rmb 1 CPU -> IOP Mailbox cell
cpu_iop1 rmb 1            -- Additional cell
cpu_iop2 rmb 1            --
cpu_iop3 rmb 1            --
cpu_iopF rmb 1 Non-zero when mailbox has data
fifo_cnt rmb 1 Count of data in FIFO
fifo_get rmb 2 FIFO consumer pointer
fifo_put rmb 2 FIFO producre pointer
         rmb 16-(*-irq_gen) ** Filler **
fifo     rmb FIFO_SIZE actual FIFO
