 sttl IOP Memory Layout
 pag
*
* Basic Memory Layout
*
RAMorg equ $0100 16K of RAM - Thru $3FFF
RAMend equ $3FFF
RAMscratch equ $8C00 1K of scratchpad RAM
RAMscrend  equ $8F00
ROMstack equ $8FFF High end of ROM Stack
ROMLOorg equ $D000 4K of ROM - Thru $DFFF
ROMHIorg equ $F000 4K of ROM - Thru $FFFF
DEBUGROM equ $B000 4K of Debug ROM $B000-$BFFF
CPUtraps equ $FFF0 CPU Trap Vectors

SYS_ACIA equ $8080
SYS_8274 equ $8000
CLOCK    equ $80C0 6840 Timer
NUM_SLOTS equ 8 Number of Physical I/O slots
BASE_SLOT equ $8000 Base address for I/O slots
NEXT_SLOT equ $0010 Offest between slots
PIA_SLOT  equ $8090 On PPI PIA
TOD_ADDR  equ $80A0 Byte address for Time of Day
TOD_DATA  equ $80B0 Data access to Time of Day Clock
TOD_SIZE  equ 14 Number of bytes in TOD register space
