 ttl SWTPc Intelligent I/O Processor
 sttl Hardware Definitions
 abs
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 lib environment

 sttl CPU Vectors
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 org CPUtraps
 fdb 0 Unused
 fdb rom_swi3 SWI3
 fdb rom_swi2 SWI2
 fdb rom_firq FIRQ
 fdb IRQ_han IRQ
 fdb rom_swi SWI
 fdb rom_nmi NMI
 fdb rom_init Reset

 sttl System RESET Code
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 org ROMLOorg

DBmsg00 fcc $d,'IOP ROM',0
DBmsg01 fcc $d,'System Initialization Complete',0
DBmsg02 fcc $d,'CPU RESET Complete',0
CPU_down fcc $d,$d,'System CPU not functioning',0

*
* System RESET code
*
rom_init lds #ROMstack initialize stack pointer
 ldx #sys_vars clear all of RAM
 ldd #0
10 std ,x++
 cmpx #end_vars
 blo 10b
 if DBG_SYS&DEBUG_CONTROL
 jsr DB_msg
 fdb DBG_SYS,20f
 ldx #DBmsg00
 jsr DB_pdata
 endif
20 lbsr stbinit go initialize system memory
 if DBG_SYS&DEBUG_CONTROL
 jsr DB_msg
 fdb DBG_SYS,30f
 ldx #DBmsg01
 jsr DB_pdata
 endif
30 lds tsktab Task 0 Stack
 leas TSKSIZ,s
 lbsr fio_reset

*
* Initialization complete - Start executing commands
*
fio_start
 ldb #ROM_VERSION
 stb iop_cpu1
 ldb #R_RESET send "system reset & running" message
 lbsr fio_msg
 if DBG_SYS&DEBUG_CONTROL
 jsr DB_msg
 fdb DBG_SYS,10f
 ldx #DBmsg02
 jsr DB_pdata
 endif
10 jmp rsched

 sttl ROM Interrupt Fielders
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rom_nmi bsr rom_int
 fcc 'NMI',0
rom_firq bsr rom_int
 fcc 'FIRQ',0
rom_swi bsr rom_int
 fcc 'SWI',0
rom_swi2 bsr rom_int
 fcc 'SWI2',0
rom_swi3 bsr rom_int
 fcc 'SWI3',0

rom_int ldx #ROM_ERR
 jsr DB_pdata
 puls x
 jsr DB_pdata
rom_bad bra *
*
ROM_ERR fcc $d,'ROM Error: ',0
