 lib environment
 lib dtab
 lib inttab
 lib bfhdr
 lib blktab
 lib chrtab
 lib fio
 lib macdefs
 data
 sttl Device Driver Tables
 pag
 name devtab
 define

*
* System Parameters - adjust accordingly
*

SSIZE equ 1 initial stack size (*PAGSIZ)
MAXJOB equ 10 maximum simult user tasks
NBLKS equ 16 Accessable pages in address space
USRHIP equ NBLKS-1 User's highest addressable page
USRHIP_4 equ USRHIP<<4

*
LIGHTS fcb 0

*
* Machine constants
*

DATBOX equ $F400 memory mapper regs
BLKHOL fcb $FF black hole memory cell
DSKTRM fcb $FC
WHTHOL fcb $CD white hole memory cell


*
* DMF3 (Floppy)
*
DMF3ADR equ $E000 dma address register
DMF3CNT equ DMF3ADR+2 dma count register
DMF3CCR equ DMF3ADR+$10 dma control register
DMF3PRI equ DMF3ADR+$14 dma priority register
DMF3INT equ DMF3ADR+$15 dma interrupt register
DMF3DCR equ DMF3ADR+$16 data chain register
DMF3COM equ DMF3ADR+$20 wd command register
DMF3TRK equ DMF3ADR+$21 wd track register
DMF3SEC equ DMF3ADR+$22 wd sector register
DMF3DAT equ DMF3ADR+$23 wd data register
DMF3DRV equ DMF3ADR+$24 drive select register
DMF3LAT equ DMF3ADR+$25 controller addr latch
VIA    equ DMF3ADR+$40 via thing

*
* Archive Tape (DMF3)
*

DMA equ DMF3ADR address of tape controller DMA

AT_C2A equ DMA+08 channel 2 address register
AT_C2C equ DMA+10 channel 2 count register
AT_C3A equ DMA+12 channel 3 address register
AT_C3C equ DMA+14 channel 3 count register
CAT_C2 equ DMA+18 channel 2 control register
CAT_C3 equ DMA+19 channel 3 control register
AT_PTY equ DMA+20 priority control register
AT_ICR equ DMA+21 interrupt control register
AT_DCR equ DMA+22 dma data chain register

AT_DTB equ VIA+00 B-Side Data Register
AT_DTA equ VIA+01 A-Side Data Register
AT_DRB equ VIA+02 B-Side Direction Register
AT_DRA equ VIA+03 A-Side Direction Register
AT_T1C equ VIA+04 Timer 1 Counter Register
AT_T1L equ VIA+06 Timer 1 Latches
AT_T2C equ VIA+08 Timer 2 Counter Register
AT_VSR equ VIA+10 Shift Register
AT_ACR equ VIA+11 Auxillary Control Register
AT_PCR equ VIA+12 Peripheral Control Register
AT_IFR equ VIA+13 Interrupt Flag Register
AT_IER equ VIA+14 Interrupt Enable Register
AT_DXA equ VIA+15 A-Side Data Register

AT_RES equ DMF3ADR+$52 drive sel / data sep
AT_XAL equ DMF3ADR+$25 extended address latch

AT_DMC equ DMF3ADR+$53 archive DMA clear
AT_DMP equ DMF3ADR+$60 archive DMA preset

*
* DMF3 Winchester Equates
*
board      equ     DMF3ADR             DMF3 base address

extaddr    equ     board+$25           74LS374 latch for 4 extended address
*                                      lines (bits 0-3),
chan0      equ     %00000000           dma channnel select
chan1      equ     %00010000           (bits 4-5),
chan2      equ     %00100000
chan3      equ     %00110000
dmahalt    equ     %10000000           dma halt mode
dmabusreq  equ     %00000000           dma bus req (low)
archread   equ     %01000000           archive edge select high (READ)
archwrite  equ     %00000000           archive edge select low (WRITE)

auxdecode  equ     board+$50           74LS139 for misc. decodes

hld_toggle equ     auxdecode+0         head load toggle
wd1000_res equ     auxdecode+1         winchester software reset
*          equ     auxdecode+2         archive reset (doesn't work)
*          equ     auxdecode+3         archive clear

dma_preset equ     board+$60           archive DMA preset

dma        equ     board+$00           68B44 dma controller

*   memory register definitions:

dmac0a     equ     dma+$00                 channel 0 address register
dmac0c     equ     dma+$02                 channel 0 byte count register
dmac1a     equ     dma+$04                 channel 1 address register
dmac1c     equ     dma+$06                 channel 1 byte count register
dmac2a     equ     dma+$08                 channel 2 address register
dmac2c     equ     dma+$0a                 channel 2 byte count register
dmac3a     equ     dma+$0c                 channel 3 address register
dmac3c     equ     dma+$0e                 channel 3 byte count register
*
*   channel control register definitions:
*
dmacc0     equ     dma+$10                 channel 0 control register
dmacc1     equ     dma+$11                 channel 1 control register
dmacc2     equ     dma+$12                 channel 2 control register
dmacc3     equ     dma+$13                 channel 3 control register

dmadend    equ     %10000000           1 => dma transfer complete
dmabusy    equ     %01000000           1 => transfer in progress
dmacntd    equ     %00001000           1 => address down count
dmadmar    equ     %00000001           1 => dma memory read
dmasteal   equ     %00000100           cycle steal dma mode
dmaburst   equ     %00000010           halt burst mode
dmahbyte   equ     %00000000           halt byte mode
*
*   priority control register definition:
*
dmaprc     equ     dma+$14                 priority control register

dmare0     equ     %00000001           1 => channel 0 request enabled
dmare1     equ     %00000010           1 => channel 1 request enabled
dmare2     equ     %00000100           1 => channel 2 request enabled
dmare3     equ     %00001000           1 => channel 3 request enabled
dmarotat   equ     %10000000           1 => rotate dma channel requests
*
*   interrupt control register definition:
*
dmaicr     equ     dma+$15                 interrupt control register

dmadie0    equ     %00000001           1 => enable irq on channel 0 dend
dmadie1    equ     %00000010           1 => enable irq on channel 1 dend
dmadie2    equ     %00000100           1 => enable irq on channel 2 dend
dmadie3    equ     %00001000           1 => enable irq on channel 3 dend
dmadirq    equ     %10000000           1 => dma irq is set
*
*   data chain register definition:
*
dmadcr     equ     dma+$16                 data chain control register

dmacsel    equ     %00001000           1 => four channel select
dmadce     equ     %00000001           1 => data chain enable
dmadcc     equ     %00000110           data chain channel select


wd1000     equ     board+$30           WD1000 5-1/4 winchester controller

wd_data    equ     wd1000+0            data register

wd_error   equ     wd1000+1            error register (read only)
*                                      bit 7 bad block detect
*                                      bit 6 CRC error, data field
*                                      bit 5 CRC error, ID field
*                                      bit 4 ID not found
*                                      bit 3 unused
*                                      bit 2 Aborted Command
*                                      bit 1 TR000 (track zero) error
*                                      bit 0 DAM not found
wd_wr_pre  equ     wd1000+1            write precomp (write only)

wd_sec_cnt equ     wd1000+2            sector count (during format)

wd_sec_num equ     wd1000+3            sector number

wd_cyl_low equ     wd1000+4            cylinder (low byte)
*                                      C0-C7
wd_cyl_hi  equ     wd1000+5            cylinder (high byte)
*                                      C8-C9

wd_sdh     equ     wd1000+6            size/drive/head
*                                      bit 7 XX,
*                                      bit 6,5 sector size (256,512,128)
*                                      bit 4,3 drive select (0,1,2,3)
*                                      bit 2,1,0 head select (0-7)
wd_secsize equ     %00000000           256 byte sectors
wd_sz_512  equ     %00100000           512 byte sectors
wd_sel0    equ     %00000000           select drive zero
wd_sel1    equ     %00001000           select drive one
wd_sel2    equ     %00010000           select drive two
wd_sel3    equ     %00011000           select drive three

wd_status  equ     wd1000+7            status (read only)
*                                      bit 7 busy
*                                      bit 6 ready
*                                      bit 5 write fault
*                                      bit 4 seek complete
*                                      bit 3 data request
*                                      bit 2,1 unused
*                                      bit 0 error (code in wd_error
wd_cmd     equ     wd1000+7            command (write only)
wd_restore equ     %00010110           restore with 3ms step rate
wd_seek    equ     %01110000           seek with 10us step rate
wd_read    equ     %00101000           read sector DMA
wd_write   equ     %00110000           write sector
wd_format  equ     %01010000           format track (SPECIAL USAGE)
*
W5STAT equ dmacc1 channel control register
W5CMD equ wd_cmd WD1000 command register

*
* CDS Winchester disk controller definitions
*
 base 0
CDSCMD rmb 1 disk command register
CDSADR rmb 2 disk address register
CDSFLG rmb 1 disk irq status register
 data
CDSdev fdb $E100 Drive 0
       fdb $E300 Drive 1

contab equ *
 ifc &a,'8'
Uni_DN equ 0 8" Floppy Diskette
 info Root device: /dev/fd0
 else
 ifc &a,'5W'
Uni_DN equ 6 5" Winchester
 info Root device:  /dev/w0
 else
Uni_DN equ 4 Default (hard disk)
 info Root device: /dev/hd0
 endif
 endif

 info Device support:
 info   IOP Communications
 info   8" Floppy diskettes
 info   5" Winchester disks (WD100x)
** info   CDS Winchester
 info   Archive Tape Unit

strm fcb 4 number of terminals
stsk fcb 64 number of tasks
siob fcb 32 number of io buffers
schl fcb 8 number of character lists
sfdn fcb 128 number of fdn entries
stxt fcb 20 number of text entries
smnt fcb 5 number of mounts
stim fcb 24 number of timeouts allowed
slok fcb 32 number of lock table entries
srtd fdb Uni_DN root device number
sppd fdb Uni_DN pipe device number
sswd fdb Uni_DN swap device number
stlm fcb 0 time limit in 25.6 X seconds (0 disables)
sfil fdb 500 max file size for reg user
scon fdb irq_gen console terminal address (acia) ####  NO ACIA  ####
sconbr fcb 0 console baud rate value
smxj fcb MAXJOB max user task count
stmz fdb 300 time zone (minutes west of gmt)
sdlt fcb 0 daylight savings here (0 if not)
sphz fcb 0 non-zero if power line is 50HZ
stup fcb 0 auto update time (0 disables) - value*4
smxm fcb NBLKS maximum mem segments per task
FD_SRT fcb 0 Floppy Disk Seek Rate
SWTPCvii fcb $FF SWTPC vii system
DATsense fcb $00 SWTPC non inverted DAT form
ROMmap fdb $FFFF Map registers for ROM space ($E000-$F000)
NMIhan fdb nmihan UniFLEX NMI handler
SWI2han fdb swi2han SWI2 handler
MAXMAP fcb 64 Number of hardware maps

*
* ROM Routines
*
Pdata lda ,x+ get next character
 beq 99f exit at null
 bsr Pchar print it
 bra Pdata continue
99 rts
Phex pshs cc
 seti
 jsr [$F802]
 puls cc,pc
Pspace pshs cc
 seti
 jsr [$F804]
 puls cc,pc
Pchar pshs cc
 seti
 jsr [$F806]
 puls cc,pc
Tinit pshs cc
 seti
 jsr [$F808]
 puls cc,pc
Phex2 pshs b
 bsr Phex
 puls a
 bra Phex


*
* fnttab
*
* Interrupt table for firq type interrupts.  It is
* the same as inttab above.
*

fnttab
fntend equ *


 pag

*
* Special tables used by IOP interface
*
IOP0 rzb IOP_SIZE
NUM_TRAN fcb 0 Number of transactions allowed

* Character table

*
* Device tables
*

chrtab
* tty device
 fdb iop_open tty open routine
 fdb iop_close tty close routine
 fdb iop_read tty read routine
 fdb iop_write tty write routine
 fdb iop_spcl special routine
* mem device
 fdb nuldev mem open
 fdb nuldev mem close
 fdb mdrd mem read
 fdb mdwr mem write
 fdb nuldev mem special
* null device
 fdb nuldev null dev open
 fdb nuldev null dev close
 fdb nuldrd null device read
 fdb nuldwr null device write
 fdb nuldev null special
* floppy disk (character)
 fdb fchop fd open
 fdb fchcl fd close
 fdb fchrd fd read
 fdb fchwr fd write
 fdb fchsp fd special
* cds character drivers
 fdb cdcop cds open
 fdb cdccl cds close
 fdb cdcrd cds read
 fdb cdcwr cds write
 fdb nuldev special
* HOLE - old serial printer drivers
 fdb nodev spopn serial open
 fdb nodev spcls serial close
 fdb nodev nodev serial read
 fdb nodev spwrt serial write
 fdb nodev spspc special
* HOLD - old parallel printer driver
 fdb nodev ppopn parallel open
 fdb nodev ppcls parallel close
 fdb nodev nodev parallel read
 fdb nodev ppwrt parallel write
 fdb nodev nuldev special
* HOLE - old nec drivers
 fdb nodev nec open
 fdb nodev nec close
 fdb nodev nec read
 fdb nodev nec write
 fdb nodev nec special
* SWTPC 5" Winchester
 fdb w5cop cds open
 fdb w5ccl cds close
 fdb w5crd cds read
 fdb w5cwr cds write
 fdb w5csp special
* Archive Tape
 fdb atopen open Archive Tape
 fdb atclose close Archive Tape
 fdb atread read Archive Tape
 fdb atwrite write Archive Tape
 fdb atspcl special
CHRDEV equ (*-chrtab)/DEVSIZ

* Block device table

blktab
 fdb BDopen,BD0open open routine
 fdb BDclose,BD0close close routine
 fdb BDio,BD0io main io routine
 fdb dmf3dt device table pointer
 fcb BD0max max minor device number (+1)
BLKDEV equ (*-blktab)/BLKSIZ

* Block Device 0 Open Handlers
BD0open
DMF3minor equ (*-BD0open)/2
DMF3major equ 0
 fdb dmf3opn fd0
 fdb dmf3opn fd1
 fdb dmf3opn fd2
 fdb dmf3opn fd3
CDSminor equ (*-BD0open)/2
CDSmajor equ 0
 fdb cdsopen hd0
 fdb cdsopen hd1
W5minor equ (*-BD0open)/2
W5major equ 0
 fdb w5open w0
 fdb w5open w1
 fdb w5open w2
 fdb w5open w3
ATminor equ (*-BD0open)/2
ATmajor equ 0
AT_DVN equ (ATmajor<<8)+ATminor
 fdb ATerr at0
BD0max equ (*-BD0open)/2

* Block Device 0 Close Handlers
BD0close fdb dmf3cls fd0
 fdb dmf3cls fd1
 fdb dmf3cls fd2
 fdb dmf3cls fd3
 fdb cdsclose hd0
 fdb cdsclose hd1
 fdb w5close w0
 fdb w5close w1
 fdb w5close w2
 fdb w5close w3
 fdb ATerr

* Block Device 0 I/O Handlers
BD0io fdb dmf3io fd0
 fdb dmf3io fd1
 fdb dmf3io fd2
 fdb dmf3io fd3
 fdb cdsio hd0
 fdb cdsio hd1
 fdb w5sto w0
 fdb w5sto w1
 fdb w5sto w2
 fdb w5sto w3
 fdb ATio

*
* Device Tables
*

dmf3dt rzb DVTSIZ device table
cdsdt equ dmf3dt
w5dt equ dmf3dt
at_dt equ dmf3dt
*
dmfcds fcb 0 used by CDS driver

* buffer header for character device

fchbuf rzb HDRSIZ buffer header
