 sttl Z8038 FIFO Input/Output Interface
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*
* FIFO I/O Controller Structure
*
 org $E000
FIOdata rmb 1
FIOctl rmb 1
FIOint rmb 1 interrupt state/hardware reset

FIO_SIZE equ 128 length of FIFO buffer

* FIO Registers
 org $0
ctl_reg0 rmb 1 Reset/Mode Control
ctl_reg1 rmb 1 Mailbox/REQ control
ist_reg0 rmb 1 Data direction/ Pattern Matching
ist_reg1 rmb 1
ist_reg2 rmb 1
ist_reg3 rmb 1
irq_reg rmb 1
byte_cnt rmb 1
byte_cmp rmb 1
ctl_reg2 rmb 1
ctl_reg3 rmb 1
msg_out rmb 1 Outgoing mailbox
msg_in rmb 1 Incoming mailbox
pat_mat rmb 1 Pattern for matching
pat_msk rmb 1 Pattern Mask (don't cares)
data_buf rmb 1 Data buffer (same as FIOdata)

*
* Control bits
*
FIO_EMI equ %11000000 Enable message interrupt
FIO_MIP equ %00100000 Message interrupt pending
FIO_CMI equ %00100000 Clear message interrupt
FIO_IN  equ %00010000 =1 -> FIFO in to CPU
