 sttl IOP Memory Layout
 pag
*
* Basic Memory Layout
*
RAMorg equ $1800 4K of RAM - Thru $37FF
ROMstack equ $27FF High end of ROM Stack
ROMorg equ $F000 4K of ROM - Thru $FFFF
DEBUGROM equ $D000 4K of Debug ROM $D000-$DFFF
CPUtraps equ $FFF0 CPU Trap Vectors
SWITCH1 equ $6000 DIP Switch #1
SWITCH2 equ $4000 DIP Switch #2
*
* This assignment of "port" addresses makes the
* board look like this:
*
*   +------------------------------------------+
*   |   +---------+  +---------+  +---------+  |
*   |   | Term #0 |  | Term #1 |  | Term #2 |  |
*   |   +---------+  +---------+  +---------+  |
*   |                                          |
*   | +-----------+ +-----------+ +----------+ |
*   | |   6551    | |   6551    | |   6551   | |
*   | +-----------+ +-----------+ +----------+ |
*   |                                          |
*   | +----------+                             +------+
*   | | Switch 1 |                                    |
*   | +----------+                                    |
*   |                                                 |
*   | +----------+                                    |
*   | | Switch 2 |                                    |
*   | +----------+                                    |
*   |                                                 |
*   |                                                 |
*   +-------------------------------------------------+
*

*
*  The switches are used for initial baud rate selection:
*
*  Terminal port 0: Switch 1, Bits 1-4
*  Terminal port 1: Switch 1, Bits 5-8
*  Terminal port 2: Switch 2, Bits 1-4
*   ** Unused **    Switch 2, Bits 5-8
*
PORT1 equ $A004 6551 Serial Ports
PORT2 equ $A008
PORT3 equ $A010
DEBUGTRM equ PORT1 Debug terminal
FIO equ $8000 FIFO I/O Controller
