 sttl Z8038 FIFO Input/Output Interface
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*
* FIFO I/O Controller Structure
*
 base 0
FIOdata rmb 1
FIOctl rmb 1
FIOint rmb 1 interrupt state/hardware reset

FIO_SIZE equ 128 length of FIFO buffer

* FIO Registers
 base 0
ctl_reg0 rmb 1 Reset/Mode Control
ctl_reg1 rmb 1 Mailbox/REQ control
ist_reg0 rmb 1 Data direction/ Pattern Matching
ist_reg1 rmb 1
ist_reg2 rmb 1
ist_reg3 rmb 1
irq_reg rmb 1
byte_cnt rmb 1
byte_cmp rmb 1
ctl_reg2 rmb 1
ctl_reg3 rmb 1
msg_out rmb 1 Outgoing mailbox
msg_in rmb 1 Incoming mailbox
pat_mat rmb 1 Pattern for matching
pat_msk rmb 1 Pattern Mask (don't cares)
data_buf rmb 1 Data buffer (same as FIOdata)

*
* Control bits
*
FIO_EMI  equ %11000000 Enable message interrupt
FIO_MIP  equ %00100000 Message interrupt pending
FIO_CMI  equ %00100000 Clear message interrupt
FIO_CIUS equ %01100000 Clear message interrupt under service
FIO_IN   equ %00010000 =1 -> FIFO in to CPU

*
* IOP Task Priority
*   -- Set to make task uninterruptable while
*   -- actually using the IOP
*
IOPPRI set 15

*
* IOP Control structures
*

* Transaction slots

 base 0
tran_seq rmb 2 Transaction sequence #
tran_resp rmb 1 Transaction response code
tran_val rmb 1 Transaction specific value (returned character, etc)
*
TRAN_SIZ equ *
MAX_TRAN equ 9 Max # concurrent transactions / IOP

* IOP Control

 base 0
iop_mbx rmb 2 Mailbox interlock - Task id of locker
iop_fifo rmb 2 FIFO interlock - Task id of locker
iop_int rmb 1 Set non-zero if message interrupt was missed
iop_tflg rmb 1 Waiting on transaction slot semaphore
iop_Q rmb 3 Input response queue
iop_Qptr rmb 2 Current Q pointer
iop_Qend rmb 2 End of Q
iop_tran rmb MAX_TRAN*TRAN_SIZE transaction slots
*
IOP_SIZE equ *
