Synopsys Transfers Ownership of PDEF Specification to OVI Committee for Use
in Delay Calculation Standard

July 24, 1995 -- Synopsys, Inc. (NASDAQ: SNPS) and Open Verilog
International (OVI) today jointly announced that Synopsys has transferred
ownership of its Physical Design Exchange Format (PDEF) specification to
OVI. OVI's Technical Coordinating Committee plans to incorporate PDEF as a
key element of its delay calculation standard proposal to the IEEE later
this year.

PDEF is a means for representing floorplanning data. It provides a critical
link between logical and physical submicron design, containing all the
information necessary for transporting floorplanning data between
synthesis and layout tools. With multiple floorplanners in use today, PDEF
addresses the need for open communication between front-end and back-end
EDA tools. Through PDEF, physical design information can be considered
early in the design cycle, reducing costly layout-related design
iterations at the back end.

"We are pleased to transfer PDEF to OVI," said Nitin Deo, product line
manager at Synopsys. "We created PDEF in cooperation with other EDA and
semiconductor suppliers because of increasing customer demand for tighter
links between front-end and back-end design tools. While netlist and
timing standards have been well established, no standard for connecting
logical and physical tools has been previously accepted. The cell
clustering information provided by PDEF is essential for accurate delay
calculation in deep submicron technologies. We are excited that the
industry, through OVI, is ready to move toward a language-independent
standard for floorplanning data and delay calculation."

"Synopsys has transferred ownership of the PDEF specification to OVI for
inclusion in our delay calculation standard proposal," added Bill Fuchs,
OVI's chairman. "The company has been outstanding to work with in terms of
efficient transfer of intellectual property for standardization purposes.
We anticipate that a delay calculation standard will give designers a much
needed common methodology for facilitating communication between front-
and back-end tools."

"Based on the assumption that the IEEE will accept our proposal for an EDA
industry delay calculation standard, future development and maintenance of
PDEF will be the responsibility of the IEEE, in cooperation with OVI."

PDEF can be used to transport many types of information, including clusters
and cells in each cluster, their relative locations and physical aspect
ratios, and various attributes of clusters and cells. Designers use PDEF
as an interchange format between floorplanning and synthesis, between
partitioning and back-end tools, and between place and route and synthesis
tools.

PDEF was pioneered by Synopsys and developed in conjunction with other EDA
and semiconductor suppliers in 1993. EDA and semiconductor suppliers
including ArcSys, Cadence, COMPASS, High Level Design Systems, LSI Logic,
Mentor Graphics, Motorola, NEC, Texas Instruments, and Viewlogic currently
support PDEF with their tools and libraries.

OVI was founded in 1990 and exists to support and promote the use of
Verilog HDL worldwide. Members include electronic systems companies, EDA
tool vendors, semiconductor companies, universities and individuals. OVI,
the EIAJ (Electronic Industries Association of Japan) and the IEEE sponsor
the annual International Verilog HDL Conference, February 27-29, 1996, in
Santa Clara, CA.

For more information about OVI contact OVI, 15466 Los Gatos Blvd., Suite
109-071, Los Gatos, CA 95032, (408) 353-8899, FAX: (408) 353-8869,
ovi@netcom.com, http://www.chronologic.com/ovi/.

For more information on the International Verilog HDL Conference:
ivcinfo@ivcconf.com, http://www.e2w3.com/ivcconf.html.
 
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