Cyrix M1 Product Features

The Cyrix M1 architecture is a revolutionary advancement in the x86 family
of microprocessors, utilizing both superscalar and superpipelined
technologies to achieve high performance. The architecture not only
overcomes such performance barriers as data dependencies, change of flow
instructions and resource conflicts, but also brings the end user a
superior performance advantage without the need for recompiled software.

As the desktop PC takes on more sophisticated tasks, the 586-class CPUs
from Cyrix will provide to the high-end business and consumer markets the
software performance they demand.

Final product details and performance numbers of Cyrix's first 586
microprocessor will be available at the formal product announcement.

Package type:

The M1 package is a 296 pin SPGA, the same package used by the P54C. The M1
and P54C pinouts are similar enough that motherboards can be designed to
accept either part with a minimal number of jumpers. The only pinout
differences are test and debug features not used by most system designs.

Bus architecture:

The M1 products have a 64-bit data bus and support two burst orders. One
burst order is compatible with existing 64-bit chipsets and allows system
vendors an easy M1 implementation. Cyrix recommends the high performance
linear burst order, standard in most workstations today, and supported by
the majority of PC chipset vendors.

Cache size:

The M1 has a 16K unified instruction and data (I+D) cache as well as a
dedicated 256 byte instruction line cache that is fully associative. This
innovative architecture achieves the goals of high bandwidth via the
combination of the instruction line cache and unified cache, as well as a
high cache hit rate via the large 16K unified cache.

The hit rate for a unified cache is higher than for a Harvard cache
architecture that is split into instruction and data caches. The advantage
of a Harvard cache is increased bandwidth. The M1 achieves this bandwidth
through the combination of the instruction line cache and unified cache.
The unified cache is dual-ported to allow for two simultaneous fetches,
reads, writes or combinations of any two.

Heat dissipation:

Cyrix has targeted the M1-based 586 products at <10 watts @ 100 MHz at 3.3
volts. Cyrix has chosen to use a standard CMOS process technology that
provides higher yield and yields chips that require less power than an
equivalent BiCMOS process.

Cooling requirements:

The M1 has no special cooling requirements. However, cooling requirements
will vary depending on the specific system implementation.

FPU design:

Products from the M1 architecture contain a single 64-bit enhanced
x87-compatible floating point pipeline. The FPU is enhanced by a
four-instruction queue and four independent, 64-bit write buffers.

The FPU is optimized for today's business applications. Floating point
instructions in today's software tend to be interspersed with integer
instructions. Cyrix chose to speculatively execute the floating point
instead of building a large parallel multiplier like the Pentium. In the
M1 architecture, up to four floating point instructions can be executed
speculatively in parallel with integer instructions. Speculative execution
can increase floating point performance by up to 40 percent. The M1 FPU is
expected to have comparable performance to the Pentium's, while achieving
this with a significantly reduced transistor budget.

Die size:

The M1 die is 20.3 by 19.4 millimeters. When the M1 design was initiated
Cyrix did not have in place its current manufacturing agreements with IBM
and SGS-Thomson. Therefore, the M1 design was targeted to run on a broad
spectrum of manufacturing processes in any fab. Currently the M1 design is
implemented in triple layer metal (TLM). Cyrix has an aggressive shrink
plan in place, which will utilize both optical shrinks and a relayout
using additional metal layers, to reduce costs and increase
competitiveness.

Power management features:

Cyrix has included the same System Management Mode (SMM) across its entire
line of processors. In addition, the coprocessor automatically reduces
power consumption when not in use. There is also a hardware method for
putting the M1 into suspend mode. These unique features, combined with 3.3
volt operation, provide a power management environment that's easy to use
and an ideal solution for today's "green PCs. "

Voltage:

The M1 requires a 3.3 volt supply and includes 5 volt tolerant 1/0
buffers.

Clock speeds:

The initial 586-class products from the M1 architecture will be clock
doubled, and will operate at 50/100.

Compatibility:

Cyrix understands the mark of compatibility to be the installed base of x86
software, rather than any one of many Intel microprocessor designs.

All of Cyrix's processors are 100% compatible with this x86 installed
software base. It is Cyrix's goal to offer our customers x86
microprocessors well beyond mere clones, giving customers an alternative
with excellent performance, differentiation and value.

To compete in today's market, all alternative architectures, such as RISC
and PowerPC, must effectively emulate the x86 architecture in software.
This emulation attempt will always result in performance penalties, and
sometimes a compatibility penalty, relative to a similar x86 class
product. M1 demonstrates that the x86 can compete with the highest
performance microprocessors while remaining compatible with an installed
base of 140 million users who want to protect their $50B software
investment.

Recompiled software:

The M1 doesn't require recompiled software to achieve its performance
potential. Cyrix chose instead to design advanced features into the
hardware that would overcome performance barriers such as dependencies and
conflicts, providing ground breaking performance without the need to run
recompiled code. Cyrix believes the responsibility for high performance
hardware lies with the hardware manufacturer, not software vendors.

At the same time, the 586-class microprocessors from the M1 architecture
will take advantage of any code that's recompiled adding a 5 - 10%
performance boost. But the superior performance of Cyrix's M1 products is
achieved with existing software.

Chipset, motherboard and BIOS support:

The M1 architecture supports a logical superset of the Pentium-style bus
and is targeted to work with almost all 64-bit chipsets. The M1 products
will work with standard PCI chipsets.

Motherboards can be designed to accept either Pentium or the M1, and Cyrix
is developing easy solutions to assist motherboard vendors with M1
implementation. The same is true for BIOS vendors. The M1 does contain
unique features not found in the Pentium that can be used to design more
cost effective systems.

Multiprocessing:

The M1 architecture is designed to fully support multiprocessor operation.
Chipsets and motherboards utilizing the Cyrix-developed SLiC/MP interrupt
architecture technology are available today. These will enable system
manufacturers to choose the Cyrix 586-class microprocessors for their dual
processor desktop systems.

Performance:

Cyrix has targeted the initial 586 product to run at 100MHz and above.
Given equivalent systems at the same clock rate, Cyrix's simulated
benchmarks show a 30% to 50% performance improvement over the Pentium.
Benchmarks run on a simulated M1 and an actual Pentium include portions of
ZD PC Bench (ZD Protected Mode and ZD Real), MIPS Power Meter and Norton
SI. Actual numbers will be implementation and system dependent.

                    Clock Cycles:      M1         Pentium
  --------------------------------------------------------
  Norton SI                              7           15
  Ziff-Davis Real Mode 1k              198          292
  Ziff-Davis Protected Mode 1k         226          291
  Power Meter MIPs 1.8                 852         1171

The initial 586-class chips based on the M1 architecture are targeted to be
the fastest x86 chips available in 1995. The M1 architecture is designed
to remove major frequency barriers. The superpipelining of the M1 achieves
high clock rates with industry standard process technologies. Cyrix's
access to state-of-the-art process technology through our partnerships
with IBM Microelectronics and SGS-Thomson will allow us to achieve
significantly higher frequencies over time.

Spec rating:

The simulated spec rating for the M1 products is >1SPECint/MHz. Final
numbers will be released at the formal product announcement.

Comparisons to Intel's Pentium:

While both the Pentium and M1 architectures are focused on the x86 market,
are superscalar, include branch prediction, and can be used in a P54C
socket, the similarities in design end there. The M1 uses numerous
innovative architectural features that will allow Cyrix processors to take
full advantage of both pipelines, avoiding stalls in instruction
execution.

These features begin with superpipelining that divides the pipeline into
seven stages (as opposed to five in the Pentium) allowing instructions to
execute more efficiently. Another important difference is a feature called
register renaming that provides 32 general purpose registers rather than 8
registers as is available in x86 predecessors, including the Pentium.
Other specific features in the M1 not found in Pentium include data
forwarding, speculative execution and out-of-order completion.

  Feature                              M1               Pentium
  -----------------------------------------------------------------
  x86 Instruction Set                   X                   X
  Superscalar                           X                   X
  Multiple Integer Units                X                   X
  Superpipelined                        X
  Register Renaming                     X
  General Purpose Registers            32                   8
  Data Forwarding                       X
  Branch Prediction                     X                   X
  Speculative Execution                 X
  Out-of-Order Completion               X
  Cache Size                          16KB                 16KB
  Cache Architecture               Unified+ILC           Harvard
  FPU                                   X                   X
  P54C Bus/Package                      X                   X

Recommended benchmarks:

Cyrix believes that benchmarks which demonstrate applications performance
(such as BAPCo, the Ziff Davis PC Bench 8.0, as well as many other
application benchmarks) are the most useful for the consumer. Synthetic
tests (such as Norton Sl, Power Meter MIPS, etc.) are also useful in
certain situations. The specific benchmarks run on a simulated M1 include
portions of ZD PC Bench (ZD Protected Mode and ZD Real), MIPS Power Meter
and Norton Sl.

Manufacturing:

Initial production of the M1 microprocessors will come from IBM
Microelectronics and SGS-Thomson. Both companies have become steadfast
partners in our efforts to produce the highest quality CPUs available.
Their superior process technology is essential to our needs for quality
products for our customers.

Process technology:

All of the M1 products will be manufactured at .5 micron using the CMOS
process, targeting a move to .4 micron by the end of 1995. Cyrix has
access to these technologies from both IBM Microelectronics and
SGS-Thomson.

Availability:

Cyrix expects to begin sampling 586 microprocessors from the M1
architecture in Q4. Considering the company's history, Cyrix expects to be
in production in Q1.

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