Intel's P6 Processor Overview

The P6 family of processors will be the next generation of Intel's processor technology. All members of the P6 family will
be designed for complete compatibility with all PC software. The high performance of the P6 will make it especially
well-suited for upcoming desktop applications like speech recognition and multimedia authoring, as well as for more 
demanding server and workstation applications.  

Intel's P6 family of processors...
o Ensures complete binary compatibility with previous generations of the Intel Architecture.

o Delivers superior performance through an innovation called Dynamic Execution*.

o Provides support for enhanced data integrity and reliability feaures: ECC (Error Checking and 
  Correction), Fault Analysis & Recovery, and Functional Redundancy Checking.

o Includes features that will greatly simplify the design of multiprocessing systems.

The first member of the P6 processor family... 
o Arrives in desktops and servers in 1995.

o Integrates about 5.5 million transistors on the chip, compared to approximately 3.1 million transistors 
  on the Pentium processor.

o Will operate at 133MHz with estimated performance at more than 200 SPECint92.

o Will initially be produced on the same high volume 0.6 micron process currently used for the 90 and 
  100 MHz versions of the Pentium processor, and will then move to a 0.35 micron process.
  
o Delivers performance that will scale up to 1000 MIPS with four processors.


* What is Dynamic Execution?
Dynamic Execution is the unique combination of three processing techniques the P6 uses to speed up 
software:

o Multiple Branch prediction:  
  First, the processor looks multiple steps ahead in the software and predicts which branches, or groups 
  of instructions, are likely to be processed next.  This increases the amount of work fed to the 
  processor.
 
o Dataflow analysis: 
  Next, the P6 analyzes which instructions are dependent on each other's results, or data, to create an 
  optimized schedule of instructions.
 
o Speculative Execution: 
  Instructions are then carried out speculatively based on this optimized schedule, keeping all the chip's 
  superscalar processing power busy, and boosting overall software performance.