            TRS 80 MODEL I CP/M HARDWARE CONVERSION
            =======================================

Description of CP/M conversion for Model I as designed by
Bruce Orr.

COMPONENTS:
        1 x 74LS04 hex inverter
        1 x 74LS367 hex tri-state bus driver
        1 x 1 M resistor
        1 x 0.022uF capacitor
        1 x SPST toggle switch
        1 x push button (N.O.)
        PCB or Veroboard

This modification adapts the TRS 80 model I for CP/M by:
        i) Remapping memory so that RAM commences at 0000H.
       ii) Adding a jump to zero reset switch.

i) MEMORY REMAPPING
This is achieved by swapping the first 16K block of memory
(ie ROM & I/O) with the last (part of RAM).

 FFFF +------+                    +-------+  video = FC00
      ! RAM  ! -------+ +-------> ! IO,ROM!  keybd = F800
 C000 +------+        ! !         +-------+  disk controller
      ! RAM  ! -----------------> !  RAM  !        = F7EC
 8000 +------+         X          +-------+  disk select
      ! RAM  ! -----------------> !  RAM  !        = F7E1
 4000 +------+        ! !         +-------+  ROM (now quite
      !IO,ROM! -------+ +-------> !  RAM  !   useless) = C000
 0000 +------+                    +-------+
    normal (TRS) mapping        CP/M mapping

The CP/M memory mapping is achieved by inverting & swapping
address bits A14 & A15 from the Z80 before they enter the
address decoding circuits.

EXISTING CIRCUIT:
+-----------+           12    11
!       A14 !--------------!>----------------
!  Z80      !
!       A15 !--------------!>----------------
+-----------+            10   9
                    Z38 (74LS367)

MODIFIED CIRCUIT:
+-----------+
!       A14 !----+---------!>---------------------X-------+--
!  Z80      !    !   Existing gates not used     Cut      !
!       A15 !-+--)---------!>---------------------X----+--)--
+-----------+ !  !                                     !  !
              !  !              4    5                 !  !
              !  +----------------!>-------------------)--+
              !  !                 !                   !  !
              !  !              2  ! 3                 !  !
              +--)----------------!>-------------------+  !
              !  !                 ! 1                 !  !
              !  !                 +----------+        !  !
              !  !  11   10    14    13       !        !  !
              !  +----!>o---------!>----------)--------+  !
              !                    !          !           !
              !      3   4     12  ! 11       !           !
              +-------!>o---------!>----------)-----------+
                                   ! 15       !
                       o----!>o----+------!>o-+
           0V ------o--o   1   2        13  12
                   switch
               closed=TRS, open=CP/M           !>  LS367
                                               !>o LS04

Suggest that this be built on a small PCB mounted near Z80 on
main board.

ii) RESET SWITCH
NB: significantly different for the Sys 80.

Requirements:
        a) Must not disable power up reset.
        b) Provides sufficient reset pulse to reset the Z80.
        c) While the Z80 is held reset, memory refreshing is
           halted.  Thus, reset pulse must not be too long,
           even if reset switch is held closed.


ORIGINAL CIRCUIT:

        +5V !
            X
        10K X
            !   NAND gate
            +======!)o---- RESET
            !
           === 10uF C42
         0V !

NEW CIRCUIT:

        +5V !
            X
        10K X
            !
            +-------+======!)o---- RESET
            !       !
         1M X      === 22nF C42 (0.022u)
reset       X       !
 P.B. _I_   !       !
 0V --o o---+-------+


TEST PROGRAMS
Two programs to test this modification have been uploaded to
the OMEN as CPMTST1/ASM & CPMTST2/ASM.  They can be assembled
using EDTASM.  Operating instructions included in the source.
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