; The format of the input file:
; each device definition begins with a line like this:
;
;       .devicename
;
;  after it go the port definitions in this format:
;
;       portname        address
;
;  the bit definitions (optional) are represented like this:
;
;       portname.bitname  bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
;       .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
; MOTOROLA SPECIFIC LINES
;------------------------
;
; the processor definition may include the memory configuration.
; the line format is:

;       area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
;       START and END are addresses, the end address is not included

; Interrupt vectors are declared in the following way:

; interrupt NAME ADDRESS COMMENT


.default 68HC05X32



.68HC05B16
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05B16&nodeId=01M98633
; 6805b6r4.pdf

; RAM=352
; ROM=15K
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_P0      0x0020:0x0050
area DATA RAM_U1      0x0050:0x0100
area DATA EEPROM      0x0100:0x0200
area BSS  RESERVED    0x0200:0x0250
area DATA RAM_U2      0x0250:0x0300
area CODE ROM_P1      0x0300:0x3DFE
area BSS  RESERVED    0x3DFE:0x3E00
area DATA ROM_P2      0x3E00:0x3FF0
area BSS  RESERVED    0x3FF0:0x3FF2
area DATA USER_VEC    0x3FF2:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x3FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x3FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x3FF4      Timer overflow
interrupt SCI               0x3FF2      SCI0


; INPUT/ OUTPUT PORTS
PORTA            0x0000    Port A data
PORTA.PA7         7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
PORTB            0x0001    Port B data
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTC            0x0002    Port C data
PORTC.PC2_ECLK    2   Port C Data Bits 2
PORTD            0x0003    Port D data
PORTD.PD7         7   Port D Data Bits 7
PORTD.PD6         6   Port D Data Bits 6
PORTD.PD5         5   Port D Data Bits 5
PORTD.PD4         4   Port D Data Bits 4
PORTD.PD3         3   Port D Data Bits 3
PORTD.PD2         2   Port D Data Bits 2
PORTD.PD1         1   Port D Data Bits 1
PORTD.PD0         0   Port D Data Bits 0
DDRA             0x0004    Port A data direction
DDRA.DDA7         7   Data Direction for Port A Bit 7
DDRA.DDA6         6   Data Direction for Port A Bit 6
DDRA.DDA5         5   Data Direction for Port A Bit 5
DDRA.DDA4         4   Data Direction for Port A Bit 4
DDRA.DDA3         3   Data Direction for Port A Bit 3
DDRA.DDA2         2   Data Direction for Port A Bit 2
DDRA.DDA1         1   Data Direction for Port A Bit 1
DDRA.DDA0         0   Data Direction for Port A Bit 0
DDRB             0x0005    Port B data direction
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRC             0x0006    Port C data direction
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
ECLK             0x0007    EEPROM/ECLK control
ECLK.ECLK         3   External clock output bit
ECLK.E1ERA        2   EEPROM erase/programming bit
ECLK.E1LAT        1   EEPROM programming latch enable bit
ECLK.E1PGM        0   EEPROM charge pump enable/disable
ADDATA           0x0008  A/D data
ADSTAT           0x0009  A/D ststus/control
ADSTAT.COCO       7   Conversion complete flag
ADSTAT.ADRC       6   A/D RC oscillator control
ADSTAT.ADON       5   A/D converter on
ADSTAT.CH3        3   A/D channel 3
ADSTAT.CH2        2   A/D channel 2
ADSTAT.CH1        1   A/D channel 1
ADSTAT.CH0        0   A/D channel 0
PLMA             0x000A  Pulse length modulation A
PLMB             0x000B  Pulse length modulation B
Miscell          0x000C  Miscellaneous
Miscell.POR       7   Power-on reset bit
Miscell.INTP      6   External interrupt sensitivity options
Miscell.INTN      5   External interrupt sensitivity options
Miscell.INTE      4   External interrupt enable
Miscell.SFA       3   Slow or fast mode selection for PLMA
Miscell.SFB       2   Slow or fast mode selection for PLMB
Miscell.SM        1   Slow mode
Miscell.WDOG      0   Watchdog enable/disable
BAUD             0x000D   SCI baud rate
BAUD.SPC1         7   Serial prescaler select bit 1
BAUD.SPC0         6   Serial prescaler select bit 0
BAUD.SCT2         5   SCI rate select bits (transmitter) 2
BAUD.SCT1         4   SCI rate select bits (transmitter) 1
BAUD.SCT0         3   SCI rate select bits (transmitter) 0
BAUD.SCR2         2   SCI rate select bits (receiver) 2
BAUD.SCR1         1   SCI rate select bits (receiver) 1
BAUD.SCR0         0   SCI rate select bits (receiver) 0
SCCR1            0x000E   SCI control 1
SCCR1.R8          7   Receive Data Bit 8            
SCCR1.T8          6   Transmit Data Bit 8           
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake Up by Address Mark/Idle  
SCCR1.CPOL        2
SCCR1.CPHA        1
SCCR1.LBCL        0
SCCR2            0x000F    SCI control 2
SCCR2.TIE         7   Transmit interrupt enable
SCCR2.TCIE        6   Transmit complete interrupt enable
SCCR2.RIE         5   Receiver interrupt enable
SCCR2.ILIE        4   Idle line interrupt enable
SCCR2.TE          3   Transmitter enable
SCCR2.RE          2   Receiver enable
SCCR2.RWU         1   Receiver wake-up
SCCR2.SBK         0   Send break
SCSR             0x0010    SCI status
SCSR.TDRE         7   Transmit data register empty flag
SCSR.TC           6   Transmit complete flag
SCSR.RDRF         5   Receive data register full flag
SCSR.IDLE         4   Idle line detected flag
SCSR.OR           3   Overrun error flag
SCSR.NF           2   Noise error flag
SCSR.FE           1   Framing error flag
SCDR             0x0011    SCI data
TCR              0x0012    Timer control
TCR.ICIE          7   Input captures interrupt enable
TCR.OCIE          6   Output compares interrupt enable
TCR.TOIE          5   Timer overflow interrupt enable
TCR.FOLV2         4   Force output compare 2
TCR.FOLV1         3   Force output compare 1
TCR.OLV2          2   Output level 2
TCR.IEDG1         1   Input edge 1
TCR.OLVL1         0   Output level 1
TSR              0x0013    Timer ststus
TSR.ICF1          7   Input capture flag 1
TSR.OCF1          6   Output compare flag 1
TSR.TOF           5   Timer overflow status flag
TSR.ICF2          4   Input capture flag 2
TSR.OCF2          3   Output compare flag 2
ICH1             0x0014    Input capture high 1
ICL1             0x0015    Input capture low 1
OCH1             0x0016    Output compare high 1
OCL1             0x0017    Output compare low 1
TCH              0x0018    Timer counter high
TCL              0x0019    Timer counter low
ACH              0x001A    Alternate counter high
ACL              0x001B    Alternate counter low
ICH2             0x001C    Input campare high 2
ICL2             0x001D    Input capture low 2
OCH2             0x001E    Output compare high 2
OCL2             0x001F    Output compare low 2
OPTR             0x0100    Options
OPTR.EE1P         1   EEPROM protect bit
OPTR.SEC          0   Secure bit


.68HC05B32
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05B32&nodeId=01M98633
; 6805b6r4.pdf

; RAM=528
; ROM=32K
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  RESERVED    0x0020:0x0050
area DATA RAM_U1      0x0050:0x0100
area DATA EEPROM      0x0100:0x0200
area DATA BootROM1    0x0200:0x0250
area DATA RAM_U2      0x0250:0x03B0
area DATA BootROM2    0x03B0:0x0400
area DATA ROM         0x0400:0x7E00
area DATA BootROM3    0x7E00:0x7FDE
area BSS  RESERVED    0x7FDE:0x7FE0
area DATA BootROM     0x7FE0:0x7FF0
area BSS  RESERVED    0x7FF0:0x7FF2
area DATA USER_VEC    0x7FF2:0x8000


; Interrupt and reset vector assignments
interrupt __RESET           0x7FFE      Processor reset
interrupt SWI               0x7FFC      Software interrupt
interrupt IRQ               0X7FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x7FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x7FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x7FF4      Timer overflow
interrupt SCI               0x7FF2      SCI0


; INPUT/ OUTPUT PORTS
PORTA            0x0000    Port A data
PORTA.PA7         7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
PORTB            0x0001    Port B data
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTC            0x0002    Port C data
PORTC.PC2_ECLK    2   Port C Data Bits 2
PORTD            0x0003    Port D data
PORTD.PD7         7   Port D Data Bits 7
PORTD.PD6         6   Port D Data Bits 6
PORTD.PD5         5   Port D Data Bits 5
PORTD.PD4         4   Port D Data Bits 4
PORTD.PD3         3   Port D Data Bits 3
PORTD.PD2         2   Port D Data Bits 2
PORTD.PD1         1   Port D Data Bits 1
PORTD.PD0         0   Port D Data Bits 0
DDRA             0x0004    Port A data direction
DDRA.DDA7         7   Data Direction for Port A Bit 7
DDRA.DDA6         6   Data Direction for Port A Bit 6
DDRA.DDA5         5   Data Direction for Port A Bit 5
DDRA.DDA4         4   Data Direction for Port A Bit 4
DDRA.DDA3         3   Data Direction for Port A Bit 3
DDRA.DDA2         2   Data Direction for Port A Bit 2
DDRA.DDA1         1   Data Direction for Port A Bit 1
DDRA.DDA0         0   Data Direction for Port A Bit 0
DDRB             0x0005    Port B data direction
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRC             0x0006    Port C data direction
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
EEPROM           0x0007    EEPROM/ECLK control
EEPROM.ECLK       3   External clock output bit
EEPROM.E1ERA      2   EEPROM erase/programming bit
EEPROM.E1LAT      1   EEPROM programming latch enable bit
EEPROM.E1PGM      0   EEPROM charge pump enable/disable
ADDATA           0x0008  A/D data
ADSTAT           0x0009  A/D status/control
ADSTAT.COCO       7   Conversion complete flag 
ADSTAT.ADRC       6   A/D RC oscillator control
ADSTAT.ADON       5   A/D converter on         
ADSTAT.CH3        3   A/D channel 3            
ADSTAT.CH2        2   A/D channel 2            
ADSTAT.CH1        1   A/D channel 1            
ADSTAT.CH0        0   A/D channel 0            
PLMA             0x000A  Pulse length modulation A
PLMB             0x000B  Pulse length modulation B
Miscell          0x000C  Miscellaneous
Miscell.POR       7   Power-on reset bit                    
Miscell.INTP      6   External interrupt sensitivity options
Miscell.INTN      5   External interrupt sensitivity options
Miscell.INTE      4   External interrupt enable             
Miscell.SFA       3   Slow or fast mode selection for PLMA  
Miscell.SFB       2   Slow or fast mode selection for PLMB  
Miscell.SM        1   Slow mode                             
Miscell.WDOG      0   Watchdog enable/disable               
BAUD             0x000D   SCI baud rate
BAUD.SPC1         7   Serial prescaler select bit 1       
BAUD.SPC0         6   Serial prescaler select bit 0       
BAUD.SCT2         5   SCI rate select bits (transmitter) 2
BAUD.SCT1         4   SCI rate select bits (transmitter) 1
BAUD.SCT0         3   SCI rate select bits (transmitter) 0
BAUD.SCR2         2   SCI rate select bits (receiver) 2   
BAUD.SCR1         1   SCI rate select bits (receiver) 1   
BAUD.SCR0         0   SCI rate select bits (receiver) 0   
SCCR1            0x000E   SCI control 1
SCCR1.R8          7   Receive Data Bit 8            
SCCR1.T8          6   Transmit Data Bit 8           
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake Up by Address Mark/Idle  
SCCR1.CPOL        2
SCCR1.CPHA        1
SCCR1.LBCL        0
SCCR2            0x000F    SCI control 2
SCCR2.TIE         7   Transmit interrupt enable         
SCCR2.TCIE        6   Transmit complete interrupt enable
SCCR2.RIE         5   Receiver interrupt enable         
SCCR2.ILIE        4   Idle line interrupt enable        
SCCR2.TE          3   Transmitter enable                
SCCR2.RE          2   Receiver enable                   
SCCR2.RWU         1   Receiver wake-up                  
SCCR2.SBK         0   Send break                        
SCSR             0x0010    SCI status
SCSR.TDRE         7   Transmit data register empty flag
SCSR.TC           6   Transmit complete flag           
SCSR.RDRF         5   Receive data register full flag  
SCSR.IDLE         4   Idle line detected flag          
SCSR.OR           3   Overrun error flag               
SCSR.NF           2   Noise error flag                 
SCSR.FE           1   Framing error flag               
SCDR             0x0011    SCI data
TCR              0x0012    Timer control
TCR.ICIE          7   Input captures interrupt enable 
TCR.OCIE          6   Output compares interrupt enable
TCR.TOIE          5   Timer overflow interrupt enable 
TCR.FOLV2         4   Force output compare 2          
TCR.FOLV1         3   Force output compare 1          
TCR.OLV2          2   Output level 2                  
TCR.IEDG1         1   Input edge 1                    
TCR.OLVL1         0   Output level 1                  
TSR              0x0013    Timer ststus
TSR.ICF1          7   Input capture flag 1      
TSR.OCF1          6   Output compare flag 1     
TSR.TOF           5   Timer overflow status flag
TSR.ICF2          4   Input capture flag 2      
TSR.OCF2          3   Output compare flag 2     
ICH1             0x0014    Input capture high 1
ICL1             0x0015    Input capture low 1
OCH1             0x0016    Output compare high 1
OCL1             0x0017    Output compare low 1
TCH              0x0018    Timer counter high
TCL              0x0019    Timer counter low
ACH              0x001A    Alternate counter high
ACL              0x001B    Alternate counter low
ICH2             0x001C    Input campare high 2
ICL2             0x001D    Input capture low 2
OCH2             0x001E    Output compare high 2
OCL2             0x001F    Output compare low 2
OPTR             0x0100    Options
OPTR.EE1P         1   EEPROM protect bit
OPTR.SEC          0   Secure bit        
MOR              0x7FDE    Mask option register
MOR.RTIM          4
MOR.RWAT          3
MOR.WWAT          2
MOR.PBPD          1
MOR.PCPD          0


.68HC05B6
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05B6&nodeId=01M98633
; 6805b6r4.pdf

; RAM=176
; ROM=6K
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR       0x0000:0x0020
area DATA ROM_P0    0x0020:0x0050
area DATA RAM       0x0050:0x0100
area DATA _EEPROM_  0x0100:0x0200
area DATA ROM_P1    0x0200:0x02C0
area BSS  RESERVED  0x02C0:0x0800
area DATA ROM_P2    0x0800:0x1F00
area DATA ROM_P3    0x1F00:0x1FF0
area BSS  RESERVED  0x1FF0:0x1FF2
area DATA USER_VEC  0x1FF2:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x1FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x1FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x1FF4      Timer overflow
interrupt SCI               0x1FF2      SCI0


; INPUT/ OUTPUT PORTS
PORTA            0x0000    Port A data
PORTA.PA7         7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
PORTB            0x0001    Port B data
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTC            0x0002    Port C data
PORTC.PC2_ECLK    2   Port C Data Bits 2
PORTD            0x0003    Port D data
PORTD.PD7         7   Port D Data Bits 7
PORTD.PD6         6   Port D Data Bits 6
PORTD.PD5         5   Port D Data Bits 5
PORTD.PD4         4   Port D Data Bits 4
PORTD.PD3         3   Port D Data Bits 3
PORTD.PD2         2   Port D Data Bits 2
PORTD.PD1         1   Port D Data Bits 1
PORTD.PD0         0   Port D Data Bits 0
DDRA             0x0004    Port A data direction
DDRA.DDA7         7   Data Direction for Port A Bit 7
DDRA.DDA6         6   Data Direction for Port A Bit 6
DDRA.DDA5         5   Data Direction for Port A Bit 5
DDRA.DDA4         4   Data Direction for Port A Bit 4
DDRA.DDA3         3   Data Direction for Port A Bit 3
DDRA.DDA2         2   Data Direction for Port A Bit 2
DDRA.DDA1         1   Data Direction for Port A Bit 1
DDRA.DDA0         0   Data Direction for Port A Bit 0
DDRB             0x0005    Port B data direction
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRC             0x0006    Port C data direction
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
EEPROM           0x0007    EEPROM/ECLK control
EEPROM.ECLK       3   External clock output bit          
EEPROM.E1ERA      2   EEPROM erase/programming bit       
EEPROM.E1LAT      1   EEPROM programming latch enable bit
EEPROM.E1PGM      0   EEPROM charge pump enable/disable  
ADDATA           0x0008  A/D data
ADSTAT           0x0009  A/D ststus/control
ADSTAT.COCO       7   Conversion complete flag 
ADSTAT.ADRC       6   A/D RC oscillator control
ADSTAT.ADON       5   A/D converter on         
ADSTAT.CH3        3   A/D channel 3            
ADSTAT.CH2        2   A/D channel 2            
ADSTAT.CH1        1   A/D channel 1            
ADSTAT.CH0        0   A/D channel 0            
PLMA             0x000A  Pulse length modulation A
PLMB             0x000B  Pulse length modulation B
Miscell          0x000C  Miscellaneous
Miscell.POR       7   Power-on reset bit                    
Miscell.INTP      6   External interrupt sensitivity options
Miscell.INTN      5   External interrupt sensitivity options
Miscell.INTE      4   External interrupt enable             
Miscell.SFA       3   Slow or fast mode selection for PLMA  
Miscell.SFB       2   Slow or fast mode selection for PLMB  
Miscell.SM        1   Slow mode                             
Miscell.WDOG      0   Watchdog enable/disable               
BAUD             0x000D   SCI baud rate
BAUD.SPC1         7   Serial prescaler select bit 1       
BAUD.SPC0         6   Serial prescaler select bit 0       
BAUD.SCT2         5   SCI rate select bits (transmitter) 2
BAUD.SCT1         4   SCI rate select bits (transmitter) 1
BAUD.SCT0         3   SCI rate select bits (transmitter) 0
BAUD.SCR2         2   SCI rate select bits (receiver) 2   
BAUD.SCR1         1   SCI rate select bits (receiver) 1   
BAUD.SCR0         0   SCI rate select bits (receiver) 0   
SCCR1            0x000E   SCI control 1
SCCR1.R8          7   Receive Data Bit 8            
SCCR1.T8          6   Transmit Data Bit 8           
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake Up by Address Mark/Idle  
SCCR1.CPOL        2
SCCR1.CPHA        1
SCCR1.LBCL        0
SCCR2            0x000F    SCI control 2
SCCR2.TIE         7   Transmit interrupt enable         
SCCR2.TCIE        6   Transmit complete interrupt enable
SCCR2.RIE         5   Receiver interrupt enable         
SCCR2.ILIE        4   Idle line interrupt enable        
SCCR2.TE          3   Transmitter enable                
SCCR2.RE          2   Receiver enable                   
SCCR2.RWU         1   Receiver wake-up                  
SCCR2.SBK         0   Send break                        
SCSR             0x0010    SCI status
SCSR.TDRE         7   Transmit data register empty flag
SCSR.TC           6   Transmit complete flag           
SCSR.RDRF         5   Receive data register full flag  
SCSR.IDLE         4   Idle line detected flag          
SCSR.OR           3   Overrun error flag               
SCSR.NF           2   Noise error flag                 
SCSR.FE           1   Framing error flag               
SCDR             0x0011    SCI data
TCR              0x0012    Timer control
TCR.ICIE          7   Input captures interrupt enable 
TCR.OCIE          6   Output compares interrupt enable
TCR.TOIE          5   Timer overflow interrupt enable 
TCR.FOLV2         4   Force output compare 2          
TCR.FOLV1         3   Force output compare 1          
TCR.OLV2          2   Output level 2                  
TCR.IEDG1         1   Input edge 1                    
TCR.OLVL1         0   Output level 1                  
TSR              0x0013    Timer ststus
TSR.ICF1          7   Input capture flag 1      
TSR.OCF1          6   Output compare flag 1     
TSR.TOF           5   Timer overflow status flag
TSR.ICF2          4   Input capture flag 2      
TSR.OCF2          3   Output compare flag 2     
ICH1             0x0014    Input capture high 1
ICL1             0x0015    Input capture low 1
OCH1             0x0016    Output compare high 1
OCL1             0x0017    Output compare low 1
TCH              0x0018    Timer counter high
TCL              0x0019    Timer counter low
ACH              0x001A    Alternate counter high
ACL              0x001B    Alternate counter low
ICH2             0x001C    Input campare high 2
ICL2             0x001D    Input capture low 2
OCH2             0x001E    Output compare high 2
OCL2             0x001F    Output compare low 2
OPTR             0x0100    Options
OPTR.EE1P         1   EEPROM protect bit
OPTR.SEC          0   Secure bit        


.68HC05B8
; MC68HC05B6/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05B8&nodeId=01M98633
; 6805b6r4.pdf

; RAM=176
; ROM=7K
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR       0x0000:0x0020
area DATA ROM_P0    0x0020:0x0050
area DATA RAM       0x0050:0x0100
area DATA _EEPROM_  0x0100:0x0200
area DATA ROM_P1    0x0200:0x02C0
area BSS  RESERVED  0x02C0:0x0300
area DATA ROM_P2    0x0300:0x1F00
area DATA ROM_P3    0x1F00:0x1FF0
area BSS  RESERVED  0x1FF0:0x1FF2
area DATA USER_VEC  0x1FF2:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x1FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x1FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x1FF4      Timer overflow
interrupt SCI               0x1FF2      SCI0


; INPUT/ OUTPUT PORTS
PORTA            0x0000    Port A data
PORTA.PA7         7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
PORTB            0x0001    Port B data
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTC            0x0002    Port C data
PORTC.PC2_ECLK    2   Port C Data Bits 2
PORTD            0x0003    Port D data
PORTD.PD7         7   Port D Data Bits 7
PORTD.PD6         6   Port D Data Bits 6
PORTD.PD5         5   Port D Data Bits 5
PORTD.PD4         4   Port D Data Bits 4
PORTD.PD3         3   Port D Data Bits 3
PORTD.PD2         2   Port D Data Bits 2
PORTD.PD1         1   Port D Data Bits 1
PORTD.PD0         0   Port D Data Bits 0
DDRA             0x0004    Port A data direction
DDRA.DDA7         7   Data Direction for Port A Bit 7
DDRA.DDA6         6   Data Direction for Port A Bit 6
DDRA.DDA5         5   Data Direction for Port A Bit 5
DDRA.DDA4         4   Data Direction for Port A Bit 4
DDRA.DDA3         3   Data Direction for Port A Bit 3
DDRA.DDA2         2   Data Direction for Port A Bit 2
DDRA.DDA1         1   Data Direction for Port A Bit 1
DDRA.DDA0         0   Data Direction for Port A Bit 0
DDRB             0x0005    Port B data direction
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRC             0x0006    Port C data direction
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
EEPROM           0x0007    EEPROM/ECLK control
EEPROM.ECLK       3   External clock output bit          
EEPROM.E1ERA      2   EEPROM erase/programming bit       
EEPROM.E1LAT      1   EEPROM programming latch enable bit
EEPROM.E1PGM      0   EEPROM charge pump enable/disable  
ADDATA           0x0008  A/D data
ADSTAT           0x0009  A/D ststus/control
ADSTAT.COCO       7   Conversion complete flag 
ADSTAT.ADRC       6   A/D RC oscillator control
ADSTAT.ADON       5   A/D converter on         
ADSTAT.CH3        3   A/D channel 3            
ADSTAT.CH2        2   A/D channel 2            
ADSTAT.CH1        1   A/D channel 1            
ADSTAT.CH0        0   A/D channel 0            
PLMA             0x000A  Pulse length modulation A
PLMB             0x000B  Pulse length modulation B
Miscell          0x000C  Miscellaneous
Miscell.POR       7   Power-on reset bit                    
Miscell.INTP      6   External interrupt sensitivity options
Miscell.INTN      5   External interrupt sensitivity options
Miscell.INTE      4   External interrupt enable             
Miscell.SFA       3   Slow or fast mode selection for PLMA  
Miscell.SFB       2   Slow or fast mode selection for PLMB  
Miscell.SM        1   Slow mode                             
Miscell.WDOG      0   Watchdog enable/disable               
BAUD             0x000D   SCI baud rate
BAUD.SPC1         7   Serial prescaler select bit 1       
BAUD.SPC0         6   Serial prescaler select bit 0       
BAUD.SCT2         5   SCI rate select bits (transmitter) 2
BAUD.SCT1         4   SCI rate select bits (transmitter) 1
BAUD.SCT0         3   SCI rate select bits (transmitter) 0
BAUD.SCR2         2   SCI rate select bits (receiver) 2   
BAUD.SCR1         1   SCI rate select bits (receiver) 1   
BAUD.SCR0         0   SCI rate select bits (receiver) 0   
SCCR1            0x000E   SCI control 1
SCCR1.R8          7   Receive Data Bit 8            
SCCR1.T8          6   Transmit Data Bit 8           
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake Up by Address Mark/Idle  
SCCR1.CPOL        2
SCCR1.CPHA        1
SCCR1.LBCL        0
SCCR2            0x000F    SCI control 2
SCCR2.TIE         7   Transmit interrupt enable         
SCCR2.TCIE        6   Transmit complete interrupt enable
SCCR2.RIE         5   Receiver interrupt enable         
SCCR2.ILIE        4   Idle line interrupt enable        
SCCR2.TE          3   Transmitter enable                
SCCR2.RE          2   Receiver enable                   
SCCR2.RWU         1   Receiver wake-up                  
SCCR2.SBK         0   Send break                        
SCSR             0x0010    SCI status
SCSR.TDRE         7   Transmit data register empty flag
SCSR.TC           6   Transmit complete flag           
SCSR.RDRF         5   Receive data register full flag  
SCSR.IDLE         4   Idle line detected flag          
SCSR.OR           3   Overrun error flag               
SCSR.NF           2   Noise error flag                 
SCSR.FE           1   Framing error flag               
SCDR             0x0011    SCI data
TCR              0x0012    Timer control
TCR.ICIE          7   Input captures interrupt enable 
TCR.OCIE          6   Output compares interrupt enable
TCR.TOIE          5   Timer overflow interrupt enable 
TCR.FOLV2         4   Force output compare 2          
TCR.FOLV1         3   Force output compare 1          
TCR.OLV2          2   Output level 2                  
TCR.IEDG1         1   Input edge 1                    
TCR.OLVL1         0   Output level 1                  
TSR              0x0013    Timer ststus
TSR.ICF1          7   Input capture flag 1      
TSR.OCF1          6   Output compare flag 1     
TSR.TOF           5   Timer overflow status flag
TSR.ICF2          4   Input capture flag 2      
TSR.OCF2          3   Output compare flag 2     
ICH1             0x0014   Input capture high 1
ICL1             0x0015   Input capture low 1
OCH1             0x0016   Output compare high 1
OCL1             0x0017   Output compare low 1
TCH              0x0018   Timer counter high
TCL              0x0019   Timer counter low
ACH              0x001A   Alternate counter high
ACL              0x001B   Alternate counter low
ICH2             0x001C   Input campare high 2
ICL2             0x001D   Input capture low 2
OCH2             0x001E   Output compare high 2
OCL2             0x001F   Output compare low 2
OPTR             0x0100   Options
OPTR.EE1P         1   EEPROM protect bit
OPTR.SEC          0   Secure bit        


.68HC05BD5
; MC68HC05BD3D/H  http://
; MC68HC05BD3D.pdf

; The user RAM consists of 256 bytes of memory, from $0080 to $017F
; The user ROM consists of 7.75K-bytes of memory, from $2000 to $3EFF

; RAM=256
; ROM=7.75K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR			0x0000:0x0030
area BSS  UNUSED		0x0030:0x0080
area DATA RAM			0x0080:0x0180
area BSS  UNUSED		0x0180:0x2000
area DATA ROM			0x2000:0x3F00
area DATA Self_Check_Prog	0x3F00:0x3FE0
area DATA Self_Check_Vect	0x3FE0:0x3FF0
area DATA USER_VEC		0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET    0x3FFE       Reset 
interrupt SWI        0x3FFC       Software
interrupt IRQ        0x3FFA       External Interrupt
interrupt SSP        0x3FF8       VSYNC
interrupt MBUS       0x3FF6       M-Bus
interrupt MFT        0x3FF4       Timer Overflow / Real Time Interrupt


; INPUT/ OUTPUT PORTS
PORTA             0x0000     Port A data
PORTA.PA7          7   Port A Data Bits 7
PORTA.PA6          6   Port A Data Bits 6
PORTA.PA5          5   Port A Data Bits 5
PORTA.PA4          4   Port A Data Bits 4
PORTA.PA3          3   Port A Data Bits 3
PORTA.PA2          2   Port A Data Bits 2
PORTA.PA1          1   Port A Data Bits 1
PORTA.PA0          0   Port A Data Bits 0
PORTB             0x0001     Port B data
PORTB.PB5          5   Port B Data Bits 5 
PORTB.PB4          4   Port B Data Bits 4 
PORTB.PB3          3   Port B Data Bits 3 
PORTB.PB2          2   Port B Data Bits 2 
PORTB.PB1          1   Port B Data Bits 1 
PORTB.PB0          0   Port B Data Bits 0 
PORTC             0x0002     Port C data
PORTC.PC7          7   Port C Data Bits 7
PORTC.PC6          6   Port C Data Bits 6
PORTC.PC5          5   Port C Data Bits 5
PORTC.PC4          4   Port C Data Bits 4
PORTC.PC3          3   Port C Data Bits 3
PORTC.PC2          2   Port C Data Bits 2
PORTC.PC1          1   Port C Data Bits 1
PORTC.PC0          0   Port C Data Bits 0
PORTD             0x0003     Port D data
PORTD.PD1          1   Port D Data Bits 1
PORTD.PD0          0   Port D Data Bits 0
DDRA              0x0004     Port A data direction
DDRA.DDRA7         7   Data Direction for Port A Bit 7
DDRA.DDRA6         6   Data Direction for Port A Bit 6
DDRA.DDRA5         5   Data Direction for Port A Bit 5
DDRA.DDRA4         4   Data Direction for Port A Bit 4
DDRA.DDRA3         3   Data Direction for Port A Bit 3
DDRA.DDRA2         2   Data Direction for Port A Bit 2
DDRA.DDRA1         1   Data Direction for Port A Bit 1
DDRA.DDRA0         0   Data Direction for Port A Bit 0
DDRB              0x0005     Port B data direction
DDRB.DDRB5         5   Data Direction for Port B Bit 5
DDRB.DDRB4         4   Data Direction for Port B Bit 4
DDRB.DDRB3         3   Data Direction for Port B Bit 3
DDRB.DDRB2         2   Data Direction for Port B Bit 2
DDRB.DDRB1         1   Data Direction for Port B Bit 1
DDRB.DDRB0         0   Data Direction for Port B Bit 0
DDRC              0x0006     Port C data direction
DDRC.DDRC7         7   Data Direction for Port C Bit 7
DDRC.DDRC6         6   Data Direction for Port C Bit 6
DDRC.DDRC5         5   Data Direction for Port C Bit 5
DDRC.DDRC4         4   Data Direction for Port C Bit 4
DDRC.DDRC3         3   Data Direction for Port C Bit 3
DDRC.DDRC2         2   Data Direction for Port C Bit 2
DDRC.DDRC1         1   Data Direction for Port C Bit 1
DDRC.DDRC0         0   Data Direction for Port C Bit 0
DDRD              0x0007     Port D data direction
DDRD.DDRD1         1   Data Direction for Port D Bit 1
DDRD.DDRD0         0   Data Direction for Port D Bit 0
MFTCS             0x0008     MFT control and status
MFTCS.TOF          7   Timer Overflow                        
MFTCS.RTIF         6   Real Time Interrupt Flag              
MFTCS.TOFIE        5   Timer Overflow Interrupt Enable       
MFTCS.RTIE         4   Real Time Interrupt Enable            
MFTCS.IRQN         3   IRQ Pin Trigger Option                
MFTCS.RT1          1   Rate Select for COP watchdog and RTI 1
MFTCS.RT0          0   Rate Select for COP watchdog and RTI 0
MFTTC             0x0009     MFT timer counter
MFTTC.MFTCR7       7
MFTTC.MFTCR6       6
MFTTC.MFTCR5       5
MFTTC.MFTCR4       4
MFTTC.MFTCR3       3
MFTTC.MFTCR2       2
MFTTC.MFTCR1       1
MFTTC.MFTCR0       0
CONFIG1           0x000A     Configuration 1
CONFIG1.PWM15      7
CONFIG1.PWM14      6
CONFIG1.PWM13      5
CONFIG1.PWM12      4
CONFIG1.PWM11      3
CONFIG1.PWM10      2
CONFIG1.PWM9       1
CONFIG1.PWM8       0
CONFIG2           0x000B     Configuration 2
CONFIG2.HTTL       7
CONFIG2.VTTL       6
CONFIG2.SCL        1
CONFIG2.SDA        0
SSPCS             0x000C     SSP control and status
SSPCS.VPOL         7   Vertical Sync Input Polarity   
SSPCS.HPOL         6   Horizontal Sync Input Polarity 
SSPCS.VDET         5   Vertical Sync Signal Detect    
SSPCS.HDET         4   Horizontal Sync Signal Detect  
SSPCS.SOUT         3   Sync Output Select             
SSPCS.INSRTB       2   Hsync Insertion Bit            
SSPCS.FOUT         1   Internal Hsync Frequency Select
SSPCS.VSIN         0   Vsync Input Source             
VFH               0x000D     Vertical frequency high
VFH.VF12           4
VFH.VF11           3
VFH.VF10           2
VFH.VF9            1
VFH.VF8            0
VFL               0x000E     Vertical frequency low
VFL.VF7            7
VFL.VF6            6
VFL.VF5            5
VFL.VF4            4
VFL.VF3            3
VFL.VF2            2
VFL.VF1            1
VFL.VF0            0
LFH               0x000F     Line frequency high
LFH.HOVER          7
LFH.LF11           3
LFH.LF10           2
LFH.LF9            1
LFH.LF8            0
LFL               0x0010     Line frequency low
LFL.LF7            7
LFL.LF6            6
LFL.LF5            5
LFL.LF4            4
LFL.LF3            3
LFL.LF2            2
LFL.LF1            1
LFL.LF0            0
SSC               0x0011     Sync signal control
SSC.VSIE           7   Vsync Interrupt Enable
Unused12          0x0012     Unused
Unused13          0x0013     Unused
Unused14          0x0014     Unused
Unused15          0x0015     Unused
Unused16          0x0016     Unused
MAD               0x0017     MBUS address
MAD.MAD7           7
MAD.MAD6           6
MAD.MAD5           5
MAD.MAD4           4
MAD.MAD3           3
MAD.MAD2           2
MAD.MAD1           1
MFD               0x0018     MBUS frequency divider
MFD.FD4            4
MFD.FD3            3
MFD.FD2            2
MFD.FD1            1
MFD.FD0            0
MC                0x0019     MBUS control
MC.MEN             7   M-Bus Enable                
MC.MIEN            6   M-Bus Interrupt Enable      
MC.MSTA            5   Master/Slave Select         
MC.MTX             4   Transmit/Receive Mode Select
MC.TXAK            3   Acknowledge Enable          
MS                0x001A     MBUS status
MS.MCF             7   Data Transfer Complete
MS.MASS            6   Addressed as Slave    
MS.MBB             5   Bus Busy              
MS.MAL             4   Arbitration Lost      
MS.SRW             2   Slave R/W Select      
MS.MIF             1   M-Bus Interrupt       
MS.RXAK            0   Receive Acknowledge   
MD                0x001B     MBUS data
MD.MD7             7
MD.MD6             6
MD.MD5             5
MD.MD4             4
MD.MD3             3
MD.MD2             2
MD.MD1             1
MD.MD0             0
Unused1C          0x001C     Unused
RESERV001D        0x001D     RESERVED
HPW               0x001E     HSYNC period width
HPW.HPWR7          7
HPW.HPWR6          6
HPW.HPWR5          5
HPW.HPWR4          4
HPW.HPWR3          3
HPW.HPWR2          2
HPW.HPWR1          1
HPW.HPWR0          0
RESERV001F        0x001F     RESERVED
0PWM              0x0020     PWM Register 0 
0PWM.0PWM4         7
0PWM.0PWM3         6
0PWM.0PWM2         5
0PWM.0PWM1         4
0PWM.0PWM0         3
0PWM.0BRM2         2
0PWM.0BRM1         1
0PWM.0BRM0         0
1PWM              0x0021     PWM Register 1 
1PWM.1PWM4         7
1PWM.1PWM3         6
1PWM.1PWM2         5
1PWM.1PWM1         4
1PWM.1PWM0         3
1PWM.1BRM2         2
1PWM.1BRM1         1
1PWM.1BRM0         0
2PWM              0x0022     PWM Register 2 
2PWM.2PWM4         7
2PWM.2PWM3         6
2PWM.2PWM2         5
2PWM.2PWM1         4
2PWM.2PWM0         3
2PWM.2BRM2         2
2PWM.2BRM1         1
2PWM.2BRM0         0
3PWM              0x0023     PWM Register 3 
3PWM.3PWM4         7
3PWM.3PWM3         6
3PWM.3PWM2         5
3PWM.3PWM1         4
3PWM.3PWM0         3
3PWM.3BRM2         2
3PWM.3BRM1         1
3PWM.3BRM0         0
4PWM              0x0024     PWM Register 4 
4PWM.4PWM4         7
4PWM.4PWM3         6
4PWM.4PWM2         5
4PWM.4PWM1         4
4PWM.4PWM0         3
4PWM.4BRM2         2
4PWM.4BRM1         1
4PWM.4BRM0         0
5PWM              0x0025     PWM Register 5 
5PWM.5PWM4         7
5PWM.5PWM3         6
5PWM.5PWM2         5
5PWM.5PWM1         4
5PWM.5PWM0         3
5PWM.5BRM2         2
5PWM.5BRM1         1
5PWM.5BRM0         0
6PWM              0x0026     PWM Register 6 
6PWM.6PWM4         7
6PWM.6PWM3         6
6PWM.6PWM2         5
6PWM.6PWM1         4
6PWM.6PWM0         3
6PWM.6BRM2         2
6PWM.6BRM1         1
6PWM.6BRM0         0
7PWM              0x0027     PWM Register 7 
7PWM.7PWM4         7
7PWM.7PWM3         6
7PWM.7PWM2         5
7PWM.7PWM1         4
7PWM.7PWM0         3
7PWM.7BRM2         2
7PWM.7BRM1         1
7PWM.7BRM0         0
8PWM              0x0028     PWM Register 8 
8PWM.8PWM4         7
8PWM.8PWM3         6
8PWM.8PWM2         5
8PWM.8PWM1         4
8PWM.8PWM0         3
8PWM.8BRM2         2
8PWM.8BRM1         1
8PWM.8BRM0         0
9PWM              0x0029     PWM Register 9 
9PWM.9PWM4         7
9PWM.9PWM3         6
9PWM.9PWM2         5
9PWM.9PWM1         4
9PWM.9PWM0         3
9PWM.9BRM2         2
9PWM.9BRM1         1
9PWM.9BRM0         0
10PWM             0x002A     PWM Register 10
10PWM.10PWM4       7
10PWM.10PWM3       6
10PWM.10PWM2       5
10PWM.10PWM1       4
10PWM.10PWM0       3
10PWM.10BRM2       2
10PWM.10BRM1       1
10PWM.10BRM0       0
11PWM             0x002B     PWM Register 11
11PWM.11PWM4       7
11PWM.11PWM3       6
11PWM.11PWM2       5
11PWM.11PWM1       4
11PWM.11PWM0       3
11PWM.11BRM2       2
11PWM.11BRM1       1
11PWM.11BRM0       0
12PWM             0x002C     PWM Register 12
12PWM.12PWM4       7
12PWM.12PWM3       6
12PWM.12PWM2       5
12PWM.12PWM1       4
12PWM.12PWM0       3
12PWM.12BRM2       2
12PWM.12BRM1       1
12PWM.12BRM0       0
13PWM             0x002D     PWM Register 13
13PWM.13PWM4       7
13PWM.13PWM3       6
13PWM.13PWM2       5
13PWM.13PWM1       4
13PWM.13PWM0       3
13PWM.13BRM2       2
13PWM.13BRM1       1
13PWM.13BRM0       0
14PWM             0x002E     PWM Register 14
14PWM.14PWM4       7
14PWM.14PWM3       6
14PWM.14PWM2       5
14PWM.14PWM1       4
14PWM.14PWM0       3
14PWM.14BRM2       2
14PWM.14BRM1       1
14PWM.14BRM0       0
15PWM             0x002F     PWM Register 15
15PWM.15PWM4       7
15PWM.15PWM3       6
15PWM.15PWM2       5
15PWM.15PWM1       4
15PWM.15PWM0       3
15PWM.15BRM2       2
15PWM.15BRM1       1
15PWM.15BRM0       0
RESERV3FF0        0x3FF0     RESERVED
RESERV3FF1        0x3FF1     RESERVED
RESERV3FF2        0x3FF2     RESERVED
RESERV3FF3        0x3FF3     RESERVED


.68HC05BS8
; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC05BS8.pdf
; MC68HC05BS8Dnew.pdf

; RAM=228
; ROM=10K
; EPROM=10K
; EEPROM=512


; MEMORY MAP
area DATA FSR        0x0000:0x0040
area DATA RAM        0x0040:0x0140
area BSS  UNUSED     0x0140:0x0200
area DATA _EEPROM_   0x0200:0x0400
area BSS  UNUSED     0x0400:0x1600
area DATA BootROM    0x1600:0x1800
area DATA ROM0_EPR0  0x1800:0x3FE0
area DATA BOOT_VEC   0x3FE0:0x3FF0
area DATA USER_VEC   0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      External signal
interrupt SSP               0x3FF8      Sync Signal Processor
interrupt TIMER             0x3FF6      Programmable Timer
interrupt CTIMER            0x3FF4      Core Timer
interrupt M_BUS             0x3FF2      M-Bus Interface
interrupt KBI               0x3FF0      KEYBOARD


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED03              0x0003    UNUSED
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006    Port C data direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
C_EEPROM              0x0007    EEPROM control
C_EEPROM.EEOSC         4   EEPROM Charge Pump Oscillator Enable
C_EEPROM.EER1          3   EEPROM Erase Mode Select Bits 1
C_EEPROM.EER0          2   EEPROM Erase Mode Select Bits 0
C_EEPROM.EELAT         1   EEPROM Programming Latch Control
C_EEPROM.EEPGM         0   EEPROM Programming Power Enable
CTCSR                 0x0008    CTimer control and Status Register
CTCSR.CTOF             7   Timer Overflow
CTCSR.RTIF             6   Real Time Interrupt Flag
CTCSR.CTOFE            5   CTimer Overflow Interrupt Enable
CTCSR.RTIE             4   Real Time Interrupt Enable
CTCSR.RT1              1   Rate Select for COP watchdog and RTI 1
CTCSR.RT0              0   Rate Select for COP watchdog and RTI 0
CTCR                  0x0009    CTimer Counter Register
CTCR.CT7               7
CTCR.CT6               6
CTCR.CT5               5
CTCR.CT4               4
CTCR.CT3               3
CTCR.CT2               2
CTCR.CT1               1
CTCR.CT0               0
SSCSR                 0x000A    Sync signal control and status
SSCSR.VPOL             7   Vertical Sync Input Polarity
SSCSR.HPOL             6   Horizontal Sync Input Polarity
SSCSR.VDET             5   Vertical Sync Signal Detect
SSCSR.HDET             4   Horizontal Sync Signal Detect
SSCSR.SOUT             3   Sync Output Select
SSCSR.INSRT            2   Hsync Insertion
SSCSR.SIN1             1   Sync Input Source 1
SSCSR.SIN0             0   Sync Input Source 0
VFREG                 0x000B    Vfreg
VFREG.VF7              7
VFREG.VF6              6
VFREG.VF5              5
VFREG.VF4              4
VFREG.VF3              3
VFREG.VF2              2
VFREG.VF1              1
VFREG.VF0              0
LFH                   0x000C    Line frequency high
LFH.VF8                7
LFH.LF11               3
LFH.LF10               2
LFH.LF9                1
LFH.LF8                0
LFL                   0x000D    Line frequency low
LFL.LF7                7
LFL.LF6                6
LFL.LF5                5
LFL.LF4                4
LFL.LF3                3
LFL.LF2                2
LFL.LF1                1
LFL.LF0                0
ILC                   0x000E    Interrupt line counter
ILC.VSIE               7   Vsync Interrupt Enable
ILC.LC6                6   Line Count for Vsync Interrupt 6
ILC.LC5                5   Line Count for Vsync Interrupt 5
ILC.LC4                4   Line Count for Vsync Interrupt 4
ILC.LC3                3   Line Count for Vsync Interrupt 3
ILC.LC2                2   Line Count for Vsync Interrupt 2
ILC.LC1                1   Line Count for Vsync Interrupt 1
ILC.LC0                0   Line Count for Vsync Interrupt 0
SP                    0x000F    Sampling pulse
SP.SP6                 6
SP.SP5                 5
SP.SP4                 4
SP.SP3                 3
SP.SP2                 2
SP.SP1                 1
SP.SP0                 0
GPWM                  0x0010    General PWM
GPWM.ODE               7   Open Drain Enable
GPWM.CRE               6   Clear Reset Enable
GPWM.GPW5              5   GPW Data 5
GPWM.GPW4              4   GPW Data 4
GPWM.GPW3              3   GPW Data 3
GPWM.GPW2              2   GPW Data 2
GPWM.GPW1              1   GPW Data 1
GPWM.GPW0              0   GPW Data 0
RSPWM                 0x0011    Raster Positioning Pulse Width Modulator Register
RSPWM.RSP              7   Raster Polarity
RSPWM.RSPW6            6   RSPWM Data 6
RSPWM.RSPW5            5   RSPWM Data 5
RSPWM.RSPW4            4   RSPWM Data 4
RSPWM.RSPW3            3   RSPWM Data 3
RSPWM.RSPW2            2   RSPWM Data 2
RSPWM.RSPW1            1   RSPWM Data 1
RSPWM.RSPW0            0   RSPWM Data 0
TCR                   0x0012    Timer control
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.IEDG               1   Input Edge
TCR.OLVL               0   Output Level Voltage Latch
TSR                   0x0013    Timer status
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICH                   0x0014    Input capture high
ICH.IC15               7
ICH.IC14               6
ICH.IC13               5
ICH.IC12               4
ICH.IC11               3
ICH.IC10               2
ICH.IC9                1
ICH.IC8                0
ICL                   0x0015    Input capture low
ICL.IC7                7
ICL.IC6                6
ICL.IC5                5
ICL.IC4                4
ICL.IC3                3
ICL.IC2                2
ICL.IC1                1
ICL.IC0                0
OCH                   0x0016    Output compare high
OCH.OC15               7
OCH.OC14               6
OCH.OC13               5
OCH.OC12               4
OCH.OC11               3
OCH.OC10               2
OCH.OC9                1
OCH.OC8                0
OCL                   0x0017    Output compare low
OCL.OC7                7
OCL.OC6                6 
OCL.OC5                5 
OCL.OC4                4
OCL.OC3                3
OCL.OC2                2
OCL.OC1                1
OCL.OC0                0
CH                    0x0018    Counter high
CH.TC15                7
CH.TC14                6
CH.TC13                5
CH.TC12                4
CH.TC11                3
CH.TC10                2
CH.TC9                 1
CH.TC8                 0
CL                    0x0019    Counter low
CL.TC7                 7
CL.TC6                 6
CL.TC5                 5
CL.TC4                 4
CL.TC3                 3
CL.TC2                 2
CL.TC1                 1
CL.TC0                 0
ACH                   0x001A    Alternate counter high
ACH.AC15               7
ACH.AC14               6
ACH.AC13               5 
ACH.AC12               4
ACH.AC11               3
ACH.AC10               2
ACH.AC9                1
ACH.AC8                0
ACL                   0x001B    Alternate counter low
ACL.AC7                7
ACL.AC6                6
ACL.AC5                5
ACL.AC4                4
ACL.AC3                3
ACL.AC2                2
ACL.AC1                1
ACL.AC0                0
RESERV001C            0x001C    RESERVED
OPTION                0x001D    Option
OPTION.INTO            7
OPTION.COP             6
KI                    0x001E    Keyboard interrupt
KI.KBIC                6   Keyboard Interrupt Clear
KI.KBE5                5   Keyboard Interrupt Enable 5
KI.KBE4                4   Keyboard Interrupt Enable 4
KI.KBE3                3   Keyboard Interrupt Enable 3
KI.KBE2                2   Keyboard Interrupt Enable 2
KI.KBE1                1   Keyboard Interrupt Enable 1
KI.KBE0                0   Keyboard Interrupt Enable 0
UNUSED1F              0x001F    UNUSED
UNUSED20              0x0020    UNUSED
UNUSED21              0x0021    UNUSED
UNUSED22              0x0022    UNUSED
UNUSED23              0x0023    UNUSED
UNUSED24              0x0024    UNUSED
UNUSED25              0x0025    UNUSED
UNUSED26              0x0026    UNUSED
UNUSED27              0x0027    UNUSED
UNUSED28              0x0028    UNUSED
UNUSED29              0x0029    UNUSED
UNUSED2A              0x002A    UNUSED
UNUSED2B              0x002B    UNUSED
UNUSED2C              0x002C    UNUSED
UNUSED2D              0x002D    UNUSED
UNUSED2E              0x002E    UNUSED
UNUSED2F              0x002F    UNUSED
UNUSED30              0x0030    UNUSED
UNUSED31              0x0031    UNUSED
UNUSED32              0x0032    UNUSED
UNUSED33              0x0033    UNUSED
UNUSED34              0x0034    UNUSED
UNUSED35              0x0035    UNUSED
UNUSED36              0x0036    UNUSED
UNUSED37              0x0037    UNUSED
UNUSED38              0x0038    UNUSED
MADR                  0x0039    M-Bus address
MADR.MAD7              7
MADR.MAD6              6
MADR.MAD5              5
MADR.MAD4              4
MADR.MAD3              3
MADR.MAD2              2
MADR.MAD1              1
MFDR                  0x003A    M-Bus frequency divider
MFDR.FD4               4
MFDR.FD3               3
MFDR.FD2               2
MFDR.FD1               1
MFDR.FD0               0
MCR                   0x003B    M-Bus control
MCR.MEN                7   M-Bus Enable
MCR.MIEN               6   M-Bus Interrupt Enable
MCR.MSTA               5   Master/Slave Select
MCR.MTX                4   Transmit/Receive Mode Select
MCR.TXAK               3   Acknowledge Enable
MCR.SIFC               1   Software M-Bus Interrupt Flag Clear
MCR.SIIC               0   Software M-Bus Enable
MSR                   0x003C    M-Bus status
MSR.MCF                7   Data Transfer Complete
MSR.MASS               6   Addressed as Slave
MSR.MBB                5   Bus Busy
MSR.MAL                4   Arbitration Lost
MSR.SIF                3   Software Supported M-Bus Interrupt Flag
MSR.SRW                2   Slave R/W Select
MSR.MIF                1   M-Bus Interrupt
MSR.RXAK               0   Receive Acknowledge
MDR                   0x003D    M-Bus data
MDR.MD7                7
MDR.MD6                6
MDR.MD5                5
MDR.MD4                4
MDR.MD3                3
MDR.MD2                2
MDR.MD1                1
MDR.MD0                0
UNUSED3E              0x003E    UNUSED
UNUSED3F              0x003F    UNUSED
EEPROM                0x0200    EEPROM options
EEPROM.EEPRT           1   EEPROM Protect
EEPROM.LVR             0   Low Voltage Reset


.68HC05C4A
; HC05C4AGRS/D  http://
; HC05C4AGRS.pdf

; RAM=176
; ROM=4144
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area DATA ROM_1        0x0020:0x0050
area DATA RAM          0x0050:0x0100
area DATA ROM_2        0x0100:0x1100
area BSS  UNUSED       0x1100:0x1F00
area DATA ROM_S_CH     0x1F00:0x1FF0
area DATA USER_VEC     0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt TIMER             0x1FF8      Timer Input Capture
interrupt SCI               0x1FF6      Serial Communications Interrupt
interrupt SPI               0x1FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED07              0x0007     UNUSED
UNUSED08              0x0008     UNUSED
UNUSED09              0x0009     UNUSED
SPCR                  0x000A     SPI Control Register
SPCR.SPIE              7   Serial Peripheral Interrupt Enable
SPCR.SPE               6   Serial Peripheral System Enable
SPCR.MSTR              4   Master Mode Select
SPCR.CPOL              3   Clock Polarity
SPCR.CPHA              2   Clock Phase
SPCR.SPR1              1   SPI Clock Rate Selects 1
SPCR.SPR0              0   SPI Clock Rate Selects 0
SPSR                  0x000B     SPI Status Register
SPSR.SPIF              7   SPI Transfer Complete Flag
SPSR.WCOL              6   Write Collision
SPSR.MODF              4   Mode Fault
SPDR                  0x000C     SPI Data Register
SPDR.SPD7              7
SPDR.SPD6              6
SPDR.SPD5              5
SPDR.SPD4              4
SPDR.SPD3              3
SPDR.SPD2              2
SPDR.SPD1              1
SPDR.SPD0              0
BAUD                  0x000D     SCI Baud Rate Register
BAUD.SCP1              5   SCI Prescaler Select Bits 1
BAUD.SCP0              3   SCI Prescaler Select Bits 0
BAUD.SCR2              2   SCI Baud Rate Select Bits 2
BAUD.SCR1              1   SCI Baud Rate Select Bits 1
BAUD.SCR0              0   SCI Baud Rate Select Bits 0
SCCR1                 0x000E     SCI Control 1
SCCR1.R8               7   Bit 8 (Received)
SCCR1.T8               6   Bit 8 (Transmitted)
SCCR1.M                4   Character Length
SCCR1.WAKE             3   Wakeup Bit
SCCR2                 0x000F     SCI Control 2
SCCR2.TIE              7   Transmit Interrupt Enable
SCCR2.TCIE             6   Transmission Complete Interrupt Enable
SCCR2.RIE              5   Receive Interrupt Enable
SCCR2.ILIE             4   Idle Line Interrupt Enable
SCCR2.TE               3   Transmit Enable
SCCR2.RE               2   Receive Enable
SCCR2.RMU              1   Receiver Wakeup Enable
SCCR2.SBK              0   Send Break
SCSR                  0x0010     SCI Status Register
SCSR.TDRE              7   Transmit Data Register Empty
SCSR.TC                6   Transmission Complete
SCSR.RDRF              5   Receive Data Register Full
SCSR.IDLE              4   Receiver Idle
SCSR.OR                3   Receiver Overrun
SCSR.NF                2   Receiver Noise Flag
SCSR.FE                1   Receiver Framing Error
SCDAT                 0x0011     SCI Data Register
SCDAT.SCD7             7   Serial Data Bit 7
SCDAT.SCD6             6   Serial Data Bit 6
SCDAT.SCD5             5   Serial Data Bit 5
SCDAT.SCD4             4   Serial Data Bit 4
SCDAT.SCD3             3   Serial Data Bit 3
SCDAT.SCD2             2   Serial Data Bit 2
SCDAT.SCD1             1   Serial Data Bit 1
SCDAT.SCD0             0   Serial Data Bit 0
TCR                   0x0012     Timer Control Register
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.IEDGE              1   Input Edge
TCR.OLVL               0   Output Level
TSR                   0x0013     Timer Status Register
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICRH                  0x0014     Input Capture Register high
ICRL                  0x0015     Input Capture Register low
OCRH                  0x0016     Output Compare Register high
OCRL                  0x0017     Output Compare Register low
TCNTH                 0x0018     Timer Counter Register high
TCNTL                 0x0019     Timer Counter Register low
ALTCNTH               0x001A     Alternate Counter Register high
ALTCNTL               0x001B     Alternate Counter Register low
UNUSED1C              0x001C     UNUSED
UNUSED1D              0x001D     UNUSED
UNUSED1E              0x001E     UNUSED
RESERV001F            0x001F     RESERVED
COPR                  0x1FF0     COP Reset
COPR.COPC              0
RESERV1FF1            0x1FF1    RESERVED
RESERV1FF2            0x1FF2    RESERVED
RESERV1FF3            0x1FF3    RESERVED


.68HC05C8A
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05C8A&nodeId=01M98633
; MC68HC05C8A.pdf

; RAM=176
; ROM=8K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_P1      0x0020:0x0050
area DATA RAM         0x0050:0x0100
area DATA ROM_P2      0x0100:0x1F00
area DATA ROM_S_CH    0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt TIMER             0x1FF8      Timer Interrupt
interrupt SCI               0x1FF6      Serial Communications Interrupt
interrupt SPI               0x1FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001    Port B data
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
PORTC          0x0002    Port C data
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
PORTD          0x0003    Port D data
PORTD.PD7       7   Port D Data Bits 7
PORTD.PD5       5   Port D Data Bits 5
PORTD.PD4       4   Port D Data Bits 4
PORTD.PD3       3   Port D Data Bits 3
PORTD.PD2       2   Port D Data Bits 2
PORTD.PD1       1   Port D Data Bits 1
PORTD.PD0       0   Port D Data Bits 0
DDRA           0x0004    Port A data direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA1      0   Data Direction for Port A Bit 0
DDRB           0x0005    Port B data direction
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRC           0x0006    Port C data direction
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC7      6   Data Direction for Port C Bit 6
DDRC.DDRC7      5   Data Direction for Port C Bit 5
DDRC.DDRC7      4   Data Direction for Port C Bit 4
DDRC.DDRC7      3   Data Direction for Port C Bit 3
DDRC.DDRC7      2   Data Direction for Port C Bit 2
DDRC.DDRC7      1   Data Direction for Port C Bit 1
DDRC.DDRC7      0   Data Direction for Port C Bit 0
UNUSED0007     0x0007    UNUSED
UNUSED0008     0x0008    UNUSED
UNUSED0009     0x0009    UNUSED
SPCR           0x000A    SPI Control
SPCR.SPIE       7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE        6   Serial Peripheral System Enable Bit
SPCR.MSTR       4   Master Mode Select Bit
SPCR.CPOL       3   Clock Polarity Bit
SPCR.CPHA       2   Clock Phase Bit
SPCR.SPR1       1   SPI Clock Rate Select Bits 1
SPCR.SPR0       0   SPI Clock Rate Select Bits 0
SPSR           0x000B    SPI Status
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Flag
SPDR           0x000C    SPI Data
SPDR.SPD7       7
SPDR.SPD6       6
SPDR.SPD5       5
SPDR.SPD4       4
SPDR.SPD3       3
SPDR.SPD2       2
SPDR.SPD1       1
SPDR.SPD0       0
BAUD           0x000D    SCI Baud Rate
BAUD.SCP1       5   SCI Prescaler Select Bits 1
BAUD.SCP0       4   SCI Prescaler Select Bits 0
BAUD.SCR2       2   SCI Baud Rate Select Bits 2
BAUD.SCR1       1   SCI Baud Rate Select Bits 1
BAUD.SCR0       0   SCI Baud Rate Select Bits 0
SCCR1          0x000E    SCI Control 1
SCCR1.R8        7   Bit 8 (Received)
SCCR1.T8        6   Bit 8 (Transmitted)
SCCR1.M         4   Character Length Bit
SCCR1.WAKE      3   Wakeup Bit
SCCR2          0x000F    SCI Control 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmission Complete Interrupt Enable Bit
SCCR2.RIE       5   Receive Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmit Enable Bit
SCCR2.RE        2   Receive Enable Bit
SCCR2.RMU       1   Receiver Wakeup Enable Bit
SCCR2.SBK       0   Send Break Bit
SCSR           0x0010    SCI Status
SCSR.TDRE       7   Transmit Data Register Empty Bit
SCSR.TC         6   Transmission Complete Bit
SCSR.RDRF       5   Receive Data Register Full Bit
SCSR.IDLE       4   Receiver Idle Bit
SCSR.OR         3   Receiver Overrun Bit
SCSR.NF         2   Receiver Noise Flag
SCSR.FE         1   Receiver Framing Error Flag
SCDAT          0x0011     SCI Data
SCDAT.SCD7      7   Serial Data Bit 7
SCDAT.SCD6      6   Serial Data Bit 6
SCDAT.SCD5      5   Serial Data Bit 5
SCDAT.SCD4      4   Serial Data Bit 4
SCDAT.SCD3      3   Serial Data Bit 3
SCDAT.SCD2      2   Serial Data Bit 2
SCDAT.SCD1      1   Serial Data Bit 1
SCDAT.SCD0      0   Serial Data Bit 0
TCR            0x0012    Timer Control
TCR.ICIE        7   Input Capture Interrupt Enable Bit
TCR.OCIE        6   Output Compare Interrupt Enable Bit
TCR.TOIE        5   Timer Overflow Interrupt Enable Bit
TCR.IEDGE       1   Input Edge Bit
TCR.OLVL1       0   Output Level Bit
TSR            0x0013    Timer Status
TSR.ICF         7   Input Capture Flag
TSR.OCF         6   Output Compare Flag
TSR.TOF         5   Timer Overflow Flag
ICH            0x0014    Input capture
ICL            0x0015    Input capture
OCH            0x0016    Output compare
OCL            0x0017    Output compare
TCNTH          0x0018    Timer counter
TCNTL          0x0019    Timer counter
ALTCNTH        0x001A    Alternate counter
ALTCNTL        0x001B    Alternate counter
UNUSED001C     0x001C    UNUSED
UNUSED001D     0x001D    UNUSED
UNUSED001E     0x001E    UNUSED
RESERV001F     0x001F    Reserved
COP            0x1FF0    COP
COP.COPR        0
UNUSED07F1     0x07F1   UNUSED
UNUSED07F2     0x07F2   UNUSED
UNUSED07F3     0x07F3   UNUSED


.68HC05C9A
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05C9A&nodeId=01M98633 
; HC05C9AGRS.pdf

; RAM=352
; ROM=16K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area DATA ROM0_RAM0    0x0020:0x0050
area DATA RAM          0x0050:0x0100
area DATA ROM1_RAM1    0x0100:0x0180
area DATA ROM          0x0180:0x3F00
area DATA ROM_S_CH     0x3F00:0x3F00
area DATA USER_VEC     0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Reset  
interrupt SWI               0x3FFC      Software Interrupt               
interrupt IRQ               0x3FFA      IRQ/IRQ2        
interrupt Timer             0x3FF8      Timer Interrupt
interrupt SCI               0x3FF6      Serial Communications Interrupt
interrupt SPI               0x3FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001     Port B data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002    Port C data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003    Port D data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004   Port A Data Direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005   Port B Data Direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006   Port C Data Direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007   Port D Data Direction
DDRD.DDRD7       7   Data Direction for Port D Bit 7
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
RESERV0008      0x0008   RESERVED
RESERV0009      0x0009   RESERVED
SPCR            0x000A   SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable
SPCR.DWOM        5   Port D Wire-OR Mode Option
SPCR.MSTR        4   Master Mode Select
SPCR.CPOL        3   Clock Polarity
SPCR.CPHA        2   Clock Phase
SPCR.SPR1        1   SPI Clock Rate Selects 1
SPCR.SPR0        0   SPI Clock Rate Selects 0
SPSR            0x000B   SPI Status Register
SPSR.SPIF        7   SPI Transfer Complete Flag
SPSR.WCOL        6   Write Collision
SPSR.MODF        4   Mode Fault
SPDR            0x000C   SPI Data Register
SPDR.SPD7        7
SPDR.SPD6        6
SPDR.SPD5        5
SPDR.SPD4        4
SPDR.SPD3        3
SPDR.SPD2        2
SPDR.SPD1        1
SPDR.SPD0        0
BAUD            0x000D   SCI Baud Rate Register
BAUD.SCP1        5   SCI Prescaler Select Bits 1
BAUD.SCP0        4   SCI Prescaler Select Bits 0
BAUD.SCR2        2   SCR0-SCI Baud Rate Select Bits 2
BAUD.SCR1        1   SCR0-SCI Baud Rate Select Bits 1
BAUD.SCR0        0   SCR0-SCI Baud Rate Select Bits 0
SCCR1           0x000E   SCI Control Register 1
SCCR1.R8         7   Bit 8 (Received)
SCCR1.T8         6   Bit 8 (Transmitted)
SCCR1.M          4   Character Length
SCCR1.WAKE       3   Wakeup Method
SCCR2           0x000F   SCI Control Register 2
SCCR2.TIE        7   Transmit Interrupt Enable
SCCR2.TCIE       6   Transmission Complete Interrupt Enable
SCCR2.RIE        5   Receiver Interrupt Enable
SCCR2.ILIE       4   Idle Line Interrupt Enable
SCCR2.TE         3   Transmitter Enable
SCCR2.RE         2   Receiver Enable
SCCR2.RWU        1   Receiver Wakeup Enable
SCCR2.SBK        0   Send Break
SCSR            0x0010   SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty
SCSR.TC          6   Transmission Complete
SCSR.RDRF        5   Receive Data Register Full
SCSR.IDLE        4   Receiver Idle
SCSR.OR          3   Receiver Overrun
SCSR.NF          2   Receiver Noise Flag
SCSR.FE          1   Receiver Framing Error
SCDR            0x0011   SCI Data Register
SCDR.SCD7        7   Serial Data Bit 7
SCDR.SCD6        6   Serial Data Bit 6
SCDR.SCD5        5   Serial Data Bit 5
SCDR.SCD4        4   Serial Data Bit 4
SCDR.SCD3        3   Serial Data Bit 3
SCDR.SCD2        2   Serial Data Bit 2
SCDR.SCD1        1   Serial Data Bit 1
SCDR.SCD0        0   Serial Data Bit 0
TCR             0x0012   Timer  Control Register
TCR.ICIE         7   Input Capture Interrupt Enable
TCR.OCIE         6   Output Compare Interrupt Enable
TCR.TOIE         5   Timer Overflow Interrupt Enable
TCR.IEDG         1   Input Edge
TCR.OLVL         0   Output Level
TSR             0x0013   Timer  Status Register
TSR.ICF          7   Input Capture Flag
TSR.OCF          6   Output Compare Flag
TSR.TOF          5   Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TRH             0x0018   Timer Counter Register High
TRL             0x0019   Timer Counter Register Low
ATRH            0x001A   Alternate  Counter Register High
ATRL            0x001B   Alternate  Counter Register Low
UNUSED001C      0x001C   UNUSED
COPRST          0x001D   COP Reset Register
COPCR           0x001E   COP Control Register
COPCR.COPF       4   Computer Operating Properly Flag
COPCR.CME        3   Clock Monitor Enable
COPCR.COPE       2   COP Enable
COPCR.CM1        1   COP Mode Bit 1
COPCR.CM0        0   COP Mode Bit 0
RESERV001F      0x001F   RESERVED
RESERV03F0      0x03F0   RESERVED
RESERV03F1      0x03F1   RESERVED
RESERV03F2      0x03F2   RESERVED
RESERV03F3      0x03F3   RESERVED


.68HC05CJ4
; http://
; HC05CJ4GRS.pdf

; RAM=256
; ROM=4K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA RAM         0x0020:0x0100
area BSS  UNUSED      0x0100:0x1000
area DATA ROM_MASK    0x1000:0x1F00
area DATA ROM_S_T     0x1F00:0x1FE0
area BSS  RESERVED    0x1FE0:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      Software Interrupt      
interrupt IRQ               0x1FFA      External Interrupt
interrupt Timer1            0x1FF8      Timer_In_Out
interrupt SCI               0x1FF6      Serial Communications Interrupt
interrupt SPI               0x1FF4      Serial Peripheral Interrupt
interrupt ICC               0x1FF2         
interrupt Timer2            0x1FF0      Timer2_In_Out


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004   Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005   Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006   Port C Data Direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED07              0x0007   UNUSED
T2CSR                 0x0008   TIMER STATUS AND CONTROL
T2CSR.TOF              7   Timer Over Flow
T2CSR.RTIF             6   Real Time Interrupt Flag
T2CSR.TOFE             5   Timer Over Flow Enable
T2CSR.RTIE             4   Real Time Interrupt Enable
T2CSR.IRQS             3   IRQ Select
T2CSR.COPE             2   COP Enable
T2CSR.RT1              1   Real Time Interrupt Rate Select 1
T2CSR.RT0              0   Real Time Interrupt Rate Select 0
T2CR                  0x0009   TIMER COUNTER REGISTER
SPCR                  0x000A   SPI CONTROL REGISTER
SPCR.SPIE              7   SPI Interrupt Enable
SPCR.SPE               6   SPI System Enable
SPCR.DOD               5   Direction Of Data
SPCR.MSTR              4   Master/Slave Mode Select
SPCR.CPOL              3   Clock Polarity
SPCR.CPHA              2   Clock Phase
SPCR.SPR1              1   SPI Clock (SCK1) Rate Select Bits 1
SPCR.SPR0              0   SPI Clock (SCK1) Rate Select Bits 0
SPSR                  0x000B   SPI STATUS REGISTER
SPSR.SPIF              7   SPI Interrupt Request
SPSR.WCOL              6   Write Collision Status Flag
SPSR.MODF              5   SPI Mode Error Interrupt Status Flag
SPDR                  0x000C   SPI DATA REGISTER
SPDR.SPD7              7
SPDR.SPD6              6
SPDR.SPD5              5
SPDR.SPD4              4
SPDR.SPD3              3
SPDR.SPD2              2
SPDR.SPD1              1
SPDR.SPD0              0
BAUD                  0x000D   SCI BAUD RATE REGISTER
BAUD.SCP1              5   SCI Prescaler Select Bits 1
BAUD.SCP0              4   SCI Prescaler Select Bits 0
BAUD.SCR2              2   SCI Baud Rate Select Bits 2
BAUD.SCR1              1   SCI Baud Rate Select Bits 1
BAUD.SCR0              0   SCI Baud Rate Select Bits 0
SCCR1                 0x000E   SCI CONTROL REGISTER 1
SCCR1.R8               7   Receiver Bit 8
SCCR1.T8               6   Transmit Bit 8
SCCR1.M                4   Mode (select character format)
SCCR1.WAKE             3   Wake Up by Address Mark/Idle
SCCR2                 0x000F   SCI CONTROL REGISTER 2
SCCR2.TIE              7   Transmit Interrupt Enable
SCCR2.TCIE             6   Transmit Complete Interrupt Enable
SCCR2.RIE              5   Receiver Interrupt Enable
SCCR2.ILIE             4   Idle Line Interrupt Enable
SCCR2.TE               3   Transmitter Enable
SCCR2.RE               2   Receiver Enable
SCCR2.RWU              1   Receiver Wake-up Control
SCCR2.SBK              0   Send Break
SCSR                  0x0010   SCI STATUS REGISTER
SCSR.TDRE              7   Transmit Data Register Empty Flag
SCSR.TC                6   Transmit Complete Flag
SCSR.RDRF              5   Receive Data Register Full Flag
SCSR.IDLE              4   Idle Line Detected Flag
SCSR.OR                3   Over-Run Error Flag
SCSR.NF                2   Noise Error Flag
SCSR.FE                1   Framing Error Flag
SCDR                  0x0011   SCI DATA REGISTER
SCDR.SCD7              7   Serial Data Bit 7
SCDR.SCD6              6   Serial Data Bit 6
SCDR.SCD5              5   Serial Data Bit 5
SCDR.SCD4              4   Serial Data Bit 4
SCDR.SCD3              3   Serial Data Bit 3
SCDR.SCD2              2   Serial Data Bit 2
SCDR.SCD1              1   Serial Data Bit 1
SCDR.SCD0              0   Serial Data Bit 0
T1CR                  0x0012   Timer  control
T1CR.ICIE              7   Input Capture Interrupt Enable
T1CR.OCIE              6   Output Compare Interrupt Enable
T1CR.TOIE              5   Timer Overflow Interrupt Enable
T1CR.IEDG              1   Input Edge
T1CR.OLVL              0   Output Level
T1SR                  0x0013   Timer  status
T1SR.ICF               7   Input Capture Flag
T1SR.OCF               6   Output Compare Flag
T1SR.TOF               5   Timer Overflow Flag
ICRH                  0x0014   Input capture MSB
ICRH.ICRH7             7
ICRH.ICRH6             6 
ICRH.ICRH5             5
ICRH.ICRH4             4
ICRH.ICRH3             3
ICRH.ICRH2             2
ICRH.ICRH1             1
ICRH.ICRH0             0
ICRL                  0x0015   Input capture  LSB
ICRL.ICRL7             7
ICRL.ICRL6             6
ICRL.ICRL5             5
ICRL.ICRL4             4
ICRL.ICRL3             3
ICRL.ICRL2             2
ICRL.ICRL1             1
ICRL.ICRL0             0
OCRH                  0x0016   Output compare MSB
OCRH.OCRH7             7
OCRH.OCRH6             6
OCRH.OCRH5             5
OCRH.OCRH4             4
OCRH.OCRH3             3
OCRH.OCRH2             2
OCRH.OCRH1             1
OCRH.OCRH0             0
OCRL                  0x0017   Output compare LSB
OCRL.OCRL7             7
OCRL.OCRL6             6
OCRL.OCRL5             5
OCRL.OCRL4             4
OCRL.OCRL3             3
OCRL.OCRL2             2
OCRL.OCRL1             1
OCRL.OCRL0             0
TRH                   0x0018   Timer  MSB
TRH.TMRH7              7
TRH.TMRH6              6
TRH.TMRH5              5
TRH.TMRH4              4
TRH.TMRH3              3
TRH.TMRH2              2
TRH.TMRH1              1
TRH.TMRH0              0
TRL                   0x0019   Timer  LSB
TRL.TMRL7              7                       
TRL.TMRL6              6
TRL.TMRL5              5
TRL.TMRL4              4
TRL.TMRL3              3
TRL.TMRL2              2
TRL.TMRL1              1
TRL.TMRL0              0
ATRH                  0x001A   Alternate  Counter MSB
ATRH.ACRH7             7
ATRH.ACRH6             6
ATRH.ACRH5             5
ATRH.ACRH4             4
ATRH.ACRH3             3
ATRH.ACRH2             2
ATRH.ACRH1             1
ATRH.ACRH0             0
ATRL                  0x001B   Alternate  Counter LSB
ATRL.ACRL7             7                                
ATRL.ACRL6             6
ATRL.ACRL5             5
ATRL.ACRL4             4
ATRL.ACRL3             3
ATRL.ACRL2             2
ATRL.ACRL1             1
ATRL.ACRL0             0
MBADR                 0x001C   MBUS ADD AND DATA REGISTER
MBADR.ADR7             7
MBADR.ADR6             6
MBADR.ADR5             5
MBADR.ADR4             4
MBADR.ADR3             3
MBADR.ADR2             2
MBADR.ADR1             1
MBADR.ADR0             0
MBCR                  0x001D   MBUS CONTROL REGISTER
MBCR.SMIE              7   Slave M-Bus Interrupt Enable
MBCR.SME               6   Slave M-Bus Enable
MBCR.T_R               5   Transmit/Receive
MBCR.NOACK             4   No Acknowledge
MBCR.CLKR              0   Clock Release
MBSR                  0x001E   MBUS STATUS REGISTER
MBSR.SMF               7   Slave M-Bus Flag
MBSR.STDF              6   Start Detect Flag
MBSR.MACK              5   Master Acknowledge
TEST                  0x001F   TEST


.68HC05CL4
; HC05CL4GRS/H  http://
; HC05CL4GRS.pdf

; RAM=1K
; ROM=6656
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR               0x0000:0x0020
area DATA LCD_RAM           0x0020:0x0050
area DATA RAM_1             0x0050:0x00C0
area DATA Stack             0x00C0:0x0100
area DATA RAM_2             0x0100:0x0450
area BSS  UNUSED            0x0450:0x0600
area DATA ROM_S_CH          0x0600:0x0800
area DATA ROM               0x0800:0x1FE0
area DATA Self_Check        0x1FE0:0x1FF0
area DATA USER_VEC          0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET	0x1FFE       Reset
interrupt SWI 		0x1FFC       Software
interrupt IRQ_KBI 	0x1FFA       External Interrupt / Key board interrupt
interrupt LVI 		0x1FF8       Low Voltage
interrupt RDI 		0x1FF6       Ring Detect
interrupt CDI 		0x1FF4       Carrier Detect
interrupt CTIMER	0x1FF2       Core Timer
interrupt TIMER 	0x1FF0       Timer


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
CFGC                  0x0006     Port C Configuration
CFGC.CFGC7             7
CFGC.CFGC6             6
CFGC.CFGC5             5
CFGC.CFGC4             4
CFGC.CFGC3             3
CFGC.CFGC2             2
CFGC.CFGC1             1
CFGC.CFGC0             0
CFGD                  0x0007     Port D Configuration
CFGD.CFGD7             7
CFGD.CFGD6             6
CFGD.CFGD5             5
CFGD.CFGD4             4
CFGD.CFGD3             3
CFGD.CFGD2             2
CFGD.CFGD1             1
CFGD.CFGD0             0
CTCSR                 0x0008     Core Timer Control
CTCSR.CTOF             7   Core Timer Overflow Flag
CTCSR.RTIF             6   Real Time Interrupt Flag
CTCSR.CTOFE            5   Core Timer Overflow Enable
CTCSR.RTIE             4   Real Time Interrupt Enable
CTCSR.RT1              1   Real Time Interrupt Select Bits 1
CTCSR.RT0              0   Real Time Interrupt Select Bits 0
CTR                   0x0009     Core Timer Register
CTR.CT7                7
CTR.CT6                6
CTR.CT5                5
CTR.CT4                4
CTR.CT3                3
CTR.CT2                2
CTR.CT1                1
CTR.CT0                0
LCDCTR                0x000A     LCD Control
LCDCTR.CC3             7   Contrast Control 3
LCDCTR.CC2             6   Contrast Control 2
LCDCTR.CC1             5   Contrast Control 1
LCDCTR.MX4             3
LCDCTR.FC              2
LCDCTR.LC              1
LCDCTR.DISON           0   Display On
RESERV000B            0x000B     RESERVED
CLCSR1                0x000C     CLRID Control Status1
CLCSR1.RDIF            7   Ring Detect Interrupt Flag
CLCSR1.RDIE            6   Ring Detect Interrupt Enable
CLCSR1.CDIF            5   Carrier Detect Interrupt Flag
CLCSR1.CDIE            4   Carrier Detect Interrupt Enable
CLCSR1.RDO             1   Ring Detect Override
CLCSR1.CDO             0   Carrier Detect Override
CLCSR2                0x000D     CLRID Control Status2
CLCSR2.CDPW            6   Ring Detect Power Up
CLCSR2.RDPW            5   Carrier Detect Power Up
CLCSR2.CIDSD           2   Caller ID Serial Data
CLCSR2.RD              1   Ring Detect
CLCSR2.CD              0   Carrier Detect
CLCSR3                0x000E     CLRID Control Status3
CLCSR3.SDSL            7   Serial Data Select
CLCSR3.RDEDG           3
CLCSR3.CDEDG           2
CLCSR3.RDOE            1   Ring Detect Override Enable
CLCSR3.CDOE            0   Carrier Detect Override Enable
ISCR                  0x000F     IRQ Status_Control
ISCR.IRQM              7   IRQ Enable Mask
ISCR.IRQS              6   IRQ Sensitivity
ISCR.EDGE              5   IRQ Active Edge Select
ISCR.REQ               3   IRQ Interrupt Request
ISCR.ACK               1   IRQ Interrupt Request Acknowledge
LVSCR                 0x0010     LVI Control
LVSCR.LVIS             2   Low Voltage Interrupt Status
LVSCR.LVIF             1   Low Voltage Reset Flag
LVSCR.LVIE             0   Low Voltage Reset Enable
KBIR                  0x0011     Keyboard Interrupt
KBIR.KBIE7             7   Keyboard Interrupt Enables 7
KBIR.KBIE6             6   Keyboard Interrupt Enables 6
KBIR.KBIE5             5   Keyboard Interrupt Enables 5
KBIR.KBIE4             4   Keyboard Interrupt Enables 4
KBIR.KEDGE             2   Keyboard Interrupt Edge
KBIR.KBIF              1   Keyboard Interrupt Flag
KBIR.KBIC              0   Keyboard Interrupt Clear
TCR                   0x0012     Timer Control
TCR.ICIE               7   input capture interrupt enable
TCR.OCIE               6   output compare interrupt enable
TCR.TOIE               5   timer overflow interrupt enable
TCR.IEDG               1   input edge
TCR.OLVL               0   value of the output level
TSR                   0x0013     Timer Status
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICH                   0x0014     Input Capture H
ICH.IC15               7
ICH.IC14               6
ICH.IC13               5
ICH.IC12               4
ICH.IC11               3
ICH.IC10               2
ICH.IC9                1
ICH.IC8                0
ICL                   0x0015     Input Capture L
ICL.IC7                7
ICL.IC6                6
ICL.IC5                5
ICL.IC4                4
ICL.IC3                3
ICL.IC2                2
ICL.IC1                1
ICL.IC0                0
OCH                   0x0016     Output Compare H
OCH.OC15               7
OCH.OC14               6
OCH.OC13               5
OCH.OC12               4
OCH.OC11               3
OCH.OC10               2
OCH.OC9                1
OCH.OC8                0
OCL                   0x0017     Output Compare L
OCL.OC7                7
OCL.OC6                6
OCL.OC5                5
OCL.OC4                4
OCL.OC3                3
OCL.OC2                2
OCL.OC1                1
OCL.OC0                0
TCH                   0x0018     Timer Counter H
TCH.TC15               7
TCH.TC14               6
TCH.TC13               5
TCH.TC12               4
TCH.TC11               3
TCH.TC10               2
TCH.TC9                1
TCH.TC8                0
TCL                   0x0019     Timer Counter L
TCL.TC7                7
TCL.TC6                6
TCL.TC5                5
TCL.TC4                4
TCL.TC3                3
TCL.TC2                2
TCL.TC1                1
TCL.TC0                0
ACH                   0x001A     Alternate Counter H
ACH.AC15               7
ACH.AC14               6
ACH.AC13               5
ACH.AC12               4
ACH.AC11               3
ACH.AC10               2
ACH.AC9                1
ACH.AC8                0
ACL                   0x001B     Alternate Counter L
ACL.AC7                7
ACL.AC6                6
ACL.AC5                5
ACL.AC4                4
ACL.AC3                3
ACL.AC2                2
ACL.AC1                1
ACL.AC0                0
RESERV001C            0x001C     RESERVED
RESERV001D            0x001D     RESERVED
RESERV001E            0x001E     RESERVED
RESERV001F            0x001F     RESERVED


.68HC05CT4
; HC05CT4GRS/D  http://
; HC05CT4GRS.pdf

; RAM=256
; ROM=5120
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR               0x0000:0x0023
area BSS  RESERVED          0x0023:0x0030
area DATA RAM               0x0030:0x0130
area BSS  UNUSED            0x0130:0x0B00
area DATA ROM               0x0B00:0x1F00
area DATA Self_Check_ROM    0x1F00:0x1FF0
area DATA USER_VEC          0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET 	0x1FFE       Reset 
interrupt SWI 		0x1FFC       Software 
interrupt CMP3_IRQ 	0x1FFA       VCMP3, External Interrupts 
interrupt TIMER 	0x1FF8       16-bit Timer Interrupts 
interrupt SSI 		0x1FF6       SSI Interrupt 
interrupt TIMER_RTI 	0x1FF4       Core Timer Interrupts 


; INPUT/ OUTPUT PORTS
PORTA           0x0000   Port A Data Register
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5	 5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001   Port B Data Register
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002   Port C Data Register
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003   Port D Data Register
PORTD.PD6        6   Port D Data Bits 6
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004   Port A Data Direction Register
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005   Port B Data Direction Register
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006   Port C Data Direction Register
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007   Port D Data Direction Register
DDRD.DDRD6       6   Data Direction for Port D Bit 6
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
TCST            0x0008   Timer Control and Status Register
TCST.CTOF        7   Core Timer Overflow
TCST.RTIF        6   Real Time Interrupt Flag
TCST.TOFE        5   Timer Overflow Enable
TCST.RTIE        4   Real-Time Interrupt Enable
TCST.TOFC        3   Timer Overflow Flag Clear
TCST.RTFC        2   Real-Time Interrupt Flag Clear
TCST.RT1         1   Real-Time Interrupt Rate Select 1
TCST.RT0         0   Real-Time Interrupt Rate Select 0
CTCR            0x0009   Core Counter Register
CTCR.D7          7
CTCR.D6          6
CTCR.D5          5
CTCR.D4          4
CTCR.D3          3
CTCR.D2          2
CTCR.D1          1
CTCR.D0          0
PLLCR           0x000A   Dual PLL Control Register
PLLCR.TLOCK      6   Transmit Lock Detect
PLLCR.RLOCK      5   Receive Lock Detect
PLLCR.REFON      4   Reference Counter Enable
PLLCR.TXON       3   TX Counter Enable
PLLCR.RXON       2   RX Counter Enable
PLLCR.PLS1       1   PLL Reference Counter Select 1
PLLCR.PLS0       0   PLL Reference Counter Select 0
PLLRCH          0x000B   PLL Reference Counter - MSB
PLLRCH.PLLRC11   3
PLLRCH.PLLRC10   2
PLLRCH.PLLRC9    1
PLLRCH.PLLRC8    0
PLLRCL          0x000C   PLL Reference Counter - LSB
PLLRCL.PLLRC7    7
PLLRCL.PLLRC6    6
PLLRCL.PLLRC5    5
PLLRCL.PLLRC4    4
PLLRCL.PLLRC3    3
PLLRCL.PLLRC2    2
PLLRCL.PLLRC1    1
PLLRCL.PLLRC0    0
PLLTXH           0x000D   PLL Transmit Counter - MSB
PLLTXH.PLLTX15   7
PLLTXH.PLLTX14   6
PLLTXH.PLLTX13   5
PLLTXH.PLLTX12   4
PLLTXH.PLLTX11   3
PLLTXH.PLLTX10   2
PLLTXH.PLLTX9    1
PLLTXH.PLLTX8    0
PLLTXL          0x000E   PLL Transmit Counter - LSB
PLLTXL.PLLTX7    7
PLLTXL.PLLTX6    6
PLLTXL.PLLTX5    5
PLLTXL.PLLTX4    4
PLLTXL.PLLTX3    3
PLLTXL.PLLTX2    2
PLLTXL.PLLTX1    1
PLLTXL.PLLTX0    0
PLLRXH          0x000F   PLL Receive Counter - MSB
PLLRXH.PLLRX15   7
PLLRXH.PLLRX14   6
PLLRXH.PLLRX13   5
PLLRXH.PLLRX12   4
PLLRXH.PLLRX11   3
PLLRXH.PLLRX10   2
PLLRXH.PLLRX9    1
PLLRXH.PLLRX8    0
PLLRXL          0x0010   PLL Receive Counter - LSB
PLLRXL.PLLRX7    7
PLLRXL.PLLRX6    6
PLLRXL.PLLRX5    5
PLLRXL.PLLRX4    4
PLLRXL.PLLRX3    3
PLLRXL.PLLRX2    2
PLLRXL.PLLRX1    1
PLLRXL.PLLRX0    0
Reserv0011      0x0011   Reserved
TCR             0x0012   Timer Control Register
TCR.ICIE         7   Input Capture Interrupt Enable
TCR.OCIE         6   Output Compare Interrupt Enable
TCR.TOIE         5   Timer Overflow Interrupt Enable
TCR.TON          2   Timer On
TCR.IEDGE        1   Input Edge
TCR.OLVL         0   Output Level
TSR             0x0013   Timer Status Register
TSR.ICF          7   Input Capture Flag
TSR.OCF          6   Output Compare Flag
TICM            0x0014   Timer Input Capture - MSB
TICM.TICM7       7
TICM.TICM6       6
TICM.TICM5       5
TICM.TICM4       4
TICM.TICM3       3
TICM.TICM2       2
TICM.TICM1       1
TICM.TICM0       0
TICL            0x0015   Timer Input Capture - LSB
TICL.TICL7       7
TICL.TICL6       6
TICL.TICL5       5
TICL.TICL4       4
TICL.TICL3       3
TICL.TICL2       2
TICL.TICL1       1
TICL.TICL0       0
TOCM            0x0016   Timer Output Compare - MSB
TOCM.TOCM7       7
TOCM.TOCM6       6
TOCM.TOCM5       5
TOCM.TOCM4       4
TOCM.TOCM3       3
TOCM.TOCM2       2
TOCM.TOCM1       1
TOCM.TOCM0       0
TOCL            0x0017   TImer Output Compare - LSB
TOCL.TOCL7       7
TOCL.TOCL6       6
TOCL.TOCL5       5
TOCL.TOCL4       4
TOCL.TOCL3       3
TOCL.TOCL2       2
TOCL.TOCL1       1
TOCL.TOCL0       0
TCM             0x0018   Timer Counter - MSB
TCM.TCM7         7
TCM.TCM6         6
TCM.TCM5         5
TCM.TCM4         4
TCM.TCM3         3
TCM.TCM2         2
TCM.TCM1         1
TCM.TCM0         0
TCL             0x0019   Timer Counter - LSB
TCL.TCL7         7
TCL.TCL6         6
TCL.TCL5         5
TCL.TCL4         4
TCL.TCL3         3
TCL.TCL2         2
TCL.TCL1         1
TCL.TCL0         0
TACM            0x001A   Timer Alternate Counter - MSB
TACM.TACM7       7
TACM.TACM6       6
TACM.TACM5       5
TACM.TACM4       4
TACM.TACM3       3
TACM.TACM2       2
TACM.TACM1       1
TACM.TACM0       0
TACL            0x001B   TImer Alternate Counter - LSB
TACL.TACL7       7
TACL.TACL6       6
TACL.TACL5       5
TACL.TACL4       4
TACL.TACL3       3
TACL.TACL2       2
TACL.TACL1       1
TACL.TACL0       0
SSR             0x001C   SSI Status Register
SSR.SF           7   SSI Flag
SSR.DCOL         6   Data Collision
SDR             0x001D   SSI Data Register
SDR.SDR7         7
SDR.SDR6         6
SDR.SDR5         5
SDR.SDR4         4
SDR.SDR3         3
SDR.SDR2         2
SDR.SDR1         1
SDR.SDR0         0
SCR             0x001E   SSI Control Register
SCR.SIE          7   SSI Interrupt Enable
SCR.SE           6   SSI Enable
SCR.LSBF         5   Least Significant Bit (LSB)First
SCR.MSTR         4   Master Mode
SCR.CPOL         3   Clock Polarity
SCR.T_R          2   Transmit/Receive
SCR.SR1          1   SSI Rate 1
SCR.SR0          0   SSI Rate 0
Reserv001F      0x001F   Reserved
PWMDR           0x0020   PWM Data Register
PWMDR.PDR5       5
PWMDR.PDR4       4
PWMDR.PDR3       3
PWMDR.PDR2       2
PWMDR.PDR1       1
PWMDR.PDR0       0
MISCR           0x0021   Miscellaneous Control Register
MISCR.SPEED      3   CPU Speed Select
MISCR.COE        2   16-Bit Timer Output Compare Enable
MISCR.PWME       1   PWM Enable
CMPCSR          0x0022   Comparator Control/Status Register
CMPCSR.CMP3      7   Comparator 3 Output
CMPCSR.CMP2      6   Comparator 2 Output
CMPCSR.CMP1      5   Comparator 1 Output
CMPCSR.CM3IE     4   Comparator 3 Interrupt Enable
CMPCSR.CEN3      2   Comparator 3 Enable
CMPCSR.CEN2      1   Comparator 2 Enable
CMPCSR.CEN1      0   Comparator 1 Enable
RESERV1FF0      0x1FF0   RESERVED
RESERV1FF1      0x1FF1   RESERVED
RESERV1FF2      0x1FF2   RESERVED
RESERV1FF3      0x1FF3   RESERVED


.68HC05E1
; http://e-www.motorola.com/brdata/PDFDB/docs/HC05E1GRS.pdf
; HC05E1GRS.pdf

; RAM=176
; ROM=6K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x0090
area DATA RAM_U1      0x0090:0x0100
area DATA RAM_U2      0x0100:0x0200
area BSS  UNUSED      0x0200:0x0F00
area DATA ROM         0x0F00:0x1F00
area DATA ROM_S_C     0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      SWI               
interrupt IRQ               0x1FFA      IRQ/IRQ2        
interrupt Timer             0x1FF8      Timer Interrupt            
interrupt CPI               0x1FF6      Custom Periodic Interrupt         


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001    Port B data
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
PORTC          0x0002    Port C data
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
UNUSED03       0x0003   UNUSED
DDRA           0x0004   Port A Data Direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005   Port B Data Direction
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRC           0x0006   Port C Data Direction
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC6      6   Data Direction for Port C Bit 6
DDRC.DDRC5      5   Data Direction for Port C Bit 5
DDRC.DDRC4      4   Data Direction for Port C Bit 4
DDRC.DDRC3      3   Data Direction for Port C Bit 3
DDRC.DDRC2      2   Data Direction for Port C Bit 2
DDRC.DDRC1      1   Data Direction for Port C Bit 1
DDRC.DDRC0      0   Data Direction for Port C Bit 0
PLLC           0x0007   PLL control register
PLLC.BCS        6   Bus Clock Select
PLLC.AUTO       5
PLLC.BWC        4   Bandwidth Control
PLLC.PLLON      3   PLL On
PLLC.VCOTST     2   VCO Test
PLLC.PS1        1   PLL Synthesizer Speed Select 1
PLLC.PS0        0   PLL Synthesizer Speed Select 0
TCS            0x0008   Timer Control & Status Register
TCS.TOF         7   Timer Over Flow
TCS.RTIF        6   Real Time Interrupt Flag
TCS.TOFE        5   Timer Over Flow Enable
TCS.RTIE        4   Real Time Interrupt Enable
TCS.RT1         1   Real Time Interrupt Rate Select 1
TCS.RT0         0   Real Time Interrupt Rate Select 0
TCR            0x0009   TIMER COUNTER REG
UNUSED0A       0x000A   UNUSED
UNUSED0B       0x000B   UNUSED
UNUSED0C       0x000C   UNUSED
UNUSED0D       0x000D   UNUSED
UNUSED0E       0x000E   UNUSED
UNUSED0F       0x000F   UNUSED
UNUSED10       0x0010   UNUSED
UNUSED11       0x0011   UNUSED
CPICSR         0x0012   CPI Control & Status Register
CPICSR.CPIF     6   Custom Periodic Interrupt Flag
CPICSR.CPIE     4   Custom Periodic Interrupt Enable
UNUSED13       0x0013   UNUSED
UNUSED14       0x0014   UNUSED
UNUSED15       0x0015   UNUSED
UNUSED16       0x0016   UNUSED
UNUSED17       0x0017   UNUSED
UNUSED18       0x0018   UNUSED
UNUSED19       0x0019   UNUSED
UNUSED1A       0x001A   UNUSED
UNUSED1B       0x001B   UNUSED
UNUSED1C       0x001C   UNUSED
UNUSED1D       0x001D   UNUSED
UNUSED1E       0x001E   UNUSED
UNUSED1F       0x001F   UNUSED
RESERV1FF0     0x1FF0   RESERVED
RESERV1FF1     0x1FF1   RESERVED
RESERV1FF2     0x1FF2   RESERVED
RESERV1FF3     0x1FF3   RESERVED
RESERV1FF4     0x1FF4   RESERVED
RESERV1FF5     0x1FF5   RESERVED


.68HC05E16
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC05E5
; http://
; HC05E5GRS.pdf

; ROM=5120
; RAM=384
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x0080
area DATA RAM_U1      0x0080:0x0100
area DATA RAM_U2      0x0100:0x0200
area BSS  UNUSED      0x0200:0x0B00
area DATA ROM         0x0B00:0x1F00
area DATA USER_VEC    0x1F00:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset                  
interrupt SWI               0x1FFC      SOFTWARE                   
interrupt _IRQ              0x1FFA      External Interrupt                     
interrupt TIMER             0x1FF8      Timer                
interrupt CPI               0x1FF6      Serial Peripheral Interrupt                   
interrupt SSI               0x1FF4      SSI         
interrupt M_BUS             0x1FF2      M_BUS


; INPUT/ OUTPUT PORTS
PORTA               0x0000      Port A data Register
PORTA.PA7            7   Port A Data Bits 7
PORTA.PA6            6   Port A Data Bits 6
PORTA.PA5            5   Port A Data Bits 5
PORTA.PA4            4   Port A Data Bits 4
PORTA.PA3            3   Port A Data Bits 3
PORTA.PA2            2   Port A Data Bits 2
PORTA.PA1            1   Port A Data Bits 1
PORTA.PA0            0   Port A Data Bits 0
PORTB               0x0001      Port B data Register
PORTB.PB7            7   Port B Data Bits 7
PORTB.PB6            6   Port B Data Bits 6
PORTB.PB5            5   Port B Data Bits 5
PORTB.PB4            4   Port B Data Bits 4
PORTB.PB3            3   Port B Data Bits 3
PORTB.PB2            2   Port B Data Bits 2
PORTB.PB1            1   Port B Data Bits 1
PORTB.PB0            0   Port B Data Bits 0
PORTC               0x0002      Port C data Register
PORTC.PC3            3   Port C Data Bits 3
PORTC.PC2            2   Port C Data Bits 2
PORTC.PC1            1   Port C Data Bits 1
PORTC.PC0            0   Port C Data Bits 0
UNUSED0003          0x0003     UNUSED
DDRA                0x0004      Port A data direction Register
DDRA.DDA7            7   Data Direction for Port A Bit 7
DDRA.DDA6            6   Data Direction for Port A Bit 6
DDRA.DDA5            5   Data Direction for Port A Bit 5
DDRA.DDA4            4   Data Direction for Port A Bit 4
DDRA.DDA3            3   Data Direction for Port A Bit 3
DDRA.DDA2            2   Data Direction for Port A Bit 2
DDRA.DDA1            1   Data Direction for Port A Bit 1
DDRA.DDA0            0   Data Direction for Port A Bit 0
DDRB                0x0005     Port B data direction Register
DDRB.DDB7            7   Data Direction for Port B Bit 7
DDRB.DDB6            6   Data Direction for Port B Bit 6
DDRB.DDB5            5   Data Direction for Port B Bit 5
DDRB.DDB4            4   Data Direction for Port B Bit 4
DDRB.DDB3            3   Data Direction for Port B Bit 3
DDRB.DDB2            2   Data Direction for Port B Bit 2
DDRB.DDB1            1   Data Direction for Port B Bit 1
DDRB.DDB0            0   Data Direction for Port B Bit 0
DDRC                0x0006     Port C data direction Register
DDRC.DDC3            3   Data Direction for Port C Bit 3
DDRC.DDC2            2   Data Direction for Port C Bit 2
DDRC.DDC1            1   Data Direction for Port C Bit 1
DDRC.DDC0            0   Data Direction for Port C Bit 0
PLLC                0x0007     PLL Control Register
PLLC.BCS             6   Bus Clock Select
PLLC.BWC             4   Bandwidth Control
PLLC.PLLON           3   PLL On
PLLC.VCOTST          2   VCO Test
PLLC.PS1             1   PLL Synthesizer Speed Select 1
PLLC.PS0             0   PLL Synthesizer Speed Select 0
TCSR                0x0008     Timer Control and Status Register
TCSR.TOF             7   Timer Over Flow
TCSR.RTIF            6   Real-Time Interrupt Flag
TCSR.TOFE            5   Timer Overflow Enable
TCSR.RTIE            4   Real-Time Interrupt Enable
TCSR.TOFA            3   Timer Over Flow Flag Acknowledge
TCSR.RTIFA           2   Real-Time Interrupt Flag Acknowledge
TCSR.RT1             1   Real-Time Interrupt Rate Select 1
TCSR.RT0             0   Real-Time Interrupt Rate Select 0
TCR                 0x0009     Timer Counter Register
SCR                 0x000A     SSI Control Register
SCR.SIE              7   SSI Interrupt Enable
SCR.SE               6   SSI Enable
SCR.LSBF             5   Least Significant Bit First
SCR.MSTR             4   Master Mode
SCR.CPOL             3   Clock Polarity
SCR.SDIR             2   Serial Data Direction
SCR.SR1              1   SSI Clock Rate Select 1
SCR.SR0              0   SSI Clock Rate Select 0
SSR                 0x000B     SSI Status Register
SSR.SF               7   SSI Flag
SSR.DCOL             6   Data Collision
SSR.TIPL             0
SDR                 0x000C     SSI Data Register
SDR.D7               7
SDR.D6               6
SDR.D5               5
SDR.D4               4
SDR.D3               3
SDR.D2               2
SDR.D1               1
SDR.D0               0
UNUSED000D          0x000D     UNUSED
UNUSED000E          0x000E     UNUSED
UNUSED000F          0x000F     UNUSED
UNUSED0010          0x0010     UNUSED
UNUSED0011          0x0011     UNUSED
CPICSR              0x0012     CPI Control and Status Register
CPICSR.CPIF          6   Custom Periodic Interrupt Flag
CPICSR.CPIE          4   Custom Periodic Interrupt Enable
SCSR                0x0013     System Conrol and Status Register
SCSR.STOPR           4   Illegal STOP Instruction Reset
SCSR.ILADR           3   Illegal Address Reset
SCSR.COPR            2   COP Reset
SCSR.CRS1            1   COP Rate Select 1
SCSR.CRS0            0   COP Rate Select 0
UNUSED0014          0x0014     UNUSED
UNUSED0015          0x0015     UNUSED
UNUSED0016          0x0016     UNUSED
UNUSED0017          0x0017     UNUSED
MADR                0x0018     M-Bus Address Register
MADR.MAD7            7
MADR.MAD6            6
MADR.MAD5            5
MADR.MAD4            4
MADR.MAD3            3
MADR.MAD2            2
MADR.MAD1            1
MFDR                0x0019     M Bus Frequency Divider Register
MFDR.FD4             4
MFDR.FD3             3
MFDR.FD2             2
MFDR.FD1             1
MFDR.FD0             0
MCR                 0x001A     M Bus Control Register
MCR.MEN              7   M-Bus Enable Bit
MCR.MIEN             6   M-Bus Interrupt Enable Bit
MCR.MSTA             5   Master/Slave Mode Select Bit
MCR.MTX              4   Transmit/Receiver Mode Select Bit
MCR.TXAK             3   Transmit Acknowledge Enable Bit
MCR.MMUX             2   M-Bus Multiplexer
MBS                 0x001B     M Bus Status Register
MBS.MCF              7   Data Transferring Bit
MBS.MAAS             6   Addressed as a Slave Bit
MBS.MBB              5   Bus Busy Bit
MBS.MAL              4   Arbitration Lost Bit
MBS.SRW              2   R/W Command Bit
MBS.MIF              1   M-Bus Interrupt Bit
MBS.RXAK             0   Receive Acknowledge Bit
MDR                 0x001C     M Bus Data I/O Register
MDR.MD7              7
MDR.MD6              6
MDR.MD5              5
MDR.MD4              4
MDR.MD3              3
MDR.MD2              2
MDR.MD1              1
MDR.MD0              0
UNUSED001D          0x001D     UNUSED
UNUSED001E          0x001E     UNUSED
RESERV001F          0x001F     Reserved
RESERV1FF0          0x1FF0     RESERVED
RESERV1FF1          0x1FF1     RESERVED


.68HC05E6
; MC68HC05E6/D     http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC05E6.pdf
; MC68HC05E6.pdf

; ROM=6000+16
; RAM=128
; EPROM=0
; EEPROM=160


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area BSS  RESERVED     0x0020:0x0080
area DATA RAM          0x0080:0x0100
area DATA EEPROM       0x0100:0x01A0
area BSS  RESERVED     0x01A0:0x0800
area CODE ROM          0x0800:0x1F70
area BSS  RESERVED     0x1F70:0x1FF0
area DATA USER_VEC     0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset                  
interrupt SWI               0x1FFC      SWI                    
interrupt _IRQ              0x1FFA      IRQ                     
interrupt TIMER             0x1FF8      Core timer                
interrupt _LVI              0x1FF6      LVI                   
interrupt TIMER16           0x1FF4      16-bit Timer         
interrupt KEY_WAKE_UP       0x1FF2      Keyboard wake-up


; INPUT/ OUTPUT PORTS
PORTA           0x0000    Port A data Register
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001    Port B data Register
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002    Port C data Register
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003    Port D data Register
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD6        6   Port D Data Bits 6
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004    Port A data direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005    Port B data direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006    Port C data direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007    Port D data direction
DDRD.DDRD7       7   Data Direction for Port D Bit 7
DDRD.DDRD6       6   Data Direction for Port D Bit 6
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
CTCSR           0x0008    Core timer control/status
CTCSR.CTOF       7   Core timer overflow
CTCSR.RTIF       6   Real time interrupt flag
CTCSR.CTOFE      5   Core timer overflow interrupt enable
CTCSR.RTIE       4   Real time interrupt enable
CTCSR.RTOF       3   Reset core timer overflow flag
CTCSR.RRTIF      2   Reset real time interrupt flag
CTCSR.RT1        1   Real time interrupt rate select 1
CTCSR.RT0        0   Real time interrupt rate select 0
CTCR            0x0009   Core timer counter
KEY_TIM         0x000A   Keyboard/timer
KEY_TIM.KSF      7   Keyboard status flag
KEY_TIM.KIE      6   Keyboard interrupt enable
KEY_TIM.KIRST    5   Keyboard interrupt reset
KEY_TIM.SEL1     1   Timer select bit 1
KEY_TIM.SEL0     0   Timer select bit 0
CONFD           0x000B   Port D configuration
PORTG           0x000C   Port G data
PORTG.PG3        3   Port G Data Bits 3
PORTG.PG2        2   Port G Data Bits 2
PORTG.PG1        1   Port G Data Bits 1
PORTG.PG0        0   Port G Data Bits 0
RESERV000D      0x000D   Reserved
CONFC           0x000E   Port C configuration
LVIOPT          0x000F   LVI/options
LVIOPT.LVIINT    7   LVI interrupt flag
LVIOPT.LVIVAL    6   LVI pin level
LVIOPT.LVIRST    5   LVI interrupt reset
LVIOPT.LVIE      4   LVI interrupt enable
; LVIOPT.COP       1   Computer operating properly watchdog enable/disable (MC68HC705E6 only)
LVIOPT.IRQ       0   Interrupt triggering sensitivity
ADDATA          0x0010   A/D data
ADSTAT          0x0011   A/D status/control
ADSTAT.COCO      7   Conversion complete flag
ADSTAT.ADRC      6   A/D RC oscillator control
ADSTAT.ADON      5   A/D converter enable/disable
ADSTAT.CH2       2   A/D channel selection 2
ADSTAT.CH1       1   A/D channel selection 1
ADSTAT.CH0       0   A/D channel selection 0
TCR             0x0012   Timer control
TCR.ICIE         7   Input capture interrupt enable
TCR.OCIE         6   Output compare interrupt enable
TCR.TOIE         5   Timer overflow interrupt enable
TCR.IEDG         1   Input edge
TCR.OLV          0   Output level
TSR             0x0013   Timer status
TSR.ICF          7   Input capture flag
TSR.OCF          6   Output compare flag
TSR.TOF          5   Timer overflow flag
ICH             0x0014   Input capture high
ICL             0x0015   Input capture low
OCH             0x0016   Output compare high
OCL             0x0017   Output compare low
TCH             0x0018   Timer counter high
TCL             0x0019   Timer counter low
ACH             0x001A   Alternate counter high
ACL             0x001B   Alternate counter low
EPROG           0x001C   EEPROM programming
EPROG.CPEN       6   Charge pump enable
EPROG.ER1        4   Erase select bits 1
EPROG.ER0        3   Erase select bits 0
EPROG.EELATCH    2   EEPROM latch control
EPROG.EERC       1   EEPROM RC oscillator control
EPROG.EEPGM      0   EEPROM programming power enable/disable
RESERV001D      0x001D   RESEREV
; PROG            0x001D   EPROM programing (MC68HC705E6)
; PROG.ELATCH      2   EPROM latch control
; PROG.EPGM        0   EPROM program control
RESERV001E      0x001E   Reserved
RESERV001F      0x001F   Reserved
COPCLR          0x1FF0   COPCLR
COPCLR.CCLR      0
RESERV1FF1      0x1FF1  RESERVED


.68HC05F12
; MC68HC05F12/D  http://
; MC68HC05F12.pdf

; RAM=384
; ROM=12160
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area DATA LCD_RAM     0x0040:0x0050
area DATA RAM         0x0050:0x01D0
area BSS  UNUSED      0x01D0:0x0200
area DATA EEPROM      0x0200:0x0300
area BSS  UNUSED      0x0300:0x5000
area DATA ROM         0x5000:0x7F80
area DATA Boot_ROM    0x7F80:0x7FF0
area DATA USER_VEC    0x7FF0:0x8000


; Interrupt and reset vector assignments
interrupt __RESET 	0x7FFE       Reset 
interrupt SWI 		0x7FFC       Software interrupt 
interrupt IRQ 		0x7FFA       External interrupt 
interrupt CTIMER 	0x7FF8       CTIMER
interrupt TIMER 	0x7FF6       TIMER
interrupt KBI 		0x7FFA       Keyboard interrupt 
interrupt LVI 		0x7FF4       Low voltage interrupt 


; INPUT/ OUTPUT PORTS
PORTA            0x0000     Port A data
PORTA.PA7         7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
; KISR             0x0000     Key interrupt status
PORTB            0x0001     Port B data
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTC            0x0002     Port C data
PORTC.PC7         7   Port C Data Bits 7
PORTC.PC6         6   Port C Data Bits 6
PORTC.PC5         5   Port C Data Bits 5
PORTC.PC4         4   Port C Data Bits 4
PORTC.PC3         3   Port C Data Bits 3
PORTC.PC2         2   Port C Data Bits 2
PORTC.PC1         1   Port C Data Bits 1
PORTC.PC0         0   Port C Data Bits 0
PORTD            0x0003     Port D data
PORTD.PD7         7   Port D Data Bits 7
PORTD.PD6         6   Port D Data Bits 6
PORTD.PD5         5   Port D Data Bits 5
PORTD.PD4         4   Port D Data Bits 4
PORTD.PD3         3   Port D Data Bits 3
PORTD.PD2         2   Port D Data Bits 2
PORTD.PD1         1   Port D Data Bits 1
PORTD.PD0         0   Port D Data Bits 0
DDRA             0x0004     Port A data direction
DDRA.DDRA7        7   Data Direction for Port A Bit 7
DDRA.DDRA6        6   Data Direction for Port A Bit 6
DDRA.DDRA5        5   Data Direction for Port A Bit 5
DDRA.DDRA4        4   Data Direction for Port A Bit 4
DDRA.DDRA3        3   Data Direction for Port A Bit 3
DDRA.DDRA2        2   Data Direction for Port A Bit 2
DDRA.DDRA1        1   Data Direction for Port A Bit 1
DDRA.DDRA0        0   Data Direction for Port A Bit 0
DDRB             0x0005     Port B data direction
DDRB.DDRB7        7   Data Direction for Port B Bit 7
DDRB.DDRB6        6   Data Direction for Port B Bit 6
DDRB.DDRB5        5   Data Direction for Port B Bit 5
DDRB.DDRB4        4   Data Direction for Port B Bit 4
DDRB.DDRB3        3   Data Direction for Port B Bit 3
DDRB.DDRB2        2   Data Direction for Port B Bit 2
DDRB.DDRB1        1   Data Direction for Port B Bit 1
DDRB.DDRB0        0   Data Direction for Port B Bit 0
DDRC             0x0006     Port C data direction
DDRC.DDRC7        7   Data Direction for Port C Bit 7
DDRC.DDRC6        6   Data Direction for Port C Bit 6
DDRC.DDRC5        5   Data Direction for Port C Bit 5
DDRC.DDRC4        4   Data Direction for Port C Bit 4
DDRC.DDRC3        3   Data Direction for Port C Bit 3
DDRC.DDRC2        2   Data Direction for Port C Bit 2
DDRC.DDRC1        1   Data Direction for Port C Bit 1
DDRC.DDRC0        0   Data Direction for Port C Bit 0
DDRD             0x0007     Port D data direction
DDRD.DDRD7        7   Data Direction for Port D Bit 7
DDRD.DDRD6        6   Data Direction for Port D Bit 6
DDRD.DDRD5        5   Data Direction for Port D Bit 5
DDRD.DDRD4        4   Data Direction for Port D Bit 4
DDRD.DDRD3        3   Data Direction for Port D Bit 3
DDRD.DDRD2        2   Data Direction for Port D Bit 2
DDRD.DDRD1        1   Data Direction for Port D Bit 1
DDRD.DDRD0        0   Data Direction for Port D Bit 0
CTCSR            0x0008     Core timer control/status
CTCSR.TOF         7   Core timer overflow
CTCSR.RTIF        6   Real time interrupt flag
CTCSR.TOFE        5   Core timer overflow enable
CTCSR.RTIE        4   Real time interrupt enable
CTCSR.RTOF        3
CTCSR.RRTIF       2
CTCSR.RT1         1   Real time interrupt rate select 1
CTCSR.RT0         0   Real time interrupt rate select 0
CTCR             0x0009     Core timer counter
CTCR.CTCR7        7
CTCR.CTCR6        6
CTCR.CTCR5        5
CTCR.CTCR4        4
CTCR.CTCR3        3
CTCR.CTCR2        2
CTCR.CTCR1        1
CTCR.CTCR0        0
PORTE            0x000A     Port E data
PORTE.PE7         7   Port E Data Bits 7
PORTE.PE6         6   Port E Data Bits 6
PORTE.PE5         5   Port E Data Bits 5
PORTE.PE4         4   Port E Data Bits 4
PORTE.PE3         3   Port E Data Bits 3
PORTE.PE2         2   Port E Data Bits 2
PORTE.PE1         1   Port E Data Bits 1
PORTE.PE0         0   Port E Data Bits 0
DDRE             0x000B     Port E data direction
DDRE.DDRE7        7   Data Direction for Port E Bit 7
DDRE.DDRE6        6   Data Direction for Port E Bit 6
DDRE.DDRE5        5   Data Direction for Port E Bit 5
DDRE.DDRE4        4   Data Direction for Port E Bit 4
DDRE.DDRE3        3   Data Direction for Port E Bit 3
DDRE.DDRE2        2   Data Direction for Port E Bit 2
DDRE.DDRE1        1   Data Direction for Port E Bit 1
DDRE.DDRE0        0   Data Direction for Port E Bit 0
PECR             0x000C     Port E control
PECR.PECR7        7
PECR.PECR6        6
PECR.PECR5        5
PECR.PECR4        4
PECR.PECR3        3
PECR.PECR1        1
FCR              0x000D     DTMF row freq. control
FCR.FCR4          4
FCR.FCR3          3
FCR.FCR2          2
FCR.FCR1          1
FCR.FCR0          0
FCC              0x000E     DTMF column freq. control
FCC.FCC4          4
FCC.FCC3          3
FCC.FCC2          2
FCC.FCC1          1
FCC.FCC0          0
TNCR             0x000F     DTMF tone control
TNCR.MS1          7   Melody select for operation 1
TNCR.MS0          6   Melody select for operation 0
TNCR.TGER         5   Tone generator enable row path
TNCR.TGEC         4   Tone generator enable column path
TNCR.TNOE         3   Tone output enable
RESERVED0010     0x0010     RESERVED
RESERVED0011     0x0011     RESERVED
PORTG            0x0012     Port G data
PORTG.PG7         7   Port G Data Bits 7
PORTG.PG6         6   Port G Data Bits 6
PORTG.PG5         5   Port G Data Bits 5
PORTG.PG4         4   Port G Data Bits 4
PORTG.PG3         3   Port G Data Bits 3
PORTG.PG2         2   Port G Data Bits 2
PORTG.PG1         1   Port G Data Bits 1
PORTG.PG0         0   Port G Data Bits 0
PGCR             0x0013     Port G control
PGCR.PGCR7        7
PGCR.PGCR6        6
PGCR.PGCR5        5
PGCR.PGCR4        4
PGCR.PGCR3        3
PGCR.PGCR2        2
PGCR.PGCR1        1
PGCR.PGCR0        0
PORTH            0x0014     Port H data
PORTH.PH7         7   Port H Data Bits 7
PORTH.PH6         6   Port H Data Bits 6
PORTH.PH5         5   Port H Data Bits 5
PORTH.PH4         4   Port H Data Bits 4
PORTH.PH3         3   Port H Data Bits 3
PORTH.PH2         2   Port H Data Bits 2
PORTH.PH1         1   Port H Data Bits 1
PORTH.PH0         0   Port H Data Bits 0
RESERVED0015     0x0015     RESERVED
RESERVED0016     0x0016     RESERVED
RESERVED0017     0x0017     RESERVED
RESERVED0018     0x0018     RESERVED
RESERVED0019     0x0019     RESERVED
RESERVED001A     0x001A     RESERVED
KCR              0x001B     Key control
KCR.KF            7   Keyboard interrupt status flag
KCR.KIE           6   keyboard interrupt enable
; KCR.EDG5          5
; KCR.EDG4          4
; KCR.EDG3          3
; KCR.EDG2          2
; KCR.EDG1          1
; KCR.EDG0          0
EEPROG           0x001C     EEPROM prog.
EEPROG.CPEN       6   Charge pump enable
EEPROG.ER1        4   Erase select bits 1
EEPROG.ER0        3   Erase select bits 0
EEPROG.LATCH      2   EEPROM latch bit
EEPROG.EERC       1   EEPROM RC oscillator control
EEPROG.EEPGM      0   EEPROM programming power enable
LCD              0x001E     LCD control
; LCD.WTLCDO        7
; LCD.FSEL1         6
; LCD.FSEL0         5
LCD.INTVLCD       4   Internal voltage generator ON/OFF
LCD.FDISP         3   Display frequency
LCD.MUX4          2   Multiplex ratio 4
LCD.MUX3          1   Multiplex ratio 3
LCD.EXTVON        0   External LCD voltage ON/OFF
RESERVED001F     0x001F     RESERVED
ICR1H            0x0020     Capture 1 high
ICR1L            0x0021     Capture 1 low
OCR1H            0x0022     Compare 1 high
OCR1L            0x0023     Compare 1 low
ICR2H            0x0024     Capture 2 high
ICR2L            0x0025     Capture 2 low
OCR2H            0x0026     Compare 2 high
OCR2L            0x0027     Compare 2 low
CNTH             0x0028     Counter high
CNTL             0x0029     Counter low
ACNTH            0x002A     Alternate counter high
ACNTL            0x002B     Alternate counter low
TCR1             0x002C     Timer control 1
TCR1.IC1IE        7   Input capture 1 interrupt enable
TCR1.IC2IE        6   Input capture 2 interrupt enable
TCR1.OC1IE        5   Output compare 1 interrupt enable
TCR1.TOIE         4   Timer overflow interrupt enable
TCR1.CO1E         3   Timer compare 1 output enable
TCR1.IEDG1        2   Input edge 1
TCR1.IEDG2        1   Input edge 2
TCR1.OLVL1        0   Output level 1
TCR2             0x002D     Timer control 2
TCR2.OC2IE        5   Output compare 2 interrupt enable
TCR2.CO2E         3   Timer compare 2 output enable
TCR2.OLVL2        0   Output level 2
TSR              0x002E     Timer status
TSR.IC1F          7   Input capture 1 flag
TSR.IC2F          6   Input capture 2 flag
TSR.OC1F          5   Output compare 1 flag
TSR.TOF           4   Timer overflow status flag
TSR.TCAP1         3
TSR.TCAP2         2
TSR.OC2F          1   Output compare 2 flag
RESERVED001F     0x002F     RESERVED
ICR3H            0x0030     Capture 3 high
ICR3L            0x0031     Capture 3 low
OCR3H            0x0032     Compare 3 high
OCR3L            0x0033     Compare 3 low
RESERVED0034     0x0034     RESERVED
RESERVED0035     0x0035     RESERVED
RESERVED0036     0x0036     RESERVED
RESERVED0037     0x0037     RESERVED
RESERVED0038     0x0038     RESERVED
RESERVED0039     0x0039     RESERVED
RESERVED003A     0x003A     RESERVED
RESERVED003B     0x003B     RESERVED
RESERVED003C     0x003C     RESERVED
SOR              0x003D     System options
SOR.LVIF          7   IF  - Low voltage interrupt bits
SOR.LVIE          6   IE  - Low voltage interrupt bits
SOR.LVION         5   ION - Low voltage interrupt bits
SOR.SC            4   System clock option
SOR.IRQ           3   Interrupt sensitivity
SOR.KEYCLR        1   Keyboard interrupt clear
SOR.PUEN          0   PORTC pull-up enable
RESERVED003E     0x003E     RESERVED
RESERVED003F     0x003F     RESERVED
RESERV7FF0       0x7FF0    RESERVED
RESERV7FF1       0x7FF1    RESERVED
RESERV7FF2       0x7FF2    RESERVED
RESERV7FF3       0x7FF3    RESERVED


.68HC05F4
; MC68HC05F4/D  http://
; MC68HC05F4.pdf

; RAM=256
; ROM=3840
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR        0x0000:0x0040
area DATA RAM        0x0040:0x0140
area BSS  UNUSED     0x0140:0x0200
area DATA EEPROM     0x0200:0x0300
area BSS  UNUSED     0x0300:0x3000
area DATA ROM        0x3000:0x3F00
area DATA BOOT_ROM   0x3F00:0x3FF0
area DATA USER_VEC   0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Reset  
interrupt SWI               0x3FFC      software interrupt               
interrupt IRQ               0x3FFA      IRQ       
interrupt CTIMER            0x3FF8      CTimer        
interrupt TIMER             0x3FF6      Programmable 16-bit timer interrupt  
interrupt KEYF              0x3FF4      Keyboard interrupt
interrupt LVI               0x3FF2      Low voltage interrupt


; INPUT/ OUTPUT PORTS
PORTA            0x0000     Port A data
PORTA.PA7         7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
PORTB            0x0001     Port B data
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTC            0x0002     Port C data
PORTC.PC7         7   Port C Data Bits 7
PORTC.PC6         6   Port C Data Bits 6
PORTC.PC5         5   Port C Data Bits 5
PORTC.PC4         4   Port C Data Bits 4
PORTC.PC3         3   Port C Data Bits 3
PORTC.PC2         2   Port C Data Bits 2
PORTC.PC1         1   Port C Data Bits 1
PORTC.PC0         0   Port C Data Bits 0
PORTD            0x0003     Port D data
PORTD.PD7         7   Port D Data Bits 7
PORTD.PD6         6   Port D Data Bits 6
PORTD.PD5         5   Port D Data Bits 5
PORTD.PD4         4   Port D Data Bits 4
PORTD.PD3         3   Port D Data Bits 3
PORTD.PD2         2   Port D Data Bits 2
PORTD.PD1         1   Port D Data Bits 1
PORTD.PD0         0   Port D Data Bits 0
DDRA             0x0004     Port A data direction
DDRA.DDRA7        7   Data Direction for Port A Bit 7
DDRA.DDRA6        6   Data Direction for Port A Bit 6
DDRA.DDRA5        5   Data Direction for Port A Bit 5
DDRA.DDRA4        4   Data Direction for Port A Bit 4
DDRA.DDRA3        3   Data Direction for Port A Bit 3
DDRA.DDRA2        2   Data Direction for Port A Bit 2
DDRA.DDRA1        1   Data Direction for Port A Bit 1
DDRA.DDRA0        0   Data Direction for Port A Bit 0
DDRB             0x0005     Port B data direction
DDRB.DDRB7        7   Data Direction for Port B Bit 7
DDRB.DDRB6        6   Data Direction for Port B Bit 6
DDRB.DDRB5        5   Data Direction for Port B Bit 5
DDRB.DDRB4        4   Data Direction for Port B Bit 4
DDRB.DDRB3        3   Data Direction for Port B Bit 3
DDRB.DDRB2        2   Data Direction for Port B Bit 2
DDRB.DDRB1        1   Data Direction for Port B Bit 1
DDRB.DDRB0        0   Data Direction for Port B Bit 0
DDRC             0x0006     Port C data direction
DDRC.DDRC7        7   Data Direction for Port C Bit 7
DDRC.DDRC6        6   Data Direction for Port C Bit 6
DDRC.DDRC5        5   Data Direction for Port C Bit 5
DDRC.DDRC4        4   Data Direction for Port C Bit 4
DDRC.DDRC3        3   Data Direction for Port C Bit 3
DDRC.DDRC2        2   Data Direction for Port C Bit 2
DDRC.DDRC1        1   Data Direction for Port C Bit 1
DDRC.DDRC0        0   Data Direction for Port C Bit 0
DDRD             0x0007     Port D data direction
DDRD.DDRD7        7   Data Direction for Port D Bit 7
DDRD.DDRD6        6   Data Direction for Port D Bit 6
DDRD.DDRD5        5   Data Direction for Port D Bit 5
DDRD.DDRD4        4   Data Direction for Port D Bit 4
DDRD.DDRD3        3   Data Direction for Port D Bit 3
DDRD.DDRD2        2   Data Direction for Port D Bit 2
DDRD.DDRD1        1   Data Direction for Port D Bit 1
DDRD.DDRD0        0   Data Direction for Port D Bit 0
CTCSR            0x0008     Core timer control_status
CTCSR.CTOF        7   Core timer overflow
CTCSR.RTIF        6   Real time interrupt flag
CTCSR.CTOFE       5   Core timer overflow enable
CTCSR.RTIE        4   Real time interrupt enable
CTCSR.RTOF        3   Reset timer overflow flag
CTCSR.RRTIF       2   Reset real time overflow flag
CTCSR.RT1         1   Real time interrupt rate select 1
CTCSR.RT0         0   Real time interrupt rate select 0
CTCR             0x0009     Core timer counter
CTCR.CTCR7        7
CTCR.CTCR6        6
CTCR.CTCR5        5
CTCR.CTCR4        4
CTCR.CTCR3        3
CTCR.CTCR2        2
CTCR.CTCR1        1
CTCR.CTCR0        0
UNUSED000A       Ox000A     UNUSED
RESERV000B       Ox000B     RESERVED
RESERV000C       Ox000C     RESERVED
FCR              0x000D     DTMF row freq. control
FCR.FCR4          4
FCR.FCR3          3
FCR.FCR2          2
FCR.FCR1          1
FCR.FCR0          0
FCC              0x000E     DTMF column freq. control
FCC.FCC4          4
FCC.FCC3          3
FCC.FCC2          2
FCC.FCC1          1
FCC.FCC0          0
TNCR             0x000F     DTMF tone control
TNCR.MS1          7   Melody select for operation 1
TNCR.MS0          6   Melody select for operation 0
TNCR.TGER         5   Tone generator enable row path
TNCR.TGEC         4   Tone generator enable column path
TNCR.TNOE         3   Tone output enable
KCR              0x0010     Key control
KCR.KF            7   Keyboard interrupt status flag
KCR.KIE           6   keyboard interrupt enable
SOR              0x0011     System options
SOR.LVIF          7   Low voltage interrupt flag
SOR.LVIE          6   Low voltage interrupt enable
SOR.LVION         5   Low voltage interrupt on
SOR.SC            4   System clock option
SOR.IRQ           3   Interrupt sensitivity
UNUSED0012       Ox0012     UNUSED
UNUSED0013       Ox0013     UNUSED
UNUSED0014       Ox0014     UNUSED
UNUSED0015       Ox0015     UNUSED
UNUSED0016       Ox0016     UNUSED
UNUSED0017       Ox0017     UNUSED
UNUSED0018       Ox0018     UNUSED
UNUSED0019       Ox0019     UNUSED
UNUSED001A       Ox001A     UNUSED
UNUSED001B       Ox001B     UNUSED
EEPROG           0x001C     EEPROM programming
EEPROG.CPEN       6   Charge pump enable
EEPROG.ER1        4   Erase select bits 1
EEPROG.ER0        3   Erase select bits 0
EEPROG.LATCH      2   EEPROM latch bit
EEPROG.EERC       1   EEPROM RC oscillator control
EEPROG.EEPGM      0   EEPROM programming power enable
UNUSED001D       0x001D     UNUSED
UNUSED001E       0x001E     UNUSED
RESERV001F       0x001F     RESERVED
ICR1H            0x0020     Input capture 1 high
ICR1L            0x0021     Input capture 1 low
OCR1H            0x0022     Output compare 1 high
OCR1L            0x0023     Output compare 1 low
ICR2H            0x0024     Input capture 2 high
ICR2L            0x0025     Input capture 2 low
OCR2H            0x0026     Output compare 2 high
OCR2L            0x0027     Output compare 2 low
CNTH             0x0028     Timer counter high
CNTL             0x0029     Timer counter low
ACNTH            0x002A     Alternate counter high
ACNTL            0x002B     Alternate counter low
TCR1             0x002C     Timer control 1
TCR1.IC1IE        7   Input capture 1 interrupt enable
TCR1.IC2IE        6   Input capture 2 interrupt enable
TCR1.OC1IE        5   Output compare 1 interrupt enable
TCR1.TOIE         4   Timer overflow interrupt enable
TCR1.CO1E         3   Timer compare 1 output enable
TCR1.IEDG1        2   Input edge 1
TCR1.IEDG2        1   Input edge 2
TCR1.OLVL1        0   Output level 1
TCR2             0x002D     Timer control 2
TCR2.OC2IE        5   Output compare 2 interrupt enable
TCR2.CO2E         3   Timer compare 2 output enable
TCR2.OLVL2        0   Output level 2
TSR              0x002E     Timer status
TSR.IC1F          7   Input capture 1 flag
TSR.IC2F          6   Input capture 2 flag
TSR.OC1F          5   Output compare 1 flag
TSR.TOF           4   Timer overflow status flag
TSR.TCAP1         3   Timer capture 1 flag
TSR.TCAP2         2   Timer capture 2 flag
TSR.OC2F          1   Output compare 2 flag
UNUSED002F       0x002F     UNUSED
UNUSED0030       0x0030     UNUSED
UNUSED0031       0x0031     UNUSED
UNUSED0032       0x0032     UNUSED
UNUSED0033       0x0033     UNUSED
UNUSED0034       0x0034     UNUSED
UNUSED0035       0x0035     UNUSED
UNUSED0036       0x0036     UNUSED
UNUSED0037       0x0037     UNUSED
UNUSED0038       0x0038     UNUSED
UNUSED0039       0x0039     UNUSED
UNUSED003A       0x003A     UNUSED
UNUSED003B       0x003B     UNUSED
UNUSED003C       0x003C     UNUSED
UNUSED003D       0x003D     UNUSED
UNUSED003E       0x003E     UNUSED
UNUSED003F       0x003F     UNUSED
COP              0x3FF0
COP.COPR          0
RESERV3FF1	 0x3FF1     RESERVED


.68HC05F8
; MC68HC05F8D/H  http://
; MC68HC05F8D.pdf

; RAM=256
; ROM=8192
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR		0x0000:0x0040
area DATA RAM		0x0040:0x0180
area BSS  UNUSED	0x0180:0xDE00
area DATA ROM		0xDE00:0xFE00
area DATA Self_Check	0xFE00:0xFFF0
area DATA USER_VEC	0xFFF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       Reset 
interrupt SWI 		0xFFFC       Software 
interrupt IRQ 		0xFFFA       External Interrupt 
interrupt TIMER_B 	0xFFF8       TIMER B
interrupt TIMER_A 	0xFFF6       TIMER A
interrupt SPI 		0xFFF4       SPI Interrupt 
interrupt MANCD 	0xFFF2       Manchester Coder
interrupt KB 		0xFFF0       Keyboard 


; INPUT/ OUTPUT PORTS
PORTA            0x0000     Port A data
PORTA.PA7         7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
PORTB            0x0001     Part B data
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTC            0x0002     Port C data
PORTC.PC7         7   Port C Data Bits 7
PORTC.PC6         6   Port C Data Bits 6
PORTC.PC5         5   Port C Data Bits 5
PORTC.PC4         4   Port C Data Bits 4
PORTC.PC3         3   Port C Data Bits 3
PORTC.PC2         2   Port C Data Bits 2
PORTC.PC1         1   Port C Data Bits 1
PORTC.PC0         0   Port C Data Bits 0
PORTD            0x0003     Port D data
PORTD.PD7         7   Port D Data Bits 7
PORTD.PD6         6   Port D Data Bits 6
PORTD.PD5         5   Port D Data Bits 5
PORTD.PD4         4   Port D Data Bits 4
PORTD.PD3         3   Port D Data Bits 3
PORTD.PD2         2   Port D Data Bits 2
PORTD.PD1         1   Port D Data Bits 1
PORTD.PD0         0   Port D Data Bits 0
PORTE            0x0004     Port E data
PORTE.PE7         7   Port E Data Bits 7
PORTE.PE6         6   Port E Data Bits 6
PORTE.PE5         5   Port E Data Bits 5
PORTE.PE4         4   Port E Data Bits 4
PORTE.PE3         3   Port E Data Bits 3
PORTE.PE2         2   Port E Data Bits 2
PORTE.PE1         1   Port E Data Bits 1
PORTE.PE0         0   Port E Data Bits 0
PORTF            0x0005     Port F data
PORTF.PF7         7   Port F Data Bits 7
PORTF.PF6         6   Port F Data Bits 6
PORTF.PF5         5   Port F Data Bits 5
PORTF.PF4         4   Port F Data Bits 4
PORTF.PF3         3   Port F Data Bits 3
PORTF.PF2         2   Port F Data Bits 2
PORTF.PF1         1   Port F Data Bits 1
PORTF.PF0         0   Port F Data Bits 0
PORTG            0x0006     Port G data
PORTG.PG1         1   Port G Data Bits 1
PORTG.PG0         0   Port G Data Bits 0
DDRA             0x0007     Port A data direction
DDRA.DDR7         7   Data Direction for Port A Bit 7
DDRA.DDR6         6   Data Direction for Port A Bit 6
DDRA.DDR5         5   Data Direction for Port A Bit 5
DDRA.DDR4         4   Data Direction for Port A Bit 4
DDRA.DDR3         3   Data Direction for Port A Bit 3
DDRA.DDR2         2   Data Direction for Port A Bit 2
DDRA.DDR1         1   Data Direction for Port A Bit 1
DDRA.DDR0         0   Data Direction for Port A Bit 0
DDRB             0x0008     Port B data direction
DDRB.DDR7         7   Data Direction for Port B Bit 7
DDRB.DDR6         6   Data Direction for Port B Bit 6
DDRB.DDR5         5   Data Direction for Port B Bit 5
DDRB.DDR4         4   Data Direction for Port B Bit 4
DDRB.DDR3         3   Data Direction for Port B Bit 3
DDRB.DDR2         2   Data Direction for Port B Bit 2
DDRB.DDR1         1   Data Direction for Port B Bit 1
DDRB.DDR0         0   Data Direction for Port B Bit 0
DDRC             0x0009     Port C data direction
DDRC.DDR7         7   Data Direction for Port C Bit 7
DDRC.DDR6         6   Data Direction for Port C Bit 6
DDRC.DDR5         5   Data Direction for Port C Bit 5
DDRC.DDR4         4   Data Direction for Port C Bit 4
DDRC.DDR3         3   Data Direction for Port C Bit 3
DDRC.DDR2         2   Data Direction for Port C Bit 2
DDRC.DDR1         1   Data Direction for Port C Bit 1
DDRC.DDR0         0   Data Direction for Port C Bit 0
DDRD             0x000A     Port D data direction
DDRD.DDR7         7   Data Direction for Port D Bit 7
DDRD.DDR6         6   Data Direction for Port D Bit 6
DDRD.DDR5         5   Data Direction for Port D Bit 5
DDRD.DDR4         4   Data Direction for Port D Bit 4
DDRD.DDR3         3   Data Direction for Port D Bit 3
DDRD.DDR2         2   Data Direction for Port D Bit 2
DDRD.DDR1         1   Data Direction for Port D Bit 1
DDRD.DDR0         0   Data Direction for Port D Bit 0
DDRE             0x000B     Port E data direction
DDRE.DDR7         7   Data Direction for Port E Bit 7
DDRE.DDR6         6   Data Direction for Port E Bit 6
DDRE.DDR5         5   Data Direction for Port E Bit 5
DDRE.DDR4         4   Data Direction for Port E Bit 4
DDRE.DDR3         3   Data Direction for Port E Bit 3
DDRE.DDR2         2   Data Direction for Port E Bit 2
DDRE.DDR1         1   Data Direction for Port E Bit 1
DDRE.DDR0         0   Data Direction for Port E Bit 0
DDRF             0x000C     Port F data direction
DDRF.DDR7         7   Data Direction for Port F Bit 7
DDRF.DDR6         6   Data Direction for Port F Bit 6
DDRF.DDR5         5   Data Direction for Port F Bit 5
DDRF.DDR4         4   Data Direction for Port F Bit 4
DDRF.DDR3         3   Data Direction for Port F Bit 3
DDRF.DDR2         2   Data Direction for Port F Bit 2
DDRF.DDR1         1   Data Direction for Port F Bit 1
DDRF.DDR0         0   Data Direction for Port F Bit 0
DDRG             0x000D     Port G data direction
DDRG.DDR1         1   Data Direction for Port G Bit 1
DDRG.DDR0         0   Data Direction for Port G Bit 0
UNUSED000E       0x000E     UNUSED
UNUSED000F       0x000F     UNUSED
SPCR             0x0010     SPI control
SPCR.SPIE         7   Serial Peripheral Interrupt Enable
SPCR.SPE          6   Serial Peripheral Enable
SPCR.MSTR         4   Master Bit
SPSR             0x0011     SPI status
SPSR.SPIF         7   Serial Peripheral Interface Flag
SPSR.DCOL         6   Data Collision
SPDR             0x0012     SPI data I/O
SPDR.SPDR7        7
SPDR.SPDR6        6
SPDR.SPDR5        5
SPDR.SPDR4        4
SPDR.SPDR3        3
SPDR.SPDR2        2
SPDR.SPDR1        1
SPDR.SPDR0        0
FCR              0x0013     Row frequency control
FCR.FCR4          4
FCR.FCR3          3
FCR.FCR2          2
FCR.FCR1          1
FCR.FCR0          0
FCC              0x0014     Column frequency control
FCC.FCC4          4
FCC.FCC3          3
FCC.FCC2          2
FCC.FCC1          1
FCC.FCC0          0
TNCR             0x0015     Tone control
TNCR.MS1          7   Mode Select 1
TNCR.MS0          6   Mode Select 0
TNCR.TGER         5   Tone Generation Enable for Row Paths
TNCR.TGEC         4   Tone Generation Enable for Column Paths
EE               0x0016     Event enable
EE.TIMH           7   Timer A Enable/Disable
EE.INTE1          6   External interrupt IRQ1 enabled/disabled 1
EE.INTE2          5   External interrupt IRQ1 enabled/disabled 2
Miscel           0x0017     Miscellaneous
Miscel.POR        7
Miscel.INTF1      6
Miscel.INTF2      5
Miscel.KEYF       4
TAC              0x0018     Timer A control
TAC.ICIE          7   Input Capture Interrupt Enable
TAC.OCIE          6   Output Compare Interrupt Enable
TAC.TOIE          5   Timer Overflow Interrupt Enable
TAC.IEDG          1   Input Edge
TAC.OLVL          0   Output Level Voltage Latch
TAS              0x0019     Timer A status
TAS.ICF           7   Input Capture Flag
TAS.OCF           6   Output Compare Flag
TAS.TOF           5   Timer Overflow Flag
TAICH            0x001A     Timer A input capture high
TAICL            0x001B     Timer A input capture low
TAOCH            0x001C     Timer A output compare high
TAOCL            0x001D     Timer A output compare low
TACH             0x001E     Timer A counter high
TACL             0x001F     Timer A counter low
TAACH            0x0020     Timer A alternative counter high
TAACL            0x0021     Timer A alternative counter low
TBC              0x0022     Timer B control
TBC.TMBE          7   Timer B Enable/Disable
TBC.TBOIE         6   Timer B Time-out Interrupt Enable/Disable
TBC.TCSB1         2   Timer B Clock Frequency Select 1
TBC.TCSB0         1   Timer B Clock Frequency Select 0
TBC.TUF           0   Timer B Underflow Flag
TBPCH            0x0023     Timer B preset counter high
TBPCL            0x0024     Timer B preset counter low
TBCH             0x0025     Timer B counter high
TBCL             0x0026     Timer B counter low
TBACH            0x0027     Timer B alternative counter high
TBACL            0x0028     Timer B alternative counter low
UNUSED0029       0x0029     UNUSED
UNUSED002A       0x002A     UNUSED
MCC              0x002B     Manchester coder control
MCC.NCE           7   Encoder Enable Bit
MCC.NIE           6   Encoder Interrupt Enable Bit
MCC.CIE           5   Encoding Complete Interrupt Enable Bit
MCC.DCE           4   Decoder Enable
MCC.DIE           3   Decode Interrupt Enable
MCC.BR1           1   Bit Rate Select 1
MCC.BR0           0   Bit Rate Select 0
MCS              0x002C     Manchester coder status
MCS.NCM           7   Encoder Data Register Empty Flag
MCS.NCC           6   Encoding Completion Flag
MCS.DCF           5   Decoder Data Register Full Flag
MCS.OVF           4   Overrun Flag
MED              0x002D     Manchester encoder data
MDD              0x002E     Manchester decoder data
UNUSED002F       0x002F     UNUSED
Reserv0030       0x0030     Reserved
UNUSED0031       0x0031     UNUSED
UNUSED0032       0x0032     UNUSED
UNUSED0033       0x0033     UNUSED
KC               0x0034     Keyboard control
KC.KEYE           7
KC.KEYX7          3
KC.KEYX6          2
KC.KEYX5          1
KC.KEYX4          0
SO               0x0035     System option
SO.TCSA1          6
SO.TCSA0          5
SO.INTN1          4
SO.INTN2          3
WTC              0x0036     Watchdog timer control
WTC.WDTE          7   Watchdog Timer Enable/Disable
WTC.KWDT          6   Kill Watchdog Timer Bit
WTC.WDTOF         5   Watchdog Timer Time-out Flag
WTC.WDT1          1   Time-out Period Select 1
WTC.WDT0          0   Time-out Period Select 0
UNUSED0037       0x0037     UNUSED
UNUSED0038       0x0038     UNUSED
UNUSED0039       0x0039     UNUSED
UNUSED003A       0x003A     UNUSED
UNUSED003B       0x003B     UNUSED
Reserv003C       0x003C     Reserved
Reserv003D       0x003D     Reserved
UNUSED003E       0x003E     UNUSED
UNUSED003F       0x003F     UNUSED


.68HC05G3
; http://
; HC05G3GRS.pdf

; RAM=768
; ROM=24K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR		  0x0000:0x0040
area DATA RAM		  0x0040:0x0340
area BSS  UNUSED	  0x0340:0x1000
area DATA MASK_ROM	  0x1000:0x7000
area BSS  UNUSED	  0x7000:0xFE00
area DATA SELF_TEST_ROM	  0xFE00:0xFEE0
area DATA TEST_VEC	  0xFEE0:0xFFF0
area DATA USER_VEC	  0xFFF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       RESET
interrupt SWI 		0xFFFC       SOFTWARE INTERRUPT 
interrupt IRQ 		0xFFFA       IRQ 
interrupt KWI 		0xFFF8       KEY WAKEUP INTERRUPT 
interrupt TIMER_1 	0xFFF6       TIMER 1 INTERRUPT 
interrupt TIMER_2 	0xFFF4       TIMER 2 INTERRUPT 
interrupt SPI 		0xFFF2       SPI1 AND SPI2 INTERRUPTS 
interrupt TBI 		0xFFF0       Time base interrupt 


; INPUT/ OUTPUT PORTS
PORTA         0x0000   PORT A DATA
PORTA.PA7       7  Port A Data Bits 7
PORTA.PA6       6  Port A Data Bits 6
PORTA.PA5       5  Port A Data Bits 5
PORTA.PA4       4  Port A Data Bits 4
PORTA.PA3       3  Port A Data Bits 3
PORTA.PA2       2  Port A Data Bits 2
PORTA.PA1       1  Port A Data Bits 1
PORTA.PA0       0  Port A Data Bits 0
PORTB         0x0001   PORT B DATA
PORTB.PB7       7  Port B Data Bits 7
PORTB.PB6       6  Port B Data Bits 6
PORTB.PB5       5  Port B Data Bits 5
PORTB.PB4       4  Port B Data Bits 4
PORTB.PB3       3  Port B Data Bits 3
PORTB.PB2       2  Port B Data Bits 2
PORTB.PB1       1  Port B Data Bits 1
PORTB.PB0       0  Port B Data Bits 0
PORTC         0x0002   PORT C DATA
PORTC.PC7       7  Port C Data Bits 7
PORTC.PC6       6  Port C Data Bits 6
PORTC.PC5       5  Port C Data Bits 5
PORTC.PC4       4  Port C Data Bits 4
PORTC.PC3       3  Port C Data Bits 3
PORTC.PC2       2  Port C Data Bits 2
PORTC.PC1       1  Port C Data Bits 1
PORTC.PC0       0  Port C Data Bits 0
PORTD         0x0003   PORT D DATA
PORTD.PD7       7  Port D Data Bits 7
PORTD.PD6       6  Port D Data Bits 6
PORTD.PD5       5  Port D Data Bits 5
PORTD.PD4       4  Port D Data Bits 4
PORTD.PD3       3  Port D Data Bits 3
PORTD.PD2       2  Port D Data Bits 2
PORTD.PD1       1  Port D Data Bits 1
PORTD.PD0       0  Port D Data Bits 0
PORTE         0x0004   PORT E DATA
PORTE.PE7       7  Port E Data Bits 7
PORTE.PE6       6  Port E Data Bits 6
PORTE.PE5       5  Port E Data Bits 5
PORTE.PE4       4  Port E Data Bits 4
PORTE.PE3       3  Port E Data Bits 3
PORTE.PE2       2  Port E Data Bits 2
PORTE.PE1       1  Port E Data Bits 1
PORTE.PE0       0  Port E Data Bits 0
PORTF         0x0005   PORT F DATA
PORTF.PF7       7  Port F Data Bits 7
PORTF.PF6       6  Port F Data Bits 6
PORTF.PF5       5  Port F Data Bits 5
PORTF.PF4       4  Port F Data Bits 4
PORTF.PF3       3  Port F Data Bits 3
PORTF.PF2       2  Port F Data Bits 2
PORTF.PF1       1  Port F Data Bits 1
PORTF.PF0       0  Port F Data Bits 0
PORTG         0x0006   PORT G DATA
PORTG.PG7       7  Port G Data Bits 7
PORTG.PG6       6  Port G Data Bits 6
PORTG.PG5       5  Port G Data Bits 5
PORTG.PG4       4  Port G Data Bits 4
PORTG.PG3       3  Port G Data Bits 3
PORTG.PG2       2  Port G Data Bits 2
PORTG.PG1       1  Port G Data Bits 1
PORTG.PG0       0  Port G Data Bits 0
PORTH         0x0007   PORT H DATA
PORTH.PH7       7  Port H Data Bits 7
PORTH.PH6       6  Port H Data Bits 6
PORTH.PH5       5  Port H Data Bits 5
PORTH.PH4       4  Port H Data Bits 4
PORTH.PH3       3  Port H Data Bits 3
PORTH.PH2       2  Port H Data Bits 2
PORTH.PH1       1  Port H Data Bits 1
PORTH.PH0       0  Port H Data Bits 0
INTCR         0x0008   INTERRUPT CONTROL
INTCR.IRQ1E     7  IRQ1 Interrupt Enable
INTCR.IRQ2E     6  IRQ2 Interrupt Enable
INTCR.KWIE      4  Key Wakeup Interrupt (KWI) Enable
INTCR.IRQ1S     3  IRQ1 Select Edge-Sensitive Only
INTCR.IRQ2S     2  IRQ2 Select Edge Sensitive Only
INTSR         0x0009   INTERRUPT STATUS
INTSR.IRQ1F     7  IRQ1 Interrupt Flag
INTSR.IRQ2F     6  IRQ2 Interrupt Flag
INTSR.KWIF      4  Key Wakeup Interrupt Flag
INTSR.RIRQ1     3  Reset IRQ1 Flag
INTSR.RIRQ2     2  Reset IRQ2 Flag
INTSR.RKWIF     0  Reset KWI Flag
SPCR1         0x000A   SPI1 CONTROL
SPCR1.SPIE1     7  SPI Interrupt Enable
SPCR1.SPE1      6  SPI Enable
SPCR1.DORD1     5  Data transmission ORDer
SPCR1.MSTR1     4  MaSTeR mode select
SPCR1.SPR1      0  SPI 1 clock rate select
SPSR1         0x000B   SPI1 STATUS
SPSR1.SPIF1     7  Serial transfer complete flag
SPSR1.DCOL1     6  Data COLlision
SPDR1         0x000C   SPI1 DATA
SPCR2         0x000D   SPI2 CONTROL
SPCR2.SPIE2     7  SPI Interrupt Enable
SPCR2.SPE2      6  SPI Enable
SPCR2.DORD2     5  Data transmission ORDer
SPCR2.MSTR2     4  MaSTeR mode select
SPCR2.SPR2      0  SPI 2 clock rate select
SPSR2         0x000E   SPI2 STATUS
SPSR2.SPIF2     7  Serial transfer complete flag
SPSR2.DCOL2     6  Data COLlision
SPDR2         0x000F   SPI2 DATA
TBCR1         0x0010   TIME BASE CONTROL REGISTER 1
TBCR1.TBCLK     7  Time Base Clock
TBCR1.T3R1      3  Prescale Rate or Clock select bits for PWM 1
TBCR1.T3R0      2  Prescale Rate or Clock select bits for PWM 0
TBCR1.T2R1      1  Preschool Rate Select bits for Timer 2 1
TBCR1.T2R0      0  Preschool Rate Select bits for Timer 2 0
TBCR2         0x0011   TIME BASE CONTROL REGISTER 2
TBCR2.TBIF      7  Time Base Interrupt Flag
TBCR2.TBIE      6  Time Base Interrupt Enable
TBCR2.TBR1      5  Time Base Interrupt Rate Select 1
TBCR2.TBR0      4  Time Base Interrupt Rate Select 0
TBCR2.RTBIF     3  Reset TB Interrupt Flag
TBCR2.COPE      1  COP Enable
TBCR2.COPC      0  COP Clear
TCR           0x0012   TIMER CONTROL
TCR.ICIE        7  Input Capture Interrupt Enable
TCR.OC1IE       6  Output Compare 1 Interrupt Enable
TCR.TOIE        5  Timer Overflow Interrupt Enable
TCR.IEDG        1  Input Edge
TCR.OLVL        0  Output Level
TSR           0x0013   TIMER STATUS
TSR.ICF         7  Input Capture Flag
TSR.OC1F        6  Output Compare 1 Flag
TSR.TOF         5  Timer Overflow Flag
ICH           0x0014   OUTPUT COMPARE REG0 (H)
ICL           0x0015   OUTPUT COMPARE REG0 (L)
OC1H          0x0016   OUTPUT COMPARE REG1 (H)
OC1L          0x0017   OUTPUT COMPARE REG1 (L)
TCNTH         0x0018   TIMER COUNTER (H)
TCNTL         0x0019   TIMER COUNTER (L)
ACNTH         0x001A   ALTERNATE COUNTER (H)
ACNTL         0x001B   ALTERNATE COUNTER (L)
TCR2          0x001C   TIMER CONTROL REG2
TCR2.TI2IE      7  Timer Input 2 Interrupt Enable
TCR2.OC2IE      6  Compare 2 Interrupt Enable
TCR2.T2CLK      4  Timer 2 Clock Select
TCR2.IM2        3  Timer Input 2 Mode Select
TCR2.IL2        2  Timer Input 2 active edge (Level) select
TCR2.OE2        1  Timer Output 2 (EVO) Output Enable
TCR2.OL2        0  Timer Output 2 Edge select for synchronization
TSR2          0x001D  TIMER STATUS REG2
TSR2.TI2F       7  Timer Input 2 (EVI) Interrupt Flag
TSR2.OC2F       6  Compare 2 Interrupt Flag
TSR2.RTI2F      3  Reset Timer Input 2 Flag
TSR2.ROC2F      2  Reset Output Compare 2 Flag
OC2           0x001E  OUTPUT COMPARE REG2
TCNT2         0x001F  TIMER COUNTER 2
Reserv0020    0x0020  RESERVED
Reserv0021    0x0021  RESERVED
Reserv0022    0x0022  RESERVED
Reserv0023    0x0023  RESERVED
Reserv0024    0x0024  RESERVED
Reserv0025    0x0025  RESERVED
Reserv0026    0x0026  RESERVED
Reserv0027    0x0027  RESERVED
Reserv0028    0x0028  RESERVED
Reserv0029    0x0029  RESERVED
Reserv002A    0x002A  RESERVED
Reserv002B    0x002B  RESERVED
Reserv002C    0x002C  RESERVED
Reserv002D    0x002D  RESERVED
Reserv002E    0x002E  RESERVED
Reserv002F    0x002F  RESERVED
Reserv0030    0x0030  RESERVED
Reserv0031    0x0031  RESERVED
Reserv0032    0x0032  RESERVED
Reserv0033    0x0033  RESERVED
PWMCR         0x0034  PWM OUT CONTROL
PWMCR.CH3       3
PWMCR.CH2       2
PWMCR.CH1       1
PWMCR.CH0       0
PWMCNT        0x0035  PWM COUNTER
PWMDR0        0x0036  PWM CHANNEL 0
PWMDR1        0x0037  PWM CHANNEL 1
PWMDR2        0x0038  PWM CHANNEL 2
PWMDR3        0x0039  PWM CHANNEL 3
ADR           0x003A  A/D DATA REG
ADSCR         0x003B  A/D STATUS/CONTROL REG
ADSCR.COCO      7  CONVERSIONS COMPLETE
ADSCR.ADRC      6  RC OSCILLATOR ON
ADSCR.ADON      5  A/D ON
ADSCR.CH3       3  CHANNEL SELECT BITS 3
ADSCR.CH2       2  CHANNEL SELECT BITS 2
ADSCR.CH1       1  CHANNEL SELECT BITS 1
ADSCR.CH0       0  CHANNEL SELECT BITS 0
PORTJ         0x003C  PORT J DATA
PORTJ.PJ3       3  Port J Data Bits 3
PORTJ.PJ2       2  Port J Data Bits 2
PORTJ.PJ1       1  Port J Data Bits 1
PORTJ.PJ0       0  Port J Data Bits 0
RESERV003D    0x003D  RESERVED
MISC          0x003E  MISCELLANEOUS REGISTER
MISC.FTUP       7  OSC Time Up Flag
MISC.STUP       6  XOSC Time Up Flag
MISC.SYS1       3  System Clock Select 1
MISC.SYS0       2  System Clock Select 0
MISC.FOSCE      1  Fast (Main) Oscillator Enable
MISC.OPTM       0  Option Map Select
Reserv003F    0x003F  RESERVED


.68HC05G4
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC05H12
; http://
; HC05H12GRS.pdf

; RAM=256
; ROM=12032
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR      	0x0000:0x0050
area DATA RAM      	0x0050:0x0150
area BSS  UNUSED   	0x0150:0x0400
area DATA EEPROM   	0x0400:0x0500
area BSS  UNUSED   	0x0500:0x1000
area DATA ROM      	0x1000:0x3F00
area DATA MONITOR_ROM  	0x3F00:0x3FF0
area DATA USER_VEC 	0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Reset
interrupt SWI               0x3FFC      Software Interrupt
interrupt KEY               0x3FFA      KEY
interrupt CTimer            0x3FF8      CTimer
interrupt TIMER_1           0x3FF6      8-Bit Timer Interrupt
interrupt TIMER_2           0x3FF4      16-Bit Timer1 Interrupt
interrupt SPI               0x3FF2      SPI
interrupt SCI               0x3FF0      SCI


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A Data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001     Port B Data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002     Port C Data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003     Port D Data
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004     Port A Data Direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005     Port B Data Direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006     Port C Data Direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
PCC             0x0007     Port C Control
PCC.TCMP1        5
PCC.TCMP0        4
CTSCR           0x0008     Core Timer Control/Status
CTSCR.TOF        7   Timer Over Flow
CTSCR.RTIF       6   Real Time Interrupt Flag
CTSCR.TOFE       5   Timer Over Flow Enable
CTSCR.RTIE       4   Real Time Interrupt Enable
CTSCR.RTOF       3   Reset Timer Overflow Flag
CTSCR.RTIF       2   Reset Real Time Interrupt Flag
CTSCR.RT1        1   Real Time Interrupt Rate Select 1
CTSCR.RT0        0   Real Time Interrupt Rate Select 0
CTCR            0x0009     Core Timer Counter
UNUSED000A      0x000A     UNUSED
UNUSED000B      0x000B     UNUSED
UNUSED000C      0x000C     UNUSED
PAIED           0x000D     Port A Interrupt Edge
PAIED.EDGE7      7   Port A Interrupt Edge 7
PAIED.EDGE6      6   Port A Interrupt Edge 6
PAIED.EDGE5      5   Port A Interrupt Edge 5
PAIED.EDGE4      4   Port A Interrupt Edge 4
PAIED.EDGE3      3   Port A Interrupt Edge 3
PAIED.EDGE2      2   Port A Interrupt Edge 2
PAIED.EDGE1      1   Port A Interrupt Edge 1
PAIED.EDGE0      0   Port A Interrupt Edge 0
PAICR           0x000E     Port A Interrupt Control
PAICR.PAIE7      7   Port A Interrupt Enable 7
PAICR.PAIE6      6   Port A Interrupt Enable 6
PAICR.PAIE5      5   Port A Interrupt Enable 5
PAICR.PAIE4      4   Port A Interrupt Enable 4
PAICR.PAIE3      3   Port A Interrupt Enable 3
PAICR.PAIE2      2   Port A Interrupt Enable 2
PAICR.PAIE1      1   Port A Interrupt Enable 1
PAICR.PAIE0      0   Port A Interrupt Enable 0
PAISR           0x000F     Port A Interrupt Status
PAISR.PAIF7      7   Port A Interrupt Flags 7
PAISR.PAIF6      6   Port A Interrupt Flags 6
PAISR.PAIF5      5   Port A Interrupt Flags 5
PAISR.PAIF4      4   Port A Interrupt Flags 4
PAISR.PAIF3      3   Port A Interrupt Flags 3
PAISR.PAIF2      2   Port A Interrupt Flags 2
PAISR.PAIF1      1   Port A Interrupt Flags 1
PAISR.PAIF0      0   Port A Interrupt Flags 0
PWMD0           0x0010     PWM Data 0
PWMD1           0x0011     PWM Data 1
PWMD2           0x0012     PWM Data 2
PWMD3           0x0013     PWM Data 3
PWMD4           0x0014     PWM Data 4
PWMD5           0x0015     PWM Data 5
PWMD6           0x0016     PWM Data 6
PWMD7           0x0017     PWM Data 7
PWMCTL          0x0018     PWM Control/Sign
PWMCTL.PWMRS     7   PWM Reset
PWMCTL.PWMC3     6   PWM Clock Rate 3
PWMCTL.PWMC2     5   PWM Clock Rate 2
PWMCTL.PWMC1     4   PWM Clock Rate 1
PWMCTL.SIGN3     3   Sign of the PWM Channel 3
PWMCTL.SIGN2     2   Sign of the PWM Channel 2
PWMCTL.SIGN1     1   Sign of the PWM Channel 1
PWMCTL.SIGN0     0   Sign of the PWM Channel 0
PWMEN           0x0019     PWM Channel Enable
PWMEN.PWME7      7   PWM Channel Enable 7
PWMEN.PWME6      6   PWM Channel Enable 6
PWMEN.PWME5      5   PWM Channel Enable 5
PWMEN.PWME4      4   PWM Channel Enable 4
PWMEN.PWME3      3   PWM Channel Enable 3
PWMEN.PWME2      2   PWM Channel Enable 2
PWMEN.PWME1      1   PWM Channel Enable 1
PWMEN.PWME0      0   PWM Channel Enable 0
PWMPOL          0x001A     PWM Channel Polarity
PWMPOL.PPOL7     7   PWM Polarity 7
PWMPOL.PPOL6     6   PWM Polarity 6
PWMPOL.PPOL5     5   PWM Polarity 5
PWMPOL.PPOL4     4   PWM Polarity 4
PWMPOL.PPOL3     3   PWM Polarity 3
PWMPOL.PPOL2     2   PWM Polarity 2
PWMPOL.PPOL1     1   PWM Polarity 1
PWMPOL.PPOL0     0   PWM Polarity 0
UNUSED001B      0x001B     UNUSED
EEPCR           0x001C     EEPROM Control
EEPCR.EEOSC      4   EEPROM RC Oscillator Control
EEPCR.ER1        3   Erase Select Bits 1
EEPCR.EER0       2   Erase Select Bits 0
EEPCR.EELAT      1   EEPROM Programming Latch
EEPCR.EEPGM      0   EEPROM Programming Power Enable
RESERV001D      0x001D     RESERVED
UNUSED001E      0x001E     UNUSED
TEST            0x001F     TEST
T1IC1H          0x0020     Timer 1 Input Capture1 High
T1IC1L          0x0021     Timer 1 Input Capture1 Low
T1OC1H          0x0022     Timer 1 Output Compare1 High
T1OC1L          0x0023     Timer 1 Output Compare1 Low
T1IC2H          0x0024     Timer 1 Input Capture2 High
T1IC2L          0x0025     Timer 1 Input Capture2 Low
T1OC2H          0x0026     Timer 1 Output Compare2 High
T1OC2L          0x0027     Timer 1 Output Compare2 Low
T1CH            0x0028     Timer 1 Counter High
T1CL            0x0029     Timer 1 Counter Low
T1ACH           0x002A     Timer 1 Alternate Counter High
T1ACL           0x002B     Timer 1 Alternate Counter Low
T1C1            0x002C     Timer 1 Control 1
T1C1.ICI1E       7   Input Capture 1 Interrupt Enable
T1C1.ICI2E       6   Input Capture 2 Interrupt Enable
T1C1.OCI1E       5   Output Compare 1 Interrupt Enable
T1C1.TOIE        4   Timer Overflow Interrupt Enable
T1C1.CO1E        3   Timer Compare 1 Output Enable
T1C1.IEDG1       2   Input Edge 1
T1C1.IEDG2       1   Input Edge 2
T1C1.OLVL1       0   Output Level 1
T1C2            0x002D     Timer 1 Control 2
T1C2.OC2IE       5   Output Compare 2 Interrupt Enable
T1C2.CO2E        3   Timer Compare 2 Output Enable
T1C2.OLVL2       0   Output Level 2
T1S             0x002E     Timer 1 Status
T1S.IC1F         7   Input Capture 1 Flag
T1S.IC2F         6   Input Capture 2 Flag
T1S.OC1F         5   Output Compare 1 Flag
T1S.TOF          4   Timer Overflow Flag
T1S.TCAP1        3   Timer Capture 1
T1S.TCAP2        2   Timer Capture 2
T1S.OC2F         1   Output Compare 2 Flag
UNUSED002F      0x002F     UNUSED
T2IC1H          0x0030     Timer 2 Input Capture1 High
T2IC1L          0x0031     Timer 2 Input Capture1 Low
T2OC1H          0x0032     Timer 2 Output Compare1 High
T2OC1L          0x0033     Timer 2 Output Compare1 Low
T2IC2H          0x0034     Timer 2 Input Capture2 High
T2IC2L          0x0035     Timer 2 Input Capture2 Low
T2OC2H          0x0036     Timer 2 Output Compare2 High
T2OC2L          0x0037     Timer 2 Output Compare2 Low
T2CH            0x0038     Timer 2 Counter High
T2CL            0x0039     Timer 2 Counter Low
T2ACH           0x003A     Timer 2 Alternate Counter High
T2ACL           0x003B     Timer 2 Alternate Counter Low
T2C1            0x003C     Timer 2 Control 1
T2C1.ICI1E       7
T2C1.ICI2E       6
T2C1.OCI1E       5
T2C1.TOIE        4
T2C1.CO1E        3
T2C1.IEDG1       2
T2C1.IEDG2       1
T2C1.OLVL1       0
T2C2            0x003D     Timer 2 Control 2
T2C2.OC2IE       5
T2C2.CO2E        3
T2C2.OLVL2       0
T2S             0x003E     Timer 2 Status
T2S.IC1F         7
T2S.IC2F         6
T2S.OC1F         5
T2S.TOF          4
T2S.TCAP1        3
T2S.TCAP2        2
T2S.OC2F         1
UNUSED003F      0x003F     UNUSED
PORTE           0x0040     Port E Data
PORTE.PE7        7   Port E Data Bits 7
PORTE.PE6        6   Port E Data Bits 6
PORTE.PE5        5   Port E Data Bits 5
PORTE.PE4        4   Port E Data Bits 4
PORTE.PE3        3   Port E Data Bits 3
PORTE.PE2        2   Port E Data Bits 2
PORTE.PE1        1   Port E Data Bits 1
PORTE.PE0        0   Port E Data Bits 0
PORTEM          0x0041     Port E Mismatch
PORTF           0x0042     Port F Data
PORTF.PF3        3   Port F Data Bits 3
PORTF.PF2        2   Port F Data Bits 2
PORTF.PF1        1   Port F Data Bits 1
PORTF.PF0        0   Port F Data Bits 0
PORTFM          0x0043     Port F Mismatch
SPIC            0x0044     SPI Control
SPIC.SPIE        7   SPI Interrupt Enable
SPIC.SPE         6   SPI System Enable
SPIC.DOD         5   Direction of Data Flow (in or out of the Serial Shift Register)
SPIC.MSTR        4   Master/Slave Mode Select
SPIC.CPOL        3   Clock Polarity
SPIC.CPHA        2   Clock Phase
SPIC.SPR1        1   SPI Clock Rate Selects 1
SPIC.SPR0        0   SPI Clock Rate Selects 0
SPIS            0x0045     SPI Status
SPIS.SPIF        7   SPI Interrupt Request Flag
SPIS.WCOL        6   Write Collision
SPID            0x0046     SPI Data
SCID            0x0047     SCI Data
SCIC1           0x0048     SCI Control 1
SCIC1.R8         7   Receive Data Bit 8
SCIC1.T8         6   Transmit Data Bit 8
SCIC1.M          4   Mode (Select Character Format)
SCIC1.WAKE       3   Wake-up Mode Select
SCIC2           0x0049     SCI Control 2
SCIC2.TIE        7   Transmit Interrupt Enable
SCIC2.TCIE       6   Transmit Complete Interrupt Enable
SCIC2.RIE        5   Receiver Interrupt Enable
SCIC2.ILIE       4   Idle Line Interrupt Enable
SCIC2.TE         3   Transmitter Enable
SCIC2.RE         2   Receiver Enable
SCIC2.RWU        1   Receiver Wake-up
SCIC2.SBK        0   Send Break
SCIS            0x004A     SCI Status
SCIS.TDRE        7   Transmit Data Register Empty Flag
SCIS.TC          6   Transmit Complete Flag
SCIS.RDRF        5   Receive Data Register Full Flag
SCIS.IDLE        4   Idle Line Detected Flag
SCIS.OR          3   Overrun Error Flag
SCIS.NF          2   Noise Error Flag
SCIS.FE          1   Framing Error Flag
SCIB            0x004B     SCI BAUD
SCIB.TCLR        7   Clear Baud Rate Counters (for test purposes only)
SCIB.SPP         6   SPI Prescaler bit
SCIB.SCP1        5   First Serial Prescaler Select bits 1
SCIB.SCP0        4   First Serial Prescaler Select bits 0
SCIB.RCKB        3   SCI Receive Baud Rate Clock Test
SCIB.SCR2        2   SCI Rate Select bits of the second prescaler stage 2
SCIB.SCR1        1   SCI Rate Select bits of the second prescaler stage 1
SCIB.SCR0        0   SCI Rate Select bits of the second prescaler stage 0
UNUSED004C      0x004C     UNUSED
SC              0x004D     System Control
SC.SC            4   System Clock Option
SC.IRQ           3   IRQ Sensitivity
SC.ECLK          0   Internal System Clock Available
ADD             0x004E     A_D Data
ADSC            0x004F     A_D Status_Control
ADSC.COCO        7   Conversions Complete
ADSC.ADRC        6   RC Oscillator On
ADSC.ADON        5   A/D On
ADSC.CH3         3   Channel Select Bit 3
ADSC.CH2         2   Channel Select Bit 2
ADSC.CH1         1   Channel Select Bit 1
ADSC.CH0         0   Channel Select Bit 0


.68HC05J1A
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05J1A&nodeId=01M98633
; MC68HC05J1A.pdf

; RAM=64
; ROM=1240
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020     I/O Register
area BSS  UNUSED      0x0020:0x00C0     Reserved
area DATA RAM         0x00C0:0x0100     Ram
area BSS  UNUSED      0x0100:0x0300
area DATA ROM         0x0300:0x07D0     User Rom
area DATA ROM_TEST    0x07D0:0x07F0     Test Rom
area DATA TEST        0x07F0:0x07F8     RESERVED FOR TEST (ROM)
area DATA USER_VEC    0x07F8:0x0800     User Vectors


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Processor reset
interrupt SWI               0x07FC      Software interrupt
interrupt IRQ               0x07FA      External Interrupt
interrupt TIMER             0x07F8      Timer         


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
UNUSED0002            0x0002    UNUSED
UNUSED0003            0x0003    UNUSED
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
UNUSED0006            0x0006    UNUSED
UNUSED0007            0x0007    UNUSED
TSCR                  0x0008  Timer Status and Control
TSCR.TOF               7   Timer Overflow Flag
TSCR.RTIF              6   Real-Time Interrupt Flag
TSCR.TOIE              5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE              4   Real-Time Interrupt Enable Bit
TSCR.TOFR              3   Timer Overflow Flag Reset Bit
TSCR.RTIFR             2   Real-Time Interrupt Flag Reset Bit
TSCR.RT1               1   Real-Time Interrupt Select Bits 1
TSCR.RT0               0   Real-Time Interrupt Select Bits 0
TCNTR                 0x0009  Timer Counter
ISCR                  0x000A  IRQ Status and Control
ISCR.IRQE              7   External Interrupt Request Enable Bit
ISCR.IRQF              3   External Interrupt Request Flag
ISCR.IRQR              1   Interrupt Request Reset Bit
UNUSED000B            0x000B    UNUSED
UNUSED000C            0x000C    UNUSED
UNUSED000D            0x000D    UNUSED
UNUSED000E            0x000E    UNUSED
UNUSED000F            0x000F    UNUSED
PDRA                  0x0010    Pulldown Register Port A
PDRA.PDRA7             7   Port A Pulldown Inhibit Bits 7
PDRA.PDRA6             6   Port A Pulldown Inhibit Bits 6
PDRA.PDRA5             5   Port A Pulldown Inhibit Bits 5
PDRA.PDRA4             4   Port A Pulldown Inhibit Bits 4
PDRA.PDRA3             3   Port A Pulldown Inhibit Bits 3
PDRA.PDRA2             2   Port A Pulldown Inhibit Bits 2
PDRA.PDRA1             1   Port A Pulldown Inhibit Bits 1
PDRA.PDRA0             0   Port A Pulldown Inhibit Bits 0
PDRB                  0x0011     Pulldown Register Port B
PDRB.PDRB5             5   Port B Pulldown Inhibit Bits 5
PDRB.PDRB4             4   Port B Pulldown Inhibit Bits 4
PDRB.PDRB3             3   Port B Pulldown Inhibit Bits 3
PDRB.PDRB2             2   Port B Pulldown Inhibit Bits 2
PDRB.PDRB1             1   Port B Pulldown Inhibit Bits 1
PDRB.PDRB0             0   Port B Pulldown Inhibit Bits 0
UNUSED0012            0x0012    UNUSED
UNUSED0013            0x0013    UNUSED
UNUSED0014            0x0014    UNUSED
UNUSED0015            0x0015    UNUSED
UNUSED0016            0x0016    UNUSED
UNUSED0017            0x0017    UNUSED
UNUSED0018            0x0018    UNUSED
UNUSED0019            0x001A    UNUSED
UNUSED001A            0x001B    UNUSED
UNUSED001B            0x001C    UNUSED
UNUSED001C            0x001D    UNUSED
UNUSED001D            0x001E    UNUSED
UNUSED001E            0x0012    UNUSED
RESERV001F            0x001F   RESERVED
COPR                  0x07F0   COP Register
COPR.COPC              0   COP Clear Bit
RESERV07F1            0x07F1   RESERVED
RESERV07F2            0x07F2   RESERVED
RESERV07F3            0x07F3   RESERVED
RESERV07F4            0x07F4   RESERVED
RESERV07F5            0x07F5   RESERVED
RESERV07F6            0x07F6   RESERVED
RESERV07F7            0x07F7   RESERVED


.68HC05J5
; http://e-www.motorola.com/brdata/PDFDB/docs/HC05J5GRS.pdf
; HC05J5GRS.pdf

; RAM=64
; ROM=1240
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR       0x0000:0x0020
area BSS  UNUSED    0x0020:0x00C0
area DATA RAM       0x00C0:0x0100
area BSS  UNUSED    0x0100:0x0300
area CODE ROM       0x0300:0x07D0
area DATA ROM_TEST  0x07D0:0x07F0
area DATA TEST      0x07F0:0x07F8   ROM Reserved for Test
area DATA USER_VEC  0x07F8:0x0800


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Reset  
interrupt SWI               0x07FC      SWI               
interrupt IRQ               0x07FA      IRQ/IRQ2        
interrupt Timer             0x07F8      Timer       
           

; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
UNUSED0002            0x0002   UNUSED
UNUSED0003            0x0003   UNUSED
DDRA                  0x0004   Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005   Port B data direction
DDRB.SLOWEA            7   Slow Transition Enabled
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
UNUSED0006            0x0006   UNUSED
UNUSED0007            0x0007   UNUSED
TCSR                  0x0008  Timer Ctrl/Status
TCSR.TOF               7   Timer Overflow Flag
TCSR.RTIF              6   Real Time Interrupt Flag
TCSR.TOFE              5   Timer Overflow Enable
TCSR.RTIE              4   Real Time Interrupt Enable
TCSR.TOFR              3   Timer Overflow Acknowledge
TCSR.RTIFR             2   Real Time Interrupt Acknowledge
TCSR.RT1               1   Real Time Interrupt Rate Select 1
TCSR.RT0               0   Real Time Interrupt Rate Select 0
TCR                   0x0009   Timer Counter
TCR.TMR7               7
TCR.TMR6               6
TCR.TMR5               5
TCR.TMR4               4
TCR.TMR3               3
TCR.TMR2               2
TCR.TMR1               1 
TCR.TMR0               0
ICSR                  0x000A   IRQ Control/Status
ICSR.IRQE              7   IRQ Interrupt Enable
ICSR.IRQE1             6   PA7 Interrupt Enable
ICSR.IRQF              3   IRQ Interrupt Request Flag
ICSR.IRQF1             2   PA7 Interrupt Request Flag
ICSR.IRQR              1   IRQ Interrupt Acknowledge
ICSR.IRQR1             0   PA7 Interrupt Acknowledge
UNUSED000B            0x000B   UNUSED
UNUSED000C            0x000C   UNUSED
UNUSED000D            0x000D   UNUSED
UNUSED000E            0x000E   UNUSED
UNUSED000F            0x000F   UNUSED
PDURA                 0x0010    Port A Pull Down/Up
PDURA.PURA7            7
PDURA.PURA6            6
PDURA.PURA5            5
PDURA.PURA4            4
PDURA.PURA3            3
PDURA.PURA2            2
PDURA.PURA1            1
PDURA.PURA0            0
PDURB                 0x0011   Port B Pull Down/Up
PDURB.PURB5            5
PDURB.PURB4            4
PDURB.PURB3            3
PDURB.PURB2            2
PDURB.PURB1            1
PDURB.PURB0            0
UNUSED0012            0x0012   UNUSED
UNUSED0013            0x0013   UNUSED
UNUSED0014            0x0014   UNUSED
UNUSED0015            0x0015   UNUSED
UNUSED0016            0x0016   UNUSED
UNUSED0017            0x0017   UNUSED
UNUSED0018            0x0018   UNUSED
UNUSED0019            0x0019   UNUSED
UNUSED001A            0x001A   UNUSED
UNUSED001B            0x001B   UNUSED
UNUSED001C            0x001C   UNUSED
UNUSED001D            0x001D   UNUSED
UNUSED001E            0x001E   UNUSED
TEST                  0x001F   Reserv for test
COP                   0x07F0  COP Watchdog Timer
COP.COPR               0 
RESERV07F1            0x07F1    RESERVED
RESERV07F2            0x07F2    RESERVED
RESERV07F3            0x07F3    RESERVED
RESERV07F4            0x07F4    RESERVED
RESERV07F5            0x07F5    RESERVED
RESERV07F6            0x07F6    RESERVED
RESERV07F7            0x07F7    RESERVED


.68HC05J5A
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05J5A&nodeId=01M98633
; HC05J5AGRS.pdf

; EPROM=0
; ROM=2560
; RAM=128
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x0080
area DATA RAM         0x0080:0x0100
area BSS  UNUSED      0x0100:0x0300
area CODE ROM         0x0300:0x0D00
area BSS  UNUSED      0x0D00:0x0E00
area DATA TEST_VEC    0x0E00:0x0FF0
area DATA USER_VEC    0x0FF0:0x1000


; Interrupt and reset vector assignments
interrupt __RESET           0x0FFE      Reset  
interrupt SWI               0x0FFC      SWI               
interrupt IRQ               0x0FFA      IRQ/IRQ2        
interrupt MFT               0x0FF8      MFT         
interrupt Timer1            0x0FF6      Timer1 Interrupt


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
T1CC                  0x0002   Timer Capture Control
T1CC.TCAPS             7   Timer Input Capture Comparator Enable
UNUSED0003            0x0003   UNUSED
DDRA                  0x0004   Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005   Port B data direction
DDRB.SLOWEA            7   Slow Transition Enable
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
UNUSED0006            0x0006   UNUSED
UNUSED0007            0x0007   UNUSED
TCSR                  0x0008  MFT Ctrl/Status
TCSR.TOF               7   Timer Overflow Flag
TCSR.RTIF              6   Real Time Interrupt Flag
TCSR.TOFE              5   Timer Overflow Enable
TCSR.RTIE              4   Real Time Interrupt Enable
TCSR.TOFR              3   Timer Overflow Acknowledge
TCSR.RTIFR             2   Real Time Interrupt Acknowledge
TCSR.RT1               1   Real Time Interrupt Rate Select 1
TCSR.RT0               0   Real Time Interrupt Rate Select 0
TCR                   0x0009   MFT Counter
TCR.TMR7               7
TCR.TMR6               6
TCR.TMR5               5
TCR.TMR4               4
TCR.TMR3               3
TCR.TMR2               2
TCR.TMR1               1 
TCR.TMR0               0
ICSR                  0x000A   IRQ Control/Status
ICSR.IRQE              7   IRQ Interrupt Enable
ICSR.IRQE1             6   PA7 Interrupt Enable
ICSR.IRQF              3   IRQ Interrupt Request Flag
ICSR.IRQF1             2   PA7 Interrupt Request Flag
ICSR.IRQR              1   IRQ Interrupt Acknowledge
ICSR.IRQR1             0   PA7 Interrupt Acknowledge
UNUSED000B            0x000B   UNUSED
UNUSED000C            0x000C   UNUSED
UNUSED000D            0x000D   UNUSED
UNUSED000E            0x000E   UNUSED
UNUSED000F            0x000F   UNUSED
PDURA                 0x0010    Port A Pull Down/Up
PDURA.PURA7            7
PDURA.PURA6            6
PDURA.PURA5            5
PDURA.PURA4            4
PDURA.PURA3            3
PDURA.PURA2            2
PDURA.PURA1            1
PDURA.PURA0            0
PDURB                 0x0011   Port B Pull Down/Up
PDURB.PURB5            5
PDURB.PURB4            4
PDURB.PURB3            3
PDURB.PURB2            2
PDURB.PURB1            1
PDURB.PURB0            0
T1CR                  0x0012    Timer1 Control
T1CR.ICIE              7   INPUT CAPTURE INTERRUPT ENABLE
T1CR.T1OIE             5   TIMER OVERFLOW INTERRUPT ENABLE
T1CR.IEDGE             1   INPUT CAPTURE EDGE SELECT
T1SR                  0x0013    Timer1 Status
T1SR.ICF               7   INPUT CAPTURE FLAG
T1SR.T1OF              5   TIMER1 OVERFLOW FLAG
ICH                   0x0014    Input Capture High
ICL                   0x0015    Input Capture Low
UNUSED0016            0x0016    UNUSED
UNUSED0017            0x0017    UNUSED
TCNTH                 0x0018    Timer1 Counter High
TCNTL                 0x0019    Timer1 Counter Low
ACNTH                 0x001A    Alt Counter High
ACNTL                 0x001B    Alt Counter Low
UNUSED001C            0x001C    UNUSED
UNUSED001D            0x001D    UNUSED
RESERV001E            0x001E    Reserved
RESERV001F            0x001F    Reserved
COP                   0x0FF0    COP Watchdog Timer
COP.COPR               0
RESERV0FF1            0x0FF1    Reserved
RESERV0FF2            0x0FF2    Reserved
RESERV0FF3            0x0FF3    Reserved
RESERV0FF4            0x0FF4    Reserved
RESERV0FF5            0x0FF5    Reserved


.68HC05JB3
; HC05JB3GRS/H  http://
; HC05JB3GRS.pdf

; RAM=144
; ROM=2.5K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR      		0x0000:0x0040
area BSS  Unused   		0x0040:0x0070
area DATA RAM      		0x0070:0x0100
area BSS  Unused   		0x0100:0x1400
area DATA ROM      		0x1400:0x1E00
area DATA Self_Check_ROM	0x1E00:0x1FF0   Self-Check ROM
area DATA USER_VEC 		0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset
interrupt SWI               0x1FFC      Software Interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt USB               0x1FF8      USB Interrupt
interrupt TIMER1            0x1FF6      Timer1
interrupt MFT               0x1FF4      MFT Interrupt


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003     UNUSED
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.SLOWE             3   Slow Transition Enable
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.OCMPO             7   OCMP Output Enable
DDRC.VROFF             6   USB 3.3V Voltage Reference
DDRC.DDRC3             3   PC3 Data Direction
DDRC.DDRC2             2   PC2 Data Direction
DDRC.DDRC1             1   PC1 Data Direction
DDRC.DDRC0             0   PC0 Data Direction
UNUSED0007            0x0007     UNUSED
TCSR                  0x0008     MFT Ctrl_Status
TCSR.TOF               7   Timer Overflow Flag
TCSR.RTIF              6   Real Time Interrupt Flag
TCSR.TOFE              5   Timer Overflow Enable
TCSR.RTIE              4   Real Time Interrupt Enable
TCSR.TOFR              3   Timer Overflow Acknowledge
TCSR.RTIFR             2   Real Time Interrupt Acknowledge
TCSR.RT1               1   Real-Time Interrupt period select bits 1
TCSR.RT0               0   Real-Time Interrupt period select bits 0
TCNT                  0x0009     MFT Counter
TCNT.TMR7              7
TCNT.TMR6              6
TCNT.TMR5              5
TCNT.TMR4              4
TCNT.TMR3              3
TCNT.TMR2              2
TCNT.TMR1              1
TCNT.TMR0              0
ICSR                  0x000A     IRQ Control_Status
ICSR.IRQE              7   IRQ Interrupt Enable
ICSR.IRQF              3   IRQ Interrupt Request Flag
ICSR.IRQR              1   IRQ Interrupt Acknowledge
ICSR.IRQPU             0   IRQ pin PUll-up resistor enable
UNUSED000B            0x000B     UNUSED
UNUSED000C            0x000C     UNUSED
UNUSED000D            0x000D     UNUSED
OIER                  0x000E     Optical Interface En.
OIER.TCMPE             7   Timer Input Capture Comparator Enable
OIER.VREF2             6   Reference Voltage Selection 3
OIER.VREF1             5   Reference Voltage Selection 1
OIER.VREF0             4   Reference Voltage Selection 0
OIER.OIE3              3   Optical Interface pair 3 Enable
OIER.OIE2              2   Optical Interface pair 2 Enable
OIER.OIE1              1   Optical Interface pair 1 Enable
OIER.OIE0              0   Optical Interface pair 0 Enable
PDURC                 0x000F     Port C Pull-down_up
PDURC.PDRC3            3   PC3 Pin Pull-down Enable
PDURC.PDRC2            2   PC2 Pin Pull-down Enable
PDURC.PDRC1            1   PC1 Pin Pull-down Enable
PDURC.PDRC0            0   PC0 Pin Pull-down Enable
PDURA                 0x0010     Port A Pull-down_up
PDURA.PDRA7            7   PA7 Pin Pull-down enable
PDURA.PDRA6            6   PA6 Pin Pull-down enable
PDURA.PDRA5            5   PA5 Pin Pull-down enable
PDURA.PDRA4            4   PA4 Pin Pull-down enable
PDURA.PDRA3            3   PA3 Pin Pull-down enable
PDURA.PDRA2            2   PA2 Pin Pull-down enable
PDURA.PDRA1            1   PA1 Pin Pull-down enable
PDURA.PDRA0            0   PA0 Pin Pull-down enable
PDURB                 0x0011     Port B Pull-down_up
PDURB.PDRB7            7   PB7 Pin Pull-down enable
PDURB.PDRB6            6   PB6 Pin Pull-down enable
PDURB.PDRB5            5   PB5 Pin Pull-down enable
PDURB.PDRB4            4   PB4 Pin Pull-down enable
PDURB.PURB2            2   PB2 Pin Pull-up enable
PDURB.PURB1            1   PB1 Pin Pull-up enable
PDURB.PDRB0            0   PB0 Pin Pull-up enable
TCR                   0x0012     Timer1 Control
TCR.ICIE               7   INPUT CAPTURE INTERRUPT ENABLE
TCR.OCIE               6   OUTPUT COMPARE INTERRUPT ENABLE
TCR.TOIE               5   TIMER OVERFLOW INTERRUPT ENABLE
TCR.IEDG               1   INPUT CAPTURE EDGE SELECT
TSR                   0x0013     Timer1 Status
TSR.ICF                7   INPUT CAPTURE FLAG
TSR.OCF                6   OUTPUT COMPARE FLAG
TSR.TOF                5   TIMER OVERFLOW FLAG
ICH                   0x0014     Input Capture MSB
ICH.ICH7               7
ICH.ICH6               6
ICH.ICH5               5
ICH.ICH4               4
ICH.ICH3               3
ICH.ICH2               2
ICH.ICH1               1
ICH.ICH0               0
ICL                   0x0015     Input Capture LSB
ICL.ICL7               7
ICL.ICL6               6
ICL.ICL5               5
ICL.ICL4               4
ICL.ICL3               3
ICL.ICL2               2
ICL.ICL1               1
ICL.ICL0               0
OCH                   0x0016     Output Compare MSB
OCH.OCH7               7
OCH.OCH6               6
OCH.OCH5               5
OCH.OCH4               4
OCH.OCH3               3
OCH.OCH2               2
OCH.OCH1               1
OCH.OCH0               0
OCL                   0x0017     Output Compare LSB
OCL.OCL7               7
OCL.OCL6               6
OCL.OCL5               5
OCL.OCL4               4
OCL.OCL3               3
OCL.OCL2               2
OCL.OCL1               1
OCL.OCL0               0
TCNTH                 0x0018     Timer1 Counter MSB
TCNTH.TCNTH7           7
TCNTH.TCNTH6           6
TCNTH.TCNTH5           5
TCNTH.TCNTH4           4
TCNTH.TCNTH3           3
TCNTH.TCNTH2           2
TCNTH.TCNTH1           1
TCNTH.TCNTH0           0
TCNTL                 0x0019     Timer1 Counter LSB
TCNTL.TCNTL7           7
TCNTL.TCNTL6           6
TCNTL.TCNTL5           5
TCNTL.TCNTL4           4
TCNTL.TCNTL3           3
TCNTL.TCNTL2           2
TCNTL.TCNTL1           1
TCNTL.TCNTL0           0
ACNTH                 0x001A     Alter. Counter MSB
ACNTH.ACNTH7           7
ACNTH.ACNTH6           6
ACNTH.ACNTH5           5
ACNTH.ACNTH4           4
ACNTH.ACNTH3           3
ACNTH.ACNTH2           2
ACNTH.ACNTH1           1
ACNTH.ACNTH0           0
ACNTL                 0x001B     Alter. Counter LSB
ACNTL.ACNTL7           7
ACNTL.ACNTL6           6
ACNTL.ACNTL5           5
ACNTL.ACNTL4           4
ACNTL.ACNTL3           3
ACNTL.ACNTL2           2
ACNTL.ACNTL1           1
ACNTL.ACNTL0           0
UNUSED001C            0x001C     UNUSED
UNUSED001D            0x001D     UNUSED
UNUSED001E            0x001E     UNUSED
UNUSED001F            0x001F     UNUSED
UD0R0                 0x0020     USB Endpoint 0 Data 0
UD0R0.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R0.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R0.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R0.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R0.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R0.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R0.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R0.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R1                 0x0021     USB Endpoint 0 Data 1
UD0R1.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R1.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R1.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R1.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R1.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R1.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R1.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R1.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R2                 0x0022     USB Endpoint 0 Data 2
UD0R2.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R2.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R2.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R2.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R2.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R2.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R2.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R2.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R3                 0x0023     USB Endpoint 0 Data 3
UD0R3.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R3.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R3.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R3.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R3.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R3.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R3.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R3.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R4                 0x0024     USB Endpoint 0 Data 4
UD0R4.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R4.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R4.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R4.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R4.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R4.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R4.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R4.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R5                 0x0025     USB Endpoint 0 Data 5
UD0R5.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R5.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R5.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R5.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R5.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R5.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R5.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R5.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R6                 0x0026     USB Endpoint 0 Data 6
UD0R6.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R6.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R6.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R6.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R6.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R6.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R6.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R6.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R7                 0x0027     USB Endpoint 0 Data 7
UD0R7.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R7.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R7.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R7.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R7.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R7.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R7.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R7.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD1R0                 0x0028     USB Endpoint 1 Data 0
UD1R0.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R0.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R0.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R0.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R0.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R0.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R0.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R0.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R1                 0x0029     USB Endpoint 1 Data 1
UD1R1.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R1.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R1.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R1.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R1.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R1.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R1.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R1.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R2                 0x002A     USB Endpoint 1 Data 2
UD1R2.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R2.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R2.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R2.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R2.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R2.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R2.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R2.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R3                 0x002B     USB Endpoint 1 Data 3
UD1R3.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R3.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R3.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R3.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R3.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R3.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R3.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R3.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R4                 0x002C     USB Endpoint 1 Data 4
UD1R4.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R4.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R4.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R4.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R4.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R4.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R4.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R4.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R5                 0x002D     USB Endpoint 1 Data 5
UD1R5.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R5.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R5.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R5.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R5.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R5.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R5.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R5.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R6                 0x002E     USB Endpoint 1 Data 6
UD1R6.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R6.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R6.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R6.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R6.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R6.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R6.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R6.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R7                 0x002F     USB Endpoint 1 Data 7
UD1R7.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R7.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R7.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R7.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R7.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R7.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R7.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R7.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UNUSED0030            0x0030     UNUSED
UNUSED0031            0x0031     UNUSED
UNUSED0032            0x0032     UNUSED
UNUSED0033            0x0033     UNUSED
UNUSED0034            0x0034     UNUSED
UNUSED0035            0x0035     UNUSED
UNUSED0036            0x0036     UNUSED
UCR2                  0x0037     USB Control 2
UCR2.TX1STR            6   Clear Transmit First Flag
UCR2.TX1ST             5   Transmit First Flag
UCR2.ENABLE2           3   Endpoint 2 Enable
UCR2.ENABLE1           2   Endpoint 1 Enable
UCR2.STALL2            1   Endpoint 2 Force Stall Bit
UCR2.STALL1            0   Endpoint 1 Force Stall Bit
UADR                  0x0038     USB Address
UADR.USBEN             7   USB Module Enable
UADR.UADD6             6   USB Function Address 6
UADR.UADD5             5   USB Function Address 5
UADR.UADD4             4   USB Function Address 4
UADR.UADD3             3   USB Function Address 3
UADR.UADD2             2   USB Function Address 2
UADR.UADD1             1   USB Function Address 1
UADR.UADD0             0   USB Function Address 0
UIR0                  0x0039     USB Interrupt 0
UIR0.TXD0F             7   Endpoint 0 Data Transmit Flag
UIR0.RXD0F             6   Endpoint 0 Data Receive Flag
UIR0.RSTF              5   USB Reset Flag
UIR0.SUSPND            4   USB Suspend Flag
UIR0.TXD0IE            3   Endpoint 0 Transmit Interrupt Enable
UIR0.RXD0IE            2   Endpoint 0 Receive Interrupt Enable
UIR0.TXD0FR            1   Endpoint 0 Transmit Flag Reset
UIR0.RXD0FR            0   Endpoint 0 Receive Flag Reset
UIR1                  0x003A     USB Interrupt 1
UIR1.TXD1F             7   Endpoint 1/Endpoint 2 Data Transmit Flag
UIR1.EOPF              6   End of Packet Detect Flag
UIR1.RESUMF            5   Resume Flag
UIR1.RESUMFR           4   Resume Flag Reset
UIR1.TXD1IE            3   Endpoint 1/Endpoint 2 Transmit Interrupt Enable
UIR1.EOPIE             2   End of Packet Detect Interrupt Enable
UIR1.TXD1FR            1   Endpoint 1/Endpoint 2 Transmit Flag Reset
UIR1.EOPFR             0   End of Packet Flag Reset
UCR0                  0x003B     USB Control 0
UCR0.T0SEQ             7   Endpoint 0 Transmit Sequence Bit
UCR0.STALL0            6   Endpoint 0 Force Stall Bit
UCR0.TX0E              5   Endpoint 0 Transmit Enable
UCR0.RX0E              4   Endpoint 0 Receive Enable
UCR0.TP0SIZ3           3   Endpoint 0 Transmit Data Packet Size 3
UCR0.TP0SIZ2           2   Endpoint 0 Transmit Data Packet Size 2
UCR0.TP0SIZ1           1   Endpoint 0 Transmit Data Packet Size 1
UCR0.TP0SIZ0           0   Endpoint 0 Transmit Data Packet Size 0
UCR1                  0x003C     USB Control 1
UCR1.T1SEQ             7   Endpoint1/Endpoint 2 Transmit Sequence Bit
UCR1.ENDADD            6   Endpoint Address Select
UCR1.TX1E              5   Endpoint 1/Endpoint 2 Transmit Enable
UCR1.FRESUM            4   Force Resume
UCR1.TP1SIZ3           3   Endpoint 1/Endpoint 2 Transmit Data Packet Size 3
UCR1.TP1SIZ2           2   Endpoint 1/Endpoint 2 Transmit Data Packet Size 2
UCR1.TP1SIZ1           1   Endpoint 1/Endpoint 2 Transmit Data Packet Size 1
UCR1.TP1SIZ0           0   Endpoint 1/Endpoint 2 Transmit Data Packet Size 0
USR                   0x003D     USB Status
USR.RSEQ               7   Endpoint 0 Receive Sequence Bit
USR.SETUP              6   SETUP Token Detect Bit
USR.RPSIZ3             3   Endpoint 0 Receive Data Packet Size 3
USR.RPSIZ2             2   Endpoint 0 Receive Data Packet Size 2
USR.RPSIZ1             1   Endpoint 0 Receive Data Packet Size 1
USR.RPSIZ0             0   Endpoint 0 Receive Data Packet Size 0
RESERV003E            0x003E     RESERVED
RESERV003F            0x003F     RESERVED
RESERV1FF0            0x1FF0     RESERVED
RESERV1FF1            0x1FF1     RESERVED
RESERV1FF2            0x1FF2     RESERVED
RESERV1FF3            0x1FF3     RESERVED


.68HC05JB4
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05JB4&nodeId=01M98633
; HC05JB4GRS.pdf

; RAM=176
; ROM=3584
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR        0x0000:0x0040
area BSS  UNUSED     0x0040:0x0080
area DATA RAM        0x0080:0x0130
area BSS  UNUSED     0x0130:0x1000
area CODE ROM        0x1000:0x1E00
area DATA ROM_S_C    0x1E00:0x1FF0   Self-Check ROM
area DATA USER_VEC   0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      SWI               
interrupt IRQ               0x1FFA      IRQ/IRQ2        
interrupt USB               0x1FF8      USB         
interrupt TIMER1            0x1FF6      Timer1 
interrupt MFT               0x1FF4      MFT


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003   UNUSED
DDRA                  0x0004   Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005   Port B data direction
DDRB.SLOWEA            7   Enable/Disable slow falling-edge output transition feature on PA6 and PA7
DDRB.SLOWEB            6   Enable/Disable slow falling-edge output transition feature on PB0 to PB4
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006   Port C data direction
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007   UNUSED
TCSR                  0x0008   MFT Ctrl/Status
TCSR.TOF               7   Timer Overflow Flag
TCSR.RTIF              6   Real Time Interrupt Flag
TCSR.TOFE              5   Timer Overflow Enable
TCSR.RTIE              4   Real Time Interrupt Enable
TCSR.TOFR              3   Timer Overflow Acknowledge
TCSR.RTIFR             2   Real Time Interrupt Acknowledge
TCSR.RT1               1   Real-Time Interrupt period select bits 1
TCSR.RT0               0   Real-Time Interrupt period select bits 0
TCNT                  0x0009   MFT Counter
TCNT.TMR7              7
TCNT.TMR6              6
TCNT.TMR5              5
TCNT.TMR4              4
TCNT.TMR3              3
TCNT.TMR2              2
TCNT.TMR1              1
TCNT.TMR0              0
ICSR                  0x000A   IRQ Control/Status
ICSR.IRQE              7   IRQ Interrupt Enable
ICSR.IRQ2E             6   IRQ2 Interrupt Enable
ICSR.IRQF              3   IRQ Interrupt Request Flag
ICSR.IRQ2F             2   IRQ2 Interrupt Request Flag
ICSR.IRQR              1   IRQ Interrupt Acknowledge
ICSR.IRQ2R             0   IRQ2 Interrupt Acknowledge
UNUSED000B            0x000B   UNUSED
UNUSED000C            0x000C   UNUSED
UNUSED000D            0x000D   UNUSED
ADSCR                 0x000E   ADC Control/Status
ADSCR.COCO             7   COnversion COmplete
ADSCR.ADRC             6   ADC RC Oscillator Control
ADSCR.ADON             5   ADC On
ADSCR.CH3              3   Channel Select Bits 3
ADSCR.CH2              2   Channel Select Bits 2
ADSCR.CH1              1   Channel Select Bits 1
ADSCR.CH0              0   Channel Select Bits 0
ADDR                  0x000F   ADC Data
ADDR.ADDR7             7
ADDR.ADDR6             6
ADDR.ADDR5             5
ADDR.ADDR4             4
ADDR.ADDR3             3
ADDR.ADDR2             2
ADDR.ADDR1             1
ADDR.ADDR0             0
PURA                  0x0010   Port A Pull-Up
PURA.PURA7             7
PURA.PURA6             6
PURA.PURA5             5
PURA.PURA4             4
PURA.PURA3             3
PURA.PURA2             2
PURA.PURA1             1
PURA.PURA0             0
PURB                  0x0011   Port B Pull-Up
PURB.PURB4             4
PURB.PURB3             3
PURB.PURB2             2
PURB.PURB1             1
PURB.PURB0             0
TCR                   0x0012   Timer1 control
TCR.ICIE               7   INPUT CAPTURE INTERRUPT ENABLE
TCR.OCIE               6   OUTPUT COMPARE INTERRUPT ENABLE
TCR.TOIE               5   TIMER OVERFLOW INTERRUPT ENABLE
TCR.IEDG               1   INPUT CAPTURE EDGE SELECT
TSR                   0x0013   Timer1 status
TSR.ICF                7   INPUT CAPTURE FLAG
TSR.OCF                6   OUTPUT COMPARE FLAG
TSR.TOF                5   TIMER OVERFLOW FLAG
ICH                   0x0014   Input capture MSB
ICH.ICH7               7
ICH.ICH6               6
ICH.ICH5               5
ICH.ICH4               4
ICH.ICH3               3
ICH.ICH2               2
ICH.ICH1               1
ICH.ICH0               0
ICL                   0x0015   Input capture LSB
ICL.ICL7               7
ICL.ICL6               6
ICL.ICL5               5
ICL.ICL4               4
ICL.ICL3               3
ICL.ICL2               2
ICL.ICL1               1
ICL.ICL0               0
OCH                   0x0016   Output compare MSB
OCH.OCH7               7
OCH.OCH6               6
OCH.OCH5               5
OCH.OCH4               4
OCH.OCH3               3
OCH.OCH2               2
OCH.OCH1               1
OCH.OCH0               0
OCL                   0x0017   Output compare LSB
OCL.OCL7               7
OCL.OCL6               6
OCL.OCL5               5
OCL.OCL4               4
OCL.OCL3               3
OCL.OCL2               2
OCL.OCL1               1
OCL.OCL0               0
TCNTH                 0x0018   Timer1 Counter MSB
TCNTH.TCNTH7           7
TCNTH.TCNTH6           6
TCNTH.TCNTH5           5
TCNTH.TCNTH4           4
TCNTH.TCNTH3           3
TCNTH.TCNTH2           2
TCNTH.TCNTH1           1
TCNTH.TCNTH0           0
TCNTL                 0x0019   Timer1 Cunter LSB
TCNTL.TCNTL7           7
TCNTL.TCNTL6           6
TCNTL.TCNTL5           5
TCNTL.TCNTL4           4
TCNTL.TCNTL3           3
TCNTL.TCNTL2           2
TCNTL.TCNTL1           1
TCNTL.TCNTL0           0
ACNTH                 0x001A   Alternate counter MSB
ACNTH.ACNTH7           7
ACNTH.ACNTH6           6
ACNTH.ACNTH5           5
ACNTH.ACNTH4           4
ACNTH.ACNTH3           3
ACNTH.ACNTH2           2
ACNTH.ACNTH1           1
ACNTH.ACNTH0           0
ACNTL                 0x001B   Alternate counter LSB
ACNTL.ACNTL7           7
ACNTL.ACNTL6           6
ACNTL.ACNTL5           5
ACNTL.ACNTL4           4
ACNTL.ACNTL3           3
ACNTL.ACNTL2           2
ACNTL.ACNTL1           1
ACNTL.ACNTL0           0
UNUSED001C            0x001C   UNUSED
UNUSED001D            0x001D   UNUSED
UNUSED001E            0x001E   UNUSED
UNUSED001F            0x001F   UNUSED
UD0R0                 0x0020     USB Endpoint 0 Data 0
UD0R0.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R0.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R0.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R0.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R0.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R0.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R0.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R0.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R1                 0x0021     USB Endpoint 0 Data 1
UD0R1.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R1.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R1.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R1.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R1.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R1.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R1.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R1.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R2                 0x0022     USB Endpoint 0 Data 2
UD0R2.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R2.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R2.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R2.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R2.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R2.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R2.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R2.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R3                 0x0023     USB Endpoint 0 Data 3
UD0R3.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R3.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R3.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R3.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R3.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R3.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R3.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R3.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R4                 0x0024     USB Endpoint 0 Data 4
UD0R4.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R4.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R4.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R4.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R4.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R4.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R4.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R4.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R5                 0x0025     USB Endpoint 0 Data 5
UD0R5.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R5.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R5.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R5.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R5.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R5.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R5.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R5.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R6                 0x0026     USB Endpoint 0 Data 6
UD0R6.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R6.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R6.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R6.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R6.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R6.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R6.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R6.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R7                 0x0027     USB Endpoint 0 Data 7
UD0R7.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R7.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R7.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R7.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R7.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R7.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R7.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R7.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD1R0                 0x0028   USB Endpoint 1 Data 0
UD1R0.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R0.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R0.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R0.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R0.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R0.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R0.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R0.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R1                 0x0029   USB Endpoint 1 Data 1
UD1R1.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R1.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R1.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R1.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R1.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R1.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R1.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R1.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R2                 0x002A   USB Endpoint 1 Data 2
UD1R2.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R2.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R2.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R2.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R2.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R2.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R2.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R2.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R3                 0x002B   USB Endpoint 1 Data 3
UD1R3.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R3.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R3.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R3.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R3.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R3.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R3.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R3.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R4                 0x002C   USB Endpoint 1 Data 4
UD1R4.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R4.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R4.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R4.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R4.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R4.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R4.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R4.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R5                 0x002D   USB Endpoint 1 Data 5
UD1R5.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R5.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R5.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R5.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R5.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R5.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R5.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R5.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R6                 0x002E   USB Endpoint 1 Data 6
UD1R6.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R6.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R6.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R6.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R6.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R6.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R6.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R6.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R7                 0x002F   USB Endpoint 1 Data 7
UD1R7.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R7.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R7.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R7.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R7.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R7.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R7.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R7.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UNUSED0030            0x0030   UNUSED
UNUSED0031            0x0031   UNUSED
UNUSED0032            0x0032   UNUSED
UNUSED0033            0x0033   UNUSED
UNUSED0034            0x0034   UNUSED
UNUSED0035            0x0035   UNUSED
UNUSED0036            0x0036   UNUSED
UCR2                  0x0037   USB Control 2
UCR2.TX1STR            6   Clear Transmit First Flag
UCR2.TX1ST             5   Transmit First Flag
UCR2.ENABLE2           3   Endpoint 2 Enable
UCR2.ENABLE1           2   Endpoint 1 Enable
UCR2.STALL2            1   Endpoint 2 Force Stall Bit
UCR2.STALL1            0   Endpoint 1 Force Stall Bit
UADR                  0x0038   USB Address
UADR.USBEN             7   USB Module Enable
UADR.UADD6             6   USB Function Address 6
UADR.UADD5             5   USB Function Address 5
UADR.UADD4             4   USB Function Address 4
UADR.UADD3             3   USB Function Address 3
UADR.UADD2             2   USB Function Address 2
UADR.UADD1             1   USB Function Address 1
UADR.UADD0             0   USB Function Address 0
UIR0                  0x0039   USB Interrupt 0
UIR0.TXD0F             7   Endpoint 0 Data Transmit Flag
UIR0.RXD0F             6   Endpoint 0 Data Receive Flag
UIR0.RSTF              5   USB Reset Flag
UIR0.SUSPND            4   USB Suspend Flag
UIR0.TXD0IE            3   Endpoint 0 Transmit Interrupt Enable
UIR0.RXD0IE            2   Endpoint 0 Receive Interrupt Enable
UIR0.TXD0FR            1   Endpoint 0 Transmit Flag Reset
UIR0.RXD0FR            0   Endpoint 0 Receive Flag Reset
UIR1                  0x003A   USB Interrupt 1
UIR1.TXD1F             7   Endpoint 1/Endpoint 2 Data Transmit Flag
UIR1.EOPF              6   End of Packet Detect Flag
UIR1.RESUMF            5   Resume Flag
UIR1.RESUMFR           4   Resume Flag Reset
UIR1.TXD1IE            3   Endpoint 1/Endpoint 2 Transmit Interrupt Enable
UIR1.EOPIE             2   End of Packet Detect Interrupt Enable
UIR1.TXD1FR            1   Endpoint 1/Endpoint 2 Transmit Flag Reset
UIR1.EOPFR             0   End of Packet Flag Reset
UCR0                  0x003B   USB Control 0
UCR0.T0SEQ             7   Endpoint 0 Transmit Sequence Bit
UCR0.STALL             6   Endpoint 0 Force Stall Bit
UCR0.TX0E              5   Endpoint 0 Transmit Enable
UCR0.RX0E              4   Endpoint 0 Receive Enable
UCR0.TP0SIZ3           3   Endpoint 0 Transmit Data Packet Size 3
UCR0.TP0SIZ2           2   Endpoint 0 Transmit Data Packet Size 2
UCR0.TP0SIZ1           1   Endpoint 0 Transmit Data Packet Size 1
UCR0.TP0SIZ0           0   Endpoint 0 Transmit Data Packet Size 0
UCR1                  0x003C   USB Control 1
UCR1.T1SEQ             7   Endpoint1/Endpoint 2 Transmit Sequence Bit
UCR1.ENDADD            6   Endpoint Address Select
UCR1.TX1E              5   Endpoint 1/Endpoint 2 Transmit Enable
UCR1.FRESUM            4   Force Resume
UCR1.TP1SIZ3           3   Endpoint 1/Endpoint 2 Transmit Data Packet Size 3
UCR1.TP1SIZ2           2   Endpoint 1/Endpoint 2 Transmit Data Packet Size 2
UCR1.TP1SIZ1           1   Endpoint 1/Endpoint 2 Transmit Data Packet Size 1
UCR1.TP1SIZ0           0   Endpoint 1/Endpoint 2 Transmit Data Packet Size 0
USR                   0x003D   USB Status
USR.RSEQ               7   Endpoint 0 Receive Sequence Bit
USR.SETUP              6   SETUP Token Detect Bit
USR.RPSIZ3             3   Endpoint 0 Receive Data Packet Size 3
USR.RPSIZ2             2   Endpoint 0 Receive Data Packet Size 2
USR.RPSIZ1             1   Endpoint 0 Receive Data Packet Size 1
USR.RPSIZ0             0   Endpoint 0 Receive Data Packet Size 0
RESERV003E            0x003E   Reserved
RESERV003F            0x003F   Reserved
COPR                  0x1FF0   COP
COPR.COPR              0   COP Clear
RESERV1FF1            0x1FF1   RESERVED
RESERV1FF2            0x1FF2   RESERVED
RESERV1FF3            0x1FF3   RESERVED


.68HC05JJ6
; HC05JJ6GRS/D  http://
; HC05JJ6GRS.pdf

; RAM=224
; ROM=6K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR			0x0000:0x0020
area DATA RAM			0x0020:0x0100
area BSS  UNUSED		0x0100:0x0700
area DATA ROM			0x0700:0x1EF8
area DATA SECURITY_CHECK_ROM	0x1EF8:0x1F00
area DATA TEST_ROM	        0x1F00:0x1FF0
area DATA USER_VEC		0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET  	0x1FFE       Reset
interrupt SWI 		0x1FFC       Software Interrupt
interrupt IRQ 		0x1FFA       External Interrupt
interrupt CTI 		0x1FF8       Core Timer Interrupts
interrupt PTI 		0x1FF6       Programmable Timer Interrupts
interrupt SI 		0x1FF4       Serial Interrupt
interrupt AI 		0x1FF2       Analog Interrupt


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
UNUSED0002            0x0002     UNUSED
AMUX                  0x0003     Analog MUX Register
AMUX.HOLD              7
AMUX.DHOLD             6
AMUX.INV               5
AMUX.VREF              4
AMUX.MUX4              3
AMUX.MUX3              2
AMUX.MUX2              1
AMUX.MUX1              0
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
UNUSED0006            0x0006     UNUSED
UNUSED0007            0x0007     UNUSED
CTSCR                 0x0008     Core Timer Status_Control
CTSCR.CTOF             7   Core Timer Overflow Flag
CTSCR.RTIF             6   Real-Time Interrupt Flag
CTSCR.CTOFE            5   Core Timer Overflow Interrupt Enable
CTSCR.RTIE             4   Real-Time Interrupt Enable
CTSCR.CTOFR            3   Core Timer Overflow Flag Reset
CTSCR.RTIFR            2   Real-Time Interrupt Flag Reset
CTSCR.RT1              1   Real-Time Interrupt Select Bit 1
CTSCR.RT0              0   Real-Time Interrupt Select Bit 0
CTCR                  0x0009     Core Timer Counter
SCR                   0x000A     Serial Control
SCR.SPIE               7   Serial Peripheral Interrupt Enable
SCR.SPE                6   Serial Peripheral Enable
SCR.LSBF               5   Least Significant Bit First
SCR.MSTR               4   Master Mode Select
SCR.SPIR               3   Serial Peripheral Interrupt Reset
SCR.CPHA               2   Clock Phase
SCR.SPR1               1   Serial Peripheral Clock Rate Selects 1
SCR.SPR0               0   Serial Peripheral Clock Rate Selects 0
SSR                   0x000B     Serial Status
SSR.SPIF               7   Serial Port Interrupt Flag
SSR.DCOL               6   Data Collision
SDR                   0x000C     Serial Data
ISCR                  0x000D     IRQ Status_Control
ISCR.IRQE              7   External Interrupt Request Enable
ISCR.OM2               6   Oscillator Selects 2
ISCR.OM1               5   Oscillator Selects 1
ISCR.IRQF              3   External Interrupt Request Flag
ISCR.IRQR              1   Interrupt Request Reset
UNUSED000E            0x000E     UNUSED
UNUSED000F            0x000F     UNUSED
UNUSED0010            0x0010     UNUSED
PDRB                  0x0011     Port B Pulldown
PDRB.PDIB7             7   Port B Pulldown Inhibit Bits 7
PDRB.PDIB6             6   Port B Pulldown Inhibit Bits 6
PDRB.PDIB5             5   Port B Pulldown Inhibit Bits 5
PDRB.PDIB4             4   Port B Pulldown Inhibit Bits 4
PDRB.PDIB3             3   Port B Pulldown Inhibit Bits 3
PDRB.PDIB2             2   Port B Pulldown Inhibit Bits 2
PDRB.PDIB1             1   Port B Pulldown Inhibit Bits 1
PDRB.PDIB0             0   Port B Pulldown Inhibit Bits 0
TCR                   0x0012     Timer Control
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.IEDG               1   Input Capture Edge Select
TCR.OLVL               0   Output Compare Output Level Select
TSR                   0x0013     Timer Status
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICRH                  0x0014     Input Capture MSB
ICRL                  0x0015     Input Capture LSB
OCRH                  0x0016     Output Compare MSB
OCRL                  0x0017     Output Compare LSB
TMRH                  0x0018     Timer Counter MSB
TMRL                  0x0019     Timer Counter LSB
ACRH                  0x001A     Alternate Counter MSB
ACRL                  0x001B     Alternate Counter LSB
UNUSED001C            0x001C     UNUSED
ACR                   0x001D     Analog Control
ACR.CHG                7
ACR.ATD2               6
ACR.ATD1               5
ACR.ICEN               4
ACR.CPIE               3
ACR.CP2EN              2
ACR.CP1EN              1
ACR.ISEN               0
ASR                   0x001E     Analog Status
ASR.CPF2               7
ASR.CPF1               6
ASR.CPFR2              5
ASR.CPFR1              4
ASR.COE1               3
ASR.VOFF               2
ASR.CMP2               1
ASR.CMP1               0
Reserv001F            0x001F     Reserved
COP                   0x1FF0
COP.COPR               0   COP Clear
UNUSED1FF1            0x1FF1     UNUSED


.68HC05JP6
; HC05JJ6GRS/D  http://
; HC05JJ6GRS.pdf

; RAM=224
; ROM=6K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR			0x0000:0x0020
area DATA RAM			0x0020:0x0100
area BSS  UNUSED		0x0100:0x0700
area DATA ROM			0x0700:0x1EF8
area DATA SECURITY_CHECK_ROM	0x1EF8:0x1F00
area DATA TEST_ROM	        0x1F00:0x1FF0
area DATA USER_VEC		0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET  	0x1FFE       Reset
interrupt SWI 		0x1FFC       Software Interrupt
interrupt IRQ 		0x1FFA       External Interrupt
interrupt CTI 		0x1FF8       Core Timer Interrupts
interrupt PTI 		0x1FF6       Programmable Timer Interrupts
interrupt SI 		0x1FF4       Serial Interrupt
interrupt AI 		0x1FF2       Analog Interrupt


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
AMUX                  0x0003     Analog MUX Register
AMUX.HOLD              7
AMUX.DHOLD             6
AMUX.INV               5
AMUX.VREF              4
AMUX.MUX4              3
AMUX.MUX3              2
AMUX.MUX2              1
AMUX.MUX1              0
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007     UNUSED
CTSCR                 0x0008     Core Timer Status_Control
CTSCR.CTOF             7   Core Timer Overflow Flag
CTSCR.RTIF             6   Real-Time Interrupt Flag
CTSCR.CTOFE            5   Core Timer Overflow Interrupt Enable
CTSCR.RTIE             4   Real-Time Interrupt Enable
CTSCR.CTOFR            3   Core Timer Overflow Flag Reset
CTSCR.RTIFR            2   Real-Time Interrupt Flag Reset
CTSCR.RT1              1   Real-Time Interrupt Select Bit 1
CTSCR.RT0              0   Real-Time Interrupt Select Bit 0
CTCR                  0x0009     Core Timer Counter
SCR                   0x000A     Serial Control
SCR.SPIE               7   Serial Peripheral Interrupt Enable
SCR.SPE                6   Serial Peripheral Enable
SCR.LSBF               5   Least Significant Bit First
SCR.MSTR               4   Master Mode Select
SCR.SPIR               3   Serial Peripheral Interrupt Reset
SCR.CPHA               2   Clock Phase
SCR.SPR1               1   Serial Peripheral Clock Rate Selects 1
SCR.SPR0               0   Serial Peripheral Clock Rate Selects 0
SSR                   0x000B     Serial Status
SSR.SPIF               7   Serial Port Interrupt Flag
SSR.DCOL               6   Data Collision
SDR                   0x000C     Serial Data
ISCR                  0x000D     IRQ Status_Control
ISCR.IRQE              7   External Interrupt Request Enable
ISCR.OM2               6   Oscillator Selects 2
ISCR.OM1               5   Oscillator Selects 1
ISCR.IRQF              3   External Interrupt Request Flag
ISCR.IRQR              1   Interrupt Request Reset
UNUSED000E            0x000E     UNUSED
UNUSED000F            0x000F     UNUSED
PDRA                  0x0010     Port A  Port C Pulldown
PDRA.PDICH             7   Upper Port C Pulldown Inhibit Bits
PDRA.PDICL             6   Lower Port C Pulldown Inhibit Bits
PDRA.PDIA5             5   Port A Pulldown Inhibit Bits 5
PDRA.PDIA4             4   Port A Pulldown Inhibit Bits 4
PDRA.PDIA3             3   Port A Pulldown Inhibit Bits 3
PDRA.PDIA2             2   Port A Pulldown Inhibit Bits 2
PDRA.PDIA1             1   Port A Pulldown Inhibit Bits 1
PDRA.PDIA0             0   Port A Pulldown Inhibit Bits 0
PDRB                  0x0011     Port B Pulldown
PDRB.PDIB7             7   Port A Pulldown Inhibit Bits 7
PDRB.PDIB6             6   Port A Pulldown Inhibit Bits 6
PDRB.PDIB5             5   Port A Pulldown Inhibit Bits 5
PDRB.PDIB4             4   Port A Pulldown Inhibit Bits 4
PDRB.PDIB3             3   Port A Pulldown Inhibit Bits 3
PDRB.PDIB2             2   Port A Pulldown Inhibit Bits 2
PDRB.PDIB1             1   Port A Pulldown Inhibit Bits 1
PDRB.PDIB0             0   Port A Pulldown Inhibit Bits 0
TCR                   0x0012     Timer Control
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.IEDG               1   Input Capture Edge Select
TCR.OLVL               0   Output Compare Output Level Select
TSR                   0x0013     Timer Status
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICRH                  0x0014     Input Capture MSB
ICRL                  0x0015     Input Capture LSB
OCRH                  0x0016     Output Compare MSB
OCRL                  0x0017     Output Compare LSB
TMRH                  0x0018     Timer Counter MSB
TMRL                  0x0019     Timer Counter LSB
ACRH                  0x001A     Alternate Counter MSB
ACRL                  0x001B     Alternate Counter LSB
UNUSED001C            0x001C     UNUSED
ACR                   0x001D     Analog Control
ACR.CHG                7
ACR.ATD2               6
ACR.ATD1               5
ACR.ICEN               4
ACR.CPIE               3
ACR.CP2EN              2
ACR.CP1EN              1
ACR.ISEN               0
ASR                   0x001E     Analog Status
ASR.CPF2               7
ASR.CPF1               6
ASR.CPFR2              5
ASR.CPFR1              4
ASR.COE1               3
ASR.VOFF               2
ASR.CMP2               1
ASR.CMP1               0
Reserv001F            0x001F     Reserved
COP                   0x1FF0
COP.COPR               0   COP Clear
RESERV1FF1            0x1FF1	 RESERVED


.68HC05K3
; http://
; HC05K3GRS.pdf

; RAM=64
; ROM=0.9K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA ROM_1		0x0020:0x00C0
area DATA RAM		0x00C0:0x0100
area DATA ROM_2		0x0100:0x03F8
area DATA USER_VEC	0x03F8:0x0400


; Interrupt and reset vector assignments
interrupt __RESET 	0x03FE       Reset 
interrupt SWI 		0x03FC       Software 
interrupt IRQ 		0x03FA       External interrupt 
interrupt TIMER 	0x03F8       Timer  


; INPUT/ OUTPUT PORTS
PORTA           0x0000   Port A Data
PORTA.PA7	  7  Port A Data Bits 7
PORTA.PA6         6  Port A Data Bits 6
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB           0x0001   Port B Data
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
UNUSED0002      0x0002   UNUSED
UNUSED0003      0x0003   UNUSED
DDRA            0x0004   Port A Data Direction
DDRA.DDRA7        7  Data Direction for Port A Bit 7
DDRA.DDRA6        6  Data Direction for Port A Bit 6
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB            0x0005   Port B Data Direction
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
UNUSED0006      0x0006   UNUSED
UNUSED0007      0x0007   UNUSED
TSCR            0x0008   Timer Status_Control
TSCR.TOF          7  Timer Overflow Bit
TSCR.RTIF         6  Real-Time Interrupt Flag Bit
TSCR.TOIE         5  Timer Overflow Interrupt Enable Bit
TSCR.RTIE         4  Real-Time Interrupt Enable Bit
TSCR.TOFR         3  Timer Overflow Acknowledge Bit
TSCR.RTIFR        2  Real-Time Interrupt Acknowledge Bit
TSCR.RT1          1  Real-Time Interrupt Rate Select Bit 1
TSCR.RT0          0  Real-Time Interrupt Rate Select Bit 0
TCNTR           0x0009   Timer Counter
TCNTR.TCR7        7
TCNTR.TCR6        6
TCNTR.TCR5        5
TCNTR.TCR4        4
TCNTR.TCR3        3
TCNTR.TCR2        2
TCNTR.TCR1        1
TCNTR.TCR0        0
ISCR            0x000A   IRQ Status_Control
ISCR.IRQE         7  IRQ Interrupt Enable Bit
ISCR.IRQF         3  IRQ Interrupt Request Bit
ISCR.IRQR         1  IRQ Interrupt Acknowledge Bit
UNUSED000B      0x000B   UNUSED
UNUSED000C      0x000C   UNUSED
UNUSED000D      0x000D   UNUSED
PEBSR           0x000E   Personality EEPROM Bit Select
PEBSR.PEB7        7
PEBSR.PEB6        6
PEBSR.PEB5        5
PEBSR.PEB4        4
PEBSR.PEB3        3
PEBSR.PEB2        2
PEBSR.PDB1        1
PEBSR.PDB0        0
PESCR           0x000F   Personality EEPROM Status_Control
PESCR.PEDATA      7  PEEPROM Data Bit
PESCR.PEBULK      6  PEEPROM Bulk Erase Bit
PESCR.PEPGM       5  PEEPROM Program Control Bit
PESCR.PEBYTE      4  PEEPROM Byte Erase Bit
PESCR.CPEN        3  Charge Pump Enable Bit
PESCR.CPCLK       2  Charge Pump Clock Source Bit
PESCR.PEPCZF      0  PEEPROM Column Zero Flag Bit
PDRA            0x0010   Port A Pulldown Inhibit
PDRA.PDIA7        7
PDRA.PDIA6        6
PDRA.PDIA5        5
PDRA.PDIA4        4
PDRA.PDIA3        3
PDRA.PDIA2        2
PDRA.PDIA1        1
PDRA.PDIA0        0
PDRB            0x0011   Port B Pulldown Inhibit
PDRB.PDIB1        1
PDRB.PDIB0        0
UNUSED0012      0x0012   UNUSED
UNUSED0013      0x0013   UNUSED
UNUSED0014      0x0014   UNUSED
UNUSED0015      0x0015   UNUSED
UNUSED0016      0x0016   UNUSED
UNUSED0017      0x0017   UNUSED
UNUSED0018      0x0018   UNUSED
UNUSED0019      0x0019   UNUSED
UNUSED001A      0x001A   UNUSED
UNUSED001B      0x001B   UNUSED
UNUSED001C      0x001C   UNUSED
UNUSED001D      0x001D   UNUSED
UNUSED001E      0x001E   UNUSED
Reserv001F	0x001F   RESERVED
RESERV3FF0      0x3FF0   RESERVED
RESERV3FF1      0x3FF1   RESERVED
RESERV3FF2      0x3FF2   RESERVED
RESERV3FF3      0x3FF3   RESERVED
RESERV3FF4      0x3FF4   RESERVED
RESERV3FF5      0x3FF5   RESERVED
RESERV3FF6      0x3FF6   RESERVED
RESERV3FF7      0x3FF7   RESERVED


.68HC05L16
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705L16&nodeId=01M98633
; HC05L16GRS.pdf
      
; RAM=512
; ROM=16K
; EPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area DATA RAM         0x0040:0x0240
area BSS  UNUSED      0x0240:0x1000
area DATA ROM_MASK    0x1000:0x5000
area BSS  UNUSED      0x5000:0xFE00
area DATA ROM_S_C     0xFE00:0xFFE0
area DATA TEST_VEC    0xFFE0:0xFFF0
area DATA USER_VEC    0xFFF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Reset  
interrupt SWI               0xFFFC      SWI               
interrupt IRQ               0xFFFA      IRQ/IRQ2        
interrupt KWI               0xFFF8        
interrupt TIMER_1           0xFFF6      TIMER 1
interrupt TIMER_2           0xFFF4      TIMER 2
interrupt SSPI              0xFFF2      SSPI     
interrupt Time_Base         0xFFF0      Time Base


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTE                 0x0004   Port E data
PORTE.PE7              7   Port E Data Bits 7
PORTE.PE6              6   Port E Data Bits 6
PORTE.PE5              5   Port E Data Bits 5
PORTE.PE4              4   Port E Data Bits 4
PORTE.PE3              3   Port E Data Bits 3
PORTE.PE2              2   Port E Data Bits 2
PORTE.PE1              1   Port E Data Bits 1
PORTE.PE0              0   Port E Data Bits 0
RESERV0005            0x0005   Reserved
RESERV0006            0x0006   Reserved
RESERV0007            0x0007   Reserved
INTCR                 0x0008   Interrupt Control
INTCR.IRQ1E            7   IRQ1 Interrupt Enable
INTCR.IRQ2E            6   IRQ2 Interrupt Enable
INTCR.KWIE             4   Key Wakeup Interrupt (KWI) Enable
INTCR.IRQ1S            3   IRQ1 Select Edge Sensitive Only
INTCR.IRQ2S            2   IRQ2 Select Edge Sensitive Only
INTSR                 0x0009   Interrupt Status
INTSR.IRQ1F            7   IRQ1 Interrupt Flag
INTSR.IRQ2F            6   IRQ2 Interrupt Flag
INTSR.KWIF             4   Key Wakeup Interrupt Flag
INTSR.RIRQ1            3   Reset IRQ1 Flag
INTSR.RIRQ2            2   Reset IRQ2 Flag
INTSR.RKWIF            0   Reset KWI Flag
SPCR                  0x000A   Serial Peripheral Control
SPCR.SPIE              7   SSPI Interrupt Enable
SPCR.SPE               6   SSPI Enable
SPCR.DORD              5   Data Transmission ORDer
SPCR.MSTR              4   MaSTeR Mode Select
SPCR.SPR               0   SSPI Clock Rate Select
SPSR                  0x000B   Serial peripheral Status
SPSR.SPIF              7   Serial Transfer Complete Flag
SPSR.DCOL              6   Data COLlision
SPDR                  0x000C   Serial Peripheral Data
SPDR.MSB               7
SPDR.LSB               0
RESERV000D            0x000D   Reserved
RESERV000E            0x000E   Reserved
RESERV000F            0x000F   Reserved
TBCR1                 0x0010   Timer Base Control Register 1
TBCR1.TBCLK            7   Timebase Clock
TBCR1.LCLK             5   LCD Clock
TBCR1.T2R1             1   Timer 2 Prescale Rate Select Bits 1
TBCR1.T2R0             0   Timer 2 Prescale Rate Select Bits 0
TBCR2                 0x0011   Timer Base Control Register 2
TBCR2.TBIF             7   Timebase Interrupt Flag
TBCR2.TBIE             6   Timebase Interrupt Enable
TBCR2.TBR1             5   Timebase Interrupt Rate Select 1
TBCR2.TBR0             4   Timebase Interrupt Rate Select 0
TBCR2.RTBIF            3   Reset TBS Interrupt Flag
TBCR2.COPE             1   COP Enable
TBCR2.COPC             0   COP Clear
TCR                   0x0012   Timer  control
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare 1 Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.IEDG               1   Input Edge
TCR.OLVL               0   Not Used
TSR                   0x0013   Timer  status
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare 1 Flag
TSR.TOF                5   Timer Overflow Flag
ICH                   0x0014   Input capture
ICL                   0x0015   Input capture
OC1H                  0x0016   Output compare
OC1L                  0x0017   Output compare
TCNTH                 0x0018   Timer  Counter
TCNTL                 0x0019   Timer  Cunter
ACNTH                 0x001A   Alternate Timer Counter
ACNTL                 0x001B   Alternate Timer Counter
TCR2                  0x001C   Timer Control Register 2
TCR2.TI2IE             7   Timer Input 2 Interrupt Enable
TCR2.OC2IE             6   Compare 2 Interrupt Enable
TCR2.T2CLK             4   Timer 2 Clock Select
TCR2.IM2               3   Timer Input 2 Mode Select
TCR2.IL2               2   Timer Input 2 Active Edge (Level) Select
TCR2.OE2               1   Timer Output 2 (EVO) Output Enable
TCR2.OL2               0   Timer Output 2 Edge Select for Synchronization
TSR2                  0x001D   Timer Status Register 2
TSR2.TI2F              7   Timer Input 2 (EVI) Interrupt Flag
TSR2.OC2F              6   Compare 2 Interrupt Flag
TSR2.RTI2F             3   Reset Timer Input 2 Flag
TSR2.ROC2F             2   Reset Output Compare 2 Flag
OC2                   0x001E   Output Compare Register 2
TCNT2                 0x001F   Timer Conter Register 2
LCDCR                 0x0020   LCD Control
LCDCR.LCDE             7   LCD Output Enable
LCDCR.DUTY1            6   LCD Duty Select 1
LCDCR.DUTY0            5   LCD Duty Select 0
LCDCR.PEH              3   Select Port E (H)
LCDCR.PEL              2   Select Port E (L)
LCDCR.PDH              1   Select Port D (H)
LCDR1                 0x0021   LCD Data Register 1
LCDR1.F1B3             7
LCDR1.F1B2             6
LCDR1.F1B1             5
LCDR1.F1B0             4
LCDR1.F0B3             3
LCDR1.F0B2             2
LCDR1.F0B1             1
LCDR1.F0B0             0
LCDR2                 0x0022   LCD Data Register 2
LCDR2.F3B3             7
LCDR2.F3B2             6
LCDR2.F3B1             5
LCDR2.F3B0             4
LCDR2.F2B3             3
LCDR2.F2B2             2
LCDR2.F2B1             1
LCDR2.F2B0             0
LCDR3                 0x0023   LCD Data Register 3
LCDR3.F5B3             7
LCDR3.F5B2             6
LCDR3.F5B1             5
LCDR3.F5B0             4
LCDR3.F4B3             3
LCDR3.F4B2             2
LCDR3.F4B1             1
LCDR3.F4B0             0
LCDR4                 0x0024   LCD Data Register 4
LCDR4.F7B3             7
LCDR4.F7B2             6
LCDR4.F7B1             5
LCDR4.F7B0             4
LCDR4.F6B3             3
LCDR4.F6B2             2
LCDR4.F6B1             1
LCDR4.F6B0             0
LCDR5                 0x0025   LCD Data Register 5
LCDR5.F9B3             7
LCDR5.F9B2             6
LCDR5.F9B1             5
LCDR5.F9B0             4
LCDR5.F8B3             3
LCDR5.F8B2             2
LCDR5.F8B1             1
LCDR5.F8B0             0
LCDR6                 0x0026   LCD Data Register 6
LCDR6.F11B3            7
LCDR6.F11B2            6
LCDR6.F11B1            5
LCDR6.F11B0            4
LCDR6.F10B3            3
LCDR6.F10B2            2
LCDR6.F10B1            1
LCDR6.F10B0            0
LCDR7                 0x0027   LCD Data Register 7
LCDR7.F13B3            7
LCDR7.F13B2            6
LCDR7.F13B1            5
LCDR7.F13B0            4
LCDR7.F12B3            3
LCDR7.F12B2            2
LCDR7.F12B1            1
LCDR7.F12B0            0
LCDR8                 0x0028   LCD Data Register 8
LCDR8.F15B3            7
LCDR8.F15B2            6
LCDR8.F15B1            5
LCDR8.F15B0            4
LCDR8.F14B3            3
LCDR8.F14B2            2
LCDR8.F14B1            1
LCDR8.F14B0            0
LCDR9                 0x0029   LCD Data Register 9
LCDR9.F17B3            7
LCDR9.F17B2            6
LCDR9.F17B1            5
LCDR9.F17B0            4
LCDR9.F16B3            3
LCDR9.F16B2            2
LCDR9.F16B1            1
LCDR9.F16B0            0
LCDR10                0x002A   LCD Data Register 10
LCDR10.F19B3           7
LCDR10.F19B2           6
LCDR10.F19B1           5
LCDR10.F19B0           4
LCDR10.F18B3           3
LCDR10.F18B2           2
LCDR10.F18B1           1
LCDR10.F18B0           0
LCDR11                0x002B   LCD Data Register 11
LCDR11.F21B3           7
LCDR11.F21B2           6
LCDR11.F21B1           5
LCDR11.F21B0           4
LCDR11.F20B3           3
LCDR11.F20B2           2
LCDR11.F20B1           1
LCDR11.F20B0           0
LCDR12                0x002C   LCD Data Register 12
LCDR12.F23B3           7
LCDR12.F23B2           6
LCDR12.F23B1           5
LCDR12.F23B0           4
LCDR12.F22B3           3
LCDR12.F22B2           2
LCDR12.F22B1           1
LCDR12.F22B0           0
LCDR13                0x002D   LCD Data Register 13
LCDR13.F25B3           7
LCDR13.F25B2           6
LCDR13.F25B1           5
LCDR13.F25B0           4
LCDR13.F25B3           3
LCDR13.F25B2           2
LCDR13.F25B1           1
LCDR13.F25B0           0
LCDR14                0x002E   LCD Data Register 14
LCDR14.F27B3           7
LCDR14.F27B2           6
LCDR14.F27B1           5
LCDR14.F27B0           4
LCDR14.F26B3           3
LCDR14.F26B2           2
LCDR14.F26B1           1
LCDR14.F26B0           0
LCDR15                0x002F   LCD Data Register 15
LCDR15.F29B3           7
LCDR15.F29B2           6
LCDR15.F29B1           5
LCDR15.F29B0           4
LCDR15.F28B3           3
LCDR15.F28B2           2
LCDR15.F28B1           1
LCDR15.F28B0           0
LCDR16                0x0030   LCD Data Register 16
LCDR16.F31B3           7
LCDR16.F31B2           6
LCDR16.F31B1           5
LCDR16.F31B0           4
LCDR16.F30B3           3
LCDR16.F30B2           2
LCDR16.F30B1           1
LCDR16.F30B0           0
LCDR17                0x0031   LCD Data Register 17
LCDR17.F33B3           7
LCDR17.F33B2           6
LCDR17.F33B1           5
LCDR17.F33B0           4
LCDR17.F32B3           3
LCDR17.F32B2           2
LCDR17.F32B1           1
LCDR17.F32B0           0
LCDR18                0x0032   LCD Data Register 18
LCDR18.F35B3           7
LCDR18.F35B2           6
LCDR18.F35B1           5
LCDR18.F35B0           4
LCDR18.F34B3           3
LCDR18.F34B2           2
LCDR18.F34B1           1
LCDR18.F34B0           0
LCDR19                0x0033   LCD Data Register 19
LCDR19.F37B3           7
LCDR19.F37B2           6
LCDR19.F37B1           5
LCDR19.F37B0           4
LCDR19.F36B3           3
LCDR19.F36B2           2
LCDR19.F36B1           1
LCDR19.F36B0           0
LCDR20                0x0034   LCD Data Register 20
LCDR20.F38B3           3
LCDR20.F38B2           2
LCDR20.F38B1           1
LCDR20.F38B0           0
RESERV0035            0x0035   Reserved
RESERV0036            0x0036   Reserved
RESERV0037            0x0037   Reserved
RESERV0038            0x0038   Reserved
RESERV0039            0x0039   Reserved
RESERV003A            0x003A   Reserved
RESERV003B            0x003B   Reserved
RESERV003C            0x003C   Reserved
RESERV003D            0x003D   Reserved
MISC                  0x003E   Miscellaneous
MISC.FTUP              7   OSC Time Up Flag
MISC.STUP              6   XOSC Time Up Flag
MISC.SYS1              3   System Clock Select 1
MISC.SYS0              2   System Clock Select 0
MISC.FORCE             1   Fast (Main) Oscillator Enable
MISC.OPTM              0   Option Map Select
RESERV003F            0x003F   Reserved


.68HC05L25
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05L25&nodeId=01M98633
; HC05L25GRS.pdf

; RAM=176
; ROM=6K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area BSS  UNUSED      0x0040:0x0050
area DATA RAM         0x0050:0x0100
area BSS  UNUSED      0x0100:0x0700
area CODE ROM         0x0700:0x1F00
area DATA TEST_VEC    0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET    0x1FFE      Reset
interrupt SWI        0x1FFC      SWI
interrupt IRQ        0x1FFA      IRQ/IRQ2
interrupt KWI        0x1FF8      KEY WAKEUP
interrupt EVI        0x1FF4      Event Counter
interrupt SPI        0x1FF2      Serial Peripheral
interrupt TBI        0x1FF0      Time Base Periodical


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003   UNUSED
UNUSED0004            0x0004   UNUSED
UNUSED0005            0x0005   UNUSED
UNUSED0006            0x0006   UNUSED
UNUSED0007            0x0007   UNUSED
INTCR                 0x0008   Interrupt Control
INTCR.IRQE             7   External Interrupt (IRQ) Enable
INTCR.KWIE             4   KWI Enable
INTCR.IRQS             3   External Interrupt (IRQ) Select Edge Sensitivity Only
INTSR                 0x0009   Interrupt Status
INTSR.IRQF             7   External Interrupt (IRQ) Flag
INTSR.KWIF             4   Key Wakeup Interrupt Flag
INTSR.RIRQ             3   Reset IRQ Flag
INTSR.RKWIF            0   Reset KWI Flag
SPCR                  0x000A   Serial Peripheral Control
SPCR.SPIE              7   SPI Interrupt Enable
SPCR.SPE               6   SPI Enable
SPCR.DORD              5   Data transmission ORDer
SPCR.MSTR              4   MaSTeR mode select
SPCR.SPR               0   SPI clock rate select
SPSR                  0x000B   Serial Peripheral Status
SPSR.SPIF              7   Serial transfer complete flag
SPSR.DCOL              6   Data COLlision
SPDR                  0x000C   Serial Peripheral Data
SPDR.SPD7              7
SPDR.SPD6              6
SPDR.SPD5              5
SPDR.SPD4              4
SPDR.SPD3              3
SPDR.SPD2              2
SPDR.SPD1              1
SPDR.SPD0              0
UNUSED000D            0x000D   UNUSED
UNUSED000E            0x000E   UNUSED
UNUSED000F            0x000F   UNUSED
TBCR1                 0x0010   Time Base Control Register 1
TBCR1.TBCLK            7   Clock Source
TBCR1.LCLK             5   LCD Clock
TBCR1.RMC4             4   Remote Control Generator Divider 4
TBCR1.RMC3             3   Remote Control Generator Divider 3
TBCR1.RMC2             2   Remote Control Generator Divider 2
TBCR1.RMC1             1   Remote Control Generator Divider 1
TBCR1.RMC0             0   Remote Control Generator Divider 0
TBCR2                 0x0011   Time Base Control Register 2
TBCR2.TBIF             7   Time Base Interrupt Flag
TBCR2.TBIE             6   Time Base Interrupt Enable
TBCR2.TBR1             5   Time Base Interrupt Rate Select 1
TBCR2.TBR0             4   Time Base Interrupt Rate Select 0
TBCR2.RTBIF            3   Reset TB Interrupt Flag
TBCR2.COPE             1   COP Enable
TBCR2.COPC             0   COP Clear
UNUSED0012            0x0012   UNUSED
UNUSED0013            0x0013   UNUSED
UNUSED0014            0x0014   UNUSED
UNUSED0015            0x0015   UNUSED
UNUSED0016            0x0016   UNUSED
UNUSED0017            0x0017   UNUSED
UNUSED0018            0x0018   UNUSED
UNUSED0019            0x0019   UNUSED
UNUSED001A            0x001A   UNUSED
UNUSED001B            0x001B   UNUSED
UNUSED001C            0x001C   UNUSED
ADDR                  0x001D   A/D Data Register
ADDR.AD7               7
ADDR.AD6               6
ADDR.AD5               5
ADDR.AD4               4
ADDR.AD3               3
ADDR.AD2               2
ADDR.AD1               1
ADDR.AD0               0
ADSCR                 0x001E   A/D Status/Control
ADSCR.CC               7   Conversion Complete
ADSCR.ADRC             6   RC Oscillator Control
ADSCR.ADON             5   A/D Subsystem On
ADSCR.CH2              2   Channel Select Bits 2
ADSCR.CH1              1   Channel Select Bits 1
ADSCR.CH0              0   Channel Select Bits 0
TBCR3                 0x001F   Time Base Control Register 3
TBCR3.RMON             6   ReMote control generator signal ON
TBCR3.RPOL             5   Remote control idle POLarity
TBCR3.RMPE             4   ReMote control generator Port output Enable
TBCR3.BCLK             3   Buzzer CLocK select
TBCR3.BZON             2   Buzzer signal ON
TBCR3.BPOL             1   Buzzer output POLarity
TBCR3.BZPE             0   Buzzer output Port Enable
LCDCR                 0x0020   LCD Control
LCDCR.LCDE             7   LCD Enable
LCDCR.PBEH             6   Port B Enable High nibble
LCDCR.DUTY             5   DUTY cycle select
LCDCR.PBEL             4   Port B Enable Low nibble
LCDCR.FC               1   Fast Charge
LCDCR.LC               0   Low Current
LDAT1                 0x0021   LCD Data
LDAT1.F1B3             7
LDAT1.F1B2             6
LDAT1.F1B1             5
LDAT1.F1B0             4
LDAT1.F0B3             3
LDAT1.F0B2             2
LDAT1.F0B1             1
LDAT1.F0B0             0
LDAT2                 0x0022   LCD Data
LDAT2.F3B3             7
LDAT2.F3B2             6
LDAT2.F3B1             5
LDAT2.F3B0             4
LDAT2.F2B3             3
LDAT2.F2B2             2
LDAT2.F2B1             1
LDAT2.F2B0             0
LDAT3                 0x0023   LCD Data
LDAT3.F5B3             7
LDAT3.F5B2             6
LDAT3.F5B1             5
LDAT3.F5B0             4
LDAT3.F4B3             3
LDAT3.F4B2             2
LDAT3.F4B1             1
LDAT3.F4B0             0
LDAT4                 0x0024   LCD Data
LDAT4.F7B3             7
LDAT4.F7B2             6
LDAT4.F7B1             5
LDAT4.F7B0             4
LDAT4.F6B3             3
LDAT4.F6B2             2
LDAT4.F6B1             1
LDAT4.F6B0             0
LDAT5                 0x0025   LCD Data
LDAT5.F9B3             7
LDAT5.F9B2             6
LDAT5.F9B1             5
LDAT5.F9B0             4
LDAT5.F8B3             3
LDAT5.F8B2             2
LDAT5.F8B1             1
LDAT5.F8B0             0
LDAT6                 0x0026   LCD Data
LDAT6.F11B3            7
LDAT6.F11B2            6
LDAT6.F11B1            5
LDAT6.F11B0            4
LDAT6.F10B3            3
LDAT6.F10B2            2
LDAT6.F10B1            1
LDAT6.F10B0            0
LDAT7                 0x0027   LCD Data
LDAT7.F13B3            7
LDAT7.F13B2            6
LDAT7.F13B1            5
LDAT7.F13B0            4
LDAT7.F12B3            3
LDAT7.F12B2            2
LDAT7.F12B1            1
LDAT7.F12B0            0
LDAT8                 0x0028   LCD Data
LDAT8.F15B3            7
LDAT8.F15B2            6
LDAT8.F15B1            5
LDAT8.F15B0            4
LDAT8.F14B3            3
LDAT8.F14B2            2
LDAT8.F14B1            1
LDAT8.F14B0            0
LDAT9                 0x0029   LCD Data
LDAT9.F17B3            7
LDAT9.F17B2            6
LDAT9.F17B1            5
LDAT9.F17B0            4
LDAT9.F16B3            3
LDAT9.F16B2            2
LDAT9.F16B1            1
LDAT9.F16B0            0
LDAT10                0x002A   LCD Data
LDAT10.F19B3           7
LDAT10.F19B2           6
LDAT10.F19B1           5
LDAT10.F19B0           4
LDAT10.F18B3           3
LDAT10.F18B2           2
LDAT10.F18B1           1
LDAT10.F18B0           0
LDAT11                0x002B   LCD Data
LDAT11.F21B3           7
LDAT11.F21B2           6
LDAT11.F21B1           5
LDAT11.F21B0           4 
LDAT11.F20B3           3
LDAT11.F20B2           2
LDAT11.F20B1           1
LDAT11.F20B0           0
LDAT12                0x002C   LCD Data
LDAT12.F23B3           7
LDAT12.F23B2           6
LDAT12.F23B1           5
LDAT12.F23B0           4
LDAT12.F22B3           3
LDAT12.F22B2           2
LDAT12.F22B1           1
LDAT12.F22B0           0
LDAT13                0x002D   LCD Data
LDAT13.F24B3           3
LDAT13.F24B2           2
LDAT13.F24B1           1
LDAT13.F24B0           0
EVSCR                 0x002E   Event Control Status/Counter
EVSCR.EVCE             7   EVent Counter Enable
EVSCR.EVIE             6   EVent counter complete Interrupt Enable
EVSCR.EVOE             5   EVent counter Overflow Enable
EVSCR.EVIF             4   EVent counter complete Interrupt Flag (read only)
EVSCR.EVOF             3   EVent counter Overflow Flag (read only)
EVSCR.RCCF             2   Reset Count Complete interrupt Flag (write only)
EVSCR.ROIF             1   Reset Overflow Interrupt Flag (write only)
EVTR                  0x002F   Event Counter Timing
EVTR.WT3               7
EVTR.WT2               6
EVTR.WT1               5
EVTR.WT0               4 
EVTR.MT3               3
EVTR.MT2               2
EVTR.MT1               1
EVTR.MT0               0
EVDH                  0x0030  Event Counter Data High
EVDL                  0x0031  Event Counter Data LOW
UNUSED0032            0x0032   UNUSED
UNUSED0033            0x0033   UNUSED
UNUSED0034            0x0034   UNUSED
UNUSED0035            0x0035   UNUSED
UNUSED0036            0x0036   UNUSED
UNUSED0037            0x0037   UNUSED
UNUSED0038            0x0038   UNUSED
UNUSED0039            0x0039   UNUSED
UNUSED003A            0x003A   UNUSED
UNUSED003B            0x003B   UNUSED
UNUSED003C            0x003C   UNUSED
UNUSED003D            0x003D   UNUSED
MISC                  0x003E   Miscellaneous
MISC.FTUP              7   OSC Time Up Flag
MISC.STUP              6   XOSC Time Up Flag
MISC.SYS1              3   System Clock Select 1
MISC.SYS0              2   System Clock Select 0
MISC.FORCE             1   Fast (Main) Oscillator Enable
MISC.OPTM              0   Option Map Select
RESERV003F            0x003F   RESERVED
RESERV1FF6            0x1FF6   RESERVED
RESERV1FF7            0x1FF7   RESERVED


.68HC05L28
; http://
; MC68HC05L28.pdf

; EPROM=0
; ROM=8176
; RAM=256
; EEPROM=240


; MEMORY MAP
area DATA FSR        0x0000:0x0040
area DATA LCDRAM     0x0040:0x004C
area BSS  RESERVED   0x004C:0x0080
area DATA RAM        0x0080:0x0180
area BSS  RESERVED   0x0180:0x0300
area CODE EEPROM     0x0300:0x03F0
area BSS  RESERVED   0x03F0:0x1000
area CODE ROM        0x1000:0x2FF0
area BSS  RESERVED   0x2FF0:0x3F00
area CODE BootROM    0x3F00:0x3FF0
area DATA USER_VEC   0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET 	0x3FFE       Reset
interrupt SWI 		0x3FFC       Software interrupt
interrupt IRQ 		0x3FFA       External interrupt
interrupt CT 		0x3FF8       Core timer
interrupt I2C 		0x3FF6       I2C
interrupt PT 		0x3FF4       Programmable timer


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
RESERV0002            0x0002    Reserved
RESERV0003            0x0003    Reserved
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005   Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
RESERV0006            0x0006   Reserved
RESERV0007            0x0007   Reserved
CTCSR                 0x0008   Core timer control/status
CTCSR.CTOF             7   Core timer overflow
CTCSR.RTIF             6   Real time interrupt flag
CTCSR.CTOFE            5   Core timer overflow enable
CTCSR.RTIE             4   Real time interrupt enable
CTCSR.RT1              1   Real time interrupt rate select 1
CTCSR.RT0              0   Real time interrupt rate select 0
CTCR                  0x0009   Core timer counter
IRQ1                  0x000A   IRQ1
IRQ1.IRQ1INT           5   IRQ1 interrupt flag
IRQ1.IRQ1ENA           4   IRQ1 interrupt enable
IRQ1.IRQ1LV            3   IRQ1 interrupt sensitivity bits
IRQ1.IRQ1EDG           2   IRQ1 interrupt sensitivity bits
IRQ1.IRQ1RST           1   IRQ1 reset
IRQ1.IRQ1VAL           0   IRQ1 pin status
IRQ2                  0x000B   IRQ2
IRQ2.IRQ2INT           5   IRQ2 interrupt flag
IRQ2.IRQ2ENA           4   IRQ2 interrupt enable
IRQ2.IRQ2LV            3   IRQ2 interrupt sensitivity bits
IRQ2.IRQ2EDG           2   IRQ2 interrupt sensitivity bits
IRQ2.IRQ2RST           1   IRQ2 reset
IRQ2.IRQ2VAL           0   IRQ2 pin status
RESERV000C            0x000C   Reserved
RESERV000D            0x000D   Reserved
RESERV000E            0x000E   Reserved
RESERV000F            0x000F   Reserved
MADR                  0x0010   I2 address
MADR.ADR7              7   Slave address bit 7
MADR.ADR6              6   Slave address bit 6
MADR.ADR5              5   Slave address bit 5
MADR.ADR4              4   Slave address bit 4
MADR.ADR3              3   Slave address bit 3
MADR.ADR2              2   Slave address bit 2
MADR.ADR1              1   Slave address bit 1
FDR                   0x0011   I2C frequency divide
FDR.MBC4               4   Clock rate select bit 4
FDR.MBC3               3   Clock rate select bit 3
FDR.MBC2               2   Clock rate select bit 2
FDR.MBC1               1   Clock rate select bit 1
FDR.MBC0               0   Clock rate select bit 0
MCR                   0x0012   I2C control
MCR.MEN                7   I2C-bus enable
MCR.MIEN               6   I2C-bus interrupt enable
MCR.MSTA               5   Master/slave mode select
MCR.MTX                4   Transmit/receive mode select
MCR.TXAK               3   Transmit acknowledge bit
MSR                   0x0013   I2C status
MSR.MCF                7   Data transferring
MSR.MAAS               6   I2C-bus addressed as a slave
MSR.MBB                5   Bus busy
MSR.MAL                4   Arbitration lost
MSR.SRW                2   Read/write command
MSR.MIF                1   I2C-bus interrupt flag
MSR.RXAK               0   Received acknowledge bit
MDR                   0x0014   I2C data
MDR.TRXD7              7
MDR.TRXD6              6
MDR.TRXD5              5
MDR.TRXD4              4 
MDR.TRXD3              3
MDR.TRXD2              2
MDR.TRXD1              1
MDR.TRXD0              0
ADSTAT                0x0015   A/D status control
ADSTAT.COCO            7   Conversion complete flag
ADSTAT.ADRC            6   A/D RC oscillator control
ADSTAT.ADON            5   A/D converter on
ADSTAT.CH3             3   A/D channels 3
ADSTAT.CH2             2   A/D channels 2
ADSTAT.CH1             1   A/D channels 1
ADSTAT.CH0             0   A/D channels 0
ADIN                  0x0016   A/D input
ADIN.AD1               1
ADIN.AD0               0
ADDATA                0x0017   A/D data
RESERV0018            0x0018   Reserved
RESERV0019            0x0019   Reserved
RESERV001A            0x001A   Reserved
EEPROG                0x001B   EEPROM Program
EEPROG.CPEN            6   Charge pump enable
EEPROG.ER1             4   Erase select bit 1
EEPROG.ER0             3   Erase select bit 0
EEPROG.LATCH           2   EEPROM latch control
EEPROG.EERC            1   EEPROM RC oscillator control
EEPROG.EEPGM           0   EEPROM program control
RESERV001C            0x001C   Reserved
OPT                   0x001D   Option
OPT.IRQED              1   IRQ edge sensitivity
OPT.COPON              0   COP function enable/disable
LCD                   0x001E   LCD control
LCD.VLCDON             6   LCD voltage select
LCD.FDISP              3   Display frequency
LCD.MUX4               2   Multiplex ratio 4
LCD.MUX3               1   Multiplex ratio 3
LCD.DISON              0   Display ON/OFF
RESERV001F            0x001F   Reserved
IC1H                  0x0020   Input capture1 HIGH
IC1L                  0x0021   Input capture1 LOW
OC1H                  0x0022   Output compare 1 HIGH
OC1L                  0x0023   Output compare 1 LOW
IC2H                  0x0024   Input capture2 HIGH
IC2L                  0x0025   Input capture2 LOW
OC2H                  0x0026   Output compare 2 HIGH
OC2L                  0x0027   Output compare 2 LOW
TCH                   0x0028   Timer counter HIGH
TCL                   0x0029   Timer counter LOW
ACH                   0x002A   Alternater counter HIGH
ACL                   0x002B   Alternater counter LOW
TCR1                  0x002C   Timer control 1
TCR1.IC1IE             7   Input capture 1 interrupt enable
TCR1.IC2IE             6   Input capture 2 interrupt enable
TCR1.OC1IE             5   Output compare 1 interrupt enable
TCR1.TOIE              4   Timer overflow interrupt enable
TCR1.CO1E              3   Timer compare 1 output enable
TCR1.IEDG1             2   Input edge 1
TCR1.IEDG2             1   Input edge 2
TCR1.OLV1              0   Output level 1
TCR2                  0x002D   Timer control 2
TCR2.OC2IE             5   Output compare 2 interrupt enable
TCR2.CO2E              3   Timer compare 2 output enable
TCR2.OLV2              0   Output level 2
TSR                   0x002E   Timer status
TSR.IC1F               7   Input capture 1 flag
TSR.IC2F               6   Input capture 2 flag
TSR.OC1F               5   Output compare 1 flag
TSR.TOF                4   Timer overflow flag
TSR.TCAP1              3   Timer capture 1
TSR.TCAP2              2   Timer capture 2
TSR.OC2F               1   Output compare 2 flag
RESERV002F            0x002F   Reserved
PORTD                 0x0030   Port D Datat
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRD                  0x0031  Port D Data direction
DDRD.DDRD5             5   Data Direction for Port D Bit 5
DDRD.DDRD4             4   Data Direction for Port D Bit 4
DDRD.DDRD3             3   Data Direction for Port D Bit 3
DDRD.DDRD2             2   Data Direction for Port D Bit 2
DDRD.DDRD1             1   Data Direction for Port D Bit 1
DDRD.DDRD0             0   Data Direction for Port D Bit 0
COND                  0x0032   Port D control
COND.COND5             5
COND.COND4             4
COND.COND3             3
COND.COND2             2
COND.COND1             1
COND.COND0             0
SELD                  0x0033   Port D select
SELD.PD5_SCL0          5   Port D pin 5/SCL0 select
SELD.PD4_SDA0          4   Port D pin 4/SCL1 select
SELD.PD3_TCMP2         3   Port D pin 3/TCMP2 select
SELD.PD2_TCAP2         2   Port D pin 2/TCAP2 select
SELD.PD1_TCMP1         1   Port D pin 1/TCMP1 select
SELD.PD0_TCAP1         0   Port D pin 0/TCAP1 select
RESERV0034            0x0034   Reserved
RESERV0035            0x0035   Reserved
RESERV0036            0x0036   Reserved
RESERV0037            0x0037   Reserved
RESERV0038            0x0038   Reserved
RESERV0039            0x0039   Reserved
RESERV003A            0x003A   Reserved
RESERV003B            0x003B   Reserved
RESERV003C            0x003C   Reserved
RESERV003D            0x003D   Reserved
RESERV003E            0x003E   Reserved
RESERV003F            0x003F   Reserved
COP                   0x3FF0   COP
COP.COPR               0
RESERV1FF1            0x3FF1   RESERVED
RESERV1FF2            0x3FF2   RESERVED
RESERV1FF3            0x3FF3   RESERVED


.68HC05LJ5
; HC05LJ5GRS/H  http://
; HC05LJ5GRS.pdf

; RAM=64
; ROM=1.2K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area BSS  UNUSED	0x0020:0x00C0
area DATA RAM		0x00C0:0x0100
area BSS  UNUSED	0x0100:0x0300
area DATA ROM		0x0300:0x0800
area BSS  UNUSED	0x0800:0x0F00
area DATA TEST_ROM	0x0F00:0x0FF0
area BSS  UNUSED	0x0FF0:0x0FF8
area DATA USER_VEC	0x0FF8:0x1000


; Interrupt and reset vector assignments
interrupt __RESET 	0x0FFE       Reset
interrupt SWI 		0x0FFC       Software
interrupt IRQ 		0x0FFA       External Interrupt
interrupt TIMER 	0x0FF8       TIMER


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
UNUSED0002            0x0002     UNUSED
UNUSED0003            0x0003     UNUSED
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.SLOWE             7   Slow Transition Enabled
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
UNUSED0006            0x0006     UNUSED
UNUSED0007            0x0007     UNUSED
TCSR                  0x0008     MFT Ctrl_Status
TCSR.TOF               7   Timer Overflow Flag
TCSR.RTIF              6   Real Time Interrupt Flag
TCSR.TOFE              5   Timer Overflow Enable
TCSR.RTIE              4   Real Time Interrupt Enable
TCSR.TOFR              3   Timer Overflow Acknowledge
TCSR.RTIFR             2   Real Time Interrupt Acknowledge
TCSR.RT1               1   Real Time Interrupt Rate Select 1
TCSR.RT0               0   Real Time Interrupt Rate Select 0
TCNT                  0x0009     MFT Counter
TCNT.TMR7              7
TCNT.TMR6              6
TCNT.TMR5              5
TCNT.TMR4              4
TCNT.TMR3              3
TCNT.TMR2              2
TCNT.TMR1              1
TCNT.TMR0              0
ICSR                  0x000A     IRQ Control_Status
ICSR.IRQE              7   IRQ Interrupt Enable
ICSR.IRQE1             6   PA7 Interrupt Enable
ICSR.IRQF              3   IRQ Interrupt Request Flag
ICSR.IRQF1             2   PA7 Interrupt Request Flag
ICSR.IRQR              1   IRQ Interrupt Acknowledge
ICSR.IRQR1             0   PA7 Interrupt Acknowledge
UNUSED000B            0x000B     UNUSED
UNUSED000C            0x000C     UNUSED
UNUSED000D            0x000D     UNUSED
UNUSED000E            0x000E     UNUSED
UNUSED000F            0x000F     UNUSED
PDURA                 0x0010     Port A Pull-down_up
PDURA.PURA7            7
PDURA.PURA6            6
PDURA.PDRA5            5
PDURA.PDRA4            4
PDURA.PDRA3            3
PDURA.PDRA2            2
PDURA.PDRA1            1
PDURA.PDRA0            0
PDURB                 0x0011     Port B Pull-down_up
PDURB.PDRB5            5
PDURB.PDRB4            4
PDURB.PDRB3            3
PDURB.PURB2            2
PDURB.PURB1            1
PDURB.PDRB0            0
UNUSED0012            0x0012     UNUSED
UNUSED0013            0x0013     UNUSED
UNUSED0014            0x0014     UNUSED
UNUSED0015            0x0015     UNUSED
UNUSED0016            0x0016     UNUSED
UNUSED0017            0x0017     UNUSED
UNUSED0018            0x0018     UNUSED
UNUSED0019            0x0019     UNUSED
UNUSED001A            0x001A     UNUSED
UNUSED001B            0x001B     UNUSED
UNUSED001C            0x001C     UNUSED
UNUSED001D            0x001D     UNUSED
UNUSED001E            0x001E     UNUSED
RESERV001F            0x001F     RESERVED
COP                   0x0FF0     COP Watchdog Timer
COP.COPR               0
RESERV0FF1            0x0FF1    RESERVED
RESERV0FF2            0x0FF2    RESERVED
RESERV0FF3            0x0FF3    RESERVED
RESERV0FF4            0x0FF4    RESERVED
RESERV0FF5            0x0FF5    RESERVED
RESERV0FF6            0x0FF6    RESERVED
RESERV01F7            0x0FF7    RESERVED


.68HC05P18A
; http://
; MC68HC05P18A.pdf

; 192 bytes of RAM
; 128 bytes of EEPROM
; 8000 bytes of user ROM
; 48 bytes of user page zero ROM
; 16 bytes of user vector ROM

; RAM=192
; ROM=8KK
; EPROM=0
; EEPROM=128


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_1       0x0020:0x0050
area DATA RAM         0x0050:0x0140
area DATA EEPROM      0x0140:0x01C0
area BSS  UNUSED      0x01C0:0x1FC0
area DATA ROM_2       0x1FC0:0x3F00
area DATA TEST_VEC    0x3F00:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      ...
interrupt Timer             0x3FF8


; INPUT/ OUTPUT PORTS
PORTA		0x0000		Port A Data Register
PORTA.PA7         7  Port A Data Bits 7
PORTA.PA6         6  Port A Data Bits 6
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB		0x0001		Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTC		0x0002		Port C Data Register
PORTC.PC7         7  Port C Data Bits 7
PORTC.PC6         6  Port C Data Bits 6
PORTC.PC5         5  Port C Data Bits 5
PORTC.PC4         4  Port C Data Bits 4
PORTC.PC3         3  Port C Data Bits 3
PORTC.PC2         2  Port C Data Bits 2
PORTC.PC1         1  Port C Data Bits 1
PORTC.PC0         0  Port C Data Bits 0
PORTD		0x0003		Port D Data Register
PORTD.PD7         7  Port D Data Bits 7
PORTD.PD5         5  Port D Data Bits 5
DDRA		0x0004		Port A Data Direction
DDRA.DDRA7        7  Data Direction for Port A Bit 7
DDRA.DDRA6        6  Data Direction for Port A Bit 6
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB		0x0005		Port B Data Direction
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRC		0x0006		Port C Data Direction
DDRC.DDRC7        7  Data Direction for Port C Bit 7
DDRC.DDRC6        6  Data Direction for Port C Bit 6
DDRC.DDRC5        5  Data Direction for Port C Bit 5
DDRC.DDRC4        4  Data Direction for Port C Bit 4
DDRC.DDRC3        3  Data Direction for Port C Bit 3
DDRC.DDRC2        2  Data Direction for Port C Bit 2
DDRC.DDRC1        1  Data Direction for Port C Bit 1
DDRC.DDRC0        0  Data Direction for Port C Bit 0
DDRD		0x0007		Port D Data Direction
DDRD.DDRD5        5  Data Direction for Port D Bit 5
UNUSED0008      0x0008          UNUSED
UNUSED0009      0x0009          UNUSED
SCR		0x000A		SIOP Control Register
SCR.SPE           6  Serial Peripheral Enable Bit
SCR.MSTR          4  Master Mode Select Bit
SSR		0x000B		SIOP Status Register
SSR.SPIF          7  Serial Port Interface Flag
SSR.DCOL          6  Data Collision Bit
SDR		0x000C		SIOP Data Register
SDR.SDR7          7
SDR.SDR6          6
SDR.SDR5          5
SDR.SDR4          4
SDR.SDR3          3
SDR.SDR2          2
SDR.SDR1          1
SDR.SDR0          0
Reserv000D	0x000D          RESERVED
UNUSED000E      0x000E          UNUSED
UNUSED000F      0x000F          UNUSED
UNUSED0010      0x0010          UNUSED
UNUSED0011      0x0011          UNUSED
TCR		0x0012		Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Comapre Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable Bit
TCR.IEDG          1  Input Capture Edge Select Bit
TCR.OLVL          0  Output Compare Output Level Select Bit
TSR		0x0013		Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Bit
TSR.TOF           5  Timer Overflow Flag
ICRH		0x0014		Input Capture Register
ICRH.ICRH7        7
ICRH.ICRH6        6
ICRH.ICRH5        5
ICRH.ICRH4        4
ICRH.ICRH3        3
ICRH.ICRH2        2
ICRH.ICRH1        1
ICRH.ICRH0        0
ICRL		0x0015		Input Capture Register
ICRL.ICRL7        7
ICRL.ICRL6        6
ICRL.ICRL5        5
ICRL.ICRL4        4
ICRL.ICRL3        3
ICRL.ICRL2        2
ICRL.ICRL1        1
ICRL.ICRL0        0
OCRH		0x0016		Output Compare Register
OCRH.OCRH7        7
OCRH.OCRH6        6
OCRH.OCRH5        5
OCRH.OCRH4        4
OCRH.OCRH3        3
OCRH.OCRH2        2
OCRH.OCRH1        1
OCRH.OCRH0        0
OCRL		0x0017		Output Compare Register
OCRL.OCRL7        7
OCRL.OCRL6        6
OCRL.OCRL5        5
OCRL.OCRL4        4
OCRL.OCRL3        3
OCRL.OCRL2        2
OCRL.OCRL1        1
OCRL.OCRL0        0
TMRH		0x0018		Timer Counter Register
TMRH.TMRH7        7
TMRH.TMRH6        6
TMRH.TMRH5        5
TMRH.TMRH4        4
TMRH.TMRH3        3
TMRH.TMRH2        2
TMRH.TMRH1        1
TMRH.TMRH0        0
TMRL		0x0019		Timer Counter Register
TMRL.TMRL7        7
TMRL.TMRL6        6
TMRL.TMRL5        5
TMRL.TMRL4        4
TMRL.TMRL3        3
TMRL.TMRL2        2
TMRL.TMRL1        1
TMRL.TMRL0        0
ACRH		0x001A		Alternate Counter Register
ACRH.ACRH7        7
ACRH.ACRH6        6
ACRH.ACRH5        5
ACRH.ACRH4        4
ACRH.ACRH3        3
ACRH.ACRH2        2
ACRH.ACRH1        1
ACRH.ACRH0        0
ACRL		0x001B		Alternate Counter Register
ACRL.ACRL7        7
ACRL.ACRL6        6
ACRL.ACRL5        5
ACRL.ACRL4        4
ACRL.ACRL3        3
ACRL.ACRL2        2
ACRL.ACRL1        1
ACRL.ACRL0        0
EEPROG		0x001C 		EEPROM Programming Register
EEPROG.CPEN       6  Charge Pump Enable Bit
EEPROG.ER1        4  Erase Select Bits 1
EEPROG.ER0        3  Erase Select Bits 0
EEPROG.LATCH      2  EEPROM Programming Latch Bit
EEPROG.EERC       1  EEPROM RC Oscillator Control Bit
EEPROG.EEPGM      0  EEPROM Programming Power Enable Bit
ADC		0x001D 		A_D Conversion Value Data Register
ADC.AD7           7
ADC.AD6           6
ADC.AD5           5
ADC.AD4           4
ADC.AD3           3
ADC.AD2           2
ADC.AD1           1
ADC.AD0           0
ADSCR		0x001E 		A_D Converter Status and Control Register
ADSCR.CC          7  Conversion Complete Bit
ADSCR.ADON        5  A/D Subsystem On Bit
ADSCR.CH2         2  Channel Select Bits 2
ADSCR.CH1         1  Channel Select Bits 1
ADSCR.CH0         0  Channel Select Bits 0
Reserv001F	0x001F          Reserved
COP             0x3FF0          COP CONTROL REGISTER
COP.COPR          0
RESERV3FF1      0x3FF1          RESERVED
RESERV3FF2      0x3FF2          RESERVED
RESERV3FF3      0x3FF3          RESERVED
RESERV3FF4      0x3FF4          RESERVED
RESERV3FF5      0x3FF5          RESERVED
RESERV3FF6      0x3FF6          RESERVED
RESERV3FF7      0x3FF7          RESERVED


.68HC05P3
; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC05P3.pdf
; MC68HC05P3.pdf

; RAM=128
; ROM=2k 
; EPROM=0 
; EEPROM=128


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x0080
area DATA RAM         0x0080:0x0100
area DATA EEPROM      0x0100:0x0180
area BSS  UNUSED      0x0180:0x0300
area DATA ROM         0x0300:0x0F00
area DATA BootROM     0x0F00:0x0FE0
area DATA BOOT_VEC    0x0FE0:0x0FF0
area BSS  RESERVED    0x0FF0:0x0FF6
area DATA USER_VEC    0x0FF6:0x1000


; Interrupt and reset vector assignments
interrupt __RESET           0x0FFE      Processor reset
interrupt SWI               0x0FFC      Software interrupt
interrupt IRQ_Keyboard      0x0FFA      ...
interrupt CoreTimer_RTI     0x0FF8
interrupt TIMER             0x0FF6


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003    UNUSED
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006    Port C data direction
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007    UNUSED
CTCSR                 0x0008    CTimer control and Status Register
CTCSR.CTOF             7   Timer Overflow Flag       
CTCSR.RTIF             6   Real Time Interrupt Flag  
CTCSR.CTOFE            5   Timer Overflow Enable     
CTCSR.RTIE             4   Real Time Interrupt Enable
CTCSR.RT1              1   Real Time Interrupt Rate Select 1
CTCSR.RT0              0   Real Time Interrupt Rate Select 0
CTCR                  0x0009    CTimer Counter Register
CTCR.CT7               7
CTCR.CT6               6
CTCR.CT5               5
CTCR.CT4               4
CTCR.CT3               3
CTCR.CT2               2
CTCR.CT1               1
CTCR.CT0               0
KEY_TIM               0x000A    Keyboard/timer
KEY_TIM.TIMEN          2
KEY_TIM.KSF            1
KEY_TIM.KIE            0        
UNUSED000B            0x000B    UNUSED
UNUSED000C            0x000C    UNUSED
UNUSED000D            0x000D    UNUSED
UNUSED000E            0x000E    UNUSED
OPT                   0x000F    URQ status/control
UNUSED0010            0x0010    UNUSED
UNUSED0011            0x0011    UNUSED
TCR                   0x0012    Timer control
TCR.ICIE               7
TCR.OCIE               6
TCR.TOIE               5
TCR.IEDG               1
TCR.OLVL               0
TSR                   0x0013    Timer status
TSR.ICF                7
TSR.OCF                6
TSR.TOF                5
ICH                   0x0014    Input capture high
ICH.IC15               7
ICH.IC14               6
ICH.IC13               5
ICH.IC12               4
ICH.IC11               3
ICH.IC10               2
ICH.IC9                1
ICH.IC8                0
ICL                   0x0015    Input capture low
ICL.IC7                7
ICL.IC6                6
ICL.IC5                5
ICL.IC4                4
ICL.IC3                3
ICL.IC2                2
ICL.IC1                1
ICL.IC0                0
OCH                   0x0016    Output compare high
OCH.OC15               7
OCH.OC14               6
OCH.OC13               5
OCH.OC12               4
OCH.OC11               3
OCH.OC10               2
OCH.OC9                1
OCH.OC8                0
OCL                   0x0017    Output compare low
OCL.OC7                7
OCL.OC6                6 
OCL.OC5                5 
OCL.OC4                4
OCL.OC3                3
OCL.OC2                2
OCL.OC1                1
OCL.OC0                0
TCH                   0x0018     Counter high
TCH.TC15               7
TCH.TC14               6
TCH.TC13               5
TCH.TC12               4
TCH.TC11               3
TCH.TC10               2
TCH.TC9                1
TCH.TC8                0
TCL                   0x0019     Counter low
TCL.TC7                7
TCL.TC6                6
TCL.TC5                5
TCL.TC4                4
TCL.TC3                3
TCL.TC2                2
TCL.TC1                1
TCL.TC0                0
ACH                   0x001A    Alternate counter high
ACH.AC15               7
ACH.AC14               6
ACH.AC13               5 
ACH.AC12               4
ACH.AC11               3
ACH.AC10               2
ACH.AC9                1
ACH.AC8                0
ACL                   0x001B    Alternate counter low
ACL.AC7                7
ACL.AC6                6
ACL.AC5                5
ACL.AC4                4
ACL.AC3                3
ACL.AC2                2
ACL.AC1                1
ACL.AC0                0
EEPROG                0x001C    EEPROM programming control
EEPROG.CPEN            6   Charge pump enable          
EEPROG.ER1             4   Erase select bit 1          
EEPROG.ER0             3   Erase select bit 0          
EEPROG.LATCH           2   EEPROM latch control        
EEPROG.EERC            1   EEPROM RC oscillator control
EEPROG.EEPGM           0   EEPROM program control      
UNUSED001D            0x001D    UNUSED
RESERV001F            0x001F    RESERVED


.68HC05P4
; http://
; MC68HC05P4.pdf

; RAM=176
; ROM=4160+240
; EPROM=0 
; EEPROM=0  


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_P1      0x0020:0x0050
area DATA RAM         0x0050:0x0100
area DATA ROM_P2      0x0100:0x1100
area BSS  UNUSED      0x1100:0x1F00
area DATA ROM_S_CH    0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      ...
interrupt Timer             0x1FF8


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001    Port B data
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTC          0x0002    Port C data
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
PORTD          0x0003    Port D data
PORTD.PD7       7   Port D Data Bits 7
PORTD.PD5       5   Port D Data Bits 5
DDRA           0x0004    Port A data direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005    Port B data direction
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRC           0x0006    Port C data direction
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC6      6   Data Direction for Port C Bit 6
DDRC.DDRC5      5   Data Direction for Port C Bit 5
DDRC.DDRC4      4   Data Direction for Port C Bit 4
DDRC.DDRC3      3   Data Direction for Port C Bit 3
DDRC.DDRC2      2   Data Direction for Port C Bit 2
DDRC.DDRC1      1   Data Direction for Port C Bit 1
DDRC.DDRC0      0   Data Direction for Port C Bit 0
DDRD           0x0007    Port D data direction
DDRD.DDRD5      5   Data Direction for Port D Bit 5
UNUSED0008     0x0008    UNUSED
UNUSED0009     0x0009    UNUSED
SCR            0x000A    SCR
SCR.CPE         6   Charge pump enable
SCR.MSTR        4
SSR            0x000B    SSR
SSR.SPIF        7   Serial Port Interface Flag
SSR.DCOL        6   Data Collision Bit
SDR            0x000C    SDR
UNUSED000D     0x000D    UNUSED
UNUSED000E     0x000E    UNUSED
UNUSED000F     0x000F    UNUSED
UNUSED0010     0x0010    UNUSED
UNUSED0011     0x0011    UNUSED
TCR            0x0012    Timer control
TCR.ICIE        7   Input Capture Interrupt Enable Bit    
TCR.OCIE        6   Output Comapre Interrupt Enable Bit   
TCR.TOIE        5   Timer Overflow Interrupt Enable Bit   
TCR.IEDG        1   Input Capture Edge Select Bit         
TCR.OLVL        0   Output Compare Output Level Select Bit
TSR            0x0013    Timer status
TSR.ICF         7   Input Capture Flag
TSR.OCF         6   Output Compare Bit
TSR.TOF         5   Timer Overflow Flag
TCAPH          0x0014    TCAPH
TCAPL          0x0015    TCAPL
TCMPH          0x0016    TCMPH
TCMPL          0x0017    TCMPL
TCNTH          0x0018    TCNTH
TCNTL          0x0019    TCNTL
ALTCNTH        0x001A    ALTCNTH
ALTCNTL        0x001B    ALTCNTL
UNUSED001C     0x001C    UNUSED
UNUSED001D     0x001D    UNUSED
UNUSED001E     0x001E    UNUSED
RESERV001F     0x001F    RESERVED
COP            0x1FF0    COP
COP.COPR        0
RESERV1FF1     0x1FF1    RESERVED
RESERV1FF2     0x1FF2    RESERVED
RESERV1FF3     0x1FF3    RESERVED
RESERV1FF4     0x1FF4    RESERVED
RESERV1FF5     0x1FF5    RESERVED
RESERV1FF6     0x1FF6    RESERVED
RESERV1FF7     0x1FF7    RESERVED


.68HC05P4A
; http://
; MC68HC05P4A.pdf

; RAM=176
; ROM=4K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_0       0x0020:0x0050
area DATA RAM         0x0050:0x0100
area DATA ROM_1       0x0100:0x1100
area BSS  UNUSED      0x1100:0x1F00
area DATA ROM_2       0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      ...
interrupt TIMER             0x1FF8      TIMER


; INPUT/ OUTPUT PORTS
PORTA		0x0000 		Port A Data Register
PORTA.PA7         7  Port A Data Bits 7
PORTA.PA6         6  Port A Data Bits 6
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB		0x0001 		Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTC		0x0002 		Port C Data Register
PORTC.PC7         7  Port C Data Bits 7
PORTC.PC6         6  Port C Data Bits 6
PORTC.PC5         5  Port C Data Bits 5
PORTC.PC4         4  Port C Data Bits 4
PORTC.PC3         3  Port C Data Bits 3
PORTC.PC2         2  Port C Data Bits 2
PORTC.PC1         1  Port C Data Bits 1
PORTC.PC0         0  Port C Data Bits 0
PORTD		0x0003 		Port D Data Register
PORTD.PD7         7  Port D Data Bits 7
PORTD.PD5         5  Port D Data Bits 6
DDRA		0x0004 		Port A Data Direction
DDRA.DDRA7        7  Data Direction for Port A Bit 7
DDRA.DDRA6        6  Data Direction for Port A Bit 6
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB		0x0005 		Port B Data Direction
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRC		0x0006 		Port C Data Direction
DDRC.DDRC7        7  Data Direction for Port C Bit 7
DDRC.DDRC6        6  Data Direction for Port C Bit 6
DDRC.DDRC5        5  Data Direction for Port C Bit 5
DDRC.DDRC4        4  Data Direction for Port C Bit 4
DDRC.DDRC3        3  Data Direction for Port C Bit 3
DDRC.DDRC2        2  Data Direction for Port C Bit 2
DDRC.DDRC1        1  Data Direction for Port C Bit 1
DDRC.DDRC0        0  Data Direction for Port C Bit 0
DDRD		0x0007 		Port D Data Direction
DDRD.DDRD5        5  Data Direction for Port D Bit 5
UNUSED0008      0x0008          UNUSED
UNUSED0009      0x0009          UNUSED
SCR		0x000A 		SIOP Control Register
SCR.SPE           6  Serial Peripheral Enable Bit
SCR.MSTR          4  Master Mode Bit
SSR		0x000B 		SIOP Status Register
SSR.SPIF          7  Serial Peripheral Interface Flag Bit
SSR.DCOL          6  Data Collision Bit
SDR		0x000C 		SIOP Data Register
UNUSED000D      0x000D          UNUSED
UNUSED000E      0x000E          UNUSED
UNUSED000F      0x000F          UNUSED
UNUSED0010      0x0010          UNUSED
UNUSED0011      0x0011          UNUSED
TCR		0x0012 		Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable Bit
TCR.IEDG          1  Input Edge Bit
TCR.OLVL          0  Output Level Bit
TSR		0x0013 		Timer Status Register
TSR.ICF           7  Input Capture Flag Bit
TSR.OCF           6  Output Compare Flag Bit
TSR.TOF           5  Timer Overflow Flag Bit
ICRH		0x0014 		Input Capture MSB
ICRH.ICRH7        7
ICRH.ICRH6        6
ICRH.ICRH5        5
ICRH.ICRH4        4
ICRH.ICRH3        3
ICRH.ICRH2        2
ICRH.ICRH1        1
ICRH.ICRH0        0
ICRL		0x0015 		Input Capture LSB
ICRL.ICRL7        7
ICRL.ICRL6        6
ICRL.ICRL5        5
ICRL.ICRL4        4
ICRL.ICRL3        3
ICRL.ICRL2        2
ICRL.ICRL1        1
ICRL.ICRL0        0
OCRH		0x0016 		Output Compare MSB
OCRH.OCRH7        7
OCRH.OCRH6        6
OCRH.OCRH5        5 
OCRH.OCRH4        4
OCRH.OCRH3        3
OCRH.OCRH2        2
OCRH.OCRH1        1
OCRH.OCRH0        0
OCRL		0x0017 		Output Compare LSB
OCRL.OCRL7        7
OCRL.OCRL6        6
OCRL.OCRL5        5
OCRL.OCRL4        4
OCRL.OCRL3        3
OCRL.OCRL2        2
OCRL.OCRL1        1
OCRL.OCRL0        0
CRH		0x0018 		Counter MSB
CRH.CRH7          7
CRH.CRH6          6
CRH.CRH5          5
CRH.CRH4          4
CRH.CRH3          3
CRH.CRH2          2
CRH.CRH1          1
CRH.CRH0          0
CRL		0x0019 		Counter LSB
CRL.CRL7          7
CRL.CRL6          6
CRL.CRL5          5
CRL.CRL4          4
CRL.CRL3          3
CRL.CRL2          2
CRL.CRL1          1
CRL.CRL0          0
DTMH		0x001A 		Dual Timer MSB Counter Alternate Register
DTMH.DTMH7        7
DTMH.DTMH6        6
DTMH.DTMH5        5
DTMH.DTMH4        4
DTMH.DTMH3        3
DTMH.DTMH2        2
DTMH.DTMH1        1
DTMH.DTMH0        0
DTML		0x001B 		Dual Timer LSB Counter Alternate Register
DTML.DTML7        7
DTML.DTML6        6
DTML.DTML5        5
DTML.DTML4        4
DTML.DTML3        3
DTML.DTML2        2
DTML.DTML1        1
DTML.DTML0        0
UNUSED001C      0x001C          UNUSED
UNUSED001D      0x001D          UNUSED
UNUSED001E      0x001E          UNUSED
RESERV001F	0x001F          RESERVED
RESERV1FF0      0x1FF0          RESERVED
RESERV1FF1      0x1FF1          RESERVED
RESERV1FF2      0x1FF2          RESERVED
RESERV1FF3      0x1FF3          RESERVED
RESERV1FF4      0x1FF4          RESERVED
RESERV1FF5      0x1FF5          RESERVED
RESERV1FF6      0x1FF6          RESERVED
RESERV1FF7      0x1FF7          RESERVED


.68HC05P6
; http://
; MC68HC05P6.pdf

; RAM=176
; ROM=4.5K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_0       0x0020:0x0050
area DATA RAM         0x0050:0x0100
area DATA ROM_1       0x0100:0x1300
area BSS  RESERVED    0x1300:0x1F00
area DATA ROM_2       0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      ...
interrupt TIMER             0x1FF8      TIMER


; INPUT/ OUTPUT PORTS
COP    0x1FF0			CONTROL REGISTER
COP.COPR           0
RESERV1FF1 0x1FF1		RESERVED
RESERV1FF2 0x1FF2		RESERVED
RESERV1FF3 0x1FF3		RESERVED
RESERV1FF4 0x1FF4		RESERVED
RESERV1FF5 0x1FF5		RESERVED
RESERV1FF6 0x1FF6		RESERVED
RESERV1FF7 0x1FF7		RESERVED


.68HC05P9
; http://

; RAM=128
; ROM=2112
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_0       0x0020:0x0050
area BSS  RESERVED    0x0050:0x0080
area DATA RAM         0x0080:0x0100
area DATA ROM_1       0x0100:0x0900
area BSS  RESERVED    0x0900:0x1F00
area DATA ROM_2       0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      ...
interrupt TIMER             0x1FF8      TIMER


; INPUT/ OUTPUT PORTS
COP    0x1FF0			CONTROL REGISTER
COP.COPR           0
RESERV1FF1 0x1FF1		RESERVED
RESERV1FF2 0x1FF2		RESERVED
RESERV1FF3 0x1FF3		RESERVED
RESERV1FF4 0x1FF4		RESERVED
RESERV1FF5 0x1FF5		RESERVED
RESERV1FF6 0x1FF6		RESERVED
RESERV1FF7 0x1FF7		RESERVED


.68HC05P9A
; MC68HC05P9A/D  http://
; MC68HC05P9A.pdf

; RAM=128
; ROM=2392
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_0       0x0020:0x0050
area BSS  UNUSED      0x0050:0x0080
area DATA RAM         0x0080:0x0100
area DATA ROM_1       0x0100:0x0900
area BSS  UNUSED      0x0900:0x1F00
area DATA ROM_2       0x1F00:0x1FF1
area BSS  RESERVED    0x1FF1:0x1FF8
area DATA USER_VEC    0x1FF8:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      ...
interrupt TIMER             0x1FF8      TIMER


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data Register
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data Register
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTC                 0x0002     Port C Data Register
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Data Register
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD5              5   Port D Data Bits 5
DDRA                  0x0004     Data Direction Register A
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Data Direction Register B
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRC                  0x0006     Data Direction Register C
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
DDRD                  0x0007     Data Direction Register D
DDRD.DDRD5             5   Data Direction for Port D Bit 5
UNUSED0008            0x0008     UNUSED
UNUSED0009            0x0009     UNUSED
SCR                   0x000A     SIOP Control Register
SCR.SPE                6   SIOP Enable
SCR.MSTR               4   Master Mode Select
SSR                   0x000B     SIOP Status Register
SSR.SPIF               7   Serial Peripheral Interface Flag
SSR.DCOL               6   Data Collision Flag
SDR                   0x000C     SIOP Data Register
UNUSED000D            0x000D     UNUSED
UNUSED000E            0x000E     UNUSED
UNUSED000F            0x000F     UNUSED
UNUSED0010            0x0010     UNUSED
UNUSED0011            0x0011     UNUSED
TCR                   0x0012     Timer Control Register
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.IEDG               1   Input Edge
TCR.OLVL               0   Output Level
TSR                   0x0013     Timer Status Register
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICRH                  0x0014     Input Capture Register High
ICRL                  0x0015     Input Capture Register Low
OCRH                  0x0016     Output Compare Register High
OCRL                  0x0017     Output Compare Register Low
TRH                   0x0018     Timer Register High
TRL                   0x0019     Timer Register Low
ATRH                  0x001A     Alternate Timer Register High
ATRL                  0x001B     Alternate Timer Register Low
UNUSED001C            0x001C     UNUSED
ADDR                  0x001D     ADC Data Register
ADSCR                 0x001E     ADC Status_Control Register
ADSCR.CCF              7   Conversion Complete Flag
ADSCR.ADRC             6   ADC RC (Oscillator)
ADSCR.ADON             5   ADC On
ADSCR.CH2              2   Channel Select Bits 2
ADSCR.CH1              1   Channel Select Bits 1
ADSCR.CH0              0   Channel Select Bits 0
Reserv001F            0x001F     Reserved


.68HC05PV8
; MC68HC05PV8/D  http://
; MC68HC05PV8.pdf

; RAM=192
; ROM=8KK
; EPROM=0
; EEPROM=128


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA FSR_1       0x0020:0x0030
area DATA FSR_EM      0x0030:0x0040       EXTERNALLY MAPPED 4-bit I/O If enabled
area DATA RAM         0x0040:0x0100
area BSS  UNUSED      0x0100:0x0180
area DATA EEPROM1     0x0180:0x0200
area BSS  UNUSED      0x0200:0x2000
area DATA EEPROM2     0x2000:0x3F00
area DATA TEST_ROM    0x3F00:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      ...
interrupt CTIMER            0x3FF8      CORE TIMER
interrupt TIMER             0x3FF6      16-BIT TIMER


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.TCAP1            5   
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003     UNUSED
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007     UNUSED
CTSCR                 0x0008     Core Timer Status and Control Register
CTSCR.TOF              7   Timer Over Flow
CTSCR.RTIF             6   Real Time Interrupt Flag
CTSCR.TOFE             5   Timer Over Flow Enable
CTSCR.RTIE             4   Real Time Interrupt Enable
CTSCR.RTOF             3   Reset TOF
CTSCR.RTIF             2   Reset RTIF
CTSCR.RT1              1   Real Time Interrupt Rate Select 1
CTSCR.RT0              0   Real Time Interrupt Rate Select 0
CTCR                  0x0009     Core Timer Counter Register
SYSCR                 0x000A     System Control
SYSCR.POR              7
SYSCR.INTP             6   External interrupt sensitivity options
SYSCR.INTN             5   External interrupt sensitivity options
SYSCR.INTE             4   External interrupt enable
SYSCR.WCOP             3
SYSCR.WCP              2
SYSCR.FPIE             1   Fast Peripheral Interface Enable
SYSCR.FPICLK           0   Fast Peripheral Clock
UNUSED000B            0x000B     UNUSED
EEPCR                 0x000C     EEPROM Control Register
EEPCR.EEOSC            4   EEPROM RC Oscillator Control
EEPCR.EER1             3   Erase Select Bits 1
EEPCR.EER0             2   Erase Select Bits 0
EEPCR.EELAT            1   EEPROM Programming Latch
EEPCR.EEPGM            0   EEPROM Programming Power Enable
UNUSED000D            0x000D     UNUSED
ADDR                  0x000E     A_D Data
ADSCR                 0x000F     A_D Status_Control
ADSCR.COCO             7   Conversion Complete
ADSCR.ADRC             6   RC Oscillator On
ADSCR.ADON             5   A/D On
ADSCR.ADTEST           4
ADSCR.CH3              3   Channel Select Bit 3
ADSCR.CH2              2   Channel Select Bit 2
ADSCR.CH1              1   Channel Select Bit 1
ADSCR.CH0              0   Channel Select Bit 0
TIC1H                 0x0010     Timer Input Capture1 High
TIC1L                 0x0011     Timer Input Capture1 Low
TOC1H                 0x0012     Timer Output Compare1 High
TOC1L                 0x0013     Timer Output Compare1 Low
TIC2H                 0x0014     Timer Input Capture2 High
TIC2L                 0x0015     Timer Input Capture2 Low
TOC2H                 0x0016     Timer Output Compare2 High
TOC2L                 0x0017     Timer Output Compare2 Low
TCH                   0x0018     Timer Counter High
TCL                   0x0019     Timer Counter Low
TACH                  0x001A     Timer Alternate Counter High
TACL                  0x001B     Timer Alternate Counter Low
TCR1                  0x001C     Timer Control1
TCR1.ICI1E             7   Input Capture 1 Interrupt Enable
TCR1.ICI2E             6   Input Capture 2 Interrupt Enable
TCR1.OCI1E             5   Output Compare 1 Interrupt Enable
TCR1.TOIE              4   Timer Overflow Interrupt Enable
TCR1.OCI2E             3   Output Compare 2 Interrupt Enable
TCR1.TOFF              0   Shut Off Timer
TCR2                  0x001D     Timer Control2
TCR2.IEDGE1            7   Input Edge
TCR2.IEDGE2            6   Input Edge
TCR2.CLK21             5   Output Compare 2 clocks output latch 1
TCR2.FOLV1             4   Force Output Level 1
TCR2.OLVL1             3   Output Level 1
TCR2.CLK12             2   Output Compare 1 clocks output latch 2
TCR2.FOLV2             1   Force Output Level 2
TCR2.OLVL2             0   Output Level 2
TSR                   0x001E     Timer Status
TSR.IC1F               7   Input Capture 1 Flag
TSR.IC2F               6   Input Capture 2 Flag
TSR.OC1F               5   Output Compare 1 Flag
TSR.TOF                4   Timer Overflow Flag
TSR.OC2F               3   Output Compare 2 Flag
TSR.SI1                2   Sample Input 1
TSR.SI2                1   Sample Input 2
TEST                  0x001F     TEST
PACFG                 0x0020     Port A Configuration
PACFG.VRHEN            7   Enable A/D High Reference Channel
PACFG.PUHEN            6   PA4-7 Pull-Up Resistor Enable Higher Nibble
PACFG.EDGEH            5   PA4-7 Interrupt Edge Higher Nibble
PACFG.PAHIE            4   PA4-7 Interrupt Enable Higher Nibble
PACFG.PULEN            3   PA0-3 Pull-Up Resistor Enable Lower Nibble
PACFG.EDGEL            2   PA0-3 Interrupt Edge Lower Nibble
PACFG.PALIE            1   PA0-3 Interrupt Enable Lower Nibble
PACFG.VRLEN            0   Enable A/D Low Reference Channel
IOCFG                 0x0021     I_O Configuration
IOCFG.TXOR             7   Timer EXOR Enable
IOCFG.OPAMP            6   Enable Operational Amplifier
IOCFG.PB4PW            4   PB4 PWM Enable
IOCFG.PB3OC            3   PB3 Output Compare Enable
IOCFG.PB2IC            2   PB2 Input Capture Enable
IOCFG.PB1OC            1   PB1 Output Compare Enable
IOCFG.PB0IC            0   PB0 Input Capture Enable
PCCFG0                0x0022     Port C Configuration
PCCFG0.ISOM            7   Driver Mode of PC4
PCCFG0.PC6PW           6   PC6 PWM Enable
PCCFG0.PWMS1           5   PWM Select Bits 1
PCCFG0.PWMS0           4   PWM Select Bits 0
PCCFG0.PC3OC           3   PC3 Output Compare Enable
PCCFG0.TS2             2   Timer Channel 1 Select Bits 2
PCCFG0.TS1             1   Timer Channel 1 Select Bits 1
PCCFG0.TS0             0   Timer Channel 1 Select Bits 0
UNUSED0023            0x0023     UNUSED
PAISR                 0x0024     Port A Interrupt Status
PAISR.PAIF7            7   Port A Interrupt Flags 7
PAISR.PAIF6            6   Port A Interrupt Flags 6
PAISR.PAIF5            5   Port A Interrupt Flags 5
PAISR.PAIF4            4   Port A Interrupt Flags 4
PAISR.PAIF3            3   Port A Interrupt Flags 3
PAISR.PAIF2            2   Port A Interrupt Flags 2
PAISR.PAIF1            1   Port A Interrupt Flags 1
PAISR.PAIF0            0   Port A Interrupt Flags 0
UNUSED0025            0x0025     UNUSED
PCCFG1                0x0026     Port C Configuration 1
PCCFG1.CSIE            7   Port C Contact Sense Interrupt Enable
PCCFG1.SCIE6           6   Low Side Driver Short Circuit Interrupt Enable
PCCFG1.SCIE5           5   Low Side Driver Short Circuit Interrupt Enable
PCCFG1.PC4CS           4   PC4 Contact Sense Enable
PCCFG1.PC3CS           3   PC3 Contact Sense Enable
PCCFG1.PC2CS           2   PC2 Contact Sense Enable
PCCFG1.PC1CS           1   PC1 Contact Sense Enable
PCCFG1.PC0CS           0   PC0 Contact Sense Enable
PCSTR                 0x0027     Port C Status
PCSTR.CSIF             7   Port C Contact Sense Interrupt Flag
PCSTR.SCIF6            6   Low Side Driver Short Circuit Interrupt Flag
PCSTR.SCIF5            5   Low Side Driver Short Circuit Interrupt Flag
PCSTR.CSD4             4   PC4 Contact Sense Data
PCSTR.CSD3             3   PC3 Contact Sense Data
PCSTR.CSD2             2   PC2 Contact Sense Data
PCSTR.CSD1             1   PC1 Contact Sense Data
PCSTR.CSD0             0   PC0 Contact Sense Data
INTCR                 0x0028     Interrupt Control Register
INTCR.HTIE             2   High Temperature Interrupt Enable
INTCR.HVIE             1   High Voltage Interrupt Enable
INTCR.LVIE             0   Low Voltage Interrupt Enable
INTSR                 0x0029     Interrupt Status Register
INTSR.RCON             7
INTSR.PC4CL            6
INTSR.HTIF             2   High Temperature Interrupt Flag
INTSR.HVIF             1   High Voltage Interrupt Flag
INTSR.LVIF             0   Low Voltage Interrupt Flag
RSR                   0x002A     Reset Status Register
RSR.PINR               7   External Reset Bit
RSR.STOPR              6   Illegal STOP Instruction Reset Bit
RSR.COPR               5   COP (Computer Operating Properly) Reset Bit
RSR.ILINR              4   Illegal Instruction Reset Bit
RSR.CMR                3   Clock Monitor Reset Bit
RSR.HTR                2   High Temperature Reset Bit
RSR.HVR                1   High Voltage Reset Bit
RSR.LVR                0   Low Voltage Reset Bit
UNUSED002B            0x002B     UNUSED
PWMPR                 0x002C     PWM Period
PWMCR                 0x002D     PWM Control
PWMCR.PWMON            7   PWM Module On
PWMCR.POL              6   PWM Polarity
PWMCR.CYCLE            4   PWM Cycle Completed
PWMCR.PRA3             3   PWM Clock Rate Bits 3
PWMCR.PRA2             2   PWM Clock Rate Bits 2
PWMCR.PRA1             1   PWM Clock Rate Bits 1
PWMCR.PRA0             0   PWM Clock Rate Bits 0
PWMDAT                0x002E     PWM Data
MFTEST                0x002F     MFTEST Register
MFTEST.HVTOFF          7   Disable of Port C Inputs
MFTEST.VSCAL           4   Disable of V SUP Scaler Circuit
MFTEST.LSOFF           3   Low Side Drivers Off
MFTEST.VT2             2   Voltage Regulator Trimming Bits 2
MFTEST.VT1             1   Voltage Regulator Trimming Bits 1
MFTEST.VT0             0   Voltage Regulator Trimming Bits 0
COPR                  0x3FF0    COP Watchdog Timer Location Register
COPR.COPR              0
RESERV3FF1            0x3FF1    RESERVED
RESERV3FF2            0x3FF2    RESERVED
RESERV3FF3            0x3FF3    RESERVED
RESERV3FF4            0x3FF4    RESERVED
RESERV3FF5            0x3FF5    RESERVED


.68HC05PV8A
; MC68HC05PV8/D  http://
; MC68HC05PV8.pdf

; RAM=192
; ROM=8KK
; EPROM=0
; EEPROM=128


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA FSR_1       0x0020:0x0030
area DATA FSR_EM      0x0030:0x0040       EXTERNALLY MAPPED 4-bit I/O If enabled
area DATA RAM         0x0040:0x0100
area BSS  RESERVED    0x0100:0x0180
area DATA EEPROM1     0x0180:0x0200
area BSS  RESERVED    0x0200:0x2000
area DATA EEPROM2     0x2000:0x3F00
area DATA TEST_ROM    0x3F00:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      ...
interrupt CTIMER            0x3FF8      CORE TIMER
interrupt TIMER             0x3FF6      16-BIT TIMER


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.TCAP1            5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003     UNUSED
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007     UNUSED
CTSCR                 0x0008     Core Timer Status and Control Register
CTSCR.TOF              7   Timer Over Flow
CTSCR.RTIF             6   Real Time Interrupt Flag
CTSCR.TOFE             5   Timer Over Flow Enable
CTSCR.RTIE             4   Real Time Interrupt Enable
CTSCR.RTOF             3   Reset TOF
CTSCR.RTIF             2   Reset RTIF
CTSCR.RT1              1   Real Time Interrupt Rate Select 1
CTSCR.RT0              0   Real Time Interrupt Rate Select 0
CTCR                  0x0009     Core Timer Counter Register
SYSCR                 0x000A     System Control
SYSCR.POR              7
SYSCR.INTP             6   External interrupt sensitivity options
SYSCR.INTN             5   External interrupt sensitivity options
SYSCR.INTE             4   External interrupt enable
SYSCR.WCOP             3
SYSCR.WCP              2
SYSCR.FPIE             1   Fast Peripheral Interface Enable
SYSCR.FPICLK           0   Fast Peripheral Clock
UNUSED000B            0x000B     UNUSED
EEPCR                 0x000C     EEPROM Control Register
EEPCR.EEOSC            4   EEPROM RC Oscillator Control
EEPCR.EER1             3   Erase Select Bits 1
EEPCR.EER0             2   Erase Select Bits 0
EEPCR.EELAT            1   EEPROM Programming Latch
EEPCR.EEPGM            0   EEPROM Programming Power Enable
UNUSED000D            0x000D     UNUSED
ADDR                  0x000E     A_D Data
ADSCR                 0x000F     A_D Status_Control
ADSCR.COCO             7   Conversion Complete
ADSCR.ADRC             6   RC Oscillator On
ADSCR.ADON             5   A/D On
ADSCR.ADTEST           4
ADSCR.CH3              3   Channel Select Bit 3
ADSCR.CH2              2   Channel Select Bit 2
ADSCR.CH1              1   Channel Select Bit 1
ADSCR.CH0              0   Channel Select Bit 0
TIC1H                 0x0010     Timer Input Capture1 High
TIC1L                 0x0011     Timer Input Capture1 Low
TOC1H                 0x0012     Timer Output Compare1 High
TOC1L                 0x0013     Timer Output Compare1 Low
TIC2H                 0x0014     Timer Input Capture2 High
TIC2L                 0x0015     Timer Input Capture2 Low
TOC2H                 0x0016     Timer Output Compare2 High
TOC2L                 0x0017     Timer Output Compare2 Low
TCH                   0x0018     Timer Counter High
TCL                   0x0019     Timer Counter Low
TACH                  0x001A     Timer Alternate Counter High
TACL                  0x001B     Timer Alternate Counter Low
TCR1                  0x001C     Timer Control1
TCR1.ICI1E             7   Input Capture 1 Interrupt Enable
TCR1.ICI2E             6   Input Capture 2 Interrupt Enable
TCR1.OCI1E             5   Output Compare 1 Interrupt Enable
TCR1.TOIE              4   Timer Overflow Interrupt Enable
TCR1.OCI2E             3   Output Compare 2 Interrupt Enable
TCR1.TOFF              0   Shut Off Timer
TCR2                  0x001D     Timer Control2
TCR2.IEDGE1            7   Input Edge
TCR2.IEDGE2            6   Input Edge
TCR2.CLK21             5   Output Compare 2 clocks output latch 1
TCR2.FOLV1             4   Force Output Level 1
TCR2.OLVL1             3   Output Level 1
TCR2.CLK12             2   Output Compare 1 clocks output latch 2
TCR2.FOLV2             1   Force Output Level 2
TCR2.OLVL2             0   Output Level 2
TSR                   0x001E     Timer Status
TSR.IC1F               7   Input Capture 1 Flag
TSR.IC2F               6   Input Capture 2 Flag
TSR.OC1F               5   Output Compare 1 Flag
TSR.TOF                4   Timer Overflow Flag
TSR.OC2F               3   Output Compare 2 Flag
TSR.SI1                2   Sample Input 1
TSR.SI2                1   Sample Input 2
TEST                  0x001F     TEST
PACFG                 0x0020     Port A Configuration
PACFG.VRHEN            7   Enable A/D High Reference Channel
PACFG.PUHEN            6   PA4-7 Pull-Up Resistor Enable Higher Nibble
PACFG.EDGEH            5   PA4-7 Interrupt Edge Higher Nibble
PACFG.PAHIE            4   PA4-7 Interrupt Enable Higher Nibble
PACFG.PULEN            3   PA0-3 Pull-Up Resistor Enable Lower Nibble
PACFG.EDGEL            2   PA0-3 Interrupt Edge Lower Nibble
PACFG.PALIE            1   PA0-3 Interrupt Enable Lower Nibble
PACFG.VRLEN            0   Enable A/D Low Reference Channel
IOCFG                 0x0021     I_O Configuration
IOCFG.TXOR             7   Timer EXOR Enable
IOCFG.OPAMP            6   Enable Operational Amplifier
IOCFG.PB4PW            4   PB4 PWM Enable
IOCFG.PB3OC            3   PB3 Output Compare Enable
IOCFG.PB2IC            2   PB2 Input Capture Enable
IOCFG.PB1OC            1   PB1 Output Compare Enable
IOCFG.PB0IC            0   PB0 Input Capture Enable
PCCFG0                0x0022     Port C Configuration
PCCFG0.PC6PW           6   PC6 PWM Enable
PCCFG0.PWMS1           5   PWM Select Bits 1
PCCFG0.PWMS0           4   PWM Select Bits 0
PCCFG0.PC3OC           3   PC3 Output Compare Enable
PCCFG0.TS2             2   Timer Channel 1 Select Bits 2
PCCFG0.TS1             1   Timer Channel 1 Select Bits 1
PCCFG0.TS0             0   Timer Channel 1 Select Bits 0
UNUSED0023            0x0023     UNUSED
PAISR                 0x0024     Port A Interrupt Status
PAISR.PAIF7            7   Port A Interrupt Flags 7
PAISR.PAIF6            6   Port A Interrupt Flags 6
PAISR.PAIF5            5   Port A Interrupt Flags 5
PAISR.PAIF4            4   Port A Interrupt Flags 4
PAISR.PAIF3            3   Port A Interrupt Flags 3
PAISR.PAIF2            2   Port A Interrupt Flags 2
PAISR.PAIF1            1   Port A Interrupt Flags 1
PAISR.PAIF0            0   Port A Interrupt Flags 0
UNUSED0025            0x0025     UNUSED
PCCFG1                0x0026     Port C Configuration 1
PCCFG1.CSIE            7   Port C Contact Sense Interrupt Enable
PCCFG1.SCIE6           6   Low Side Driver Short Circuit Interrupt Enable
PCCFG1.SCIE5           5   Low Side Driver Short Circuit Interrupt Enable
PCCFG1.PC4CS           4   PC4 Contact Sense Enable
PCCFG1.PC3CS           3   PC3 Contact Sense Enable
PCCFG1.PC2CS           2   PC2 Contact Sense Enable
PCCFG1.PC1CS           1   PC1 Contact Sense Enable
PCCFG1.PC0CS           0   PC0 Contact Sense Enable
PCSTR                 0x0027     Port C Status
PCSTR.CSIF             7   Port C Contact Sense Interrupt Flag
PCSTR.SCIF6            6   Low Side Driver Short Circuit Interrupt Flag
PCSTR.SCIF5            5   Low Side Driver Short Circuit Interrupt Flag
PCSTR.CSD4             4   PC4 Contact Sense Data
PCSTR.CSD3             3   PC3 Contact Sense Data
PCSTR.CSD2             2   PC2 Contact Sense Data
PCSTR.CSD1             1   PC1 Contact Sense Data
PCSTR.CSD0             0   PC0 Contact Sense Data
INTCR                 0x0028     Interrupt Control Register
INTCR.ULPM             7
INTCR.HTIE             2   High Temperature Interrupt Enable
INTCR.HVIE             1   High Voltage Interrupt Enable
INTCR.LVIE             0   Low Voltage Interrupt Enable
INTSR                 0x0029     Interrupt Status Register
INTSR.RCON             7
INTSR.PC4CL            6
INTSR.HTIF             2   High Temperature Interrupt Flag
INTSR.HVIF             1   High Voltage Interrupt Flag
INTSR.LVIF             0   Low Voltage Interrupt Flag
RSR                   0x002A     Reset Status Register
RSR.PINR               7   External Reset Bit
RSR.STOPR              6   Illegal STOP Instruction Reset Bit
RSR.COPR               5   COP (Computer Operating Properly) Reset Bit
RSR.ILINR              4   Illegal Instruction Reset Bit
RSR.CMR                3   Clock Monitor Reset Bit
RSR.HTR                2   High Temperature Reset Bit
RSR.HVR                1   High Voltage Reset Bit
RSR.LVR                0   Low Voltage Reset Bit
UNUSED002B            0x002B     UNUSED
PWMPR                 0x002C     PWM Period
PWMCR                 0x002D     PWM Control
PWMCR.PWMON            7   PWM Module On
PWMCR.POL              6   PWM Polarity
PWMCR.CYCLE            4   PWM Cycle Completed
PWMCR.PRA3             3   PWM Clock Rate Bits 3
PWMCR.PRA2             2   PWM Clock Rate Bits 2
PWMCR.PRA1             1   PWM Clock Rate Bits 1
PWMCR.PRA0             0   PWM Clock Rate Bits 0
PWMDAT                0x002E     PWM Data
MFTEST                0x002F     MFTEST Register
MFTEST.HVTOFF          7   Disable of Port C Inputs
MFTEST.VSCAL           4   Disable of V SUP Scaler Circuit
MFTEST.LSOFF           3   Low Side Drivers Off
MFTEST.VT2             2   Voltage Regulator Trimming Bits 2
MFTEST.VT1             1   Voltage Regulator Trimming Bits 1
MFTEST.VT0             0   Voltage Regulator Trimming Bits 0
COPR                  0x3FF0    COP Watchdog Timer Location Register
COPR.COPR              0
RESERV3FF1            0x3FF1    RESERVED
RESERV3FF2            0x3FF2    RESERVED
RESERV3FF3            0x3FF3    RESERVED
RESERV3FF4            0x3FF4    RESERVED
RESERV3FF5            0x3FF5    RESERVED


.68HC05SR3
; MC68HC05SR3D/H  http://
; MC68HC05SR3D.pdf

; RAM=192
; ROM=3.75K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0010
area DATA RAM         0x0010:0x0090
area BSS  UNUSED      0x0090:0x00C0
area DATA STACK       0x00C0:0x0100
area BSS  UNUSED      0x0100:0x1000
area DATA ROM         0x1000:0x1F00
area DATA ROM_S_CH    0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt IRQ2              0x1FF8      External Interrupt 2
interrupt TIMER             0x1FF6      Timer Overflow
interrupt KBI               0x1FF4      Keyboard


; INPUT/ OUTPUT PORTS
PORTA          0x0000     Port A Data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001     Port B Data
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
PORTC          0x0002     Port C Data
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
PORTD          0x0003     Port D Data
PORTD.PD7       7   Port D Data Bits 7
PORTD.PD6       6   Port D Data Bits 6
PORTD.PD5       5   Port D Data Bits 5
PORTD.PD4       4   Port D Data Bits 4
PORTD.PD3       3   Port D Data Bits 3
PORTD.PD2       2   Port D Data Bits 2
PORTD.PD1       1   Port D Data Bits 1
PORTD.PD0       0   Port D Data Bits 0
DDRA           0x0004     Port A Data Direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005     Port B Data Direction
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRC           0x0006     Port C Data Direction
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC6      6   Data Direction for Port C Bit 6
DDRC.DDRC5      5   Data Direction for Port C Bit 5
DDRC.DDRC4      4   Data Direction for Port C Bit 4
DDRC.DDRC3      3   Data Direction for Port C Bit 3
DDRC.DDRC2      2   Data Direction for Port C Bit 2
DDRC.DDRC1      1   Data Direction for Port C Bit 1
DDRC.DDRC0      0   Data Direction for Port C Bit 0
DDRD           0x0007     Port D Data Direction
DDRD.DDRD7      7   Data Direction for Port D Bit 7
DDRD.DDRD6      6   Data Direction for Port D Bit 6
DDRD.DDRD5      5   Data Direction for Port D Bit 5
DDRD.DDRD4      4   Data Direction for Port D Bit 4
DDRD.DDRD3      3   Data Direction for Port D Bit 3
DDRD.DDRD2      2   Data Direction for Port D Bit 2
DDRD.DDRD1      1   Data Direction for Port D Bit 1
DDRD.DDRD0      0   Data Direction for Port D Bit 0
TDR            0x0008     Timer Data
TDR.TD7         7
TDR.TD6         6
TDR.TD5         5
TDR.TD4         4
TDR.TD3         3
TDR.TD2         2
TDR.TD1         1
TDR.TD0         0
TCR            0x0009     Timer Control
TCR.TIF         7   Timer Interrupt Flag
TCR.TIM         6   Timer Interrupt Mask
TCR.TCEX        5   Timer Clock EXternal
TCR.TINE        4   Timer INput Enable
TCR.PRER        3   PREscaler Reset
TCR.PR2         2
TCR.PR1         1
TCR.PR0         0
POPR           0x000A     Port Option
POPR.PIL        5   PB5:PB7 current drive select
POPR.PDP        4   Port D Pull-up
POPR.PCP        3   Port C Pull-up
POPR.PBP        2   PB2:PB7 Pull-up
POPR.PB1        1   PB1 pull-up
POPR.PB0        0   PB0 pull-up
KBIM           0x000B     KBI Mask
KBIM.KBE7       7   PA7 Keyboard Interrupt Enable
KBIM.KBE6       6   PA6 Keyboard Interrupt Enable
KBIM.KBE5       5   PA5 Keyboard Interrupt Enable
KBIM.KBE4       4   PA4 Keyboard Interrupt Enable
KBIM.KBE3       3   PA3 Keyboard Interrupt Enable
KBIM.KBE2       2   PA2 Keyboard Interrupt Enable
KBIM.KBE1       1   PA1 Keyboard Interrupt Enable
KBIM.KBE0       0   PA0 Keyboard Interrupt Enable
MCR            0x000C     Miscellaneous Control
MCR.KBIE        7   KeyBoard Interrupt Enable
MCR.KBIC        6   KeyBoard Interrupt Clear
MCR.INTO        5   INTerrupt Option
MCR.INTE        4   INTerrupt Enable
MCR.LVRE        3   Low Voltage Reset Enable
MCR.SM          2   Slow Mode
MCR.IRQ2F       1   IRQ2 Flag clear
MCR.IRQ2E       0   IRQ2 Enable
RESERV000D     0x000D     RESERVED
; EPC            0x000D     EPROM Programming Control (MC68HC705SR3)
; EPC.ELAT        1   EPROM Latch Control
; EPC.PGM         0   EPROM Program Command
ADSCR          0x000E     ADC Status and Control
ADSCR.COCO      7   COnversion COmplete
ADSCR.ADRC      6   ADC RC Oscillator Control
ADSCR.ADON      5   ADC On
ADSCR.CH2       2   Channel Select Bits 2
ADSCR.CH1       1   Channel Select Bits 1
ADSCR.CH0       0   Channel Select Bits 0
ADDR           0x000F     ADC Data
ADDR.AD7        7
ADDR.AD6        6
ADDR.AD5        5
ADDR.AD4        4
ADDR.AD3        3
ADDR.AD2        2
ADDR.AD1        1
ADDR.AD0        0
RESERV1FF0     0x1FF0     Reserved
RESERV1FF1     0x1FF1     Reserved
RESERV1FF2     0x1FF2     Reserved
RESERV1FF3     0x1FF3     Reserved


.68HC05SU3A
; MC68HC05SU3A/H  http://
; MC68HC05SU3A.pdf

; RAM=192
; ROM=4080
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0010
area DATA RAM         0x0010:0x0090
area BSS  UNUSED      0x0090:0x00C0
area DATA STACK       0x00C0:0x0100
area BSS  UNUSED      0x0100:0x1000
area DATA ROM         0x1000:0x1F00
area DATA ROM_S_CH    0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt IRQ2              0x1FF8      External Interrupt 2
interrupt TIMER             0x1FF6      Timer Overflow
interrupt KBI               0x1FF4      Keyboard


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A Data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001     Port B Data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002     Port C Data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003     Port D Data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD6        6   Port D Data Bits 6
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004     Port A Data Direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005     Port B Data Direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006     Port C Data Direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007     Port D Data Direction
DDRD.DDRD7       7   Data Direction for Port D Bit 7
DDRD.DDRD6       6   Data Direction for Port D Bit 6
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
TDR             0x0008     Timer Data
TDR.TD7          7
TDR.TD6          6
TDR.TD5          5
TDR.TD4          4
TDR.TD3          3
TDR.TD2          2
TDR.TD1          1
TDR.TD0          0
TCR             0x0009     Timer Control
TCR.TIF          7   Timer Interrupt Flag
TCR.TIM          6   Timer Interrupt Mask
TCR.TCEX         5   Timer Clock EXternal
TCR.TINE         4   Timer INput Enable
TCR.PRER         3   PREscaler Reset
TCR.PR2          2
TCR.PR1          1
TCR.PR0          0
POPR            0x000A     Port Option
POPR.PIL         5   PB5:PB7 current drive select
POPR.PDP         4   Port D Pull-up
POPR.PCP         3   Port C Pull-up
POPR.PBP         2   PB2:PB7 Pull-up
KBIM            0x000B     KBI Mask
KBIM.KBE7        7   PA7 Keyboard Interrupt Enable
KBIM.KBE6        6   PA6 Keyboard Interrupt Enable
KBIM.KBE5        5   PA5 Keyboard Interrupt Enable
KBIM.KBE4        4   PA4 Keyboard Interrupt Enable
KBIM.KBE3        3   PA3 Keyboard Interrupt Enable
KBIM.KBE2        2   PA2 Keyboard Interrupt Enable
KBIM.KBE1        1   PA1 Keyboard Interrupt Enable
KBIM.KBE0        0   PA0 Keyboard Interrupt Enable
MCR             0x000C     Miscellaneous Control
MCR.KBIE         7   KeyBoard Interrupt Enable
MCR.KBIC         6   KeyBoard Interrupt Clear
MCR.INTO         5   INTerrupt Option
MCR.INTE         4   INTerrupt Enable
MCR.LVRE         3   Low Voltage Reset Enable
MCR.SM           2   Slow Mode
MCR.IRQ2F        1   IRQ2 Flag clear
MCR.IRQ2E        0   IRQ2 Enable
Reserv000D      0x000D     Reserved
Reserv000E      0x000E     Reserved
Reserv000F      0x000F     Reserved
RESERV1FF0      0x1FF0    RESERVED
RESERV1FF1      0x1FF1    RESERVED
RESERV1FF2      0x1FF2    RESERVED
RESERV1FF3      0x1FF3    RESERVED


.68HC05V12
; MC68HC05V12/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05PV8A&nodeId=01M98633
; MC68HC05V12.pdf

; RAM=320
; ROM=12032
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area DATA RAM         0x0040:0x01C0
area BSS  UNUSED      0x01C0:0x0240
area DATA EEPROM      0x0240:0x0340
area BSS  UNUSED      0x0340:0x0D00
area DATA ROM         0x0D00:0x3C00
area DATA BOOT_ROM    0x3C00:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      ...
interrupt TIMER_16bit       0x3FF8
interrupt BDLC              0x3FF6
interrupt SPI               0x3FF4
interrupt TIMER_8bit        0x3FF2
interrupt GAUGE             0x3FF0


; INPUT/ OUTPUT PORTS
PORTA		0x0000		Port A Data Register
PORTA.PA6         6  Port A Data Bits 6
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB		0x0001		Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
PORTC		0x0002		Port C Data Register
PORTC.PC7         7  Port C Data Bits 7
PORTC.PC6         6  Port C Data Bits 6
PORTC.PC5         5  Port C Data Bits 5
PORTC.PC4         4  Port C Data Bits 4
PORTC.PC3         3  Port C Data Bits 3
PORTC.PC2         2  Port C Data Bits 2
PORTC.PC1         1  Port C Data Bits 1
PORTC.PC0         0  Port C Data Bits 0
PORTD		0x0003		Port D Data Register
PORTD.PD4         4  Port D Data Bits 4
PORTD.PD3         3  Port D Data Bits 3
PORTD.PD2         2  Port D Data Bits 2
PORTD.PD1         1  Port D Data Bits 1
PORTD.PD0         0  Port D Data Bits 0
DDRA		0x0004		Port A Data Direction
DDRA.DDRA6        6  Data Direction for Port A Bit 6
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB		0x0005		Port B Data Direction
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
DDRC		0x0006		Port C Data Direction
DDRC.DDRC7        7  Data Direction for Port C Bit 7
DDRC.DDRC6        6  Data Direction for Port C Bit 6
DDRC.DDRC5        5  Data Direction for Port C Bit 5
DDRC.DDRC4        4  Data Direction for Port C Bit 4
DDRC.DDRC3        3  Data Direction for Port C Bit 3
DDRC.DDRC2        2  Data Direction for Port C Bit 2
DDRC.DDRC1        1  Data Direction for Port C Bit 1
DDRC.DDRC0        0  Data Direction for Port C Bit 0
UNUSED0007      0x0007          UNUSED
CTSCR		0x0008 		Core Timer Status and Control Register 
CTSCR.CTOF        7  Core Timer Overflow Bit
CTSCR.RTIF        6  Real Time Interrupt Flag
CTSCR.TOFE        5  Timer Overflow Enable Bit
CTSCR.RTIE        4  Real-Time Interrupt Enable Bit
CTSCR.TOFC        3  Timer Overflow Flag Clear Bit
CTSCR.RTFC        2  Real-Time Interrupt Flag Clear Bit
CTSCR.RT1         1  Real-Time Interrupt Rate Select Bits 1
CTSCR.RT0         0  Real-Time Interrupt Rate Select Bits 0
CTCR		0x0009		Core Timer Counter Register
CTCR.TMR7         7
CTCR.TMR6         6
CTCR.TMR5         5
CTCR.TMR4         4
CTCR.TMR3         3
CTCR.TMR2         2
CTCR.TMR1         1
CTCR.TMR0         0
SPCR		0x000A		SPI Control Register
SPCR.SPIE         7  Serial Peripheral Interrupt Enable Bit
SPCR.SPE          6  Serial Peripheral System Enable Bit
SPCR.MSTR         4  Master Mode Select Bit
SPCR.CPOL         3  Clock Polarity Bit
SPCR.CPHA         2  Clock Phase Bit
SPCR.SPR1         1  SPI Clock Rate Select Bits 1
SPCR.SPR0         0  SPI Clock Rate Select Bits 0
SPSR		0x000B		SPI Status Register
SPSR.SPIF         7  SPI Transfer Complete Flag
SPSR.WCOL         6  Write Collision Bit
SPSR.MODF         4  Mode Fault Bit
SPDR		0x000C		SPI Data Register
SPDR.SPD7         7
SPDR.SPD6         6
SPDR.SPD5         5
SPDR.SPD4         4
SPDR.SPD3         3
SPDR.SPD2         2
SPDR.SPD1         1
SPDR.SPD0         0
UNUSED000D      0x000D          UNUSED
UNUSED000E      0x000E          UNUSED
UNUSED000F      0x000F          UNUSED
UNUSED0010      0x0010          UNUSED
UNUSED0011      0x0011          UNUSED
TMRCR		0x0012		16-Bit Timer Control Register
TMRCR.ICIE        7  Input Capture Interrupt Enable Bit
TMRCR.OCIE        6  Output Compare Interrupt Enable Bit
TMRCR.TOIE        5  Timer Overflow Interrupt Enable Bit
TMRCR.TON         2  Timer On Bit
TMRCR.IEDG        1  Input Edge Bit
TMRCR.OLVL        0  Output Level Bit
TMRSR		0x0013		16-Bit Timer Status Register
TMRSR.ICF         7  Input Capture Flag
TMRSR.OCF         6  Output Compare Flag
TMRSR.TOF         5  Timer Overflow Flag
TCAPH		0x0014		Input Capture MSB Register
TCAPH.IC15        7
TCAPH.IC14        6
TCAPH.IC13        5
TCAPH.IC12        4
TCAPH.IC11        3
TCAPH.IC10        2
TCAPH.IC9         1
TCAPH.IC8         0
TCAPL		0x0015		Input Capture LSB Register
TCAPL.IC7         7
TCAPL.IC6         6
TCAPL.IC5         5
TCAPL.IC4         4
TCAPL.IC3         3
TCAPL.IC2         2
TCAPL.IC1         1
TCAPL.IC0         0
TCMPH		0x0016 		Output Compare MSB Register
TCMPH.OC15        7
TCMPH.OC14        6
TCMPH.OC13        5
TCMPH.OC12        4
TCMPH.OC11        3
TCMPH.OC10        2
TCMPH.OC9         1
TCMPH.OC8         0
TCMPL		0x0017 		Output Compare LSB Register
TCMPL.OC7         7
TCMPL.OC6         6
TCMPL.OC5         5
TCMPL.OC4         4
TCMPL.OC3         3
TCMPL.OC2         2
TCMPL.OC1         1
TCMPL.OC0         0
TCNTH		0x0018		Timer Counter MSB Register
TCNTH.CNT15       7
TCNTH.CNT14       6
TCNTH.CNT13       5
TCNTH.CNT12       4
TCNTH.CNT11       3
TCNTH.CNT10       2
TCNTH.CNT9        1
TCNTH.CNT8        0
TCNTL		0x0019		Timer Counter LSB Register
TCNTL.CNT7        7
TCNTL.CNT6        6
TCNTL.CNT5        5
TCNTL.CNT4        4
TCNTL.CNT3        3
TCNTL.CNT2        2
TCNTL.CNT1        1
TCNTL.CNT0        0
ALTCNTH		0x001A 		Alternate Counter MSB Register
ALTCNTH.AC15      7
ALTCNTH.AC14      6
ALTCNTH.AC13      5
ALTCNTH.AC12      4
ALTCNTH.AC11      3
ALTCNTH.AC10      2
ALTCNTH.AC9       1
ALTCNTH.AC8       0
ALTCNTL		0x001B 		Alternate Counter LSB Register
ALTCNTL.AC7       7
ALTCNTL.AC6       6
ALTCNTL.AC5       5
ALTCNTL.AC4       4
ALTCNTL.AC3       3
ALTCNTL.AC2       2
ALTCNTL.AC1       1
ALTCNTL.AC0       0
EEPROG		0x001C 		EEPROM Programming Register
EEPROG.CPEN       6  Charge Pump Enable Bit
EEPROG.ER1        4  Erase Select Bits 1
EEPROG.ER0        3  Erase Select Bits 0
EEPROG.EELAT      2  EEPROM Programming Latch Bit
EEPROG.EERC       1  EEPROM RC Oscillator Control Bit
EEPROG.EEPGM      0  EEPROM Programming Power Enable Bit
ADDR		0x001D		A/D Data Register
ADDR.D7           7
ADDR.D6           6
ADDR.D5           5
ADDR.D4           4
ADDR.D3           3
ADDR.D2           2
ADDR.D1           1
ADDR.D0           0
ADSCR		0x001E 		A_D Status and Control Register
ADSCR.COCO        7  Conversions Complete Bit
ADSCR.ADRC        6  RC Oscillator Control Bit
ADSCR.ADON        5  A/D On Bit
ADSCR.CH4         4  Channel Select Bits 4
ADSCR.CH3         3  Channel Select Bits 3
ADSCR.CH2         2  Channel Select Bits 2
ADSCR.CH1         1  Channel Select Bits 1
ADSCR.CH0         0  Channel Select Bits 0
ISCR		0x001F 		IRQ Status and Control Register
ISCR.IRQE         7  IRQ Interrupt Enable Bit
ISCR.IPCE         5  Port C IRQ Interrupt Enable Bit
ISCR.IRQF         3  IRQ Interrupt Request Bit
ISCR.IPCF         1  Port C IRQ Interrupt Request Bit
ISCR.IRQA         0  IRQ Interrupt Acknowledge Bit
GER		0x0020		Gauge Enable Register
GER.MJAON         7  Major Gauge A On Bit
GER.MJBON         6  Major Gauge B On Bit
GER.MIAON         5  Minor Gauge A On Bit
GER.MIBON         4  Minor Gauge B On Bit
GER.MICON         3  Minor Gauge C On Bit
GER.MIDON         2  Minor Gauge D On Bit
GER.CMPS          1  Feedback Compensation Select Bit
SSCR		0x0021 		Scan Status and Control Register
SSCR.SYNIE        7  Synchronize Interrupt Enable Bit
SSCR.SYNF         6  Synchronize Flag Bit
SSCR.SYNR         5  Synchronize Flag Reset Bit
SSCR.GCS1         3  Gauge Clock Select Bits 1
SSCR.GCS0         2  Gauge Clock Select Bits 0
SSCR.SCNS         1  Scan Start Bit
SSCR.AUTOS        0  Automatic Mode Select Bit
MAJA1		0x0022		MAJA1 Magnitude Register  
MAJA2		0x0023		MAJA2 Magnitude Register  
MAJB1		0x0024		MAJB1 Magnitude Register  
MAJB2		0x0025		MAJB2 Magnitude Register  
MINA1		0x0026		MINA1 Magnitude Register  
MINA2		0x0027		MINA2 Magnitude Register 
MINB1		0x0028		MINB1 Magnitude Register  
MINB2		0x0029		MINB2 Magnitude Register  
MINC1		0x002A		MINC1 Magnitude Register  
MINC2		0x002B		MINC2 Magnitude Register  
MIND1		0x002C		MIND1 Magnitude Register  
MIND2		0x002D		MIND2 Magnitude Register  
DMAJA		0x002E 		MAJA Current Direction Register
DMAJA.DMJA1       1  Current Direction Bits for Major Gauge A
DMAJA.DMJA2       0  Current Direction Bits for Major Gauge A
DMAJB		0x002F 		MAJB Current Direction Register
DMAJB.DMJB1       1  Current Direction Bits for Major Gauge B
DMAJB.DMJB2       0  Current Direction Bits for Major Gauge B
DMINA		0x0030 		MINA Current Direction Register
DMINA.DMIA        0  Current Direction Bit for Minor Gauge A
MINB		0x0031 		MINB Current Direction Register
MINB.DMIB         0  Current Direction Bit for Minor Gauge B
DMINC		0x0032 		MINC Current Direction Register
DMINC.DMIC        0  Current Direction Bit for Minor Gauge C
DMIND		0x0033 		MIND Current Direction Register
DMIND.DMID        0  Current Direction Bit for Minor Gauge D
Reserv0034	0x0034          Reserved
MISCR		0x0035		Miscellaneous Register 
MISCR.OCE         6  Output Compare Enable Bit
PWMAD		0x0036		PWMA Data Register 
PWMAD.POLA        7  PWMB Polarity Bit
PWMAD.D5          5
PWMAD.D4          4
PWMAD.D3          3
PWMAD.D2          2
PWMAD.D1          1
PWMAD.D0          0
PWMAC		0x0037		PWMA Control Register 
PWMAC.PSA1A       7  PSA1A - PWMA Clock Rate Bits
PWMAC.PSA0A       6  PSA0A - PWMA Clock Rate Bits
PWMAC.PSB3A       3  PSB3A - PWMA Clock Rate Bits
PWMAC.PSB2A       2  PSB2A - PWMA Clock Rate Bits
PWMAC.PSB1A       1  PSB1A - PWMA Clock Rate Bits
PWMAC.PSB0A       0  PSB0A - PWMA Clock Rate Bits
PWMBD		0x0038		PWMB Data Register 
PWMBD.POLB        7  PWMB Polarity Bit
PWMBD.D5          5
PWMBD.D4          4
PWMBD.D3          3
PWMBD.D2          2
PWMBD.D1          1
PWMBD.D0          0
PWMBC		0x0039		PWMB Control Register
PWMBC.PSA1B       7  PSA1B - PWM Clock Rate Bits
PWMBC.PSA0B       6  PSA0B - PWM Clock Rate Bits
PWMBC.PSB3B       3  PSB3B - PWM Clock Rate Bits
PWMBC.PSB2B       2  PSB2B - PWM Clock Rate Bits
PWMBC.PSB1B       1  PSB1B - PWM Clock Rate Bits
PWMBC.PSB0B       0  PSB0B - PWM Clock Rate Bits
BCR1		0x003A		BDLC Control 1 Register 
BCR1.IMSG         7  Ignore Message Bit
BCR1.CLKS         6  Clock Bit
BCR1.R1           5  Rate Select Bits 1
BCR1.R0           4  Rate Select Bits 0
BCR1.IE           1  Interrupt Enable Bit
BCR1.WCM          0  Wait Clock Mode Bit
BCR2		0x003B		BDLC Control 2 Register
BCR2.ALOOP        7  Analog Loopback Mode Bit
BCR2.DLOOP        6  Digital Loopback Mode Bit
BCR2.RX4XE        5  Receive 4X Enable Bit
BCR2.NBFS         4  Normalization Bit Format Select Bit
BCR2.TEOD         3  Transmit End-of-Data Bit
BCR2.TSIFR        2  Transmit In-Frame Response Control Bits
BCR2.TMIFR1       1  Transmit In-Frame Response Control Bits
BCR2.TMIFR0       0  Transmit In-Frame Response Control Bits
BSVR		0x003C		BDLC State Vector Register
BSVR.I3           5  I3 - Interrupt Source Bits
BSVR.I2           4  I2 - Interrupt Source Bits
BSVR.I1           3  I1 - Interrupt Source Bits
BSVR.I0           2  I0 - Interrupt Source Bits
BDATR		0x003D		BDLC Data Register 
BDATR.BD7         7
BDATR.BD6         6
BDATR.BD5         5
BDATR.BD4         4
BDATR.BD3         3
BDATR.BD2         2
BDATR.BD1         1
BDATR.BD0         0
BARD		0x003E 		BDLC Analog Roundtrip Delay Register
BARD.ATE          7  Analog Transceiver Enable Bit
BARD.RXPOL        6  Receive Pin Polarity Bit
BARD.BO3          3  BARD Offset Bits 3
BARD.BO2          2  BARD Offset Bits 2
BARD.BO1          1  BARD Offset Bits 1
BARD.BO0          0  BARD Offset Bits 0
Reserv003F	0x003F          Reserved


.68HC05V7
; HC05V7GRS/D  http://
; HC05V7GRS.pdf

; RAM=320
; ROM=10208
; EPROM=0
; EEPROM=128


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area DATA RAM         0x0040:0x01C0
area BSS  UNUSED      0x01C0:0x0240
area DATA EEPROM      0x0240:0x02C0
area BSS  UNUSED      0x02C0:0x1600
area DATA TEST_ROM    0x1600:0x1800
area DATA ROM         0x1800:0x3FE0
area DATA BOOT_VEC    0x3FE0:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      ...
interrupt TIMER_16bit       0x3FF8
interrupt MDLC              0x3FF6
interrupt SPI               0x3FF4
interrupt TIMER_8bit        0x3FF2


; INPUT/ OUTPUT PORTS
PORTA          0x0000     PORT A DATA
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001     PORT B DATA
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
PORTC          0x0002     PORT C DATA
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
PORTD          0x0003     PORT D DATA
PORTD.PD7       7   Port D Data Bits 7
PORTD.PD6       6   Port D Data Bits 6
PORTD.PD5       5   Port D Data Bits 5
PORTD.PD4       4   Port D Data Bits 4
PORTD.PD3       3   Port D Data Bits 3
PORTD.PD2       2   Port D Data Bits 2
PORTD.PD1       1   Port D Data Bits 1
PORTD.PD0       0   Port D Data Bits 0
DDRA           0x0004     PORT A DATA DIRECTION
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005     PORT B DATA DIRECTION
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRC           0x0006     PORT C DATA DIRECTION
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC6      6   Data Direction for Port C Bit 6
DDRC.DDRC5      5   Data Direction for Port C Bit 5
DDRC.DDRC4      4   Data Direction for Port C Bit 4
DDRC.DDRC3      3   Data Direction for Port C Bit 3
DDRC.DDRC2      2   Data Direction for Port C Bit 2
DDRC.DDRC1      1   Data Direction for Port C Bit 1
DDRC.DDRC0      0   Data Direction for Port C Bit 0
UNUSED0007     0x0007     UNUSED
CTCSR          0x0008     8 BIT TIMER STATUS/CONTROL
CTCSR.CTOF      7   Core Timer Over Flow
CTCSR.RTIF      6   Real Time Interrupt Flag
CTCSR.TOFE      5   Timer Over Flow Enable
CTCSR.RTIE      4   Real Time Interrupt Enable
CTCSR.TOFC      3   Timer Over Flow Flag Clear
CTCSR.RTFC      2   Real Time Interrupt Flag Clear
CTCSR.RT1       1   Real Time Interrupt Rate Select 1
CTCSR.RT0       0   Real Time Interrupt Rate Select 0
CTCR           0x0009     CORE TIMER COUNTER REGISTER
CTCR.D7         7
CTCR.D6         6
CTCR.D5         5
CTCR.D4         4
CTCR.D3         3
CTCR.D2         2
CTCR.D1         1
CTCR.D0         0
SPCR           0x000A     SPI CONTROL REGISTER
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable
SPCR.MSTR       4   Master Mode Select
SPCR.CPOL       3   Clock Polarity
SPCR.CPHA       2   Clock Phase
SPCR.SPR1       1   SPI Clock Rate Selects 1
SPCR.SPR0       0   SPI Clock Rate Selects 0
SPSR           0x000B     SPI STATUS REGISTER
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision
SPSR.MODF       4   Mode Fault
SPDR           0x000C     SPI DATA REGISTER
SPDR.SPD7       7
SPDR.SPD6       6
SPDR.SPD5       5
SPDR.SPD4       4
SPDR.SPD3       3
SPDR.SPD2       2
SPDR.SPD1       1
SPDR.SPD0       0
UNUSED000D     0x000D     UNUSED
MCR            0x000E     MDLC CONTROL REGISTER
MCR.RXBM        7   Receive Block Mode
MCR.TXAB        6   Transmit Abort
MCR.R1          5   Rate Select 1
MCR.R0          4   Rate Select 0
MCR.IE          1   Interrupt Enable
MCR.WCM         0   Wait Clock Mode
MSR            0x000F     MDLC STATUS REGISTER
MSR.TXMS        3   Transmitted Message Successfully
MSR.RXMS        2   Received Message Successfully
MTCR           0x0010     MDLC TX CONTROL REGISTER
MTCR.TC3        3   Transmit Count 3
MTCR.TC2        2   Transmit Count 2
MTCR.TC1        1   Transmit Count 1
MTCR.TC0        0   Transmit Count 0
MRSR           0x0011     MDLC RX STATUS REGISTER
MRSR.RC3        3   Receive Count 3
MRSR.RC2        2   Receive Count 2
MRSR.RC1        1   Receive Count 1
MRSR.RC0        0   Receive Count 0
TCR            0x0012     TIMER CONTROL REGISTER
TCR.ICIE        7   Input Capture Interrupt Enable
TCR.OCIE        6   Output Compare Interrupt Enable
TCR.TOIE        5   Timer Overflow Interrupt Enable
TCR.TON         2   Timer On
TCR.IEDG        1   Input Edge
TCR.OLVL        0   Output Level
TSR            0x0013     TIMER STATUS REGISTER
TSR.ICF         7   Input Capture Flag
TSR.OCF         6   Output Compare Flag
TSR.TOF         5   Timer Overflow Flag
ICH            0x0014     INPUT CAPTURE HIGH
ICL            0x0015     INPUT CAPTURE LOW
OCH            0x0016     OUTPUT COMPARE HIGH
OCL            0x0017     OUTPUT COMPARE LOW
TCH            0x0018     TIMER COUNTER HIGH
TCL            0x0019     TIMER COUNTER LOW
ACH            0x001A     ALT. COUNTER HIGH
ACL            0x001B     ALT. COUNTER LOW
EPROG          0x001C     EEPROM PROGRAMMING
EPROG.CPEN      6   Charge Pump Enable
EPROG.ER1       4   Erase Select Bits 1
EPROG.ER0       3   Erase Select Bits 0
EPROG.LATCH     2
EPROG.EERC      1   EEPROM RC Oscillator Control
EPROG.EEPGM     0   EEPROM Programming Power Enable
ADD            0x001D     A/D DATA
ADD.D7          7
ADD.D6          6
ADD.D5          5
ADD.D4          4
ADD.D3          3
ADD.D2          2
ADD.D1          1
ADD.D0          0
ADSCR          0x001E     A_D STATUS AND CONTROL
ADSCR.COCO      7   Conversions Complete
ADSCR.ADRC      6   RC Oscillator Control
ADSCR.ADON      5   A/D On
ADSCR.CH4       4   Channel Select Bits 4
ADSCR.CH3       3   Channel Select Bits 3
ADSCR.CH2       2   Channel Select Bits 2
ADSCR.CH1       1   Channel Select Bits 1
ADSCR.CH0       0   Channel Select Bits 0
ICSR           0x001F     IRQ CONTROL AND STATUS
ICSR.IRQE       7   IRQ Interrupt Enable
ICSR.IRQPAE     6   Port A IRQ Interrupt Enable
ICSR.IRQPCE     5   Port C IRQ Interrupt Enable
ICSR.IRQF       3   IRQ Interrupt Request
ICSR.IRQPAF     2   Port A IRQ Interrupt Request
ICSR.IRQPCF     1   Port C IRQ Interrupt Request
ICSR.IRQA       0   IRQ Interrupt Acknowledge
MTDR0          0x0020     MDLC TX DATA REGISTER 0
MTDR0.D7        7
MTDR0.D6        6
MTDR0.D5        5
MTDR0.D4        4
MTDR0.D3        3
MTDR0.D2        2
MTDR0.D1        1
MTDR0.D0        0
MTDR1          0x0021     MDLC TX DATA REGISTER 1
MTDR1.D7        7
MTDR1.D6        6
MTDR1.D5        5
MTDR1.D4        4
MTDR1.D3        3
MTDR1.D2        2
MTDR1.D1        1
MTDR1.D0        0
MTDR2          0x0022     MDLC TX DATA REGISTER 2
MTDR2.D7        7
MTDR2.D6        6
MTDR2.D5        5
MTDR2.D4        4
MTDR2.D3        3
MTDR2.D2        2
MTDR2.D1        1
MTDR2.D0        0
MTDR3          0x0023     MDLC TX DATA REGISTER 3
MTDR3.D7        7
MTDR3.D6        6
MTDR3.D5        5
MTDR3.D4        4
MTDR3.D3        3
MTDR3.D2        2
MTDR3.D1        1
MTDR3.D0        0
MTDR4          0x0024     MDLC TX DATA REGISTER 4
MTDR4.D7        7
MTDR4.D6        6
MTDR4.D5        5
MTDR4.D4        4
MTDR4.D3        3
MTDR4.D2        2
MTDR4.D1        1
MTDR4.D0        0
MTDR5          0x0025     MDLC TX DATA REGISTER 5
MTDR5.D7        7
MTDR5.D6        6
MTDR5.D5        5
MTDR5.D4        4
MTDR5.D3        3
MTDR5.D2        2
MTDR5.D1        1
MTDR5.D0        0
MTDR6          0x0026     MDLC TX DATA REGISTER 6
MTDR6.D7        7
MTDR6.D6        6
MTDR6.D5        5
MTDR6.D4        4
MTDR6.D3        3
MTDR6.D2        2
MTDR6.D1        1
MTDR6.D0        0
MTDR7          0x0027     MDLC TX DATA REGISTER 7
MTDR7.D7        7
MTDR7.D6        6
MTDR7.D5        5
MTDR7.D4        4
MTDR7.D3        3
MTDR7.D2        2
MTDR7.D1        1
MTDR7.D0        0
MTDR8          0x0028     MDLC TX DATA REGISTER 8
MTDR8.D7        7
MTDR8.D6        6
MTDR8.D5        5
MTDR8.D4        4
MTDR8.D3        3
MTDR8.D2        2
MTDR8.D1        1
MTDR8.D0        0
MTDR9          0x0029     MDLC TX DATA REGISTER 9
MTDR9.D7        7
MTDR9.D6        6
MTDR9.D5        5
MTDR9.D4        4
MTDR9.D3        3
MTDR9.D2        2
MTDR9.D1        1
MTDR9.D0        0
MTDR10         0x002A     MDLC TX DATA REGISTER 10
MTDR10.D7       7
MTDR10.D6       6
MTDR10.D5       5
MTDR10.D4       4
MTDR10.D3       3
MTDR10.D2       2
MTDR10.D1       1
MTDR10.D0       0
PORTE          0x002B     PORT E DATA
PORTE.PE7       7   Port E Data Bits 7
PORTE.PE6       6   Port E Data Bits 6
PORTE.PE5       5   Port E Data Bits 5
PORTE.PE4       4   Port E Data Bits 4
PORTE.PE3       3   Port E Data Bits 3
PORTE.PE2       2   Port E Data Bits 2
PORTE.PE1       1   Port E Data Bits 1
PORTE.PE0       0   Port E Data Bits 0
PORTF          0x002C     PORT F DATA
PORTF.PF3       3   Port F Data Bits 3
PORTF.PF2       2   Port F Data Bits 2
PORTF.PF1       1   Port F Data Bits 1
PORTF.PF0       0   Port F Data Bits 0
UNUSED002D     0x002D     UNUSED
DDRF           0x002E     PORT F DATA DIRECTION
DDRF.DDRF3      3   Data Direction for Port F Bit 3
DDRF.DDRF2      2   Data Direction for Port F Bit 2
DDRF.DDRF1      1   Data Direction for Port F Bit 1
DDRF.DDRF0      0   Data Direction for Port F Bit 0
MISCELL        0x002F     MISCELLANEOUS
MISCELL.IGNS    7   Ignition status bit
MISCELL.OCE     6   Output compare enable
MISCELL.PDC     0   Power Down Control
PWMD           0x0030     PWM DATA
PWMD.POL        7   PWM Polarity
PWMD.D5         5
PWMD.D4         4
PWMD.D3         3
PWMD.D2         2
PWMD.D1         1
PWMD.D0         0
PWMC           0x0031     PWM CONTROL
PWMC.PSA1       7   PSA1 - PWM Clock Rate
PWMC.PSA0       6   PSA0 - PWM Clock Rate
PWMC.PSB3       3   PSB3 - PWM Clock Rate
PWMC.PSB2       2   PSB2 - PWM Clock Rate
PWMC.PSB1       1   PSB1 - PWM Clock Rate
PWMC.PSB0       0   PSB0 - PWM Clock Rate
UNUSED0032     0x0032     UNUSED
UNUSED0033     0x0033     UNUSED
MRDR0          0x0034     MDLC RX DATA REGISTER 0
MRDR0.D7        7
MRDR0.D6        6
MRDR0.D5        5
MRDR0.D4        4
MRDR0.D3        3
MRDR0.D2        2
MRDR0.D1        1
MRDR0.D0        0
MRDR1          0x0035     MDLC RX DATA REGISTER 1
MRDR1.D7        7
MRDR1.D6        6
MRDR1.D5        5
MRDR1.D4        4
MRDR1.D3        3
MRDR1.D2        2
MRDR1.D1        1
MRDR1.D0        0
MRDR2          0x0036     MDLC RX DATA REGISTER 2
MRDR2.D7        7
MRDR2.D6        6
MRDR2.D5        5
MRDR2.D4        4
MRDR2.D3        3
MRDR2.D2        2
MRDR2.D1        1
MRDR2.D0        0
MRDR3          0x0037     MDLC RX DATA REGISTER 3
MRDR3.D7        7
MRDR3.D6        6
MRDR3.D5        5
MRDR3.D4        4
MRDR3.D3        3
MRDR3.D2        2
MRDR3.D1        1
MRDR3.D0        0
MRDR4          0x0038     MDLC RX DATA REGISTER 4
MRDR4.D7        7
MRDR4.D6        6
MRDR4.D5        5
MRDR4.D4        4
MRDR4.D3        3
MRDR4.D2        2
MRDR4.D1        1
MRDR4.D0        0
MRDR5          0x0039     MDLC RX DATA REGISTER 5
MRDR5.D7        7
MRDR5.D6        6
MRDR5.D5        5
MRDR5.D4        4
MRDR5.D3        3
MRDR5.D2        2
MRDR5.D1        1
MRDR5.D0        0
MRDR6          0x003A     MDLC RX DATA REGISTER 6
MRDR6.D7        7
MRDR6.D6        6
MRDR6.D5        5
MRDR6.D4        4
MRDR6.D3        3
MRDR6.D2        2
MRDR6.D1        1
MRDR6.D0        0
MRDR7          0x003B     MDLC RX DATA REGISTER 7
MRDR7.D7        7
MRDR7.D6        6
MRDR7.D5        5
MRDR7.D4        4
MRDR7.D3        3
MRDR7.D2        2
MRDR7.D1        1
MRDR7.D0        0
MRDR8          0x003C     MDLC RX DATA REGISTER 8
MRDR8.D7        7
MRDR8.D6        6
MRDR8.D5        5
MRDR8.D4        4
MRDR8.D3        3
MRDR8.D2        2
MRDR8.D1        1
MRDR8.D0        0
MRDR9          0x003D     MDLC RX DATA REGISTER 9
MRDR9.D7        7
MRDR9.D6        6
MRDR9.D5        5
MRDR9.D4        4
MRDR9.D3        3
MRDR9.D2        2
MRDR9.D1        1
MRDR9.D0        0
MRDR10         0x003E     MDLC RX DATA REGISTER 10
MRDR10.D7       7
MRDR10.D6       6
MRDR10.D5       5
MRDR10.D4       4
MRDR10.D3       3
MRDR10.D2       2
MRDR10.D1       1
MRDR10.D0       0
RESERV003F     0x003F     RESERVED
COP            0x3FF0
COP.COPR        0
RESER3FF1      0x3FF1	RESERVED


.68HC05X16
; MC68HC05X16/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05X16&nodeId=01M98633
; MC68HC05X16.pdf

; RAM=352
; ROM=14.75K
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR           0x0000:0x0020
area DATA MCAN          0x0020:0x003E
area BSS  RESERVED      0x003E:0x0050
area DATA RAM_U1        0x0050:0x0100
area DATA EEPROM        0x0100:0x0200
area DATA BootROM_U1    0x0200:0x0250
area DATA RAM_U2        0x0250:0x0300
area DATA ROM           0x0300:0x3DFE
area BSS  RESERVED      0x3DFE:0x3E00
area DATA BootROM_U2    0x3E00:0x3FF0
area DATA USER_VEC      0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x3FF8      Timer input captures
interrupt TIMER_Out_Comp    0x3FF6      Timer output compares
interrupt TIMER_Overf       0x3FF4      Timer overflow
interrupt SCI               0x3FF2      Serial communications interface
interrupt CIRQ              0x3FF0      MCAN interrupt


; INPUT/ OUTPUT PORTS
PORTA           0x0000    Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001    Port B data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002    Port C data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2_ECLK   2   Port C Data Bit 2/ External clock option bit
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003    Port D data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD6        6   Port D Data Bits 6
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004     PORT A DATA DIRECTION
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005     PORT B DATA DIRECTION
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006     PORT C DATA DIRECTION
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
C_EEPROM        0x0007  EEPROM/ECLK control
C_EEPROM.WOIE    7   WOIE - Wired-OR interrupt enable
C_EEPROM.CAF     6   CAF - MCAN asleep flag
C_EEPROM.ECLK    3   ECLK - External clock option bit
C_EEPROM.E1ERA   2   E1ERA - EEPROM erase/programming bit
C_EEPROM.E1LAT   1   E1LAT - EEPROM programming latch enable bit
C_EEPROM.E1PGM   0   E1PGM - EEPROM charge pump enable/disable
ADDATA          0x0008  A/D data
ADSTAT          0x0009  A/D ststus/control
ADSTAT.COCO      7   Conversion complete flag
ADSTAT.ADRC      6   A/D RC oscillator control
ADSTAT.ADON      5   ADON - A/D converter on
ADSTAT.CH3       3   A/D channels 3
ADSTAT.CH2       2   A/D channels 2
ADSTAT.CH1       1   A/D channels 1
ADSTAT.CH0       0   A/D channels 0
PLMA            0x000A  Pulse length modulation A
PLMB            0x000B  Pulse length modulation B
Miscell         0x000C  Miscellaneous
Miscell.POR      7   Power-on reset bit
Miscell.INTP     6   External interrupt sensitivity options
Miscell.INTN     5   External interrupt sensitivity options
Miscell.INTE     4   External interrupt enable
Miscell.SFA      3   Slow or fast mode selection for PLMA
Miscell.SFB      2   Slow or fast mode selection for PLMB
Miscell.SM       1   Slow mode
Miscell.WDOG     0   Watchdog enable/disable
BAUD            0x000D  Baud rate register
BAUD.SCP1        7   Serial prescaler select bits 1
BAUD.SCP0        6   Serial prescaler select bits 0
BAUD.SCT2        5   SCI rate select bits 2
BAUD.SCT1        4   SCI rate select bits 1
BAUD.SCT0        3   SCI rate select bits 0
BAUD.SCR2        2   SCI rate select bits 2
BAUD.SCR1        1   SCI rate select bits 1
BAUD.SCR0        0   SCI rate select bits 0
SCCR1           0x000E   Serial communications control register 1
SCCR1.R8         7   Receive data bit
SCCR1.T8         6   Transmit data bit
SCCR1.M          4   Mode
SCCR1.WAKE       3   Wake-up mode select
SCCR1.CPOL       2   Clock polarity
SCCR1.CPHA       1   Clock phase
SCCR1.LBCL       0   Last bit clock
SCCR2           0x000F   Serial communications control register 2
SCCR2.TIE        7   Transmit interrupt enable
SCCR2.TCIE       6   Transmit complete interrupt enable
SCCR2.RIE        5   Receiver interrupt enable
SCCR2.ILIE       4   Idle line interrupt enable
SCCR2.TE         3   Transmitter enable
SCCR2.RE         2   Receiver enable
SCCR2.RWU        1   Receiver wake-up
SCCR2.SBK        0   Send break
SCSR            0x0010   Serial communications status register
SCSR.TDRE        7   Transmit data register empty flag
SCSR.TC          6   Transmit complete flag
SCSR.RDRF        5   Receive data register full flag
SCSR.IDLE        4   Idle line detected flag
SCSR.OR          3   Overrun error flag
SCSR.NF          2   Noise error flag
SCSR.FE          1   Framing error flag
SCDR            0x0011    SCI data
TCR             0x0012    Timer control register
TCR.ICIE         7   Input captures interrupt enable
TCR.OCIE         6   Output compares interrupt enable
TCR.TOIE         5   Timer overflow interrupt enable
TCR.FOLV2        4   Force output compare 2
TCR.FOLV1        3   Force output compare 1
TCR.OLV2         2   Output level 2
TCR.IEDG1        1   Input edge 1
TCR.OLVL1        0   Output level 1
TSR             0x0013    Timer status register
TSR.ICF1         7   Input capture flag 1
TSR.OCF1         6   Output compare flag 1
TSR.TOF          5   Timer overflow status flag
TSR.ICF2         4   Input capture flag 2
TSR.OCF2         3   Output compare flag 2
ICH1            0x0014   Input capture high 1
ICL1            0x0015   Input capture low 1
OCH1            0x0016   Output compare high 1
OCL1            0x0017   Output compare low 1
TCH             0x0018   Timer counter high
TCL             0x0019   Timer counter low
ACH             0x001A   Alternate counter high
ACL             0x001B   Alternate counter low
ICH2            0x001C   Input campare high 2
ICL2            0x001D   Input capture low 2
OCH2            0x001E   Output compare high 2
OCL2            0x001F   Output compare low 2
CANCTRL         0x0020   MCAN control register
CANCTRL.MODE     7   Undefined mode
CANCTRL.SPD      6   Speed mode
CANCTRL.OIE      4   Overrun interrupt enable
CANCTRL.EIE      3   Error interrupt enable
CANCTRL.TIE      2   Transmit interrupt enable
CANCTRL.RIE      1   Receive interrupt enable
CANCTRL.RR       0   Reset request
CANCOM          0x0021   MCAN command register
CANCOM.RX0       7   Receive pin 0 (passive)
CANCOM.RX1       6   Receive pin 1
CANCOM.COMPSEL   5   Comparator selector
CANCOM.SLEEP     4   Go to sleep
CANCOM.COS       3   Clear overrun status
CANCOM.RRB       2   Release receive buffer
CANCOM.AT        1   Abort transmission
CANCOM.TR        0   Transmission request
CANSTAT         0x0022   MCAN status register (CSTAT)
CANSTAT.BS       7   BS - Bus status
CANSTAT.ES       6   ES - Error status
CANSTAT.TS       5   Transmit status
CANSTAT.RS       4   Receive status
CANSTAT.TCS      3   Transmission complete status
CANSTAT.TBA      2   Transmit buffer access
CANSTAT.DO       1   Data overrun
CANSTAT.RBS      0   Receive buffer status
CANINT          0x0023   MCAN interrupt register
CANINT.WIF       4   Wake-up interrupt flag
CANINT.OIF       3   Overrun interrupt flag
CANINT.EIF       2   Error interrupt flag
CANINT.TIF       1   Transmit interrupt flag
CANINT.RIF       0   Receive interrupt flag
CANACC          0x0024   Acceptance code
CANACC.AC7       7   Acceptance code bits 7
CANACC.AC6       6   Acceptance code bits 6
CANACC.AC5       5   Acceptance code bits 5
CANACC.AC4       4   Acceptance code bits 4
CANACC.AC3       3   Acceptance code bits 3
CANACC.AC2       2   Acceptance code bits 2
CANACC.AC1       1   Acceptance code bits 1
CANACC.AC0       0   Acceptance code bits 0
CANACM          0x0025   MCAN acceptance mask register
CANACM.AM7       7   Acceptance mask bit 7
CANACM.AM6       6   Acceptance mask bit 6
CANACM.AM5       5   Acceptance mask bit 5
CANACM.AM4       4   Acceptance mask bit 4
CANACM.AM3       3   Acceptance mask bit 3
CANACM.AM2       2   Acceptance mask bit 2
CANACM.AM1       1   Acceptance mask bit 1
CANACM.AM0       0   Acceptance mask bit 0
CANBT0          0x0026   MCAN bus timing register 00
CANBT0.SJW1      7   Synchronization jump width bits 1
CANBT0.SJW0      6   Synchronization jump width bits 0
CANBT0.BRP5      5   Baud rate prescaler bits 5
CANBT0.BRP4      4   Baud rate prescaler bits 4
CANBT0.BRP3      3   Baud rate prescaler bits 3
CANBT0.BRP2      2   Baud rate prescaler bits 2
CANBT0.BRP1      1   Baud rate prescaler bits 1
CANBT0.BRP0      0   Baud rate prescaler bits 0
CANBT1          0x0027   MCAN bus timing register 1
CANBT1.SAMP      7   Sampling
CANBT1.TSEG22    6   Time segment bits 22
CANBT1.TSEG21    5   Time segment bits 21
CANBT1.TSEG20    4   Time segment bits 20
CANBT1.TSEG13    3   Time segment bits 13
CANBT1.TSEG12    2   Time segment bits 12
CANBT1.TSEG11    1   Time segment bits 11
CANBT1.TSEG10    0   Time segment bits 10
CANOPC          0x0028   MCAN output control register
CANOPC.OCTP1     7
CANOPC.OCTN1     6
CANOPC.OCPOL1    5
CANOPC.OCTP0     4
CANOPC.OCTN0     3
CANOPC.OCPOL0    2
CANOPC.OCM1      1   Output control mode bits 1
CANOPC.OCM0      0   Output control mode bits 0
Reserv0029      0x0029   reserved
CANTBI          0x002A   Transmit buffere identifiner
CANTBI.ID10      7   Identifier bit 10
CANTBI.ID9       6   Identifier bit 9 
CANTBI.ID8       5   Identifier bit 8 
CANTBI.ID7       4   Identifier bit 7 
CANTBI.ID6       3   Identifier bit 6 
CANTBI.ID5       2   Identifier bit 5 
CANTBI.ID4       1   Identifier bit 4 
CANTBI.ID3       0   Identifier bit 3 
CANTRTDL        0x002B   RTR-bit data length code
CANTRTDL.ID2     7   Identifier bit 2
CANTRTDL.ID1     6   Identifier bit 1
CANTRTDL.ID0     5   Identifier bit 0
CANTRTDL.RTR     4   Remote transmission request
CANTRTDL.DLC3    3   Data length code bits 3    
CANTRTDL.DLC2    2   Data length code bits 2    
CANTRTDL.DLC1    1   Data length code bits 1    
CANTRTDL.DLC0    0   Data length code bits 0    
CANTDS1         0x002C    Transmit data segment 1
CANTDS1.DB7      7   data bit 7
CANTDS1.DB6      6   data bit 6
CANTDS1.DB5      5   data bit 5
CANTDS1.DB4      4   data bit 4
CANTDS1.DB3      3   data bit 3
CANTDS1.DB2      2   data bit 2
CANTDS1.DB1      1   data bit 1
CANTDS1.DB0      0   data bit 0
CANTDS2         0x002D    Transmit data segment 2
CANTDS2.DB7      7   data bit 7
CANTDS2.DB6      6   data bit 6
CANTDS2.DB5      5   data bit 5
CANTDS2.DB4      4   data bit 4
CANTDS2.DB3      3   data bit 3
CANTDS2.DB2      2   data bit 2
CANTDS2.DB1      1   data bit 1
CANTDS2.DB0      0   data bit 0
CANTDS3         0x002E    Transmit data segment 3
CANTDS3.DB7      7   data bit 7
CANTDS3.DB6      6   data bit 6
CANTDS3.DB5      5   data bit 5
CANTDS3.DB4      4   data bit 4
CANTDS3.DB3      3   data bit 3
CANTDS3.DB2      2   data bit 2
CANTDS3.DB1      1   data bit 1
CANTDS3.DB0      0   data bit 0
CANTDS4         0x002F    Transmit data segment 4
CANTDS4.DB7      7   data bit 7
CANTDS4.DB6      6   data bit 6
CANTDS4.DB5      5   data bit 5
CANTDS4.DB4      4   data bit 4
CANTDS4.DB3      3   data bit 3
CANTDS4.DB2      2   data bit 2
CANTDS4.DB1      1   data bit 1
CANTDS4.DB0      0   data bit 0
CANTDS5         0x0030    Transmit data segment 5
CANTDS5.DB7      7   data bit 7
CANTDS5.DB6      6   data bit 6
CANTDS5.DB5      5   data bit 5
CANTDS5.DB4      4   data bit 4
CANTDS5.DB3      3   data bit 3
CANTDS5.DB2      2   data bit 2
CANTDS5.DB1      1   data bit 1
CANTDS5.DB0      0   data bit 0
CANTDS6         0x0031    Transmit data segment 6
CANTDS6.DB7      7   data bit 7
CANTDS6.DB6      6   data bit 6
CANTDS6.DB5      5   data bit 5
CANTDS6.DB4      4   data bit 4
CANTDS6.DB3      3   data bit 3
CANTDS6.DB2      2   data bit 2
CANTDS6.DB1      1   data bit 1
CANTDS6.DB0      0   data bit 0
CANTDS7         0x0032    Transmit data segment 7
CANTDS7.DB7      7   data bit 7
CANTDS7.DB6      6   data bit 6
CANTDS7.DB5      5   data bit 5
CANTDS7.DB4      4   data bit 4
CANTDS7.DB3      3   data bit 3
CANTDS7.DB2      2   data bit 2
CANTDS7.DB1      1   data bit 1
CANTDS7.DB0      0   data bit 0
CANTDS8         0x0033    Transmit data segment 8
CANTDS8.DB7      7   data bit 7
CANTDS8.DB6      6   data bit 6
CANTDS8.DB5      5   data bit 5
CANTDS8.DB4      4   data bit 4
CANTDS8.DB3      3   data bit 3
CANTDS8.DB2      2   data bit 2
CANTDS8.DB1      1   data bit 1
CANTDS8.DB0      0   data bit 0
CANRBI          0x0034    Receive buffer idertifiner
CANRBI.ID10      7   Identifier bit 10
CANRBI.ID9       6   Identifier bit 9 
CANRBI.ID8       5   Identifier bit 8 
CANRBI.ID7       4   Identifier bit 7 
CANRBI.ID6       3   Identifier bit 6 
CANRBI.ID5       2   Identifier bit 5 
CANRBI.ID4       1   Identifier bit 4 
CANRBI.ID3       0   Identifier bit 3 
CANRRTDL        0x0035    RTR-bit , data length code
CANRRTDL.ID2     7   Identifier bit 2
CANRRTDL.ID1     6   Identifier bit 1
CANRRTDL.ID0     5   Identifier bit 0
CANRRTDL.RTR     4   Remote transmission request
CANRRTDL.DLC3    3   Data length code bits 3
CANRRTDL.DLC2    2   Data length code bits 2
CANRRTDL.DLC1    1   Data length code bits 1
CANRRTDL.DLC0    0   Data length code bits 0
CANRDS1         0x0036    Receive data segment 1
CANRDS1.DB7      7   data bit 7
CANRDS1.DB6      6   data bit 6
CANRDS1.DB5      5   data bit 5
CANRDS1.DB4      4   data bit 4
CANRDS1.DB3      3   data bit 3
CANRDS1.DB2      2   data bit 2
CANRDS1.DB1      1   data bit 1
CANRDS1.DB0      0   data bit 0
CANRDS2         0x0037    Receive data segment 2
CANRDS2.DB7      7   data bit 7
CANRDS2.DB6      6   data bit 6
CANRDS2.DB5      5   data bit 5
CANRDS2.DB4      4   data bit 4
CANRDS2.DB3      3   data bit 3
CANRDS2.DB2      2   data bit 2
CANRDS2.DB1      1   data bit 1
CANRDS2.DB0      0   data bit 0
CANRDS3         0x0038    Receive data segment 3
CANRDS3.DB7      7   data bit 7
CANRDS3.DB6      6   data bit 6
CANRDS3.DB5      5   data bit 5
CANRDS3.DB4      4   data bit 4
CANRDS3.DB3      3   data bit 3
CANRDS3.DB2      2   data bit 2
CANRDS3.DB1      1   data bit 1
CANRDS3.DB0      0   data bit 0
CANRDS4         0x0039    Receive data segment 4
CANRDS4.DB7      7   data bit 7
CANRDS4.DB6      6   data bit 6
CANRDS4.DB5      5   data bit 5
CANRDS4.DB4      4   data bit 4
CANRDS4.DB3      3   data bit 3
CANRDS4.DB2      2   data bit 2
CANRDS4.DB1      1   data bit 1
CANRDS4.DB0      0   data bit 0
CANRDS5         0x003A    Receive data segment 5
CANRDS5.DB7      7   data bit 7
CANRDS5.DB6      6   data bit 6
CANRDS5.DB5      5   data bit 5
CANRDS5.DB4      4   data bit 4
CANRDS5.DB3      3   data bit 3
CANRDS5.DB2      2   data bit 2
CANRDS5.DB1      1   data bit 1
CANRDS5.DB0      0   data bit 0
CANRDS6         0x003B    Receive data segment 6
CANRDS6.DB7      7   data bit 7
CANRDS6.DB6      6   data bit 6
CANRDS6.DB5      5   data bit 5
CANRDS6.DB4      4   data bit 4
CANRDS6.DB3      3   data bit 3
CANRDS6.DB2      2   data bit 2
CANRDS6.DB1      1   data bit 1
CANRDS6.DB0      0   data bit 0
CANRDS7         0x003C    Receive data segment 7
CANRDS7.DB7      7   data bit 7
CANRDS7.DB6      6   data bit 6
CANRDS7.DB5      5   data bit 5
CANRDS7.DB4      4   data bit 4
CANRDS7.DB3      3   data bit 3
CANRDS7.DB2      2   data bit 2
CANRDS7.DB1      1   data bit 1
CANRDS7.DB0      0   data bit 0
CANRDS8         0x003D    Receive data segment 8
CANRDS8.DB7      7   data bit 7
CANRDS8.DB6      6   data bit 6
CANRDS8.DB5      5   data bit 5
CANRDS8.DB4      4   data bit 4
CANRDS8.DB3      3   data bit 3
CANRDS8.DB2      2   data bit 2
CANRDS8.DB1      1   data bit 1
CANRDS8.DB0      0   data bit 0
OPTR            0x0100    Options register
OPTR.EE1P        1   EEPROM protect bit
OPTR.SEC	 0   Security bit


.68HC05X32
; MC68HC05X16/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05X32&nodeId=01M98633
; MC68HC05X16.pdf

; RAM=528
; ROM=31232(user ROM)+654(bootstrap ROM) = 31870 bytes
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR            0x0000:0x0020
area DATA MCAN           0x0020:0x003E
area BSS  RESERVED       0x003E:0x0050
area DATA RAM_U1         0x0050:0x0100
area DATA EEPROM         0x0100:0x0200
area DATA BOOTROM_U1     0x0200:0x0250
area DATA RAM_U2         0x0250:0x03B0
area DATA BOOTROM_U2     0x03B0:0x0400
area CODE ROM            0x0400:0x7E00
area DATA BOOTROM_U3     0x7E00:0x7FDE
area BSS  RESERVED       0x7FDE:0x7FE0
area DATA BOOT_VEC       0x7FE0:0x7FF0
area DATA USER_VEC       0x7FF0:0x8000


; Interrupt and reset vector assignments
interrupt __RESET           0x7FFE      Processor reset
interrupt SWI               0x7FFC      Software interrupt
interrupt IRQ               0x7FFA      External interrupt
interrupt TIMER_In_Cap      0x7FF8      Timer input captures
interrupt TIMER_Out_Comp    0x7FF6      Timer output compares
interrupt TIMER_Overf       0x7FF4      Timer overflow
interrupt SCI               0x7FF2      Serial communications interface
interrupt CIRQ              0x7FF0


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2_ECLK         2   Port C Data Bit 2/ External clock option bit
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006    Port C data direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
C_EEPROM              0x0007    EEPROM/ECLK control
C_EEPROM.WOIE          7   Wired-OR interrupt enable bit
C_EEPROM.CAF           6   MCAN asleep flag
C_EEPROM.ECLK          3   External clock output
C_EEPROM.E1ERA         2   EEPROM erase/programming bit
C_EEPROM.E1LAT         1   EPROM programming latch enable bit
C_EEPROM.E1PGM         0   EPROM program enable bit
ADDATA                0x0008    A/D data
ADSTAT                0x0009    A/D status/control
ADSTAT.COCO            7   Conversion complete flag
ADSTAT.ADRC            6   A/D RC oscillator control
ADSTAT.ADON            5   A/D converter on
ADSTAT.CH3             3   A/D channels 3
ADSTAT.CH2             2   A/D channels 2
ADSTAT.CH1             1   A/D channels 1
ADSTAT.CH0             0   A/D channels 0
PLMA                  0x000A    Pulse length modulation A
PLMB                  0x000B    Pulse length modulation B
Miscell               0x000C    Miscellaneous
Miscell.POR            7   Power-on reset bit
Miscell.INTP           6   External interrupt sensitivity options
Miscell.INTN           5
Miscell.INTE           4   External interrupt enable
Miscell.SFA            3   Slow or fast mode selection for PLMA
Miscell.SFB            2   Slow or fast mode selection for PLMB
Miscell.SM             1   Slow mode
Miscell.WDOG           0   Watchdog enable/disable
BAUD                  0x000D    Baud rate register
BAUD.SCP1              7   Serial prescaler select bits 1
BAUD.SCP0              6   Serial prescaler select bits 0
BAUD.SCT2              5   SCI rate select bits 2
BAUD.SCT1              4   SCI rate select bits 1
BAUD.SCT0              3   SCI rate select bits 0
BAUD.SCR2              2   SCI rate select bits 2
BAUD.SCR1              1   SCI rate select bits 1
BAUD.SCR0              0   SCI rate select bits 0
SCCR1                 0x000E    Serial communications control register 1
SCCR1.R8               7   Receive data bit 8
SCCR1.T8               6   Transmit data bit 8
SCCR1.M                4   Mode
SCCR1.WAKE             3   Wake-up mode select
SCCR1.CPOL             2   Clock polarity
SCCR1.CPHA             1   Clock phase
SCCR1.LBCL             0   Last bit clock
SCCR2                 0x000F    Serial communications control register 2
SCCR2.TIE              7   Transmit interrupt enable
SCCR2.TCIE             6   Transmit complete interrupt enable
SCCR2.RIE              5   Receiver interrupt enable
SCCR2.ILIE             4   Idle line interrupt enable
SCCR2.TE               3   Transmitter enable
SCCR2.RE               2   Receiver enable
SCCR2.RWU              1   Receiver wake-up
SCCR2.SBK              0   Send break
SCSR                  0x0010    Serial communications status register
SCSR.TDRE              7   Transmit data register empty flag
SCSR.TC                6   Transmit complete flag
SCSR.RDRF              5   Receive data register full flag
SCSR.IDLE              4   Idle line detected flag
SCSR.OR                3   Overrun error flag
SCSR.NF                2   Noise error flag
SCSR.FE                1   Framing error flag
SCDR                  0x0011    SCI status
TCR                   0x0012    Timer control register (TCR)
TCR.ICIE               7   Input captures interrupt enable
TCR.OCIE               6   Output compares interrupt enable
TCR.TOIE               5   Timer overflow interrupt enable
TCR.FOLV2              4   Force output compare 2
TCR.FOLV1              3   Force output compare 1
TCR.OLV2               2   Output level 2
TCR.IEDG1              1   Input edge 1
TCR.OLVL1              0   Output level 1
TSR                   0x0013    Timer status register
TSR.ICF1               7   Input capture flag 1
TSR.OCF1               6   Output compare flag 1
TSR.TOF                5   Timer overflow status flag
TSR.ICF2               4   Input capture flag 2
TSR.OCF2               3   Output compare flag 2
ICH1                  0x0014    Input capture high 1
ICL1                  0x0015    Input capture low 1
OCH1                  0x0016    Output compare high 1
OCL1                  0x0017    Output compare low 1
TCH                   0x0018    Timer counter high
TCL                   0x0019    Timer counter low
ACH                   0x001A    Alternate counter high
ACL                   0x001B    Alternate counter low
ICH2                  0x001C    Input capture high 2
ICL2                  0x001D    Input capture low 2
OCH2                  0x001E    Output compare high 2
OCL2                  0x001F    Output compare low 2
CANCNTRL              0x0020    CAN Control Register
CANCNTRL.MODE          7   Mode
CANCNTRL.SPD           6   Sped Mode
CANCNTRL.OIE           4   Overrun Interrupt Enable
CANCNTRL.EIE           3   Error Interrupt Enable
CANCNTRL.TIE           2   Transmit Interrupt Enable
CANCNTRL.RIE           1   Receive Interrupt Enable
CANCNTRL.RR            0   Reset Reguest
CANCOM                0x0021    CAN Command Register
CANCOM.RX0             7   RX0 - Receive pin 0 (passive)
CANCOM.RX1             6   RX1 - Receive pin 1 (passive)
CANCOM.COMPSEL         5   Comparator selector
CANCOM.SLEEP           4   Go to sleep
CANCOM.COS             3   Clear overrun status
CANCOM.RRB             2   Release receive buffer
CANCOM.AT              1   Abort transmission
CANCOM.TR              0   Abort transmission
CANSTAT               0x0022   CAN Status Register
CANSTAT.BS             7   Bus status
CANSTAT.ES             6   Error status
CANSTAT.TS             5   Transmit status
CANSTAT.RS             4   Receive status
CANSTAT.TCS            3   Transmission complete status
CANSTAT.TBA            2   Transmit buffer access
CANSTAT.D0             1   Data overrun
CANSTAT.RBS            0   Receive buffer status
CANINT                0x0023   CAN Interrupt Register
CANINT.WIF             4   Wake-up interrupt flag
CANINT.OIF             3   Overrun interrupt flag
CANINT.EIF             2   Error interrupt flag
CANINT.TIF             1   Transmit interrupt flag
CANINT.RIF             0   Receive interrupt flag
CANACC                0x0024   CAN Acceptance Code Register
CANACC.AC7             7   Acceptance code bits 7
CANACC.AC6             6   Acceptance code bits 6
CANACC.AC5             5   Acceptance code bits 5
CANACC.AC4             4   Acceptance code bits 4
CANACC.AC3             3   Acceptance code bits 3
CANACC.AC2             2   Acceptance code bits 2
CANACC.AC1             1   Acceptance code bits 1
CANACC.AC0             0   Acceptance code bits 0
CANACM                0x0025   CAN Acceptance Mask Register
CANACM.AM7             7   Acceptance mask bits 7
CANACM.AM6             6   Acceptance mask bits 6
CANACM.AM5             5   Acceptance mask bits 5
CANACM.AM4             4   Acceptance mask bits 4
CANACM.AM3             3   Acceptance mask bits 3
CANACM.AM2             2   Acceptance mask bits 2
CANACM.AM1             1   Acceptance mask bits 1
CANACM.AM0             0   Acceptance mask bits 0
CANBT0                0x0026   CAN Bus Timing Register 1
CANBT0.SJW1            7   Synchronization jump width bits 1
CANBT0.SJW0            6   Synchronization jump width bits 0
CANBT0.BRP5            5   Baud rate prescaler bits 5
CANBT0.BRP4            4   Baud rate prescaler bits 4
CANBT0.BRP3            3   Baud rate prescaler bits 3
CANBT0.BRP2            2   Baud rate prescaler bits 2
CANBT0.BRP1            1   Baud rate prescaler bits 1
CANBT0.BRP0            0   Baud rate prescaler bits 0
CANBT1                0x0027   CAN Bus Timing Register 2
CANBT1.SAMP            7   Sampling
CANBT1.TSEG22          6   Time segment bits 16
CANBT1.TSEG21          5   Time segment bits 15
CANBT1.TSEG20          4   Time segment bits 14
CANBT1.TSEG13          3   Time segment bits 13
CANBT1.TSEG12          2   Time segment bits 12
CANBT1.TSEG11          1   Time segment bits 11
CANBT1.TSEG10          0   Time segment bits 10
CANOPC                0x0028   CAN O/P Control Register
CANOPC.OCTP1           7       
CANOPC.OCTN1           6       
CANOPC.OCPOL1          5
CANOPC.OCTP0           4
CANOPC.OCTN0           3
CANOPC.OCPOL0          2
CANOPC.OCM1            1   Output control mode bits 1
CANOPC.OCM0            0   Output control mode bits 0
RESERV0029            0x0029   RESERVED
CANTBI                0x002A   CAN Transmit Buffere Identifier Reg.
CANTBI.ID10            7   Identifier bits 10
CANTBI.ID9             6   Identifier bits 9
CANTBI.ID8             5   Identifier bits 8
CANTBI.ID7             4   Identifier bits 7
CANTBI.ID6             3   Identifier bits 6
CANTBI.ID5             2   Identifier bits 5
CANTBI.ID4             1   Identifier bits 4
CANTBI.ID3             0   Identifier bits 3
CANTRTDL              0x002B   RTR-bit data length code
CANTRTDL.ID2           7   Identifier bits 2
CANTRTDL.ID1           6   Identifier bits 1
CANTRTDL.ID0           5   Identifier bits 0
CANTRTDL.RTR           4   Remote transmission request
CANTRTDL.DLC3          3   Data length code bits 3
CANTRTDL.DLC2          2   Data length code bits 2
CANTRTDL.DLC1          1   Data length code bits 1
CANTRTDL.DLC0          0   Data length code bits 0
CANTDS1               0x002C    Transmit data segment 1
CANTDS1.DB7            7   data bit 7
CANTDS1.DB6            6   data bit 6
CANTDS1.DB5            5   data bit 5
CANTDS1.DB4            4   data bit 4
CANTDS1.DB3            3   data bit 3
CANTDS1.DB2            2   data bit 2
CANTDS1.DB1            1   data bit 1
CANTDS1.DB0            0   data bit 0
CANTDS2               0x002D    Transmit data segment 2
CANTDS2.DB7            7   data bit 7
CANTDS2.DB6            6   data bit 6
CANTDS2.DB5            5   data bit 5
CANTDS2.DB4            4   data bit 4
CANTDS2.DB3            3   data bit 3
CANTDS2.DB2            2   data bit 2
CANTDS2.DB1            1   data bit 1
CANTDS2.DB0            0   data bit 0
CANTDS3               0x002E    Transmit data segment 3
CANTDS3.DB7            7   data bit 7
CANTDS3.DB6            6   data bit 6
CANTDS3.DB5            5   data bit 5
CANTDS3.DB4            4   data bit 4
CANTDS3.DB3            3   data bit 3
CANTDS3.DB2            2   data bit 2
CANTDS3.DB1            1   data bit 1
CANTDS3.DB0            0   data bit 0
CANTDS4               0x002F    Transmit data segment 4
CANTDS4.DB7            7   data bit 7
CANTDS4.DB6            6   data bit 6
CANTDS4.DB5            5   data bit 5
CANTDS4.DB4            4   data bit 4
CANTDS4.DB3            3   data bit 3
CANTDS4.DB2            2   data bit 2
CANTDS4.DB1            1   data bit 1
CANTDS4.DB0            0   data bit 0
CANTDS5               0x0030    Transmit data segment 5
CANTDS5.DB7            7   data bit 7
CANTDS5.DB6            6   data bit 6
CANTDS5.DB5            5   data bit 5
CANTDS5.DB4            4   data bit 4
CANTDS5.DB3            3   data bit 3
CANTDS5.DB2            2   data bit 2
CANTDS5.DB1            1   data bit 1
CANTDS5.DB0            0   data bit 0
CANTDS6               0x0031    Transmit data segment 6
CANTDS6.DB7            7   data bit 7
CANTDS6.DB6            6   data bit 6
CANTDS6.DB5            5   data bit 5
CANTDS6.DB4            4   data bit 4
CANTDS6.DB3            3   data bit 3
CANTDS6.DB2            2   data bit 2
CANTDS6.DB1            1   data bit 1
CANTDS6.DB0            0   data bit 0
CANTDS7               0x0032    Transmit data segment 7
CANTDS7.DB7            7   data bit 7
CANTDS7.DB6            6   data bit 6
CANTDS7.DB5            5   data bit 5
CANTDS7.DB4            4   data bit 4
CANTDS7.DB3            3   data bit 3
CANTDS7.DB2            2   data bit 2
CANTDS7.DB1            1   data bit 1
CANTDS7.DB0            0   data bit 0
CANTDS8               0x0033    Transmit data segment 8
CANTDS8.DB7            7   data bit 7
CANTDS8.DB6            6   data bit 6
CANTDS8.DB5            5   data bit 5
CANTDS8.DB4            4   data bit 4
CANTDS8.DB3            3   data bit 3
CANTDS8.DB2            2   data bit 2
CANTDS8.DB1            1   data bit 1
CANTDS8.DB0            0   data bit 0
CANRBI                0x0034    Receive buffer idertifiner
CANRBI.ID10            7   Identifier bit 10
CANRBI.ID9             6   Identifier bit 9 
CANRBI.ID8             5   Identifier bit 8 
CANRBI.ID7             4   Identifier bit 7 
CANRBI.ID6             3   Identifier bit 6 
CANRBI.ID5             2   Identifier bit 5 
CANRBI.ID4             1   Identifier bit 4 
CANRBI.ID3             0   Identifier bit 3 
CANRRTDL              0x0035    RTR-bit , data length code
CANRRTDL.ID2           7   Identifier bit 2           
CANRRTDL.ID1           6   Identifier bit 1           
CANRRTDL.ID0           5   Identifier bit 0           
CANRRTDL.RTR           4   Remote transmission request
CANRRTDL.DLC3          3   Data length code bits 3    
CANRRTDL.DLC2          2   Data length code bits 2    
CANRRTDL.DLC1          1   Data length code bits 1    
CANRRTDL.DLC0          0   Data length code bits 0    
CANRDS1               0x0036    Receive data segment 1
CANRDS1.DB7            7   data bit 7
CANRDS1.DB6            6   data bit 6
CANRDS1.DB5            5   data bit 5
CANRDS1.DB4            4   data bit 4
CANRDS1.DB3            3   data bit 3
CANRDS1.DB2            2   data bit 2
CANRDS1.DB1            1   data bit 1
CANRDS1.DB0            0   data bit 0
CANRDS2               0x0037    Receive data segment 2
CANRDS2.DB7            7   data bit 7
CANRDS2.DB6            6   data bit 6
CANRDS2.DB5            5   data bit 5
CANRDS2.DB4            4   data bit 4
CANRDS2.DB3            3   data bit 3
CANRDS2.DB2            2   data bit 2
CANRDS2.DB1            1   data bit 1
CANRDS2.DB0            0   data bit 0
CANRDS3               0x0038    Receive data segment 3
CANRDS3.DB7            7   data bit 7
CANRDS3.DB6            6   data bit 6
CANRDS3.DB5            5   data bit 5
CANRDS3.DB4            4   data bit 4
CANRDS3.DB3            3   data bit 3
CANRDS3.DB2            2   data bit 2
CANRDS3.DB1            1   data bit 1
CANRDS3.DB0            0   data bit 0
CANRDS4               0x0039    Receive data segment 4
CANRDS4.DB7            7   data bit 7
CANRDS4.DB6            6   data bit 6
CANRDS4.DB5            5   data bit 5
CANRDS4.DB4            4   data bit 4
CANRDS4.DB3            3   data bit 3
CANRDS4.DB2            2   data bit 2
CANRDS4.DB1            1   data bit 1
CANRDS4.DB0            0   data bit 0
CANRDS5               0x003A    Receive data segment 5
CANRDS5.DB7            7   data bit 7
CANRDS5.DB6            6   data bit 6
CANRDS5.DB5            5   data bit 5
CANRDS5.DB4            4   data bit 4
CANRDS5.DB3            3   data bit 3
CANRDS5.DB2            2   data bit 2
CANRDS5.DB1            1   data bit 1
CANRDS5.DB0            0   data bit 0
CANRDS6               0x003B    Receive data segment 6
CANRDS6.DB7            7   data bit 7
CANRDS6.DB6            6   data bit 6
CANRDS6.DB5            5   data bit 5
CANRDS6.DB4            4   data bit 4
CANRDS6.DB3            3   data bit 3
CANRDS6.DB2            2   data bit 2
CANRDS6.DB1            1   data bit 1
CANRDS6.DB0            0   data bit 0
CANRDS7               0x003C    Receive data segment 7
CANRDS7.DB7            7   data bit 7
CANRDS7.DB6            6   data bit 6
CANRDS7.DB5            5   data bit 5
CANRDS7.DB4            4   data bit 4
CANRDS7.DB3            3   data bit 3
CANRDS7.DB2            2   data bit 2
CANRDS7.DB1            1   data bit 1
CANRDS7.DB0            0   data bit 0
CANRDS8               0x003D    Receive data segment 8
CANRDS8.DB7            7   data bit 7
CANRDS8.DB6            6   data bit 6
CANRDS8.DB5            5   data bit 5
CANRDS8.DB4            4   data bit 4
CANRDS8.DB3            3   data bit 3
CANRDS8.DB2            2   data bit 2
CANRDS8.DB1            1   data bit 1
CANRDS8.DB0            0   data bit 0
OPTR                  0x0100    Options register
OPTR.EE1P	       1   EEPROM protect bit
OPTR.SEC	       0   Security bit


.68HC05X4
; MC68HC05X4/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05X4&nodeId=01M98633

; RAM=176
; ROM=4K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA MCAN        0x0020:0x003E
area BSS  RESERVED    0x003E:0x0050
area DATA RAM         0x0050:0x0100
area BSS  RESERVED    0x0100:0x0F00
area DATA ROM         0x0F00:0x1F00
area DATA BootROM     0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt CIRQ              0x1FFA      WOI External IRQ
interrupt Core_timer        0x1FF8
interrupt WOI               0x1FF6
interrupt 16_bit_timer      0x1FF4


; INPUT/ OUTPUT PORTS
PADAT               0x0000      Port A data
PADAT.PA7            7   Port A Data Bits 7
PADAT.PA6            6   Port A Data Bits 6
PADAT.PA5            5   Port A Data Bits 5
PADAT.PA4            4   Port A Data Bits 4
PADAT.PA3            3   Port A Data Bits 3
PADAT.PA2            2   Port A Data Bits 2
PADAT.PA1            1   Port A Data Bits 1
PADAT.PA0            0   Port A Data Bits 0
PBDAT               0x0001      Port B data
PBDAT.PB7            7   Port B Data Bits 7
PBDAT.PB6            6   Port B Data Bits 6
PBDAT.PB5            5   Port B Data Bits 5
PBDAT.PB4            4   Port B Data Bits 4
PBDAT.PB3            3   Port B Data Bits 3
PBDAT.PB2            2   Port B Data Bits 2
PBDAT.PB1            1   Port B Data Bits 1
PBDAT.PB0            0   Port B Data Bits 0
Reserv0002          0x0002      Reserved
PCR                 0x0003      Port configuration
PCR.WOIF             5
PCR.TIMEN            4   Timer enable
PCR.CAF              3   MCAN asleep flag
PCR.BPDE             2
PCR.BWIE             1
PCR.AWPS             0
PADDDR              0x0004      Port A DDR
PBDDDR              0x0005      Port B DDR
Reserv0006          0x0006      Reserved
Reserv0007          0x0007      Reserved
CTCSR               0x0008      Core timer control & status
CTCSR.CTOF           7   Core timer overflow
CTCSR.RTIF           6   Real time interrupt flag
CTCSR.CTOFE          5   Core timer overflow interrupt enable
CTCSR.RTIE           4   Real time interrupt enable
CTCSR.RT1            1   Real time interrupt rate select 1
CTCSR.RT0            0   Real time interrupt rate select 0
CTCR                0x0009      Core timer counter
Reserv000A          0x000A      Reserved
Reserv000B          0x000B      Reserved
Reserv000C          0x000C      Reserved
Reserv000E          0x000E      Reserved
Reserv000F          0x000F      Reserved
Reserv0010          0x0010      Reserved
Reserv0011          0x0011      Reserved
TCR                 0x0012      Timer control
TCR.ICIE             7   Input capture interrupt enable
TCR.OCIE             6   Output compare interrupt enable
TCR.TOIE             5   Timer overflow interrupt enable
TCR.IEDG             1   Input edge
TCR.OLVL             0   Output level
TSR                 0x0013      Timer status
TSR.ICF              7   Input capture flag
TSR.OCF              6   Output compare flag
TSR.TOF              5   Timer overflow flag
ICH                 0x0014      Input capture high
ICL                 0x0015      Input capture low
OCH                 0x0016      Output compare high
OCL                 0x0017      Output compare low
COUNT_H             0x0018      Timer counter high
COUNT_L             0x0019      Timer counter low
ACH                 0x001A      Alternate counter high
ACL                 0x001B      Alternate counter low
UNUSED001C          0x001C      UNUSED
RESERV001D          0x001D      RESERVED
RESERV001E          0x001E      RESERVED
RESERV001F          0x001F      RESERVED
CANCTRL             0x0020      Control
CANCTRL.MODE         7   Undefined mode
CANCTRL.SPD          6   Speed mode
CANCTRL.OIE          4   Overrun interrupt enable
CANCTRL.EIE          3   Error interrupt enable
CANCTRL.TIE          2   Transmit interrupt enable
CANCTRL.RIE          1   Receive interrupt enable
CANCTRL.RR           0   Reset request
CANCOM              0x0021     Command
CANCOM.RX0           7   Receive pin 0 (passive)
CANCOM.RX1           6   Receive pin 1 (passive)
CANCOM.COMPSEL       5   Comparator selector
CANCOM.SLEEP         4   Go to sleep
CANCOM.COS           3   Clear overrun status
CANCOM.RRB           2   Release receive buffer
CANCOM.AT            1   Abort transmission
CANCOM.TR            0   Transmission request
CANSTAT             0x0022     Status
CANSTAT.BS           7   Bus status
CANSTAT.ES           6   Error status
CANSTAT.TS           5   Transmit status
CANSTAT.RS           4   Receive status
CANSTAT.TCS          3   Transmission complete status
CANSTAT.TBA          2   Transmit buffer access
CANSTAT.DO           1   Data overrun
CANSTAT.RBS          0   Receive buffer status
CANINT              0x0023     Interrupt
CANINT.WIF           4   Wake-up interrupt flag
CANINT.OIF           3   Overrun interrupt flag
CANINT.EIF           2   Error interrupt flag
CANINT.TIF           1   Transmit interrupt flag
CANINT.RIF           0   Receive interrupt flag
CANACC              0x0024     Acceptance code
CANACC.AC7           7   Acceptance code bits 7
CANACC.AC6           6   Acceptance code bits 6
CANACC.AC5           5   Acceptance code bits 5
CANACC.AC4           4   Acceptance code bits 4
CANACC.AC3           3   Acceptance code bits 3
CANACC.AC2           2   Acceptance code bits 2
CANACC.AC1           1   Acceptance code bits 1
CANACC.AC0           0   Acceptance code bits 0
CANACM              0x0025     Acceptance mask
CANACM.AM7           7   Acceptance mask bit 7
CANACM.AM6           6   Acceptance mask bit 6
CANACM.AM5           5   Acceptance mask bit 5
CANACM.AM4           4   Acceptance mask bit 4
CANACM.AM3           3   Acceptance mask bit 3
CANACM.AM2           2   Acceptance mask bit 2
CANACM.AM1           1   Acceptance mask bit 1
CANACM.AM0           0   Acceptance mask bit 0
CANBT0              0x0026     Bus timing 0
CANBT0.SJW1          7   Synchronization jump width bits 1
CANBT0.SJW0          6   Synchronization jump width bits 0
CANBT0.BRP5          5   Baud rate prescaler bits 5
CANBT0.BRP4          4   Baud rate prescaler bits 4
CANBT0.BRP3          3   Baud rate prescaler bits 3
CANBT0.BRP2          2   Baud rate prescaler bits 2
CANBT0.BRP1          1   Baud rate prescaler bits 1
CANBT0.BRP0          0   Baud rate prescaler bits 0
CANBT1              0x0027     Bus timing 1
CANBT1.SAMP          7   Sampling
CANBT1.TSEG22        6   Time segment bits 22
CANBT1.TSEG21        5   Time segment bits 21
CANBT1.TSEG20        4   Time segment bits 20
CANBT1.TSEG13        3   Time segment bits 13
CANBT1.TSEG12        2   Time segment bits 12
CANBT1.TSEG11        1   Time segment bits 11
CANBT1.TSEG10        0   Time segment bits 10
CANOPC              0x0028     Output control
CANOPC.OCTP1         7
CANOPC.OCTN1         6
CANOPC.OCPOL1        5
CANOPC.OCTP0         4
CANOPC.OCTN0         3
CANOPC.OCPOL0        2
CANOPC.OCM1          1   Output control mode bits 1
CANOPC.OCM0          0   Output control mode bits 0
Reserv0029          0x0029     reserved
CANTBI              0x002A     Transmit buffere identifiner
CANTBI.ID10          7   Identifier bit 10
CANTBI.ID9           6   Identifier bit 9 
CANTBI.ID8           5   Identifier bit 8 
CANTBI.ID7           4   Identifier bit 7 
CANTBI.ID6           3   Identifier bit 6 
CANTBI.ID5           2   Identifier bit 5 
CANTBI.ID4           1   Identifier bit 4 
CANTBI.ID3           0   Identifier bit 3 
CANTRTDL            0x002B     RTR-bit data length code
CANTRTDL.ID2         7   Identifier bit 2           
CANTRTDL.ID1         6   Identifier bit 1           
CANTRTDL.ID0         5   Identifier bit 0           
CANTRTDL.RTR         4   Remote transmission request
CANTRTDL.DLC3        3   Data length code bits 3    
CANTRTDL.DLC2        2   Data length code bits 2    
CANTRTDL.DLC1        1   Data length code bits 1    
CANTRTDL.DLC0        0   Data length code bits 0    
CANTDS1             0x002C      Transmit data segment 1
CANTDS1.DB7          7   data bit 7
CANTDS1.DB6          6   data bit 6
CANTDS1.DB5          5   data bit 5
CANTDS1.DB4          4   data bit 4
CANTDS1.DB3          3   data bit 3
CANTDS1.DB2          2   data bit 2
CANTDS1.DB1          1   data bit 1
CANTDS1.DB0          0   data bit 0
CANTDS2             0x002D      Transmit data segment 2
CANTDS2.DB7          7   data bit 7
CANTDS2.DB6          6   data bit 6
CANTDS2.DB5          5   data bit 5
CANTDS2.DB4          4   data bit 4
CANTDS2.DB3          3   data bit 3
CANTDS2.DB2          2   data bit 2
CANTDS2.DB1          1   data bit 1
CANTDS2.DB0          0   data bit 0
CANTDS3             0x002E      Transmit data segment 3
CANTDS3.DB7          7   data bit 7
CANTDS3.DB6          6   data bit 6
CANTDS3.DB5          5   data bit 5
CANTDS3.DB4          4   data bit 4
CANTDS3.DB3          3   data bit 3
CANTDS3.DB2          2   data bit 2
CANTDS3.DB1          1   data bit 1
CANTDS3.DB0          0   data bit 0
CANTDS4             0x002F      Transmit data segment 4
CANTDS4.DB7          7   data bit 7
CANTDS4.DB6          6   data bit 6
CANTDS4.DB5          5   data bit 5
CANTDS4.DB4          4   data bit 4
CANTDS4.DB3          3   data bit 3
CANTDS4.DB2          2   data bit 2
CANTDS4.DB1          1   data bit 1
CANTDS4.DB0          0   data bit 0
CANTDS5             0x0030      Transmit data segment 5
CANTDS5.DB7          7   data bit 7
CANTDS5.DB6          6   data bit 6
CANTDS5.DB5          5   data bit 5
CANTDS5.DB4          4   data bit 4
CANTDS5.DB3          3   data bit 3
CANTDS5.DB2          2   data bit 2
CANTDS5.DB1          1   data bit 1
CANTDS5.DB0          0   data bit 0
CANTDS6             0x0031      Transmit data segment 6
CANTDS6.DB7          7   data bit 7
CANTDS6.DB6          6   data bit 6
CANTDS6.DB5          5   data bit 5
CANTDS6.DB4          4   data bit 4
CANTDS6.DB3          3   data bit 3
CANTDS6.DB2          2   data bit 2
CANTDS6.DB1          1   data bit 1
CANTDS6.DB0          0   data bit 0
CANTDS7             0x0032      Transmit data segment 7
CANTDS7.DB7          7   data bit 7
CANTDS7.DB6          6   data bit 6
CANTDS7.DB5          5   data bit 5
CANTDS7.DB4          4   data bit 4
CANTDS7.DB3          3   data bit 3
CANTDS7.DB2          2   data bit 2
CANTDS7.DB1          1   data bit 1
CANTDS7.DB0          0   data bit 0
CANTDS8             0x0033      Transmit data segment 8
CANTDS8.DB7          7   data bit 7
CANTDS8.DB6          6   data bit 6
CANTDS8.DB5          5   data bit 5
CANTDS8.DB4          4   data bit 4
CANTDS8.DB3          3   data bit 3
CANTDS8.DB2          2   data bit 2
CANTDS8.DB1          1   data bit 1
CANTDS8.DB0          0   data bit 0
CANRBI              0x0034      Receive buffer idertifiner
CANRBI.ID10          7   Identifier bit 10
CANRBI.ID9           6   Identifier bit 9 
CANRBI.ID8           5   Identifier bit 8 
CANRBI.ID7           4   Identifier bit 7 
CANRBI.ID6           3   Identifier bit 6 
CANRBI.ID5           2   Identifier bit 5 
CANRBI.ID4           1   Identifier bit 4 
CANRBI.ID3           0   Identifier bit 3 
CANRRTDL            0x0035      RTR-bit , data length code
CANRRTDL.ID2         7   Identifier bit 2           
CANRRTDL.ID1         6   Identifier bit 1           
CANRRTDL.ID0         5   Identifier bit 0           
CANRRTDL.RTR         4   Remote transmission request
CANRRTDL.DLC3        3   Data length code bits 3    
CANRRTDL.DLC2        2   Data length code bits 2    
CANRRTDL.DLC1        1   Data length code bits 1    
CANRRTDL.DLC0        0   Data length code bits 0    
CANRDS1             0x0036      Receive data segment 1
CANRDS1.DB7          7   data bit 7
CANRDS1.DB6          6   data bit 6
CANRDS1.DB5          5   data bit 5
CANRDS1.DB4          4   data bit 4
CANRDS1.DB3          3   data bit 3
CANRDS1.DB2          2   data bit 2
CANRDS1.DB1          1   data bit 1
CANRDS1.DB0          0   data bit 0
CANRDS2             0x0037      Receive data segment 2
CANRDS2.DB7          7   data bit 7
CANRDS2.DB6          6   data bit 6
CANRDS2.DB5          5   data bit 5
CANRDS2.DB4          4   data bit 4
CANRDS2.DB3          3   data bit 3
CANRDS2.DB2          2   data bit 2
CANRDS2.DB1          1   data bit 1
CANRDS2.DB0          0   data bit 0
CANRDS3             0x0038      Receive data segment 3
CANRDS3.DB7          7   data bit 7
CANRDS3.DB6          6   data bit 6
CANRDS3.DB5          5   data bit 5
CANRDS3.DB4          4   data bit 4
CANRDS3.DB3          3   data bit 3
CANRDS3.DB2          2   data bit 2
CANRDS3.DB1          1   data bit 1
CANRDS3.DB0          0   data bit 0
CANRDS4             0x0039      Receive data segment 4
CANRDS4.DB7          7   data bit 7
CANRDS4.DB6          6   data bit 6
CANRDS4.DB5          5   data bit 5
CANRDS4.DB4          4   data bit 4
CANRDS4.DB3          3   data bit 3
CANRDS4.DB2          2   data bit 2
CANRDS4.DB1          1   data bit 1
CANRDS4.DB0          0   data bit 0
CANRDS5             0x003A      Receive data segment 5
CANRDS5.DB7          7   data bit 7
CANRDS5.DB6          6   data bit 6
CANRDS5.DB5          5   data bit 5
CANRDS5.DB4          4   data bit 4
CANRDS5.DB3          3   data bit 3
CANRDS5.DB2          2   data bit 2
CANRDS5.DB1          1   data bit 1
CANRDS5.DB0          0   data bit 0
CANRDS6             0x003B      Receive data segment 6
CANRDS6.DB7          7   data bit 7
CANRDS6.DB6          6   data bit 6
CANRDS6.DB5          5   data bit 5
CANRDS6.DB4          4   data bit 4
CANRDS6.DB3          3   data bit 3
CANRDS6.DB2          2   data bit 2
CANRDS6.DB1          1   data bit 1
CANRDS6.DB0          0   data bit 0
CANRDS7             0x003C      Receive data segment 7
CANRDS7.DB7          7   data bit 7
CANRDS7.DB6          6   data bit 6
CANRDS7.DB5          5   data bit 5
CANRDS7.DB4          4   data bit 4
CANRDS7.DB3          3   data bit 3
CANRDS7.DB2          2   data bit 2
CANRDS7.DB1          1   data bit 1
CANRDS7.DB0          0   data bit 0
CANRDS8             0x003D      Receive data segment 8
CANRDS8.DB7          7   data bit 7
CANRDS8.DB6          6   data bit 6
CANRDS8.DB5          5   data bit 5
CANRDS8.DB4          4   data bit 4
CANRDS8.DB3          3   data bit 3
CANRDS8.DB2          2   data bit 2
CANRDS8.DB1          1   data bit 1
CANRDS8.DB0          0   data bit 0
RESERV1FF0          0x1FF0      RESERVED
RESERV1FF1          0x1FF1      RESERVED
RESERV1FF2          0x1FF2      RESERVED
RESERV1FF3          0x1FF3      RESERVED


.68HC705B16
; MC68HC05B6/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705B16&nodeId=01M98633
; 6805b6r4.pdf

; RAM=352
; ROM=0
; EPROM=15K
; EEPROM=256


; MEMORY MAP
area DATA FSR           0x0000:0x0020
area DATA EPROM_P0      0x0020:0x0050
area DATA RAM_U1        0x0050:0x0100
area DATA EEPROM        0x0100:0x0200
area DATA BootROM_U1    0x0200:0x0250
area DATA RAM_U2        0x0250:0x0300
area DATA EPROM_P1      0x0300:0x3DFF
area BSS  RESERVED      0x3DFF:0x3E00
area DATA BootROM_U2    0x3E00:0x3FF0
area BSS  RESERVED      0x3FF0:0x3FF2
area DATA USER_VEC      0x3FF2:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0X3FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x3FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x3FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x3FF4      Timer overflow
interrupt SCI               0x3FF2      SCI


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2_ECLK         2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004    Port A data direction
DDRA.DDA7              7   Data Direction for Port A Bit 7
DDRA.DDA6              6   Data Direction for Port A Bit 6
DDRA.DDA5              5   Data Direction for Port A Bit 5
DDRA.DDA4              4   Data Direction for Port A Bit 4
DDRA.DDA3              3   Data Direction for Port A Bit 3
DDRA.DDA2              2   Data Direction for Port A Bit 2
DDRA.DDA1              1   Data Direction for Port A Bit 1
DDRA.DDA0              0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006    Port C data direction
DDRC.DDC7              7   Data Direction for Port C Bit 7
DDRC.DDC6              6   Data Direction for Port C Bit 6
DDRC.DDC5              5   Data Direction for Port C Bit 5
DDRC.DDC4              4   Data Direction for Port C Bit 4
DDRC.DDC3              3   Data Direction for Port C Bit 3
DDRC.DDC2              2   Data Direction for Port C Bit 2
DDRC.DDC1              1   Data Direction for Port C Bit 1
DDRC.DDC0              0   Data Direction for Port C Bit 0
EPROM                 0x0007    EPROM/EEPROM/ECLK control
EPROM.E6LAT            5
EPROM.E6PGM            4
EPROM.ECLK             3   External clock output bit
EPROM.E1ERA            2   EEPROM erase/programming bit
EPROM.E1LAT            1   EEPROM programming latch enable bit
EPROM.E1PGM            0   EEPROM charge pump enable/disable
ADDATA                0x0008    A/D data
ADSTAT                0x0009    A/D ststus/control
ADSTAT.COCO            7   Conversion complete flag 
ADSTAT.ADRC            6   A/D RC oscillator control
ADSTAT.ADON            5   A/D converter on         
ADSTAT.CH3             3   A/D channel 3            
ADSTAT.CH2             2   A/D channel 2            
ADSTAT.CH1             1   A/D channel 1            
ADSTAT.CH0             0   A/D channel 0            
PLMA                  0x000A    Pulse length modulation A
PLMB                  0x000B    Pulse length modulation B
Miscell               0x000C    Miscellaneous
Miscell.POR            7   Power-on reset bit
Miscell.INTP           6   External interrupt sensitivity options
Miscell.INTN           5   External interrupt sensitivity options
Miscell.INTE           4   External interrupt enable
Miscell.SFA            3   Slow or fast mode selection for PLMA  
Miscell.SFB            2   Slow or fast mode selection for PLMB  
Miscell.SM             1   Slow mode
Miscell.WDOG           0   Watchdog enable/disable
BAUD                  0x000D   SCI baud rate
BAUD.SPC1              7   Serial prescaler select bit 1       
BAUD.SPC0              6   Serial prescaler select bit 0       
BAUD.SCT2              5   SCI rate select bits (transmitter) 2
BAUD.SCT1              4   SCI rate select bits (transmitter) 1
BAUD.SCT0              3   SCI rate select bits (transmitter) 0
BAUD.SCR2              2   SCI rate select bits (receiver) 2   
BAUD.SCR1              1   SCI rate select bits (receiver) 1   
BAUD.SCR0              0   SCI rate select bits (receiver) 0   
SCCR1                 0x000E   SCI control 1
SCCR1.R8               7   Receive Data Bit 8            
SCCR1.T8               6   Transmit Data Bit 8           
SCCR1.M                4   Mode (Select Character Format)
SCCR1.WAKE             3   Wake Up by Address Mark/Idle  
SCCR1.CPOL             2
SCCR1.CPHA             1
SCCR1.LBCL             0
SCCR2                 0x000F    SCI control 2
SCCR2.TIE              7   Transmit interrupt enable         
SCCR2.TCIE             6   Transmit complete interrupt enable
SCCR2.RIE              5   Receiver interrupt enable         
SCCR2.ILIE             4   Idle line interrupt enable        
SCCR2.TE               3   Transmitter enable                
SCCR2.RE               2   Receiver enable                   
SCCR2.RWU              1   Receiver wake-up                  
SCCR2.SBK              0   Send break                        
SCSR                  0x0010    SCI status
SCSR.TDRE              7   Transmit data register empty flag
SCSR.TC                6   Transmit complete flag           
SCSR.RDRF              5   Receive data register full flag  
SCSR.IDLE              4   Idle line detected flag          
SCSR.OR                3   Overrun error flag               
SCSR.NF                2   Noise error flag                 
SCSR.FE                1   Framing error flag               
SCDR                  0x0011    SCI data
TCR                   0x0012    Timer control
TCR.ICIE               7   Input captures interrupt enable 
TCR.OCIE               6   Output compares interrupt enable
TCR.TOIE               5   Timer overflow interrupt enable 
TCR.FOLV2              4   Force output compare 2          
TCR.FOLV1              3   Force output compare 1          
TCR.OLV2               2   Output level 2                  
TCR.IEDG1              1   Input edge 1                    
TCR.OLVL1              0   Output level 1                  
TSR                   0x0013    Timer ststus
TSR.ICF1               7   Input capture flag 1      
TSR.OCF1               6   Output compare flag 1     
TSR.TOF                5   Timer overflow status flag
TSR.ICF2               4   Input capture flag 2      
TSR.OCF2               3   Output compare flag 2     
ICH1                  0x0014    Input capture high 1
ICL1                  0x0015    Input capture low 1
OCH1                  0x0016    Output compare high 1
OCL1                  0x0017    Output compare low 1
TCH                   0x0018    Timer counter high
TCL                   0x0019    Timer counter low
ACH                   0x001A    Alternate counter high
ACL                   0x001B    Alternate counter low
ICH2                  0x001C    Input campare high 2
ICL2                  0x001D    Input capture low 2
OCH2                  0x001E    Output compare high 2
OCL2                  0x001F    Output compare low 2
OPTR                  0x0100    Options
OPTR.EE1P              1   EEPROM protect bit
OPTR.SEC               0   Secure bit        
MOR                   0x3DFE    Mask option register
MOR.RTIM               4   Reset time
MOR.RWAT               3   Watchdog after reset
MOR.WWAT               2   Watchdog during WAIT mode
MOR.PBPD               1   Port B pull-down
MOR.PCPD               0   Port C pull-down


.68HC705B16N
; MC68HC05B6/D  http://
; MC68HC05B6.pdf

; RAM=352
; ROM=576
; EPROM=15K
; EEPROM=


; MEMORY MAP
area DATA FSR			0x0000:0x0020
area DATA EPROM_1		0x0020:0x0050
area DATA RAM_1			0x0050:0x0100
area DATA FSR_1			0x0100:0x0120
area DATA EEPROM		0x0120:0x0200
area DATA BOOT_ROM_1		0x0200:0x0250
area DATA RAM_2                 0x0250:0x0300
area DATA EPROM_2               0x0300:0x3DFE
area DATA BOOT_ROM_2		0x3DFE:0x3FF0
area DATA USER_VEC		0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0X3FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x3FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x3FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x3FF4      Timer overflow
interrupt SCI               0x3FF2      SCI


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2_ECLK         2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004    Port A data direction
DDRB                  0x0005    Port B data direction
DDRC                  0x0006    Port C data direction
EPROM                 0x0007    EPROM/EEPROM/ECLK control
EPROM.E6LAT            5
EPROM.E6PGM            4
EPROM.ECLK             3   External clock output bit          
EPROM.E1ERA            2   EEPROM erase/programming bit       
EPROM.E1LAT            1   EEPROM programming latch enable bit
EPROM.E1PGM            0   EEPROM charge pump enable/disable  
ADDATA                0x0008  A/D data
ADSTAT                0x0009  A/D ststus/control
ADSTAT.COCO            7   Conversion complete flag 
ADSTAT.ADRC            6   A/D RC oscillator control
ADSTAT.ADON            5   A/D converter on         
ADSTAT.CH3             3   A/D channel 3            
ADSTAT.CH2             2   A/D channel 2            
ADSTAT.CH1             1   A/D channel 1            
ADSTAT.CH0             0   A/D channel 0                        
PLMA                  0x000A  Pulse length modulation A
PLMB                  0x000B  Pulse length modulation B
Miscell               0x000C  Miscellaneous
Miscell.POR            7   Power-on reset bit                    
Miscell.INTP           6   External interrupt sensitivity options
Miscell.INTN           5   External interrupt sensitivity options
Miscell.INTE           4   External interrupt enable             
Miscell.SFA            3   Slow or fast mode selection for PLMA  
Miscell.SFB            2   Slow or fast mode selection for PLMB  
Miscell.SM             1   Slow mode                             
Miscell.WDOG           0   Watchdog enable/disable               
BAUD                  0x000D   SCI baud rate
BAUD.SPC1              7   Serial prescaler select bit 1       
BAUD.SPC0              6   Serial prescaler select bit 0       
BAUD.SCT2              5   SCI rate select bits (transmitter) 2
BAUD.SCT1              4   SCI rate select bits (transmitter) 1
BAUD.SCT0              3   SCI rate select bits (transmitter) 0
BAUD.SCR2              2   SCI rate select bits (receiver) 2   
BAUD.SCR1              1   SCI rate select bits (receiver) 1   
BAUD.SCR0              0   SCI rate select bits (receiver) 0   
SCCR1                 0x000E   SCI control 1
SCCR1.R8               7   Receive Data Bit 8            
SCCR1.T8               6   Transmit Data Bit 8           
SCCR1.M                4   Mode (Select Character Format)
SCCR1.WAKE             3   Wake Up by Address Mark/Idle  
SCCR1.CPOL             2
SCCR1.CPHA             1
SCCR1.LBCL             0
SCCR2                 0x000F    SCI control 2
SCCR2.TIE              7   Transmit interrupt enable         
SCCR2.TCIE             6   Transmit complete interrupt enable
SCCR2.RIE              5   Receiver interrupt enable         
SCCR2.ILIE             4   Idle line interrupt enable        
SCCR2.TE               3   Transmitter enable                
SCCR2.RE               2   Receiver enable                   
SCCR2.RWU              1   Receiver wake-up                  
SCCR2.SBK              0   Send break                        
SCSR                  0x0010    SCI status
SCSR.TDRE              7   Transmit data register empty flag
SCSR.TC                6   Transmit complete flag           
SCSR.RDRF              5   Receive data register full flag  
SCSR.IDLE              4   Idle line detected flag          
SCSR.OR                3   Overrun error flag               
SCSR.NF                2   Noise error flag                 
SCSR.FE                1   Framing error flag               
SCDR                  0x0011    SCI data
TCR                   0x0012    Timer control
TCR.ICIE               7   Input captures interrupt enable 
TCR.OCIE               6   Output compares interrupt enable
TCR.TOIE               5   Timer overflow interrupt enable 
TCR.FOLV2              4   Force output compare 2          
TCR.FOLV1              3   Force output compare 1          
TCR.OLV2               2   Output level 2                  
TCR.IEDG1              1   Input edge 1                    
TCR.OLVL1              0   Output level 1                  
TSR                   0x0013    Timer status
TSR.ICF1               7   Input capture flag 1      
TSR.OCF1               6   Output compare flag 1     
TSR.TOF                5   Timer overflow status flag
TSR.ICF2               4   Input capture flag 2      
TSR.OCF2               3   Output compare flag 2     
ICH1                  0x0014    Input capture high 1
ICL1                  0x0015    Input capture low 1
OCH1                  0x0016    Output compare high 1
OCL1                  0x0017    Output compare low 1
TCH                   0x0018    Timer counter high
TCL                   0x0019    Timer counter low
ACH                   0x001A    Alternate counter high
ACL                   0x001B    Alternate counter low
ICH2                  0x001C   Input campare high 2
ICL2                  0x001D   Input capture low 2
OCH2                  0x001E   Output compare high 2
OCL2                  0x001F   Output compare low 2
OPTR                  0x0100   Options
OPTR.EE1P              1   EEPROM protect bit
OPTR.SEC               0   Secure bit        
MOR                   0x3DFE    Mask option register
MOR.RTIM               4   Reset time               
MOR.RWAT               3   Watchdog after reset     
MOR.WWAT               2   Watchdog during WAIT mode
MOR.PBPD               1   Port B pull-down         
MOR.PCPD               0   Port C pull-down         
RESERV3FF0            0x3FF0    RESERVED
RESERV3FF1            0x3FF1    RESERVED


.68HC705B32
; MC68HC05B6/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705B32&nodeId=01M98633
; 6805b6r4.pdf

; RAM=528
; ROM=0
; EPROM=32K
; EEPROM=256


; MEMORY MAP
area DATA FSR           0x0000:0x0020
area BSS  RESERVED      0x0020:0x0050
area DATA RAM_U1        0x0050:0x0100
area DATA EEPROM        0x0100:0x0200
area DATA BootROM_U1    0x0200:0x0250
area DATA RAM_U2        0x0250:0x03B0
area DATA BootROM_U2    0x03B0:0x0400
area DATA _EPROM_       0x0400:0x7E00
area DATA BootROM_U3    0x7E00:0x7FDF
area BSS  RESERVED      0x7FDF:0x7FE0
area DATA BootROM_U4    0x7FE0:0x7FF0
area DATA USER_VEC      0x7FF0:0x8000


; Interrupt and reset vector assignments
interrupt __RESET           0x7FFE      Processor reset
interrupt SWI               0x7FFC      Software interrupt
interrupt IRQ               0x7FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x7FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x7FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x7FF4      Timer overflow
interrupt SCI               0x7FF2      SCI0


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2_ECLK         2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004   Port A data direction
DDRB                  0x0005   Port B data direction
DDRC                  0x0006   Port C data direction
EPROM                 0x0007   EPROM/EEPROM/ECLK control
EPROM.E6LAT            5
EPROM.E6PGM            4
EPROM.ECLK             3   External clock output bit          
EPROM.E1ERA            2   EEPROM erase/programming bit       
EPROM.E1LAT            1   EEPROM programming latch enable bit
EPROM.E1PGM            0   EEPROM charge pump enable/disable  
ADDATA                0x0008   A/D data
ADSTAT                0x0009   A/D ststus/control
ADSTAT.COCO            7   Conversion complete flag 
ADSTAT.ADRC            6   A/D RC oscillator control
ADSTAT.ADON            5   A/D converter on         
ADSTAT.CH3             3   A/D channel 3            
ADSTAT.CH2             2   A/D channel 2            
ADSTAT.CH1             1   A/D channel 1            
ADSTAT.CH0             0   A/D channel 0                        
PLMA                  0x000A   Pulse length modulation A
PLMB                  0x000B   Pulse length modulation B
Miscell               0x000C   Miscellaneous
Miscell.POR            7   Power-on reset bit                    
Miscell.INTP           6   External interrupt sensitivity options
Miscell.INTN           5   External interrupt sensitivity options
Miscell.INTE           4   External interrupt enable             
Miscell.SFA            3   Slow or fast mode selection for PLMA  
Miscell.SFB            2   Slow or fast mode selection for PLMB  
Miscell.SM             1   Slow mode                             
Miscell.WDOG           0   Watchdog enable/disable               
BAUD                  0x000D   SCI baud rate
BAUD.SPC1              7   Serial prescaler select bit 1       
BAUD.SPC0              6   Serial prescaler select bit 0       
BAUD.SCT2              5   SCI rate select bits (transmitter) 2
BAUD.SCT1              4   SCI rate select bits (transmitter) 1
BAUD.SCT0              3   SCI rate select bits (transmitter) 0
BAUD.SCR2              2   SCI rate select bits (receiver) 2   
BAUD.SCR1              1   SCI rate select bits (receiver) 1   
BAUD.SCR0              0   SCI rate select bits (receiver) 0   
SCCR1                 0x000E   SCI control 1
SCCR1.R8               7   Receive Data Bit 8            
SCCR1.T8               6   Transmit Data Bit 8           
SCCR1.M                4   Mode (Select Character Format)
SCCR1.WAKE             3   Wake Up by Address Mark/Idle  
SCCR1.CPOL             2
SCCR1.CPHA             1
SCCR1.LBCL             0
SCCR2                 0x000F   SCI control 2
SCCR2.TIE              7   Transmit interrupt enable         
SCCR2.TCIE             6   Transmit complete interrupt enable
SCCR2.RIE              5   Receiver interrupt enable         
SCCR2.ILIE             4   Idle line interrupt enable        
SCCR2.TE               3   Transmitter enable                
SCCR2.RE               2   Receiver enable                   
SCCR2.RWU              1   Receiver wake-up                  
SCCR2.SBK              0   Send break                        
SCSR                  0x0010   SCI status
SCSR.TDRE              7   Transmit data register empty flag
SCSR.TC                6   Transmit complete flag           
SCSR.RDRF              5   Receive data register full flag  
SCSR.IDLE              4   Idle line detected flag          
SCSR.OR                3   Overrun error flag               
SCSR.NF                2   Noise error flag                 
SCSR.FE                1   Framing error flag               
SCDR                  0x0011   SCI data
TCR                   0x0012   Timer control
TCR.ICIE               7   Input captures interrupt enable 
TCR.OCIE               6   Output compares interrupt enable
TCR.TOIE               5   Timer overflow interrupt enable 
TCR.FOLV2              4   Force output compare 2          
TCR.FOLV1              3   Force output compare 1          
TCR.OLV2               2   Output level 2                  
TCR.IEDG1              1   Input edge 1                    
TCR.OLVL1              0   Output level 1                  
TSR                   0x0013   Timer ststus
TSR.ICF1               7   Input capture flag 1      
TSR.OCF1               6   Output compare flag 1     
TSR.TOF                5   Timer overflow status flag
TSR.ICF2               4   Input capture flag 2      
TSR.OCF2               3   Output compare flag 2     
ICH1                  0x0014   Input capture high 1
ICL1                  0x0015   Input capture low 1
OCH1                  0x0016   Output compare high 1
OCL1                  0x0017   Output compare low 1
TCH                   0x0018   Timer counter high
TCL                   0x0019   Timer counter low
ACH                   0x001A   Alternate counter high
ACL                   0x001B   Alternate counter low
ICH2                  0x001C   Input campare high 2
ICL2                  0x001D   Input capture low 2
OCH2                  0x001E   Output compare high 2
OCL2                  0x001F   Output compare low 2
OPTR                  0x0100   Options
OPTR.EE1P              1   EEPROM protect bit
OPTR.SEC               0   Secure bit        
MOR                   0x7FDE   Mask option register
MOR.RTIM               4   Reset time               
MOR.RWAT               3   Watchdog after reset     
MOR.WWAT               2   Watchdog during WAIT mode
MOR.PBPD               1   Port B pull-down         
MOR.PCPD               0   Port C pull-down         
RESERV7FF0            0x7FF0    RESERVED
RESERV7FF1            0x7FF1    RESERVED


.68HC705BS8
; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC05BS8.pdf
; MC68HC05BS8Dnew.pdf

; RAM=228
; ROM=10K
; EPROM=10K
; EEPROM=512


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area DATA RAM         0x0040:0x0140
area BSS  UNUSED      0x0140:0x0200
area DATA _EEPROM_    0x0200:0x0400
area BSS  UNUSED      0x0400:0x1600
area DATA BootROM     0x1600:0x1800
area DATA EPROM       0x1800:0x3FE0
area DATA BOOT_VEC    0x3FE0:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      ...
interrupt VSYNC             0x3FF8
interrupt TIMER             0x3FF6
interrupt CTIMER            0x3FF4
interrupt M_BUS             0x3FF2
interrupt KEYBOARD          0x3FF0


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0        
UNUSED03              0x0003    UNUSED
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006    Port C data direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
EEPROM                0x0007    EEPROM control
EEPROM.EEOSC           4   EEPROM Charge Pump Oscillator Enable
EEPROM.EER1            3   EEPROM Erase Mode Select Bits 1
EEPROM.EER0            2   EEPROM Erase Mode Select Bits 0
EEPROM.EELAT           1   EEPROM Programming Latch Control
EEPROM.EEPGM           0   EEPROM Programming Power Enable
CTCSR                 0x0008    CTimer control and Status Register
CTCSR.CTOF             7   Timer Overflow
CTCSR.RTIF             6   Real Time Interrupt Flag
CTCSR.CTOFE            5   CTimer Overflow Interrupt Enable
CTCSR.RTIE             4   Real Time Interrupt Enable
CTCSR.RT1              1   Rate Select for COP watchdog and RTI 1
CTCSR.RT0              0   Rate Select for COP watchdog and RTI 0
CTCR                  0x0009    CTimer Counter Register
CTCR.CT7               7
CTCR.CT6               6
CTCR.CT5               5
CTCR.CT4               4
CTCR.CT3               3
CTCR.CT2               2
CTCR.CT1               1
CTCR.CT0               0
SSCSR                 0x000A    Sync signal control and status
SSCSR.VPOL             7   Vertical Sync Input Polarity
SSCSR.HPOL             6   Horizontal Sync Input Polarity
SSCSR.VDET             5   Vertical Sync Signal Detect
SSCSR.HDET             4   Horizontal Sync Signal Detect
SSCSR.SOUT             3   Sync Output Select
SSCSR.INSRT            2   Hsync Insertion
SSCSR.SIN1             1   Sync Input Source 1
SSCSR.SIN0             0   Sync Input Source 0
VFREG                 0x000B    Vfreg
VFREG.VF7              7
VFREG.VF6              6
VFREG.VF5              5
VFREG.VF4              4
VFREG.VF3              3
VFREG.VF2              2
VFREG.VF1              1
VFREG.VF0              0
LFH                   0x000C    Line frequency high
LFH.VF8                7
LFH.LF11               3
LFH.LF10               2
LFH.LF9                1
LFH.LF8                0
LFL                   0x000D    Line frequency low
LFL.LF7                7
LFL.LF6                6
LFL.LF5                5
LFL.LF4                4
LFL.LF3                3
LFL.LF2                2
LFL.LF1                1
LFL.LF0                0
ILC                   0x000E    Interrupt line counter
ILC.VSIE               7   Vsync Interrupt Enable
ILC.LC6                6   Line Count for Vsync Interrupt 6
ILC.LC5                5   Line Count for Vsync Interrupt 5
ILC.LC4                4   Line Count for Vsync Interrupt 4
ILC.LC3                3   Line Count for Vsync Interrupt 3
ILC.LC2                2   Line Count for Vsync Interrupt 2
ILC.LC1                1   Line Count for Vsync Interrupt 1
ILC.LC0                0   Line Count for Vsync Interrupt 0
SP                    0x000F    Sampling pulse
SP.SP6                 6
SP.SP5                 5
SP.SP4                 4
SP.SP3                 3
SP.SP2                 2
SP.SP1                 1
SP.SP0                 0
GPWM                  0x0010    General PWM
GPWM.ODE               7   Open Drain Enable
GPWM.CRE               6   Clear Reset Enable
GPWM.GPW5              5   GPW Data 5
GPWM.GPW4              4   GPW Data 4
GPWM.GPW3              3   GPW Data 3
GPWM.GPW2              2   GPW Data 2
GPWM.GPW1              1   GPW Data 1
GPWM.GPW0              0   GPW Data 0
RSPWM                 0x0011    Raster Positioning Pulse Width Modulator Register
RSPWM.RSP              7   Raster Polarity
RSPWM.RSPW6            6   RSPWM Data 6
RSPWM.RSPW5            5   RSPWM Data 5
RSPWM.RSPW4            4   RSPWM Data 4
RSPWM.RSPW3            3   RSPWM Data 3
RSPWM.RSPW2            2   RSPWM Data 2
RSPWM.RSPW1            1   RSPWM Data 1
RSPWM.RSPW0            0   RSPWM Data 0
TCR                   0x0012    Timer control
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.IEDG               1   Input Edge
TCR.OLVL               0   Output Level Voltage Latch
TSR                   0x0013    Timer status
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICH                   0x0014    Input capture high
ICH.IC15               7
ICH.IC14               6
ICH.IC13               5
ICH.IC12               4
ICH.IC11               3
ICH.IC10               2
ICH.IC9                1
ICH.IC8                0
ICL                   0x0015    Input capture low
ICL.IC7                7
ICL.IC6                6
ICL.IC5                5
ICL.IC4                4
ICL.IC3                3
ICL.IC2                2
ICL.IC1                1
ICL.IC0                0
OCH                   0x0016    Output compare high
OCH.OC15               7
OCH.OC14               6
OCH.OC13               5
OCH.OC12               4
OCH.OC11               3
OCH.OC10               2
OCH.OC9                1
OCH.OC8                0
OCL                   0x0017    Output compare low
OCL.OC7                7
OCL.OC6                6 
OCL.OC5                5 
OCL.OC4                4
OCL.OC3                3
OCL.OC2                2
OCL.OC1                1
OCL.OC0                0
CH                    0x0018    Counter high
CH.TC15                7
CH.TC14                6
CH.TC13                5
CH.TC12                4
CH.TC11                3
CH.TC10                2
CH.TC9                 1
CH.TC8                 0
CL                    0x0019    Counter low
CL.TC7                 7
CL.TC6                 6
CL.TC5                 5
CL.TC4                 4
CL.TC3                 3
CL.TC2                 2
CL.TC1                 1
CL.TC0                 0
ACH                   0x001A    Alternate counter high
ACH.AC15               7
ACH.AC14               6
ACH.AC13               5 
ACH.AC12               4
ACH.AC11               3
ACH.AC10               2
ACH.AC9                1
ACH.AC8                0
ACL                   0x001B    Alternate counter low
ACL.AC7                7
ACL.AC6                6
ACL.AC5                5
ACL.AC4                4
ACL.AC3                3
ACL.AC2                2
ACL.AC1                1
ACL.AC0                0
EPROG                 0x001C    EPROM programming control
EPROG.ELAT             1   EPROM Latch Control
EPROG.PGM              0   EPROM Program Command
OPTION                0x001D    Option
OPTION.INTO            7
OPTION.COP             6
KI                    0x001E    Keyboard interrupt
KI.KBIC                6
KI.KBE5                5 
KI.KBE4                4
KI.KBE3                3
KI.KBE2                2
KI.KBE1                1
KI.KBE0                0
UNUSED1F              0x001F    UNUSED
UNUSED20              0x0020    UNUSED
UNUSED21              0x0021    UNUSED
UNUSED22              0x0022    UNUSED
UNUSED23              0x0023    UNUSED
UNUSED24              0x0024    UNUSED
UNUSED25              0x0025    UNUSED
UNUSED26              0x0026    UNUSED
UNUSED27              0x0027    UNUSED
UNUSED28              0x0028    UNUSED
UNUSED29              0x0029    UNUSED
UNUSED2A              0x002A    UNUSED
UNUSED2B              0x002B    UNUSED
UNUSED2C              0x002C    UNUSED
UNUSED2D              0x002D    UNUSED
UNUSED2E              0x002E    UNUSED
UNUSED2F              0x002F    UNUSED
UNUSED30              0x0030    UNUSED
UNUSED31              0x0031    UNUSED
UNUSED32              0x0032    UNUSED
UNUSED33              0x0033    UNUSED
UNUSED34              0x0034    UNUSED
UNUSED35              0x0035    UNUSED
UNUSED36              0x0036    UNUSED
UNUSED37              0x0037    UNUSED
UNUSED38              0x0038    UNUSED
MADR                  0x0039    M-Bus address
MADR.MAD7              7
MADR.MAD6              6
MADR.MAD5              5
MADR.MAD4              4
MADR.MAD3              3
MADR.MAD2              2
MADR.MAD1              1
MFDR                  0x003A    M-Bus frequency divider
MFDR.FD4               4
MFDR.FD3               3
MFDR.FD2               2
MFDR.FD1               1
MFDR.FD0               0
MCR                   0x003B    M-Bus control
MCR.MEN                7   M-Bus Enable
MCR.MIEN               6   M-Bus Interrupt Enable
MCR.MSTA               5   Master/Slave Select
MCR.MTX                4   Transmit/Receive Mode Select
MCR.TXAK               3   Acknowledge Enable
MCR.SIFC               1   Software M-Bus Interrupt Flag Clear
MCR.SIIC               0   Software M-Bus Enable
MSR                   0x003C    M-Bus status
MSR.MCF                7   Data Transfer Complete
MSR.MASS               6   Addressed as Slave
MSR.MBB                5   Bus Busy
MSR.MAL                4   Arbitration Lost
MSR.SIF                3   Software Supported M-Bus Interrupt Flag
MSR.SRW                2   Slave R/W Select
MSR.MIF                1   M-Bus Interrupt
MSR.RXAK               0   Receive Acknowledge
MDR                   0x003D    M-Bus data
MDR.MD7                7
MDR.MD6                6
MDR.MD5                5
MDR.MD4                4
MDR.MD3                3
MDR.MD2                2
MDR.MD1                1
MDR.MD0                0
UNUSED3E              0x003E    UNUSED
UNUSED3F              0x003F    UNUSED
EEPROM_OPT            0x0200    EEPROM options
EEPROM_OPT.EEPRT       1   EEPROM Protect
EEPROM_OPT.LVR         0   Low Voltage Reset


.68HC705C4A
; MC68HC705C4A/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC705C4A.pdf
; MC68HC705C4A.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR        0x0000:0x0020
area DATA ROM_1      0x0020:0x0050
area DATA RAM        0x0050:0x0100
area DATA ROM_2      0x0100:0x1100
area BSS  UNUSED     0x1100:0x1F00
area DATA BootROM    0x1F00:0x1FF0
area DATA USER_VEC   0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      Software       
interrupt IRQ               0x1FFA      External Interrupt
interrupt Timer             0x1FF8      Timer_In_Out
interrupt SCI               0x1FF6      SCI
interrupt SPI               0x1FF4      SPI


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data Register
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data Register
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data Register
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Fixed Input Register
PORTD.PD7              7
PORTD.SS               5
PORTD.SCK              4
PORTD.MOSI             3
PORTD.MISO             2
PORTD.TDO              1
PORTD.RDI              0
DDRA                  0x0004     Port A Data Direction Register
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction Register
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction Register
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
RESERV0007            0x0007     RESERVED
RESERV0008            0x0008     RESERVED
RESERV0009            0x0009     RESERVED
SPCR                  0x000A     SPI Control Register
SPCR.SPIE              7   SPI Interrupt Enable Bit
SPCR.SPE               6   SPI Enable Bit
SPCR.MSTR              4   Master Bit
SPCR.CPOL              3   Clock Polarity Bit
SPCR.CPHA              2   Clock Phase Bit
SPCR.SPR1              1   SPI Clock Rate Bits 1
SPCR.SPR0              0   SPI Clock Rate Bits 0
SPSR                  0x000B     SPI Status Register
SPSR.SPIF              7   SPI Flag
SPSR.WCOL              6   Write Collision Bit
SPSR.MODF              4   Mode Fault Bit
SPDR                  0x000C     SPI Data Register
Baud                  0x000D     Baud Rate Register
Baud.SCP1              5   SCI Prescaler Select Bit 1
Baud.SCP0              4   SCI Prescaler Select Bit 0
Baud.SCR2              2   SCI Baud Rate Select Bit 2
Baud.SCR1              1   SCI Baud Rate Select Bit 1
Baud.SCR0              0   SCI Baud Rate Select Bit 0
SCCR1                 0x000E     SCI Control Register 1
SCCR1.R8               7   Bit 8 (Received)
SCCR1.T8               6   Bit 8 (Transmitted)
SCCR1.M                4   Character Length Bit
SCCR1.WAKE             3   Wakeup Bit
SCCR2                 0x000F     SCI Control Register 2
SCCR2.TIE              7   Transmit Interrupt Enable Bit
SCCR2.TCIE             6   Transmission Complete Interrupt Enable Bit
SCCR2.RIE              5   Receive Interrupt Enable Bit
SCCR2.ILIE             4   Idle Line Interrupt Enable Bit
SCCR2.TE               3   Transmit Enable Bit
SCCR2.RE               2   Receive Enable Bit
SCCR2.RWU              1   Receiver Wakeup Enable Bit
SCCR2.SBK              0   Send Break Bit
SCSR                  0x0010     SCI Status Register
SCSR.TDRE              7   Transmit Data Register Empty Bit
SCSR.TC                6   Transmission Complete Bit
SCSR.RDRF              5   Receive Data Register Full Bit
SCSR.IDLE              4   Receiver Idle Bit
SCSR.OR                3   Receiver Overrun Bit
SCSR.NF                2   Receiver Noise Flag
SCSR.FE                1   Receiver Framing Error Bit
SCDR                  0x0011     SCI Data Register
TCR                   0x0012     Timer Control Register
TCR.ICIE               7   Input Capture Interrupt Enable Bit
TCR.OCIE               6   Output Compare Interrupt Enable Bit
TCR.TOIE               5   Timer Overflow Interrupt Enable Bit
TCR.IEDG               1   Input Edge Bit
TCR.OLVL               0   Output Level Bit
TSR                   0x0013     Timer Status Register
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICRH                  0x0014     Input Capture Register High
ICRL                  0x0015     Input Capture Register Low
OCRH                  0x0016     Output Compare Register High
OCRL                  0x0017     Output Compare Register Low
TRH                   0x0018     Timer Register High
TRL                   0x0019     Timer Register Low
ATRH                  0x001A     Alternate Timer Register High
ATRL                  0x001B     Alternate Timer Register Low
PROG                  0x001C     EPROM Programming Register
PROG.LAT               2   Latch Enable Bit
PROG.PGM               0   Program Bit
RESERV001D            0x001D     RESERVED
RESERV001E            0x001E     RESERVED
RESERV001F            0x001F     RESERVED
Option                0x1FDF     Option Register
Option.SEC             3   Security Bit
Option.IRQ             1   Interrupt Request Pin Sensitivity Bit
MOR1                  0x1FF0     Mask Option Register 1
MOR1.PBPU7             7   Port B Pullup Enable Bit 7
MOR1.PBPU6             6   Port B Pullup Enable Bit 6
MOR1.PBPU5             5   Port B Pullup Enable Bit 5
MOR1.PBPU4             4   Port B Pullup Enable Bit 4
MOR1.PBPU3             3   Port B Pullup Enable Bit 3
MOR1.PBPU2             2   Port B Pullup Enable Bit 2
MOR1.PBPU1             1   Port B Pullup Enable Bit 1
MOR1.PBPU0_COPC        0   Port B Pullup Enable Bit 0
MOR2                  0x1FF1     Mask Option Register 2
MOR2.NCOPE             0   Non-Programmable COP Watchdog Enable Bit
RESERV1FF2            0x1FF2    RESERVED
RESERV1FF3            0x1FF3    RESERVED


.68HC705C8A
; MC68HC705C8A/D   http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705C8A&nodeId=01M98633
; MC68HC705C8A.pdf

; RAM=304
; ROM=0K
; EPROM=8K
; EEPROM=0


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA RAM_PROM	0x0020:0x0050
area DATA RAM		0x0050:0x0100
area DATA PROM_RAM	0x0100:0x0160
area DATA PROM		0x0160:0x1F00
area DATA BOOT_ROM_1	0x1F00:0x1FDF
area DATA OPTION	0x1FDF:0x1FE0
area DATA BOOT_ROM_2	0x1FE0:0x1FF0
area DATA FSR_1		0x1FF0:0x1FF2
area DATA USER_VEC	0x1FF2:0x2000


; Interrupt and reset vector assignments
interrupt __RESET 	0x1FFE       Reset 
interrupt SWI 		0x1FFC       Software interrupt
interrupt IRQ 		0x1FFA       External interrupt
interrupt TIMER 	0x1FF8       Timer interrupts
interrupt SCI 		0x1FF6       SCI interrupts
interrupt SPI 		0x1FF4       SPI interrupts


; INPUT/ OUTPUT PORTS
PORTA		0x0000		Port A Data Register
PORTA.PA7         7  Port A Data Bits 7
PORTA.PA6         6  Port A Data Bits 6
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB		0x0001		Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
PORTC		0x0002		Port C Data Register
PORTC.PC7         7  Port C Data Bits 7
PORTC.PC6         6  Port C Data Bits 6
PORTC.PC5         5  Port C Data Bits 5
PORTC.PC4         4  Port C Data Bits 4
PORTC.PC3         3  Port C Data Bits 3
PORTC.PC2         2  Port C Data Bits 2
PORTC.PC1         1  Port C Data Bits 1
PORTC.PC0         0  Port C Data Bits 0
PORTD		0x0003		Port D Fixed Input Register
PORTD.PD7         7
PORTD.SS          5
PORTD.SCK         4
PORTD.MOSI        3
PORTD.MISO        2
PORTD.TDO         1
PORTD.RDI         0
DDRA		0x0004 		Port A Data Direction Register
DDRA.DDRA7        7  Data Direction for Port A Bit 7
DDRA.DDRA6        6  Data Direction for Port A Bit 6
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB		0x0005 		Port B Data Direction Register
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
DDRC		0x0006		Port C Data Direction
DDRC.DDRC7        7  Data Direction for Port C Bit 7
DDRC.DDRC6        6  Data Direction for Port C Bit 6
DDRC.DDRC5        5  Data Direction for Port C Bit 5
DDRC.DDRC4        4  Data Direction for Port C Bit 4
DDRC.DDRC3        3  Data Direction for Port C Bit 3
DDRC.DDRC2        2  Data Direction for Port C Bit 2
DDRC.DDRC1        1  Data Direction for Port C Bit 1
DDRC.DDRC0        0  Data Direction for Port C Bit 0
RESERV0007      0x0007          RESERVED
RESERV0008      0x0008          RESERVED
RESERV0009      0x0009          RESERVED
SPCR		0x000A		SPI Control Register
SPCR.SPIE         7  SPI Interrupt Enable Bit
SPCR.SPE          6  SPI Enable Bit
SPCR.MSTR         4  Master Bit
SPCR.CPOL         3  Clock Polarity Bit
SPCR.CPHA         2  Clock Phase Bit
SPCR.SPR1         1  SPI Clock Rate Bits 1
SPCR.SPR0         0  SPI Clock Rate Bits 0
SPSR		0x000B		SPI Status Register
SPSR.SPIF         7  SPI Flag
SPSR.WCOL         6  Write Collision Bit
SPSR.MODF         4  Mode Fault Bit
SPDR		0x000C		SPI Data Register
Baud		0x000D		Baud Rate Register
Baud.SCP1         5  SCI Prescaler Select Bit 1
Baud.SCP0         4  SCI Prescaler Select Bit 0
Baud.SCR2         2  SCI Baud Rate Select Bit 2
Baud.SCR1         1  SCI Baud Rate Select Bit 1
Baud.SCR0         0  SCI Baud Rate Select Bit 0
SCCR1		0x000E		SCI Control Register 1
SCCR1.R8          7  Bit 8 (Received)
SCCR1.T8          6  Bit 8 (Transmitted)
SCCR1.M           4  Character Length Bit
SCCR1.WAKE        3  Wakeup Bit
SCCR2		0x000F		SCI Control Register 2
SCCR2.TIE         7  Transmit Interrupt Enable Bit
SCCR2.TCIE        6  Transmission Complete Interrupt Enable Bit
SCCR2.RIE         5  Receive Interrupt Enable Bit
SCCR2.ILIE        4  Idle Line Interrupt Enable Bit
SCCR2.TE          3  Transmit Enable Bit
SCCR2.RE          2  Receive Enable Bit
SCCR2.RWU         1  Receiver Wakeup Enable Bit
SCCR2.SBK         0  Send Break Bit
SCSR		0x0010		SCI Status Register
SCSR.TDRE         7  Transmit Data Register Empty Bit
SCSR.TC           6  Transmission Complete Bit
SCSR.RDRF         5  Receive Data Register Full Bit
SCSR.IDLE         4  Receiver Idle Bit
SCSR.OR           3  Receiver Overrun Bit
SCSR.NF           2  Receiver Noise Flag Bit
SCSR.FE           1  Receiver Framing Error Bit
SCDR		0x0011		SCI Data Register
TCR		0x0012		Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable Bit
TCR.IEDG          1  Input Edge Bit
TCR.OLVL          0  Output Level Bit
TSR		0x0013		Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Flag
TSR.TOF           5  Timer Overflow Flag
ICRH		0x0014 		Input Capture Register High
ICRL		0x0015 		Input Capture Register Low
OCRH		0x0016 		Output Compare Register  High
OCRL		0x0017 		Output Compare Register Low
TRH		0x0018		Timer Register High
TRL		0x0019		Timer Register Low
ATRH		0x001A 		Alternate Timer Register High
ATRL		0x001B 		Alternate Timer Register Low
PROG		0x001C 		EPROM Programming Register
PROG.LAT          2  Latch Enable Bit
PROG.PGM          0  Program Bit
COPRST		0x001D 		Programmable COP Reset Register
COPCR		0x001E 		Programmable COP Control Register
COPCR.COPF        4  COP Flag
COPCR.CME         3  Clock Monitor Enable Bit
COPCR.PCOPE       2  Programmable COP Enable Bit
COPCR.CM1         1  COP Mode Bits 1
COPCR.CM0         0  COP Mode Bits 0
RESERV001F      0x001F          RESERVED
Option		0x1FDF		Option Register
Option.RAM0       7  Random-Access Memory Control Bit 0
Option.RAM1       6  Random-Access Memory Control Bit 1
Option.SEC        3  Security Bit
Option.IRQ        1  Interrupt Request Pin Sensitivity Bit
MOR1		0x1FF0		Mask Option Register 1
MOR1.PBPU7        7  Port B Pullup Enable Bit 7
MOR1.PBPU6        6  Port B Pullup Enable Bit 6
MOR1.PBPU5        5  Port B Pullup Enable Bit 5
MOR1.PBPU4        4  Port B Pullup Enable Bit 4
MOR1.PBPU3        3  Port B Pullup Enable Bit 3
MOR1.PBPU2        2  Port B Pullup Enable Bit 2
MOR1.PBPU1        1  Port B Pullup Enable Bit 1
MOR1.PBPU0_COPC   0  Port B Pullup Enable Bit 0
MOR2		0x1FF1		Mask Option Register 2
MOR2.NCOPE        0  Non-Programmable COP Watchdog Enable Bit
RESERV1FF2      0x1FF2          RESERVED
RESERV1FF3      0x1FF3          RESERVED


.68HC705C9A
; 68HC705C9A  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705C9A&nodeId=01M98633
; MC68HC705C9A.pdf

; RAM=352
; ROM=0K
; EPROM=16K
; EEPROM=0


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA EPROM_RAM_0	0x0020:0x0050
area DATA RAM		0x0050:0x0100
area DATA EPROM_RAM_1	0x0100:0x0180
area DATA EPROM		0x0180:0x3F00
area DATA BOOT_ROM	0x3F00:0x3FF0
area DATA USER_VEC	0x3FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Reset  
interrupt SWI               0x3FFC      Software       
interrupt IRQ               0x3FFA      External Interrupt
interrupt Timer             0x3FF8      Timer_In_Out
interrupt SCI               0x3FF6      SCI
interrupt SPI               0x3FF4      SPI


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data Register
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data Register
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data Register
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Data Register
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     Port A Data Direction Register
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction Register
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction Register
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
DDRD                  0x0007     Port D Data Direction Register C9A Only
DDRD.DDRC7             7   Data Direction for Port D Bit 7
DDRD.DDRC5             5   Data Direction for Port D Bit 5
DDRD.DDRC4             4   Data Direction for Port D Bit 4
DDRD.DDRC3             3   Data Direction for Port D Bit 3
DDRD.DDRC2             2   Data Direction for Port D Bit 2
DDRD.DDRC1             1   Data Direction for Port D Bit 1
DDRD.DDRC0             0   Data Direction for Port D Bit 0
UNUSED0008            0x0008    UNUSED
UNUSED0009            0x0009    UNUSED
SPCR                  0x000A     SPI Control Register
SPCR.SPIE              7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE               6   Serial Peripheral System Enable Bit
SPCR.DWOM              5   Port D Wire-OR Mode Option Bit
SPCR.MSTR              4   Master Mode Select Bit
SPCR.CPOL              3   Clock Polarity Bit
SPCR.CPHA              2   Clock Phase Bit
SPCR.SPR1              1   SPI Clock Rate Selects 1
SPCR.SPR0              0   SPI Clock Rate Selects 0
SPSR                  0x000B     SPI Status Register
SPSR.SPIF              7   SPI Transfer Complete Flag
SPSR.WCOL              6   Write Collision Bit
SPSR.MODF              4   Mode Fault
SPDR                  0x000C     SPI Data Register
SPDR.SPD7              7
SPDR.SPD6              6
SPDR.SPD5              5
SPDR.SPD4              4
SPDR.SPD3              3
SPDR.SPD2              2
SPDR.SPD1              1
SPDR.SPD0              0
BAUD                  0x000D     SCI Baud Rate Register
BAUD.SCP1              5   SCI Prescaler Select Bit 1
BAUD.SCP0              4   SCI Prescaler Select Bit 0
BAUD.SCR2              2   SCI Baud Rate Select Bit 2
BAUD.SCR1              1   SCI Baud Rate Select Bit 1
BAUD.SCR0              0   SCI Baud Rate Select Bit 0
SCCR1                 0x000E     SCI Control Register 1
SCCR1.R8               7   Bit 8 (Received)
SCCR1.T8               6   Bit 8 (Transmitted)
SCCR1.M                4   Character Length Bit
SCCR1.WAKE             3   Wakeup Method Bit
SCCR2                 0x000F     SCI Control Register 2
SCCR2.TIE              7   Transmit Interrupt Enable Bit
SCCR2.TCIE             6   Transmission Complete Interrupt Enable Bit
SCCR2.RIE              5   Receiver Interrupt Enable Bit
SCCR2.ILIE             4   Idle Line Interrupt Enable Bit
SCCR2.TE               3   Transmitter Enable Bit
SCCR2.RE               2   Receiver Enable Bit
SCCR2.RWU              1   Receiver Wakeup Enable Bit
SCCR2.SBK              0   Send Break Bit
SCSR                  0x0010     SCI Status Register
SCSR.TDRE              7   Transmit Data Register Empty Flag
SCSR.TC                6   Transmission Complete Flag
SCSR.RDRF              5   Receive Data Register Full Flag
SCSR.IDLE              4   Receiver Idle Flag
SCSR.OR                3   Receiver Overrun Flag
SCSR.NF                2   Receiver Noise Flag
SCSR.FE                1   Receiver Framing Error Flag
SCDR                  0x0011     SCI Data Register
SCDR.SCD7              7
SCDR.SDC6              6
SCDR.SCD5              5
SCDR.SCD4              4
SCDR.SCD3              3
SCDR.SCD2              2
SCDR.SCD1              1
SCDR.SCD0              0
TCR                   0x0012     Timer Control Register
TCR.ICIE               7   Input Capture Interrupt Enable Bit
TCR.OCIE               6   Output Compare Interrupt Enable Bit
TCR.TOIE               5   Timer Overflow Interrupt Enable Bit
TCR.IEDG               1   Input Edge Bit
TCR.OLVL               0   Output Level Bit
TSR                   0x0013     Timer Status Register
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICRH                  0x0014     Input Capture Register High
ICRL                  0x0015     Input Capture Register Low
OCRH                  0x0016     Output Compare Register High
OCRL                  0x0017     Output Compare Register Low
TRH                   0x0018     Timer Register High
TRL                   0x0019     Timer Register Low
ATRH                  0x001A     Alternate Timer Register High
ATRL                  0x001B     Alternate Timer Register Low
EPR                   0x001C     EPROM Programming Register
EPR.LATCH              2
EPR.EPGM               0
COPRST                0x001D     COP Reset Register C9A Only
COPCR                 0x001E     COP Control Register C9A Only
COPCR.COPF             4   Computer Operating Properly Flag
COPCR.CME              3   Clock Monitor Enable Bit
COPCR.COPE             2   COP Enable Bit
COPCR.CM1              1   COP Mode Bit 1
COPCR.CM0              0   COP Mode Bit 0
Reserv001F            0x001F    Reserved
PBMOR                 0x3FF0    PORT B MASK OPTIONS REGISTER
MOR                   0x3FF1    MASK OPTION REGISTER
UNUSED3FF2            0x3FF2    UNUSED
UNUSED3FF3            0x3FF3    UNUSED


.68HC705CJ4
; http://
; HC05CJ4GRS.pdf

; RAM=256
; ROM=0
; EPROM=4K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA RAM         0x0020:0x0100
area BSS  UNUSED      0x0100:0x1000
area DATA EPROM       0x1000:0x1F00
area DATA BootROM     0x1F00:0x1FE0
area BSS  RESERVED    0x1FE0:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      Software       
interrupt IRQ               0x1FFA      External Interrupt
interrupt Timer1            0x1FF8      Timer_In_Out
interrupt SCI               0x1FF6      SCI
interrupt SPI               0x1FF4      SPI
interrupt ICC               0x1FF2         
interrupt Timer2            0x1FF0      Timer2_In_Out


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004   Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005   Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006   Port C Data Direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED07              0x0007   UNUSED
T2CSR                 0x0008   TIMER STATUS AND CONTROL
T2CSR.TOF              7   Timer Over Flow
T2CSR.RTIF             6   Real Time Interrupt Flag
T2CSR.TOFE             5   Timer Over Flow Enable
T2CSR.RTIE             4   Real Time Interrupt Enable
T2CSR.IRQS             3   IRQ Select
T2CSR.COPE             2   COP Enable
T2CSR.RT1              1   Real Time Interrupt Rate Select 1
T2CSR.RT0              0   Real Time Interrupt Rate Select 0
T2CR                  0x0009   TIMER COUNTER REGISTER
SPCR                  0x000A   SPI CONTROL REGISTER
SPCR.SPIE              7   SPI Interrupt Enable
SPCR.SPE               6   SPI System Enable
SPCR.DOD               5   Direction Of Data
SPCR.MSTR              4   Master/Slave Mode Select
SPCR.CPOL              3   Clock Polarity
SPCR.CPHA              2   Clock Phase
SPCR.SPR1              1   SPI Clock (SCK1) Rate Select Bits 1
SPCR.SPR0              0   SPI Clock (SCK1) Rate Select Bits 0
SPSR                  0x000B   SPI STATUS REGISTER
SPSR.SPIF              7   SPI Interrupt Request
SPSR.WCOL              6   Write Collision Status Flag
SPSR.MODF              5   SPI Mode Error Interrupt Status Flag
SPDR                  0x000C   SPI DATA REGISTER
SPDR.SPD7              7
SPDR.SPD6              6
SPDR.SPD5              5
SPDR.SPD4              4
SPDR.SPD3              3
SPDR.SPD2              2
SPDR.SPD1              1
SPDR.SPD0              0
BAUD                  0x000D   SCI BAUD RATE REGISTER
BAUD.SCP1              5   SCI Prescaler Select Bits 1     
BAUD.SCP0              4   SCI Prescaler Select Bits 0     
BAUD.SCR2              2   SCR0-SCI Baud Rate Select Bits 2
BAUD.SCR1              1   SCR0-SCI Baud Rate Select Bits 1
BAUD.SCR0              0   SCR0-SCI Baud Rate Select Bits 0
SCCR1                 0x000E   SCI CONTROL REGISTER 1
SCCR1.R8               7   Receiver Bit 8
SCCR1.T8               6   Transmit Bit 8
SCCR1.M                4   Mode (select character format)
SCCR1.WAKE             3   Wake Up by Address Mark/Idle
SCCR2                 0x000F   SCI CONTROL REGISTER 2
SCCR2.TIE              7   Transmit Interrupt Enable
SCCR2.TCIE             6   Transmit Complete Interrupt Enable
SCCR2.RIE              5   Receiver Interrupt Enable
SCCR2.ILIE             4   Idle Line Interrupt Enable
SCCR2.TE               3   Transmitter Enable
SCCR2.RE               2   Receiver Enable
SCCR2.RWU              1   Receiver Wake-up Control
SCCR2.SBK              0   Send Break
SCSR                  0x0010   SCI STATUS REGISTER
SCSR.TDRE              7   Transmit Data Register Empty Flag
SCSR.TC                6   Transmit Complete Flag
SCSR.RDRF              5   Receive Data Register Full Flag
SCSR.IDLE              4   Idle Line Detected Flag
SCSR.OR                3   Over-Run Error Flag
SCSR.NF                2   Noise Error Flag
SCSR.FE                1   Framing Error Flag
SCDR                  0x0011   SCI DATA REGISTER
SCDR.SCD7              7   SCD0 Serial Data Bit 7
SCDR.SCD6              6   SCD0 Serial Data Bit 6
SCDR.SCD5              5   SCD0 Serial Data Bit 5
SCDR.SCD4              4   SCD0 Serial Data Bit 4
SCDR.SCD3              3   SCD0 Serial Data Bit 3
SCDR.SCD2              2   SCD0 Serial Data Bit 2
SCDR.SCD1              1   SCD0 Serial Data Bit 1
SCDR.SCD0              0   SCD0 Serial Data Bit 0
T1CR                  0x0012   Timer  control
T1CR.ICIE              7   Input Capture Interrupt Enable
T1CR.OCIE              6   Output Compare Interrupt Enable
T1CR.TOIE              5   Timer Overflow Interrupt Enable
T1CR.IEDG              1   Input Edge
T1CR.OLVL              0   Output Level
T1SR                  0x0013   Timer  status
T1SR.ICF               7   Input Capture Flag
T1SR.OCF               6   Output Compare Flag
T1SR.TOF               5   Timer Overflow Flag
ICRH                  0x0014   Input capture MSB
ICRH.ICRH7             7
ICRH.ICRH6             6 
ICRH.ICRH5             5
ICRH.ICRH4             4
ICRH.ICRH3             3
ICRH.ICRH2             2
ICRH.ICRH1             1
ICRH.ICRH0             0
ICRL                  0x0015   Input capture  LSB
ICRL.ICRL7             7
ICRL.ICRL6             6
ICRL.ICRL5             5
ICRL.ICRL4             4
ICRL.ICRL3             3
ICRL.ICRL2             2
ICRL.ICRL1             1
ICRL.ICRL0             0
OCRH                  0x0016   Output compare MSB
OCRH.OCRH7             7
OCRH.OCRH6             6
OCRH.OCRH5             5
OCRH.OCRH4             4
OCRH.OCRH3             3
OCRH.OCRH2             2
OCRH.OCRH1             1
OCRH.OCRH0             0
OCRL                  0x0017   Output compare LSB
OCRL.OCRL7             7
OCRL.OCRL6             6
OCRL.OCRL5             5
OCRL.OCRL4             4
OCRL.OCRL3             3
OCRL.OCRL2             2
OCRL.OCRL1             1
OCRL.OCRL0             0
TRH                   0x0018   Timer  MSB
TRH.TMRH7              7
TRH.TMRH6              6
TRH.TMRH5              5
TRH.TMRH4              4
TRH.TMRH3              3
TRH.TMRH2              2
TRH.TMRH1              1
TRH.TMRH0              0
TRL                   0x0019   Timer  LSB
TRL.TMRL7              7                       
TRL.TMRL6              6
TRL.TMRL5              5
TRL.TMRL4              4
TRL.TMRL3              3
TRL.TMRL2              2
TRL.TMRL1              1
TRL.TMRL0              0
ATRH                  0x001A   Alternate  Counter MSB
ATRH.ACRH7             7
ATRH.ACRH6             6
ATRH.ACRH5             5
ATRH.ACRH4             4
ATRH.ACRH3             3
ATRH.ACRH2             2
ATRH.ACRH1             1
ATRH.ACRH0             0
ATRL                  0x001B   Alternate  Counter LSB
ATRL.ACRL7             7                                
ATRL.ACRL6             6
ATRL.ACRL5             5
ATRL.ACRL4             4
ATRL.ACRL3             3
ATRL.ACRL2             2
ATRL.ACRL1             1
ATRL.ACRL0             0
MBADR                 0x001C   MBUS ADD AND DATA REGISTER
MBADR.ADR7             7
MBADR.ADR6             6
MBADR.ADR5             5
MBADR.ADR4             4
MBADR.ADR3             3
MBADR.ADR2             2
MBADR.ADR1             1
MBADR.ADR0             0
MBCR                  0x001D   MBUS CONTROL REGISTER
MBCR.SMIE              7   Slave M-Bus Interrupt Enable
MBCR.SME               6   Slave M-Bus Enable
MBCR.T_R               5   Transmit/Receive
MBCR.NOACK             4   No Acknowledge
MBCR.CLKR              0   Clock Release
MBSR                  0x001E   MBUS STATUS REGISTER
MBSR.SMF               7   Slave M-Bus Flag
MBSR.STDF              6   Start Detect Flag
MBSR.MACK              5   Master Acknowledge
TEST                  0x001F   TEST


.68HC705CL4
; HC05CL4GRS/H  http://
; HC05CL4GRS.pdf

; RAM=1K
; ROM=0
; EPROM=6K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA LCD_RAM     0x0020:0x0050
area DATA RAM_1       0x0050:0x00C0
area DATA STACK       0x00C0:0x0100
area DATA RAM_2       0x0100:0x0450
area BSS  UNUSED      0x0450:0x0600
area DATA BootROM     0x0600:0x0800
area DATA EPROM       0x0800:0x1FE0
area DATA BOOT_VEC    0x1FE0:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset                  
interrupt SWI               0x1FFC      SWI                    
interrupt IRQ               0x1FFA      IRQ                     
interrupt LVI               0x1FF8      LVI                
interrupt RDI               0x1FF6      RDI
interrupt CDI               0x1FF4      CDI
interrupt CTimer            0x1FF2      CTimer
interrupt TIMER             0x1FF0      TIMER


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
CFGC                  0x0006     Port C Configuration
CFGC.CFGC7             7
CFGC.CFGC6             6
CFGC.CFGC5             5
CFGC.CFGC4             4
CFGC.CFGC3             3
CFGC.CFGC2             2
CFGC.CFGC1             1
CFGC.CFGC0             0
CFGD                  0x0007     Port D Configuration
CFGD.CFGD7             7
CFGD.CFGD6             6
CFGD.CFGD5             5
CFGD.CFGD4             4
CFGD.CFGD3             3
CFGD.CFGD2             2
CFGD.CFGD1             1
CFGD.CFGD0             0
CTCSR                 0x0008     Core Timer Control
CTCSR.CTOF             7   Core Timer Overflow Flag
CTCSR.RTIF             6   Real Time Interrupt Flag
CTCSR.CTOFE            5   Core Timer Overflow Enable
CTCSR.RTIE             4   Real Time Interrupt Enable
CTCSR.RT1              1   Real Time Interrupt Select Bits 1
CTCSR.RT0              0   Real Time Interrupt Select Bits 0
CTR                   0x0009     Core Timer Register
CTR.CT7                7
CTR.CT6                6
CTR.CT5                5
CTR.CT4                4
CTR.CT3                3
CTR.CT2                2
CTR.CT1                1
CTR.CT0                0
LCDCTR                0x000A     LCD Control
LCDCTR.CC3             7   Contrast Control 3
LCDCTR.CC2             6   Contrast Control 2
LCDCTR.CC1             5   Contrast Control 1
LCDCTR.MX4             3
LCDCTR.FC              2
LCDCTR.LC              1
LCDCTR.DISON           0   Display On
RESERV000B            0x000B     RESERVED
CLCSR1                0x000C     CLRID Control Status1
CLCSR1.RDIF            7   Ring Detect Interrupt Flag
CLCSR1.RDIE            6   Ring Detect Interrupt Enable
CLCSR1.CDIF            5   Carrier Detect Interrupt Flag
CLCSR1.CDIE            4   Carrier Detect Interrupt Enable
CLCSR1.RDO             1   Ring Detect Override
CLCSR1.CDO             0   Carrier Detect Override
CLCSR2                0x000D     CLRID Control Status2
CLCSR2.CDPW            6   Ring Detect Power Up
CLCSR2.RDPW            5   Carrier Detect Power Up
CLCSR2.CIDSD           2   Caller ID Serial Data
CLCSR2.RD              1   Ring Detect
CLCSR2.CD              0   Carrier Detect
CLCSR3                0x000E     CLRID Control Status3
CLCSR3.SDSL            7   Serial Data Select
CLCSR3.RDEDG           3
CLCSR3.CDEDG           2
CLCSR3.RDOE            1   Ring Detect Override Enable
CLCSR3.CDOE            0   Carrier Detect Override Enable
ISCR                  0x000F     IRQ Status_Control
ISCR.IRQM              7   IRQ Enable Mask
ISCR.IRQS              6   IRQ Sensitivity
ISCR.EDGE              5   IRQ Active Edge Select
ISCR.REQ               3   IRQ Interrupt Request
ISCR.ACK               1   IRQ Interrupt Request Acknowledge
LVSCR                 0x0010     LVI Control
LVSCR.LVIS             2   Low Voltage Interrupt Status
LVSCR.LVIF             1   Low Voltage Reset Flag
LVSCR.LVIE             0   Low Voltage Reset Enable
KBIR                  0x0011     Keyboard Interrupt
KBIR.KBIE7             7   Keyboard Interrupt Enables 7
KBIR.KBIE6             6   Keyboard Interrupt Enables 6
KBIR.KBIE5             5   Keyboard Interrupt Enables 5
KBIR.KBIE4             4   Keyboard Interrupt Enables 4
KBIR.KEDGE             2   Keyboard Interrupt Edge
KBIR.KBIF              1   Keyboard Interrupt Flag
KBIR.KBIC              0   Keyboard Interrupt Clear
TCR                   0x0012     Timer Control
TCR.ICIE               7   Input capture interrupt enable 
TCR.OCIE               6   Output compare interrupt enable
TCR.TOIE               5   Timer overflow interrupt enable
TCR.IEDG               1   Input edge                     
TCR.OLVL               0   Value of the output level      
TSR                   0x0013     Timer Status
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICH                   0x0014     Input Capture H
ICH.IC15               7
ICH.IC14               6
ICH.IC13               5
ICH.IC12               4
ICH.IC11               3
ICH.IC10               2
ICH.IC9                1
ICH.IC8                0
ICL                   0x0015     Input Capture L
ICL.IC7                7
ICL.IC6                6
ICL.IC5                5
ICL.IC4                4
ICL.IC3                3
ICL.IC2                2
ICL.IC1                1
ICL.IC0                0
OCH                   0x0016     Output Compare H
OCH.OC15               7
OCH.OC14               6
OCH.OC13               5
OCH.OC12               4
OCH.OC11               3
OCH.OC10               2
OCH.OC9                1
OCH.OC8                0
OCL                   0x0017     Output Compare L
OCL.OC7                7
OCL.OC6                6
OCL.OC5                5
OCL.OC4                4
OCL.OC3                3
OCL.OC2                2
OCL.OC1                1
OCL.OC0                0
TCH                   0x0018     Timer Counter H
TCH.TC15               7
TCH.TC14               6
TCH.TC13               5
TCH.TC12               4
TCH.TC11               3
TCH.TC10               2
TCH.TC9                1
TCH.TC8                0
TCL                   0x0019     Timer Counter L
TCL.TC7                7
TCL.TC6                6
TCL.TC5                5
TCL.TC4                4
TCL.TC3                3
TCL.TC2                2
TCL.TC1                1
TCL.TC0                0
ACH                   0x001A     Alternate Counter H
ACH.AC15               7
ACH.AC14               6
ACH.AC13               5
ACH.AC12               4
ACH.AC11               3
ACH.AC10               2
ACH.AC9                1
ACH.AC8                0
ACL                   0x001B     Alternate Counter L
ACL.AC7                7
ACL.AC6                6
ACL.AC5                5
ACL.AC4                4
ACL.AC3                3
ACL.AC2                2
ACL.AC1                1
ACL.AC0                0
PCR                   0x001C     RESERVED FOR EPROM CONTROL
PCR.ELAT               1   EPROM LATch control
PCR.PGM                0   EPROM ProGraM command
OPT                   0x001D     OPTION
OPT.COP                6   Computer Operating Properly
OPT.LVRE               2   Low Voltage Reset Enable
RESERV001E            0x001E     RESERVED
RESERV001F            0x001F     RESERVED


.68HC705E1
; http://

; RAM=367
; ROM=0
; EPROM=4096
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  RESERVED    0x0020:0x0090
area DATA RAM_U1      0x0090:0x0100
area DATA RAM_U2      0x0100:0x0200
area BSS  RESERVED    0x0200:0x0F00
area CODE EPROM       0x0F00:0x1F00
area DATA BootROM     0x1F01:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset                  
interrupt SWI               0x1FFC      SWI                    
interrupt IRQ               0x1FFA      IRQ                     
interrupt TIMER             0x1FF8      Timer                
interrupt CPI               0x1FF6      CPI                   


; INPUT/ OUTPUT PORTS
MOR 0x1F00                      Mask Option Register
RESERV1FF0 0x1FF0               RESERVED
RESERV1FF1 0x1FF1               RESERVED
RESERV1FF2 0x1FF2               RESERVED
RESERV1FF3 0x1FF3               RESERVED
RESERV1FF4 0x1FF4               RESERVED
RESERV1FF5 0x1FF5               RESERVED






.68HC705E5
; HC705E5GRS/D  http://
; HC705E5GRS.pdf

; RAM=384
; ROM=0
; EPROM=5120
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x0080
area DATA RAM_U1      0x0080:0x0100
area DATA RAM_U2      0x0100:0x0200
area BSS  UNUSED      0x0200:0x0B00
area CODE EPROM       0x0B00:0x1F00
area DATA BootROM     0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset                  
interrupt SWI               0x1FFC      SWI                    
interrupt IRQ               0x1FFA      IRQ                     
interrupt TIMER             0x1FF8      Timer                
interrupt CPI               0x1FF6      CPI                   
interrupt SSI               0x1FF4      SSI         
interrupt M_BUS             0x1FF2      M-BUS


; INPUT/ OUTPUT PORTS
PORTA          0x0000     Port A Data Register
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001     Port B Data Register
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
PORTC          0x0002     Port C Data Register
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
UNUSED0003     0x0003     UNUSED
DDRA           0x0004     Port A Data Direction Register
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005     Port B Data Direction Register
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRC           0x0006     Port C Data Direction Register
DDRC.DDRC7      7
DDRC.DDRC6      6
DDRC.DDRC5      5
DDRC.DDRC4      4
DDRC.DDRC3      3   Data Direction for Port C Bit 3
DDRC.DDRC2      2   Data Direction for Port C Bit 2
DDRC.DDRC1      1   Data Direction for Port C Bit 1
DDRC.DDRC0      0   Data Direction for Port C Bit 0
PCR            0x0007     PLL Control Register
PCR.BCS         6   Bus Clock Select
PCR.BWC         4   Bandwidth Control
PCR.PLLON       3   PLL On
PCR.VCOTST      2   VCO Test
PCR.PS1         1   PLL Synthesizer Speed Select 1
PCR.PS0         0   PLL Synthesizer Speed Select 0
TCSR           0x0008     Timer Control and Status Register
TCSR.TOF        7   Timer Over Flow
TCSR.RTIF       6   Real-Time Interrupt Flag
TCSR.TOFE       5   Timer Overflow Enable
TCSR.RTIE       4   Real-Time Interrupt Enable
TCSR.TOFA       3   Timer Over Flow Flag Acknowledge
TCSR.RTIFA      2   Real-Time Interrupt Flag Acknowledge
TCSR.RT1        1   Real-Time Interrupt Rate Select 1
TCSR.RT0        0   Real-Time Interrupt Rate Select 0
TCR            0x0009     Timer Counter Register
SCR            0x000A     SSI Control Register
SCR.SIE         7   SSI Interrupt Enable
SCR.SE          6   SSI Enable
SCR.LSBF        5   Least Significant Bit First
SCR.MSTR        4   Master Mode
SCR.CPOL        3   Clock Polarity
SCR.SDIR        2   Serial Data Direction
SCR.SR1         1   SSI Clock Rate Select 1
SCR.SR0         0   SSI Clock Rate Select 0
SSR            0x000B     SSI Status Register
SSR.SF          7   SSI Flag
SSR.DCOL        6   Data Collision
SSR.TIPL        0
SDR            0x000C     SSI Data Register
SDR.D7          7
SDR.D6          6
SDR.D5          5
SDR.D4          4
SDR.D3          3
SDR.D2          2
SDR.D1          1
SDR.D0          0
UNUSED000D     0x000D     UNUSED
UNUSED000E     0x000E     UNUSED
UNUSED000F     0x000F     UNUSED
UNUSED0010     0x0010     UNUSED
PROGR          0x0011     Programming Register
PROGR.LATCH     2   EPROM Latch Control
PROGR.EPGM      0   EPROM Program Control
CCSR           0x0012     CPI Control and Status Register
CCSR.CPIF       6   Custom Periodic Interrupt Flag
CCSR.CPIE       4   Custom Periodic Interrupt Enable
SCSR           0x0013     System Control and Status Register
SCSR.STOPR      4   Illegal STOP Instruction Reset
SCSR.ILADR      3   Illegal Address Reset
SCSR.COPR       2   COP Reset
SCSR.CRS1       1   COP Rate Select 1
SCSR.CRS0       0   COP Rate Select 0
UNUSED0014     0x0014     UNUSED
UNUSED0015     0x0015     UNUSED
UNUSED0016     0x0016     UNUSED
UNUSED0017     0x0017     UNUSED
MBAR           0x0018     M-Bus Address Register
MBAR.MAD7       7
MBAR.MAD6       6
MBAR.MAD5       5
MBAR.MAD4       4
MBAR.MAD3       3
MBAR.MAD2       2
MBAR.MAD1       1
MBFDR          0x0019     M Bus Frequency Divider Register
MBFDR.FD4       4
MBFDR.FD3       3
MBFDR.FD2       2
MBFDR.FD1       1
MBFDR.FD0       0
MBCR           0x001A     M Bus Control Register
MBCR.MEN        7   M-Bus Enable Bit
MBCR.MIEN       6   M-Bus Interrupt Enable Bit
MBCR.MSTA       5   Master/Slave Mode Select Bit
MBCR.MTX        4   Transmit/Receiver Mode Select Bit
MBCR.TXAK       3   Transmit Acknowledge Enable Bit
MBCR.MMUX       2   M-Bus Multiplexer
MBSR           0x001B     M Bus Status Register
MBSR.MCF        7   Data Transferring Bit
MBSR.MAAS       6   Addressed as a Slave Bit
MBSR.MBB        5   Bus Busy Bit
MBSR.MAL        4   Arbitration Lost Bit
MBSR.SRW        2   R/W Command Bit
MBSR.MIF        1   M-Bus Interrupt Bit
MBSR.RXAK       0   Receive Acknowledge Bit
MBDIOR         0x001C     M Bus Data I_O Register
MBDIOR.MD7      7
MBDIOR.MD6      6
MBDIOR.MD5      5
MBDIOR.MD4      4
MBDIOR.MD3      3
MBDIOR.MD2      2
MBDIOR.MD1      1
MBDIOR.MD0      0
UNUSED001D     0x001D     UNUSED
UNUSED001E     0x001E     UNUSED
Reserv001F     0x001F     Reserved
MOR	       0x1F00	 MOR
MOR.STOPEN      4   STOP Enable
MOR.CPI1        3   CPI Rate bits 1
MOR.CPI0        2   CPI Rate bits 0
MOR.IRQ         1   IRQ sensitivity
MOR.COP         0   COP Enable
RESERV1FF0     0x1FF0    RESERVED
RESERV1FF1     0x1FF1    RESERVED


.68HC705E6
; http://
; MC68HC05E6.pdf
 
; RAM=128
; ROM=0
; EPROM=6144
; EEPROM=160


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area BSS  RESERVED     0x0020:0x0080
area DATA RAM          0x0080:0x0100
area DATA EEPROM       0x0100:0x01A0
area BSS  RESERVED     0x01A0:0x0700
area CODE EPROM        0x0700:0x1F00
area DATA BootROM      0x1F00:0x1FEF
area DATA USER_VEC     0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset                  
interrupt SWI               0x1FFC      SWI                    
interrupt IRQ               0x1FFA      IRQ                     
interrupt TIMER             0x1FF8      Core timer                
interrupt LVI               0x1FF6      LVI                   
interrupt TIMER16           0x1FF4      16-bit Timer         
interrupt KEY_WAKE_UP       0x1FF2      Keyboard wake-up


; INPUT/ OUTPUT PORTS
PORTA           0x0000    Port A data Register
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001    Port B data Register
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002    Port C data Register
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003    Port D data Register
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD6        6   Port D Data Bits 6
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004    Port A data direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005    Port B data direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006    Port C data direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007    Port D data direction
DDRD.DDRD7       7   Data Direction for Port D Bit 7
DDRD.DDRD6       6   Data Direction for Port D Bit 6
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
CTCSR           0x0008    Core timer control/status
CTCSR.CTOF       7   Core timer overflow
CTCSR.RTIF       6   Real time interrupt flag
CTCSR.CTOFE      5   Core timer overflow interrupt enable
CTCSR.RTIE       4   Real time interrupt enable
CTCSR.RTOF       3   Reset core timer overflow flag
CTCSR.RRTIF      2   Reset real time interrupt flag
CTCSR.RT1        1   Real time interrupt rate select 1
CTCSR.RT0        0   Real time interrupt rate select 0
CTCR            0x0009   Core timer counter
KEY_TIM         0x000A   Keyboard/timer
KEY_TIM.KSF      7   Keyboard status flag
KEY_TIM.KIE      6   Keyboard interrupt enable
KEY_TIM.KIRST    5   Keyboard interrupt reset
KEY_TIM.SEL1     1   Timer select bit 1
KEY_TIM.SEL0     0   Timer select bit 0
CONFD           0x000B   Port D configuration
PORTG           0x000C   Port G data
RESERV000D      0x000D   Reserved
CONFC           0x000E   Port C configuration
LVIOPT          0x000F   LVI/options
LVIOPT.LVIINT    7   LVI interrupt flag
LVIOPT.LVIVAL    6   LVI pin level
LVIOPT.LVIRST    5   LVI interrupt reset
LVIOPT.LVIE      4   LVI interrupt enable
LVIOPT.IRQ       0
ADDATA          0x0010   A/D data
ADSTAT          0x0011   A/D status/control
ADSTAT.COCO      7   Conversion complete flag
ADSTAT.ADRC      6   A/D RC oscillator control
ADSTAT.ADON      5   A/D converter enable/disable
ADSTAT.CH2       2   A/D channel selection 2
ADSTAT.CH1       1   A/D channel selection 1
ADSTAT.CH0       0   A/D channel selection 0
TCR             0x0012   Timer control
TCR.ICIE         7   Input capture interrupt enable
TCR.OCIE         6   Output compare interrupt enable
TCR.TOIE         5   Timer overflow interrupt enable
TCR.IEDG         1   Input edge
TCR.OLV          0   Output level
TSR             0x0013   Timer status
TSR.ICF          7   Input capture flag
TSR.OCF          6   Output compare flag
TSR.TOF          5   Timer overflow flag
ICH             0x0014   Input capture high
ICL             0x0015   Input capture low
OCH             0x0016   Output compare high
OCL             0x0017   Output compare low
TCH             0x0018   Timer counter high
TCL             0x0019   Timer counter low
ACH             0x001A   Alternate counter high
ACL             0x001B   Alternate counter low
EPROG           0x001C   EEPROM programming
EPROG.CPEN       6   Charge pump enable
EPROG.ER1        4   Erase select bits 1
EPROG.ER0        3   Erase select bits 0
EPROG.EELATCH    2   EEPROM latch control
EPROG.EERC       1   EEPROM RC oscillator control
EPROG.EEPGM      0   EEPROM programming power enable/disable
PROG            0x001D   EPROM programing (MC68HC705E6)
PROG.ELATCH      2   EPROM latch control
PROG.EPGM        0   EPROM program control
RESERV001E      0x001E   Reserved
RESERV001F      0x001F   Reserved
COPCLR          0x1FF0   COPCLR
COPCLR.CCLR      0
RESERV1FF1      0x1FF1  RESERVED


.68HC705F32
; MC68HC05F32/D  http://
; MC68HC05F32.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR         0x0000:0x0050
area BSS  UNUSED      0x0050:0x0054
area DATA LCD_RAM     0x0054:0x0068
area DATA RAM         0x0068:0x0400
area DATA EEPROM      0x0400:0x0500
area BSS  UNUSED      0x0500:0x8000
area DATA EPROM       0x8000:0xFF00
area DATA BOOT_ROM    0xFF00:0xFFF0
area DATA USER_VEC    0xFFF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Reset  
interrupt SWI               0xFFFC      SWI               
interrupt IRQ               0xFFFA      IRQ       
interrupt CTimer            0xFFF8      CTimer        
interrupt TIMER             0xFFF6      Timer  
interrupt KEYF              0xFFF4      KEYF
interrupt SPI               0xFFF2      LVI
interrupt SCI               0xFFF0      SCI


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001     Port B data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002     Port C data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003     Port D data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD6        6   Port D Data Bits 6
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004     Port A data direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005     Port B data direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006     Port C data direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007     Port D data direction
DDRD.DDRD7       7   Data Direction for Port D Bit 7
DDRD.DDRD6       6   Data Direction for Port D Bit 6
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
CTCSR           0x0008     Core timer control_status
CTCSR.TOF        7   Core timer overflow
CTCSR.RTIF       6   Real time interrupt flag
CTCSR.TOFE       5   Core timer overflow enable
CTCSR.RTIE       4   Real time interrupt enable
CTCSR.RTOF       3
CTCSR.RRTIF      2
CTCSR.RT1        1   Real time interrupt rate select 1
CTCSR.RT0        0   Real time interrupt rate select 0
CTCR            0x0009     Core timer counter
PORTE           0x000A     Port E data
PORTE.PE7        7   Port E Data Bits 7
PORTE.PE6        6   Port E Data Bits 6
PORTE.PE5        5   Port E Data Bits 5
PORTE.PE4        4   Port E Data Bits 4
PORTE.PE3        3   Port E Data Bits 3
PORTE.PE2        2   Port E Data Bits 2
PORTE.PE1        1   Port E Data Bits 1
PORTE.PE0        0   Port E Data Bits 0
DDRE            0x000B     Port E data direction
DDRE.DDRE7       7   Data Direction for Port E Bit 7
DDRE.DDRE6       6   Data Direction for Port E Bit 6
DDRE.DDRE5       5   Data Direction for Port E Bit 5
DDRE.DDRE4       4   Data Direction for Port E Bit 4
DDRE.DDRE3       3   Data Direction for Port E Bit 3
DDRE.DDRE2       2   Data Direction for Port E Bit 2
DDRE.DDRE1       1   Data Direction for Port E Bit 1
DDRE.DDRE0       0   Data Direction for Port E Bit 0
PECR            0x000C     Port E control
FCR             0x000D     DTMF row freq. control
FCR.FCR4         4
FCR.FCR3         3
FCR.FCR2         2
FCR.FCR1         1
FCR.FCR0         0
FCC             0x000E     DTMF column freq. control
FCC.FCC4         4
FCC.FCC3         3
FCC.FCC2         2
FCC.FCC1         1
FCC.FCC0         0
TNCR            0x000F     DTMF tone control
TNCR.MS1         7   Melody select for operation 1
TNCR.MS0         6   Melody select for operation 0
TNCR.TGER        5   Tone generator enable row path
TNCR.TGEC        4   Tone generator enable column path
TNCR.TNOE        3   Tone output enable
PORTF           0x0010     Port F data
PORTF.PF7        7   Port F Data Bits 7
PORTF.PF6        6   Port F Data Bits 6
PORTF.PF5        5   Port F Data Bits 5
PORTF.PF4        4   Port F Data Bits 4
PORTF.PF3        3   Port F Data Bits 3
PORTF.PF2        2   Port F Data Bits 2
PORTF.PF1        1   Port F Data Bits 1
PORTF.PF0        0   Port F Data Bits 0
PFCR            0x0011     Port F control
PORTG           0x0012     Port G data
PORTG.PG7        7   Port G Data Bits 7
PORTG.PG6        6   Port G Data Bits 6
PORTG.PG5        5   Port G Data Bits 5
PORTG.PG4        4   Port G Data Bits 4
PORTG.PG3        3   Port G Data Bits 3
PORTG.PG2        2   Port G Data Bits 2
PORTG.PG1        1   Port G Data Bits 1
PORTG.PG0        0   Port G Data Bits 0
PGCR            0x0013     Port G control
PORTH           0x0014     Port H data
PORTH.PH7        7   Port H Data Bits 7
PORTH.PH6        6   Port H Data Bits 6
PORTH.PH5        5   Port H Data Bits 5
PORTH.PH4        4   Port H Data Bits 4
PORTH.PH3        3   Port H Data Bits 3
PORTH.PH2        2   Port H Data Bits 2
PORTH.PH1        1   Port H Data Bits 1
PORTH.PH0        0   Port H Data Bits 0
PHCR            0x0015     Port H control
PORTI           0x0016     Port I data
PORTI.PI7        7   Port I Data Bits 7
PORTI.PI6        6   Port I Data Bits 6
PORTI.PI5        5   Port I Data Bits 5
PORTI.PI4        4   Port I Data Bits 4
PORTI.PI3        3   Port I Data Bits 3
PORTI.PI2        2   Port I Data Bits 2
PORTI.PI1        1   Port I Data Bits 1
PORTI.PI0        0   Port I Data Bits 0
PICR            0x0017     Port I control
PORTJ           0x0018     Port J data
PORTJ.PJ7        7   Port J Data Bits 7
PORTJ.PJ6        6   Port J Data Bits 6
PORTJ.PJ5        5   Port J Data Bits 5
PORTJ.PJ4        4   Port J Data Bits 4
PORTJ.PJ3        3   Port J Data Bits 3
PORTJ.PJ2        2   Port J Data Bits 2
PORTJ.PJ1        1   Port J Data Bits 1
PORTJ.PJ0        0   Port J Data Bits 0
PJCR            0x0019     Port J control
PDCR            0x001A     Port D control
KCR             0x001B     Key control
KCR.KF           7   Keyboard interrupt status flag
KCR.KIE          6   keyboard interrupt enable
KCR.EDG5         5   trigger edge control 5
KCR.EDG4         4   trigger edge control 4
KCR.EDG3         3   trigger edge control 3
KCR.EDG2         2   trigger edge control 2
KCR.EDG1         1   trigger edge control 1
KCR.EDG0         0   trigger edge control 0
EEPROG          0x001C     EEPROM prog.
EEPROG.CPEN      6   Charge pump enable
EEPROG.ER1       4   Erase select bits 1
EEPROG.ER0       3   Erase select bits 0
EEPROG.LATCH     2   EEPROM latch bit
EEPROG.EERC      1   EEPROM RC oscillator control
EEPROG.EEPGM     0   EEPROM programming power enable
PROG            0x001D     EPROM prog.
PROG.ELATCH      2   EPROM latch control
PROG.EPGM        0   EPROM program control
LCD             0x001E     LCD control
LCD.WTLCDO       7   WAIT mode LCD only
LCD.FSEL1        6   LCD operation frequency 1
LCD.FSEL0        5   LCD operation frequency 0
LCD.NTVLCD       4   Internal voltage generator ON/OFF
LCD.FDISP        3   Display frequency
LCD.MUX4         2   Multiplex ratio 4
LCD.MUX3         1   Multiplex ratio 3
LCD.EXTVON       0   External LCD voltage ON/OFF
Reserv001F      0x001F     RESERVED
ICR1H           0x0020     Capture 1 high
ICR1L           0x0021     Capture 1 low
OCR1H           0x0022     Compare 1 high
OCR1L           0x0023     Compare 1 low
ICR2H           0x0024     Capture 2 high
ICR2L           0x0025     Capture 2 low
OCR2H           0x0026     Compare 2 high
OCR2L           0x0027     Compare 2 low
CNTH_1          0x0028     Counter 1 high
CNTL_1          0x0029     Counter 1 low
ACNTH_1         0x002A     Alternate counter 1 high
ACNTL_1         0x002B     Alternate counter 1 low
TCR1_1          0x002C     Timer1 control 1
TCR1_1.IC1IE     7   Input capture 1 interrupt enable
TCR1_1.IC2IE     6   Input capture 2 interrupt enable
TCR1_1.OC1IE     5   Output compare 1 interrupt enable
TCR1_1.TOIE      4   Timer overflow interrupt enable
TCR1_1.CO1E      3   Timer compare 1 output enable
TCR1_1.IEDG1     2   Input edge 1
TCR1_1.IEDG2     1   Input edge 2
TCR1_1.OLVL1     0   Output level 1
TCR2_1          0x002D     Timer1 control 2
TCR2_1.OC2IE     5   Output compare 2 interrupt enable
TCR2_1.CO2E      3   Timer compare 2 output enable
TCR2_1.OLVL2     0   Output level 2
TSR_1           0x002E     Timer1 status
TSR_1.IC1F       7   Input capture 1 flag
TSR_1.IC2F       6   Input capture 2 flag
TSR_1.OC1F       5   Output compare 1 flag
TSR_1.TOF        4   Timer overflow status flag
TSR_1.TCAP1      3   Timer capture 1 status flag
TSR_1.TCAP2      2   Timer capture 2 status flag
TSR_1.OC2F       1   Output compare 2 flag
Reserv002F      0x002F     RESERVED
ICR3H           0x0030     Capture 3 high
ICR3L           0x0031     Capture 3 low
OCR3H           0x0032     Compare 3 high
OCR3L           0x0033     Compare 3 low
ICR4H           0x0034     Capture 4 high
ICR4L           0x0035     Capture 4 low
OCR4H           0x0036     Compare 4 high
OCR4L           0x0037     Compare 4 low
CNTH_1          0x0038     Counter 1 high
CNTL_1          0x0039     Counter 1 low
ACNTH_1         0x003A     Alternate counter 2 high
ACNTL_1         0x003B     Alternate counter 2 low
TCR1_2          0x003C     Timer2 control 1
TCR1_2.ICI3E     7
TCR1_2.ICI4E     6
TCR1_2.OCI3E     5
TCR1_2.TOIE      4
TCR1_2.CO3E      3
TCR1_2.IEDG3     2
TCR1_2.IEDG4     1
TCR2_2          0x003D     Timer2 control 2
TCR2_2.OCI4E     5
TCR2_2.CO4E      3
TSR_2           0x003E     Timer2 status
TSR_2.IC3F       7
TSR_2.IC4F       6
TSR_2.OC3F       5
TSR_2.TOF        4
TSR_2.TCAP3      3
TSR_2.TCAP4      2
TSR_2.OC4F       1
Reserv003F      0x003F     RESERVED
PWMCR           0x0040     PWM control
PWMCR.POL3       4   PWM3 polarity
PWMCR.POL2       3   PWM2 polarity
PWMCR.POL1       2   PWM1 polarity
PWMCR.RA1        1   PWM clock rate bits 1
PWMCR.RA0        0   PWM clock rate bits 0
PWMD1           0x0041     PWM data 1
PWMD2           0x0042     PWM data 2
PWMD3           0x0043     PWM data 3
SPCR            0x0044     SPI control
SPCR.SPIE        7   SPI interrupt enable
SPCR.SPE         6   SPI system enable
SPCR.DOD         5   Direction of data
SPCR.MSTR        4   Master/slave mode select
SPCR.CPOL        3   Clock polarity
SPCR.CPHA        2   Clock phase
SPCR.SPR1        1   SPI clock (SCK) rate select bits 1
SPCR.SPR0        0   SPI clock (SCK) rate select bits 0
SPSR            0x0045     SPI status
SPSR.SPIF        7   SPI interrupt request flag
SPSR.WCOL        6   Write collision
SPSR.MODF        4   SPI mode error interrupt status flag
SPDAT           0x0046     SPI data I_O
SCDAT           0x0047     SCI data
SCCR1           0x0048     SCI control 1
SCCR1.R8         7   Receive data bit 8
SCCR1.T8         6   Transmit data bit 8
SCCR1.M          4   Mode (select character format)
SCCR1.WAKE       3   Wake-up mode select
SCCR2           0x0049     SCI control 2
SCCR2.TIE        7   Transmit interrupt enable
SCCR2.TCIE       6   Transmit complete interrupt enable
SCCR2.RIE        5   Receiver interrupt enable
SCCR2.ILIE       4   Idle line interrupt enable
SCCR2.TE         3   Transmitter enable
SCCR2.RE         2   Receiver enable
SCCR2.RWU        1   Receiver wake-up
SCCR2.SBK        0   Send break
SCSR            0x004A     SCI status
SCSR.TDRE        7   Transmit data register empty flag
SCSR.TC          6   Transmit complete flag
SCSR.RDRF        5   Receive data register full flag
SCSR.IDLE        4   Idle line detected flag
SCSR.OR          3   Overrun error flag
SCSR.NF          2   Noise error flag
SCSR.FE          1   Framing error flag
BAUD            0x004B     SCI baud rate
BAUD.TCLR        7   Clear baud rate counters (test purposes only)
BAUD.SCP1        5   Serial prescaler select bits 1
BAUD.SCP0        4   Serial prescaler select bits 0
BAUD.RCKB        3   SCI receive baud rate clock test
BAUD.SCR2        2   SCI rate select bits 2
BAUD.SCR1        1   SCI rate select bits 1
BAUD.SCR0        0   SCI rate select bits 0
CPICSR          0x004C     CPI control status
CPICSR.CPIF      6   Custom periodic interrupt flag
CPICSR.CPIE      4   Custom periodic interrupt enable
CPICSR.RFQ1      1   Refresh frequency select 1
CPICSR.RFQ0      0   Refresh frequency select 0
SOR             0x004D     System options
SOR.LVIF         7   LVIF - Low voltage interrupt bit          
SOR.LVIE         6   LVIE - Low voltage interrupt bit          
SOR.LVION        5   LVION - Low voltage interrupt bit         
SOR.SC           4   System clock option                       
SOR.IRQ          3   Interrupt sensitivity                     
SOR.KEYMUX       2   Multiplex bit for access of interrupt flag
SOR.KEYCLR       1   Keyboard interrupt clear                  
SOR.PUEN         0   PORTC pull-up enable                      
ADDATA          0x004E     A_D data
ADSCR           0x004F     A_D status_control
ADSCR.COCO       7   Conversion complete flag
ADSCR.ADRC       6   A/D RC oscillator control
ADSCR.ADON       5   A/D converter on
ADSCR.CH3        3   A/D channel selection 3
ADSCR.CH2        2   A/D channel selection 2
ADSCR.CH1        1   A/D channel selection 1
ADSCR.CH0        0   A/D channel selection 0


.68HC705F4
; MC68HC05F4/D  http://
; MC68HC05F4.pdf

; RAM=384
; ROM=0
; EPROM=7680
; EEPROM=256


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area DATA RAM         0x0040:0x0140
area BSS  UNUSED      0x0140:0x0200
area DATA EEPROM      0x0200:0x0300
area BSS  UNUSED      0x0300:0x3000
area DATA EPROM       0x3000:0x3F00
area DATA BOOT_ROM    0x3F00:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Reset
interrupt SWI               0x3FFC      SWI
interrupt IRQ               0x3FFA      IRQ
interrupt CTimer            0x3FF8      CTimer
interrupt TIMER             0x3FF6      Timer
interrupt KEYF              0x3FF4      KEYF
interrupt LVI               0x3FF2      LVI


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C data direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
DDRD                  0x0007     Port D data direction
DDRD.DDRD7             7   Data Direction for Port D Bit 7
DDRD.DDRD6             6   Data Direction for Port D Bit 6
DDRD.DDRD5             5   Data Direction for Port D Bit 5
DDRD.DDRD4             4   Data Direction for Port D Bit 4
DDRD.DDRD3             3   Data Direction for Port D Bit 3
DDRD.DDRD2             2   Data Direction for Port D Bit 2
DDRD.DDRD1             1   Data Direction for Port D Bit 1
DDRD.DDRD0             0   Data Direction for Port D Bit 0
CTCSR                 0x0008     Core timer control_status
CTCSR.CTOF             7   Core timer overflow
CTCSR.RTIF             6   Real time interrupt flag
CTCSR.CTOFE            5   Core timer overflow enable
CTCSR.RTIE             4   Real time interrupt enable
CTCSR.RTOF             3   Reset timer overflow flag
CTCSR.RRTIF            2   Reset real time overflow flag
CTCSR.RT1              1   Real time interrupt rate select 1
CTCSR.RT0              0   Real time interrupt rate select 0
CTCR                  0x0009     Core timer counter
CTCR.CTCR7             7
CTCR.CTCR6             6
CTCR.CTCR5             5
CTCR.CTCR4             4
CTCR.CTCR3             3
CTCR.CTCR2             2
CTCR.CTCR1             1
CTCR.CTCR0             0
UNUSED000A            Ox000A     UNUSED
RESERV000B            Ox000B     RESERVED
RESERV000C            Ox000C     RESERVED
FCR                   0x000D     DTMF row freq. control
FCR.FCR4               4
FCR.FCR3               3
FCR.FCR2               2
FCR.FCR1               1
FCR.FCR0               0
FCC                   0x000E     DTMF column freq. control
FCC.FCC4               4
FCC.FCC3               3
FCC.FCC2               2
FCC.FCC1               1
FCC.FCC0               0
TNCR                  0x000F     DTMF tone control
TNCR.MS1               7   Melody select for operation 1
TNCR.MS0               6   Melody select for operation 0
TNCR.TGER              5   Tone generator enable row path
TNCR.TGEC              4   Tone generator enable column path
TNCR.TNOE              3   Tone output enable
KCR                   0x0010     Key control
KCR.KF                 7   Keyboard interrupt status flag
KCR.KIE                6   keyboard interrupt enable
SOR                   0x0011     System options
SOR.LVIF               7   Low voltage interrupt flag
SOR.LVIE               6   Low voltage interrupt enable
SOR.LVION              5   Low voltage interrupt on
SOR.SC                 4   System clock option
SOR.IRQ                3   Interrupt sensitivity
UNUSED0012            Ox0012     UNUSED
UNUSED0013            Ox0013     UNUSED
UNUSED0014            Ox0014     UNUSED
UNUSED0015            Ox0015     UNUSED
UNUSED0016            Ox0016     UNUSED
UNUSED0017            Ox0017     UNUSED
UNUSED0018            Ox0018     UNUSED
UNUSED0019            Ox0019     UNUSED
UNUSED001A            Ox001A     UNUSED
UNUSED001B            Ox001B     UNUSED
EEPROG                0x001C     EEPROM programming
EEPROG.CPEN            6   Charge pump enable
EEPROG.ER1             4   Erase select bits 1
EEPROG.ER0             3   Erase select bits 0
EEPROG.LATCH           2   EEPROM latch bit
EEPROG.EERC            1   EEPROM RC oscillator control
EEPROG.EEPGM           0   EEPROM programming power enable
EPROG                 0x001D     EPROM programming
EPROG.ELATCH           2   EPROM latch control
EPROG.EPGM             0   EPROM program control
UNUSED001E            0x001E     UNUSED
RESERV001F            0x001F     RESERVED
ICR1H                 0x0020     Input capture 1 high
ICR1L                 0x0021     Input capture 1 low
OCR1H                 0x0022     Output compare 1 high
OCR1L                 0x0023     Output compare 1 low
ICR2H                 0x0024     Input capture 2 high
ICR2L                 0x0025     Input capture 2 low
OCR2H                 0x0026     Output compare 2 high
OCR2L                 0x0027     Output compare 2 low
CNTH                  0x0028     Timer counter high
CNTL                  0x0029     Timer counter low
ACNTH                 0x002A     Alternate counter high
ACNTL                 0x002B     Alternate counter low
TCR1                  0x002C     Timer control 1
TCR1.IC1IE             7   Input capture 1 interrupt enable
TCR1.IC2IE             6   Input capture 2 interrupt enable
TCR1.OC1IE             5   Output compare 1 interrupt enable
TCR1.TOIE              4   Timer overflow interrupt enable
TCR1.CO1E              3   Timer compare 1 output enable
TCR1.IEDG1             2   Input edge 1
TCR1.IEDG2             1   Input edge 2
TCR1.OLVL1             0   Output level 1
TCR2                  0x002D     Timer control 2
TCR2.OC2IE             5   Output compare 2 interrupt enable
TCR2.CO2E              3   Timer compare 2 output enable
TCR2.OLVL2             0   Output level 2
TSR                   0x002E     Timer status
TSR.IC1F               7   Input capture 1 flag
TSR.IC2F               6   Input capture 2 flag
TSR.OC1F               5   Output compare 1 flag
TSR.TOF                4   Timer overflow status flag
TSR.TCAP1              3   Timer capture 1 flag
TSR.TCAP2              2   Timer capture 2 flag
TSR.OC2F               1   Output compare 2 flag
UNUSED002F            0x002F     UNUSED
UNUSED0030            0x0030     UNUSED
UNUSED0031            0x0031     UNUSED
UNUSED0032            0x0032     UNUSED
UNUSED0033            0x0033     UNUSED
UNUSED0034            0x0034     UNUSED
UNUSED0035            0x0035     UNUSED
UNUSED0036            0x0036     UNUSED
UNUSED0037            0x0037     UNUSED
UNUSED0038            0x0038     UNUSED
UNUSED0039            0x0039     UNUSED
UNUSED003A            0x003A     UNUSED
UNUSED003B            0x003B     UNUSED
UNUSED003C            0x003C     UNUSED
UNUSED003D            0x003D     UNUSED
UNUSED003E            0x003E     UNUSED
UNUSED003F            0x003F     UNUSED


.68HC705F8
; MC68HC05F8D/H  http://
; MC68HC05F8D.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR		0x0000:0x0040
area DATA RAM		0x0040:0x0180
area BSS  UNUSED	0x0180:0xDE00
area DATA _EPROM_	0xDE00:0xFE00
area DATA BOOT_VEC	0xFE00:0xFFF0
area DATA USER_VEC	0xFFF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       Reset 
interrupt SWI 		0xFFFC       Software 
interrupt IRQ 		0xFFFA       External Interrupt 
interrupt TIMER_B 	0xFFF8       TIMER B
interrupt TIMER_A 	0xFFF6       TIMER A
interrupt SPI 		0xFFF4       SPI Interrupt 
interrupt MANCD 	0xFFF2       Manchester Coder
interrupt KB 		0xFFF0       Keyboard 


; INPUT/ OUTPUT PORTS
PORTA          0x0000     Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001     Part B data
PORTB.PB7       7   Port C Data Bits 7
PORTB.PB6       6   Port C Data Bits 6
PORTB.PB5       5   Port C Data Bits 5
PORTB.PB4       4   Port C Data Bits 4
PORTB.PB3       3   Port C Data Bits 3
PORTB.PB2       2   Port C Data Bits 2
PORTB.PB1       1   Port C Data Bits 1
PORTB.PB0       0   Port C Data Bits 0
PORTC          0x0002     Port C data
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
PORTD          0x0003     Port D data
PORTD.PD7       7   Port D Data Bits 7
PORTD.PD6       6   Port D Data Bits 6
PORTD.PD5       5   Port D Data Bits 5
PORTD.PD4       4   Port D Data Bits 4
PORTD.PD3       3   Port D Data Bits 3
PORTD.PD2       2   Port D Data Bits 2
PORTD.PD1       1   Port D Data Bits 1
PORTD.PD0       0   Port D Data Bits 0
PORTE          0x0004     Port E data
PORTE.PE7       7   Port E Data Bits 7
PORTE.PE6       6   Port E Data Bits 6
PORTE.PE5       5   Port E Data Bits 5
PORTE.PE4       4   Port E Data Bits 4
PORTE.PE3       3   Port E Data Bits 3
PORTE.PE2       2   Port E Data Bits 2
PORTE.PE1       1   Port E Data Bits 1
PORTE.PE0       0   Port E Data Bits 0
PORTF          0x0005     Port F data
PORTF.PF7       7   Port F Data Bits 7
PORTF.PF6       6   Port F Data Bits 6
PORTF.PF5       5   Port F Data Bits 5
PORTF.PF4       4   Port F Data Bits 4
PORTF.PF3       3   Port F Data Bits 3
PORTF.PF2       2   Port F Data Bits 2
PORTF.PF1       1   Port F Data Bits 1
PORTF.PF0       0   Port F Data Bits 0
PORTG          0x0006     Port G data
PORTG.PG1       1   Port G Data Bits 1
PORTG.PG0       0   Port G Data Bits 0
DDRA           0x0007     Port A data direction
DDRA.DDR7       7   Data Direction for Port A Bit 7
DDRA.DDR6       6   Data Direction for Port A Bit 6
DDRA.DDR5       5   Data Direction for Port A Bit 5
DDRA.DDR4       4   Data Direction for Port A Bit 4
DDRA.DDR3       3   Data Direction for Port A Bit 3
DDRA.DDR2       2   Data Direction for Port A Bit 2
DDRA.DDR1       1   Data Direction for Port A Bit 1
DDRA.DDR0       0   Data Direction for Port A Bit 0
DDRB           0x0008     Port B data direction
DDRB.DDR7       7   Data Direction for Port B Bit 7
DDRB.DDR6       6   Data Direction for Port B Bit 6
DDRB.DDR5       5   Data Direction for Port B Bit 5
DDRB.DDR4       4   Data Direction for Port B Bit 4
DDRB.DDR3       3   Data Direction for Port B Bit 3
DDRB.DDR2       2   Data Direction for Port B Bit 2
DDRB.DDR1       1   Data Direction for Port B Bit 1
DDRB.DDR0       0   Data Direction for Port B Bit 0
DDRC           0x0009     Port C data direction
DDRC.DDR7       7   Data Direction for Port C Bit 7
DDRC.DDR6       6   Data Direction for Port C Bit 6
DDRC.DDR5       5   Data Direction for Port C Bit 5
DDRC.DDR4       4   Data Direction for Port C Bit 4
DDRC.DDR3       3   Data Direction for Port C Bit 3
DDRC.DDR2       2   Data Direction for Port C Bit 2
DDRC.DDR1       1   Data Direction for Port C Bit 1
DDRC.DDR0       0   Data Direction for Port C Bit 0
DDRD           0x000A     Port D data direction
DDRD.DDR7       7   Data Direction for Port D Bit 7
DDRD.DDR6       6   Data Direction for Port D Bit 6
DDRD.DDR5       5   Data Direction for Port D Bit 5
DDRD.DDR4       4   Data Direction for Port D Bit 4
DDRD.DDR3       3   Data Direction for Port D Bit 3
DDRD.DDR2       2   Data Direction for Port D Bit 2
DDRD.DDR1       1   Data Direction for Port D Bit 1
DDRD.DDR0       0   Data Direction for Port D Bit 0
DDRE           0x000B     Port E data direction
DDRE.DDR7       7   Data Direction for Port E Bit 7
DDRE.DDR6       6   Data Direction for Port E Bit 6
DDRE.DDR5       5   Data Direction for Port E Bit 5
DDRE.DDR4       4   Data Direction for Port E Bit 4
DDRE.DDR3       3   Data Direction for Port E Bit 3
DDRE.DDR2       2   Data Direction for Port E Bit 2
DDRE.DDR1       1   Data Direction for Port E Bit 1
DDRE.DDR0       0   Data Direction for Port E Bit 0
DDRF           0x000C     Port F data direction
DDRF.DDR7       7   Data Direction for Port F Bit 7
DDRF.DDR6       6   Data Direction for Port F Bit 6
DDRF.DDR5       5   Data Direction for Port F Bit 5
DDRF.DDR4       4   Data Direction for Port F Bit 4
DDRF.DDR3       3   Data Direction for Port F Bit 3
DDRF.DDR2       2   Data Direction for Port F Bit 2
DDRF.DDR1       1   Data Direction for Port F Bit 1
DDRF.DDR0       0   Data Direction for Port F Bit 0
DDRG           0x000D     Port G data direction
DDRG.DDR1       1   Data Direction for Port G Bit 1
DDRG.DDR0       0   Data Direction for Port G Bit 0
UNUSED000E     0x000E     UNUSED
UNUSED000F     0x000F     UNUSED
SPCR           0x0010     SPI control
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral Enable
SPCR.MSTR       4   Master Bit
SPSR           0x0011     SPI status
SPSR.SPIF       7   Serial Peripheral Interface Flag
SPSR.DCOL       6   Data Collision
SPDR           0x0012     SPI data I_O
SPDR.SPDR7      7
SPDR.SPDR6      6
SPDR.SPDR5      5
SPDR.SPDR4      4
SPDR.SPDR3      3
SPDR.SPDR2      2
SPDR.SPDR1      1
SPDR.SPDR0      0
FCR            0x0013     Row frequency control
FCR.FCR4        4
FCR.FCR3        3
FCR.FCR2        2
FCR.FCR1        1
FCR.FCR0        0
FCC            0x0014     Column frequency control
FCC.FCC4        4
FCC.FCC3        3
FCC.FCC2        2
FCC.FCC1        1
FCC.FCC0        0
TNCR           0x0015     Tone control
TNCR.MS1        7   Mode Select 1
TNCR.MS0        6   Mode Select 0
TNCR.TGER       5   Tone Generation Enable for Row Paths
TNCR.TGEC       4   Tone Generation Enable for Column Paths
EE             0x0016     Event enable
EE.TIMH         7   Timer A Enable/Disable
EE.INTE1        6   External interrupt IRQ1 enabled/disabled 1
EE.INTE2        5   External interrupt IRQ1 enabled/disabled 2
Miscel         0x0017     Miscellaneous
Miscel.POR      7
Miscel.INTF1    6
Miscel.INTF2    5
Miscel.KEYF     4
TAC            0x0018     Timer A control
TAC.ICIE        7   Input Capture Interrupt Enable
TAC.OCIE        6   Output Compare Interrupt Enable
TAC.TOIE        5   Timer Overflow Interrupt Enable
TAC.IEDG        1   Input Edge
TAC.OLVL        0   Output Level Voltage Latch
TAS            0x0019     Timer A status
TAS.ICF         7   Input Capture Flag
TAS.OCF         6   Output Compare Flag
TAS.TOF         5   Timer Overflow Flag
TAICH          0x001A     Timer A input capture high
TAICL          0x001B     Timer A input capture low
TAOCH          0x001C     Timer A output compare high
TAOCL          0x001D     Timer A output compare low
TACH           0x001E     Timer A counter high
TACL           0x001F     Timer A counter low
TAACH          0x0020     Timer A alternative counter high
TAACL          0x0021     Timer A alternative counter low
TBC            0x0022     Timer B control
TBC.TMBE        7   Timer B Enable/Disable
TBC.TBOIE       6   Timer B Time-out Interrupt Enable/Disable
TBC.TCSB1       2   Timer B Clock Frequency Select 1
TBC.TCSB0       1   Timer B Clock Frequency Select 0
TBC.TUF         0   Timer B Underflow Flag
TBPCH          0x0023     Timer B preset counter high
TBPCL          0x0024     Timer B preset counter low
TBCH           0x0025     Timer B counter high
TBCL           0x0026     Timer B counter low
TBACH          0x0027     Timer B alternative counter high
TBACL          0x0028     Timer B alternative counter low
UNUSED0029     0x0029     UNUSED
UNUSED002A     0x002A     UNUSED
MCC            0x002B     Manchester coder control
MCC.NCE         7   Encoder Enable Bit
MCC.NIE         6   Encoder Interrupt Enable Bit
MCC.CIE         5   Encoding Complete Interrupt Enable Bit
MCC.DCE         4   Decoder Enable
MCC.DIE         3   Decode Interrupt Enable
MCC.BR1         1   Bit Rate Select 1
MCC.BR0         0   Bit Rate Select 0
MCS            0x002C     Manchester coder status
MCS.NCM         7   Encoder Data Register Empty Flag
MCS.NCC         6   Encoding Completion Flag
MCS.DCF         5   Decoder Data Register Full Flag
MCS.OVF         4   Overrun Flag
MED            0x002D     Manchester encoder data
MDD            0x002E     Manchester decoder data
UNUSED002F     0x002F     UNUSED
Reserv0030     0x0030     Reserved
UNUSED0031     0x0031     UNUSED
UNUSED0032     0x0032     UNUSED
UNUSED0033     0x0033     UNUSED
KC             0x0034     Keyboard control
KC.KEYE         7
KC.KEYX7        3
KC.KEYX6        2
KC.KEYX5        1
KC.KEYX4        0
SO             0x0035     System option
SO.TCSA1        6
SO.TCSA0        5
SO.INTN1        4
SO.INTN2        3
WTC            0x0036     Watchdog timer control
WTC.WDTE        7   Watchdog Timer Enable/Disable
WTC.KWDT        6   Kill Watchdog Timer Bit
WTC.WDTOF       5   Watchdog Timer Time-out Flag
WTC.WDT1        1   Time-out Period Select 1
WTC.WDT0        0   Time-out Period Select 0
UNUSED0037     0x0037     UNUSED
UNUSED0038     0x0038     UNUSED
UNUSED0039     0x0039     UNUSED
UNUSED003A     0x003A     UNUSED
UNUSED003B     0x003B     UNUSED
Reserv003C     0x003C     Reserved
Reserv003D     0x003D     Reserved
UNUSED003E     0x003E     UNUSED
EPROM          0x003F     EPROM programming control
EPROM.LAT       1   Latch EPROM Data and Address
EPROM.EPGM      0   EPROM Programming Mode Enable


.68HC705H12
; HC05H12GRS/D  http://
; HC05H12GRS.pdf

; RAM=256
; ROM=12032
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR         0x0000:0x0050
area DATA RAM         0x0050:0x0150
area BSS  RESERVED    0x0150:0x0400
area DATA EEPROM      0x0400:0x0500
area BSS  RESERVED    0x0500:0x1000
area DATA ROM         0x1000:0x3F00
area DATA BootROM     0x3F00:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Reset  
interrupt SWI               0x3FFC      SWI               
interrupt KEY               0x3FFA      KEY       
interrupt CTimer            0x3FF8              
interrupt TIMER_1           0x3FF6      Timer1
interrupt TIMER_2           0x3FF4      Timer2
interrupt SPI               0x3FF2      SPI
interrupt SCI               0x3FF0      SCI


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Data
PORTD.PD3              7   Port D Data Bits 3
PORTD.PD2              6   Port D Data Bits 2
PORTD.PD1              5   Port D Data Bits 1
PORTD.PD0              4   Port D Data Bits 0
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
PCC                   0x0007     Port C Control
PCC.TCMP1              5
PCC.TCMP0              4
CTSCR                 0x0008     Core Timer Control/Status
CTSCR.TOF              7   Timer Over Flow
CTSCR.RTIF             6   Real Time Interrupt Flag
CTSCR.TOFE             5   Timer Over Flow Enable
CTSCR.RTIE             4   Real Time Interrupt Enable
CTSCR.RTOF             3   Reset Timer Overflow Flag
CTSCR.RTIF             2   Reset Real Time Interrupt Flag
CTSCR.RT1              1   Real Time Interrupt Rate Select 1
CTSCR.RT0              0   Real Time Interrupt Rate Select 0
CTCR                  0x0009     Core Timer Counter
UNUSED000A            0x000A     UNUSED
UNUSED000B            0x000B     UNUSED
UNUSED000C            0x000C     UNUSED
PAIED                 0x000D     Port A Interrupt Edge
PAIED.EDGE7            7   Port A Interrupt Edge 7
PAIED.EDGE6            6   Port A Interrupt Edge 6
PAIED.EDGE5            5   Port A Interrupt Edge 5
PAIED.EDGE4            4   Port A Interrupt Edge 4
PAIED.EDGE3            3   Port A Interrupt Edge 3
PAIED.EDGE2            2   Port A Interrupt Edge 2
PAIED.EDGE1            1   Port A Interrupt Edge 1
PAIED.EDGE0            0   Port A Interrupt Edge 0
PAICR                 0x000E     Port A Interrupt Control
PAICR.PAIE7            7   Port A Interrupt Enable 7
PAICR.PAIE6            6   Port A Interrupt Enable 6
PAICR.PAIE5            5   Port A Interrupt Enable 5
PAICR.PAIE4            4   Port A Interrupt Enable 4
PAICR.PAIE3            3   Port A Interrupt Enable 3
PAICR.PAIE2            2   Port A Interrupt Enable 2
PAICR.PAIE1            1   Port A Interrupt Enable 1
PAICR.PAIE0            0   Port A Interrupt Enable 0
PAISR                 0x000F     Port A Interrupt Status
PAISR.PAIF7            7   Port A Interrupt Flags 7
PAISR.PAIF6            6   Port A Interrupt Flags 6
PAISR.PAIF5            5   Port A Interrupt Flags 5
PAISR.PAIF4            4   Port A Interrupt Flags 4
PAISR.PAIF3            3   Port A Interrupt Flags 3
PAISR.PAIF2            2   Port A Interrupt Flags 2
PAISR.PAIF1            1   Port A Interrupt Flags 1
PAISR.PAIF0            0   Port A Interrupt Flags 0
PWMD0                 0x0010     PWM Data 0
PWMD1                 0x0011     PWM Data 1
PWMD2                 0x0012     PWM Data 2
PWMD3                 0x0013     PWM Data 3
PWMD4                 0x0014     PWM Data 4
PWMD5                 0x0015     PWM Data 5
PWMD6                 0x0016     PWM Data 6
PWMD7                 0x0017     PWM Data 7
PWMCTL                0x0018     PWM Control/Sign
PWMCTL.PWMRS           7   PWM Reset                
PWMCTL.PWMC3           6   PWM Clock Rate 3         
PWMCTL.PWMC2           5   PWM Clock Rate 2         
PWMCTL.PWMC1           4   PWM Clock Rate 1         
PWMCTL.SIGN3           3   Sign of the PWM Channel 3
PWMCTL.SIGN2           2   Sign of the PWM Channel 2
PWMCTL.SIGN1           1   Sign of the PWM Channel 1
PWMCTL.SIGN0           0   Sign of the PWM Channel 0
PWMEN                 0x0019     PWM Channel Enable
PWMEN.PWME7            7   PWM Channel Enable 7
PWMEN.PWME6            6   PWM Channel Enable 6
PWMEN.PWME5            5   PWM Channel Enable 5
PWMEN.PWME4            4   PWM Channel Enable 4
PWMEN.PWME3            3   PWM Channel Enable 3
PWMEN.PWME2            2   PWM Channel Enable 2
PWMEN.PWME1            1   PWM Channel Enable 1
PWMEN.PWME0            0   PWM Channel Enable 0
PWMPOL                0x001A     PWM Channel Polarity
PWMPOL.PPOL7           7   PWM Polarity 7
PWMPOL.PPOL6           6   PWM Polarity 6
PWMPOL.PPOL5           5   PWM Polarity 5
PWMPOL.PPOL4           4   PWM Polarity 4
PWMPOL.PPOL3           3   PWM Polarity 3
PWMPOL.PPOL2           2   PWM Polarity 2
PWMPOL.PPOL1           1   PWM Polarity 1
PWMPOL.PPOL0           0   PWM Polarity 0
UNUSED001B            0x001B     UNUSED
EEPCR                 0x001C     EEPROM Control
EEPCR.EEOSC            4   EEPROM RC Oscillator Control
EEPCR.ER1              3   Erase Select Bits 1
EEPCR.EER0             2   Erase Select Bits 0
EEPCR.EELAT            1   EEPROM Programming Latch
EEPCR.EEPGM            0   EEPROM Programming Power Enable
EPROG                 0x001D     EPROM Programming Register (MC68HC705H12)
EPROG.ELAT             2   EPROM Latch Control
EPROG.EPGM             0   EPROM Program Control
UNUSED001E            0x001E     UNUSED
TEST                  0x001F     TEST
T1IC1H                0x0020     Timer 1 Input Capture1 High
T1IC1L                0x0021     Timer 1 Input Capture1 Low
T1OC1H                0x0022     Timer 1 Output Compare1 High
T1OC1L                0x0023     Timer 1 Output Compare1 Low
T1IC2H                0x0024     Timer 1 Input Capture2 High
T1IC2L                0x0025     Timer 1 Input Capture2 Low
T1OC2H                0x0026     Timer 1 Output Compare2 High
T1OC2L                0x0027     Timer 1 Output Compare2 Low
T1CH                  0x0028     Timer 1 Counter High
T1CL                  0x0029     Timer 1 Counter Low
T1ACH                 0x002A     Timer 1 Alternate Counter High
T1ACL                 0x002B     Timer 1 Alternate Counter Low
T1C1                  0x002C     Timer 1 Control 1
T1C1.ICI1E             7   Input Capture 1 Interrupt Enable
T1C1.ICI2E             6   Input Capture 2 Interrupt Enable
T1C1.OCI1E             5   Output Compare 1 Interrupt Enable
T1C1.TOIE              4   Timer Overflow Interrupt Enable
T1C1.CO1E              3   Timer Compare 1 Output Enable
T1C1.IEDG1             2   Input Edge 1
T1C1.IEDG2             1   Input Edge 2
T1C1.OLVL1             0   Output Level 1
T1C2                  0x002D     Timer 1 Control 2
T1C2.OC2IE             5   Output Compare 2 Interrupt Enable
T1C2.CO2E              3   Timer Compare 2 Output Enable
T1C2.OLVL2             0   Output Level 2
T1S                   0x002E     Timer 1 Status
T1S.IC1F               7   Input Capture 1 Flag
T1S.IC2F               6   Input Capture 2 Flag
T1S.OC1F               5   Output Compare 1 Flag
T1S.TOF                4   Timer Overflow Flag
T1S.TCAP1              3   Timer Capture 1
T1S.TCAP2              2   Timer Capture 2
T1S.OC2F               1   Output Compare 2 Flag
UNUSED002F            0x002F     UNUSED
T2IC1H                0x0030     Timer 2 Input Capture1 High
T2IC1L                0x0031     Timer 2 Input Capture1 Low
T2OC1H                0x0032     Timer 2 Output Compare1 High
T2OC1L                0x0033     Timer 2 Output Compare1 Low
T2IC2H                0x0034     Timer 2 Input Capture2 High
T2IC2L                0x0035     Timer 2 Input Capture2 Low
T2OC2H                0x0036     Timer 2 Output Compare2 High
T2OC2L                0x0037     Timer 2 Output Compare2 Low
T2CH                  0x0038     Timer 2 Counter High
T2CL                  0x0039     Timer 2 Counter Low
T2ACH                 0x003A     Timer 2 Alternate Counter High
T2ACL                 0x003B     Timer 2 Alternate Counter Low
T2C1                  0x003C     Timer 2 Control 1
T2C1.ICI1E             7
T2C1.ICI2E             6
T2C1.OCI1E             5
T2C1.TOIE              4
T2C1.CO1E              3
T2C1.IEDG1             2
T2C1.IEDG2             1
T2C1.OLVL1             0
T2C2                  0x003D     Timer 2 Control 2
T2C2.OC2IE             5
T2C2.CO2E              3
T2C2.OLVL2             0
T2S                   0x003E     Timer 2 Status
T2S.IC1F               7
T2S.IC2F               6
T2S.OC1F               5
T2S.TOF                4
T2S.TCAP1              3
T2S.TCAP2              2
T2S.OC2F               1
UNUSED003F            0x003F     UNUSED
PORTE                 0x0040     Port E Data
PORTE.PE7              7   Port E Data Bits 7
PORTE.PE6              6   Port E Data Bits 6
PORTE.PE5              5   Port E Data Bits 5
PORTE.PE4              4   Port E Data Bits 4
PORTE.PE3              3   Port E Data Bits 3
PORTE.PE2              2   Port E Data Bits 2
PORTE.PE1              1   Port E Data Bits 1
PORTE.PE0              0   Port E Data Bits 0
PORTEM                0x0041     Port E Mismatch
PORTF                 0x0042     Port F Data
PORTF.PF3              3   Port F Data Bits 3
PORTF.PF2              2   Port F Data Bits 2
PORTF.PF1              1   Port F Data Bits 1
PORTF.PF0              0   Port F Data Bits 0
PORTFM                0x0043     Port F Mismatch
SPIC                  0x0044     SPI Control
SPIC.SPIE              7   SPI Interrupt Enable
SPIC.SPE               6   SPI System Enable
SPIC.DOD               5   Direction of Data Flow (in or out of the Serial Shift Register)
SPIC.MSTR              4   Master/Slave Mode Select
SPIC.CPOL              3   Clock Polarity
SPIC.CPHA              2   Clock Phase
SPIC.SPR1              1   SPI Clock Rate Selects 1
SPIC.SPR0              0   SPI Clock Rate Selects 0
SPIS                  0x0045     SPI Status
SPIS.SPIF              7   SPI Interrupt Request Flag
SPIS.WCOL              6   Write Collision
SPID                  0x0046     SPI Data
SCID                  0x0047     SCI Data
SCIC1                 0x0048     SCI Control 1
SCIC1.R8               7   Receive Data Bit 8
SCIC1.T8               6   Transmit Data Bit 8
SCIC1.M                4   Mode (Select Character Format)
SCIC1.WAKE             3   Wake-up Mode Select
SCIC2                 0x0049     SCI Control 2
SCIC2.TIE              7   Transmit Interrupt Enable
SCIC2.TCIE             6   Transmit Complete Interrupt Enable
SCIC2.RIE              5   Receiver Interrupt Enable
SCIC2.ILIE             4   Idle Line Interrupt Enable
SCIC2.TE               3   Transmitter Enable
SCIC2.RE               2   Receiver Enable
SCIC2.RWU              1   Receiver Wake-up
SCIC2.SBK              0   Send Break
SCIS                  0x004A     SCI Status
SCIS.TDRE              7   Transmit Data Register Empty Flag
SCIS.TC                6   Transmit Complete Flag
SCIS.RDRF              5   Receive Data Register Full Flag
SCIS.IDLE              4   Idle Line Detected Flag
SCIS.OR                3   Overrun Error Flag
SCIS.NF                2   Noise Error Flag
SCIS.FE                1   Framing Error Flag
SCIB                  0x004B     SCI BAUD
SCIB.TCLR              7   Clear Baud Rate Counters (for test purposes only)
SCIB.SPP               6   SPI Prescaler bit
SCIB.SCP1              5   First Serial Prescaler Select bits 1
SCIB.SCP0              4   First Serial Prescaler Select bits 0
SCIB.RCKB              3   SCI Receive Baud Rate Clock Test
SCIB.SCR2              2   SCI Rate Select bits of the second prescaler stage 2
SCIB.SCR1              1   SCI Rate Select bits of the second prescaler stage 1
SCIB.SCR0              0   SCI Rate Select bits of the second prescaler stage 0
UNUSED004C            0x004C     UNUSED
SC                    0x004D     System Control
SC.SC                  4   System Clock Option
SC.IRQ                 3   IRQ Sensitivity
SC.ECLK                0   Internal System Clock Available
ADD                   0x004E     A_D Data
ADSC                  0x004F     A_D Status_Control
ADSC.COCO              7   Conversions Complete
ADSC.ADRC              6   RC Oscillator On
ADSC.ADON              5   A/D On
ADSC.CH3               3   Channel Select Bit 3
ADSC.CH2               2   Channel Select Bit 2
ADSC.CH1               1   Channel Select Bit 1
ADSC.CH0               0   Channel Select Bit 0


.68HC705J1A
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705J1A&nodeId=01M98633
; MC68HC705J1A.pdf

; RAM=64
; ROM=0
; EPROM=1.2K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x00C0
area DATA RAM         0x00C0:0x0100
area BSS  UNUSED      0x0100:0x0300
area CODE EPROM       0x0300:0x07D0
area BSS  UNUSED      0x07D0:0x07EE
area DATA TES_TROM    0x07EE:0x07F0
area DATA USER_VEC    0x07F0:0x0800


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Processor reset
interrupt SWI               0x07FC      Software interrupt
interrupt EI                0x07FA      External Interrupt
interrupt TIMER_In          0x07F8      Timer Interupt


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
UNUSED0002            0x0002    UNUSED
UNUSED0003            0x0003    UNUSED
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
UNUSED0006            0x0006    UNUSED
UNUSED0007            0x0007    UNUSED
TSCR                  0x0008  Timer Status and Control
TSCR.TOF               7   Timer Overflow Flag
TSCR.RTIF              6   Real-Time Interrupt Flag
TSCR.TOIE              5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE              4   Real-Time Interrupt Enable Bit
TSCR.TOFR              3   Timer Overflow Flag Reset Bit
TSCR.RTIFR             2   Real-Time Interrupt Flag Reset Bit
TSCR.RT1               1   Real-Time Interrupt Select Bits 1
TSCR.RT0               0   Real-Time Interrupt Select Bits 0
TCR                   0x0009  Timer Counter
TCR.TMR7               7
TCR.TMR6               6
TCR.TMR5               5
TCR.TMR4               4
TCR.TMR3               3
TCR.TMR2               2
TCR.TMR1               1
TCR.TMR0               0
ISCR                  0x000A  IRQ Status and Control
ISCR.IRQE              7   External Interrupt Request Enable Bit
ISCR.IRQF              3   External Interrupt Request Flag
ISCR.IRQR              1   Interrupt Request Reset Bit
UNUSED000B            0x000B    UNUSED
UNUSED000C            0x000C    UNUSED
UNUSED000D            0x000D    UNUSED
UNUSED000E            0x000E    UNUSED
UNUSED000F            0x000F    UNUSED
PDRA                  0x0010    Pulldown Register Port A
PDRA.PDIA7             7   Pulldown Inhibit A Bits 7
PDRA.PDIA6             6   Pulldown Inhibit A Bits 6
PDRA.PDIA5             5   Pulldown Inhibit A Bits 5
PDRA.PDIA4             4   Pulldown Inhibit A Bits 4
PDRA.PDIA3             3   Pulldown Inhibit A Bits 3
PDRA.PDIA2             2   Pulldown Inhibit A Bits 2
PDRA.PDIA1             1   Pulldown Inhibit A Bits 1
PDRA.PDIA0             0   Pulldown Inhibit A Bits 0
PDRB                  0x0011     Pulldown Register Port B
PDRB.PDIB5             5   Pulldown Inhibit B Bits 5
PDRB.PDIB4             4   Pulldown Inhibit B Bits 4
PDRB.PDIB3             3   Pulldown Inhibit B Bits 3
PDRB.PDIB2             2   Pulldown Inhibit B Bits 2
PDRB.PDIB1             1   Pulldown Inhibit B Bits 1
PDRB.PDIB0             0   Pulldown Inhibit B Bits 0
UNUSED0012            0x0012    UNUSED
UNUSED0013            0x0013    UNUSED
UNUSED0014            0x0014    UNUSED
UNUSED0015            0x0015    UNUSED
UNUSED0016            0x0016    UNUSED
UNUSED0017            0x0017    UNUSED
EPROG                 0x0018    EPROM Programming
EPROG.ELAT             2   EPROM Bus Latch Bit
EPROG.MPGM             1   MOR Programming Bit
EPROG.EPGM             0   EPROM Programming Bit
UNUSED0019            0x0019    UNUSED
UNUSED001A            0x001A    UNUSED
UNUSED001B            0x001B    UNUSED
UNUSED001C            0x001C    UNUSED
UNUSED001D            0x001D    UNUSED
UNUSED001E            0x001E    UNUSED
RESERV001F            0x001F    RESERVED
COPR                  0x07F0    COP Register
COPR.COPC              0   COP Clear Bit
MOR                   0x07F1    Mask Options
MOR.SOSCD              7   Short Oscillator Delay Bit
MOR.EPMSEC             6   EPROM Security Bit
MOR.OSCRES             5   Oscillator Internal Resistor Bit
MOR.SWAIT              4   Stop-to-Wait Conversion Bit
MOR.PDI                3   Software Pulldown Inhibit Bit
MOR.PIRQ               2   Port A External Interrupt Bit
MOR.LEVEL              1   External Interrupt Sensitivity Bit
MOR.COPEN              0   COP Enable Bit
RESERV07F2            0x07F2    RESERVED
RESERV07F3            0x07F3    RESERVED
RESERV07F4            0x07F4    RESERVED
RESERV07F5            0x07F5    RESERVED
RESERV07F6            0x07F6    RESERVED
RESERV07F7            0x07F7    RESERVED


.68HC705J2
; MC68HC705J2/D  http://
; MC68HC705J2.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area BSS  UNUSED	0x0020:0x0090
area DATA SRAM		0x0090:0x0100
area BSS  UNUSED	0x0100:0x0700
area DATA EPROM		0x0700:0x0F00
area DATA MASK_OPTION	0x0F00:0x0F01
area DATA BOOT_ROM	0x0F01:0x0FF0
area DATA USER_VEC	0x0FF0:0x1000


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       Reset 
interrupt SWI 		0x0FFC       software interrupt vector
interrupt IRQ 		0x0FFA       external interrupt vector
interrupt TIMER 	0x0FF8       timer interrupt vector


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001     Port B
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
UNUSED0002      0x0002     UNUSED
UNUSED0003      0x0003     UNUSED
DDRA            0x0004     Port A data direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005     Port B data direction
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
UNUSED0006      0x0006     UNUSED
UNUSED0007      0x0007     UNUSED
TCSR            0x0008     TIMER CONTROL AND STATUS REGISTER
TCSR.TOF         7   Timer Overflow Flag                
TCSR.RTIF        6   Real-Time Interrupt Flag           
TCSR.TOIE        5   Timer Overflow Interrupt Enable Bit
TCSR.RTIE        4   Real-Time Interrupt Enable Bit     
TCSR.RT1         1   Real-Time Interrupt Select Bits 1
TCSR.RT0         0   Real-Time Interrupt Select Bits 0
TCR             0x0009     TIMER COUNTER REGISTER
UNUSED000A      0x000A     UNUSED
UNUSED000B      0x000B     UNUSED
UNUSED000C      0x000C     UNUSED
UNUSED000D      0x000D     UNUSED
UNUSED000E      0x000E     UNUSED
UNUSED000F      0x000F     UNUSED
UNUSED0010      0x0010     UNUSED
UNUSED0011      0x0011     UNUSED
UNUSED0012      0x0012     UNUSED
UNUSED0013      0x0013     UNUSED
UNUSED0014      0x0014     UNUSED
UNUSED0015      0x0015     UNUSED
UNUSED0016      0x0016     UNUSED
UNUSED0017      0x0017     UNUSED
UNUSED0018      0x0018     UNUSED
UNUSED0019      0x0019     UNUSED
UNUSED001A      0x001A     UNUSED
UNUSED001B      0x001B     UNUSED
PROG            0x001C     EPROM PROGRAMMING REGISTER
PROG.LATCH       2   EPROM Bus Latch
PROG.EPGM        0   EPROM Programming
UNUSED001D      0x001D     UNUSED
UNUSED001E      0x001E     UNUSED
UNUSED001F      0x001F     UNUSED
MOR             0x0F00     Mask Option Register
MOR.J1           2   MC68HC05J1 Emulation Mode Select
MOR.IRQ          1   Interrupt Request
MOR.COP          0   COP Timer Enable
COP             0x0FF0     COP Control Register
COP.COPR         0   COP Reset


.68HC705J5A
; http://
; HC05J5AGRS.pdf

; RAM=128
; ROM=0K
; EPROM=2.5K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x0080
area DATA RAM         0x0080:0x0100
area BSS  UNUSED      0x0100:0x0200
area DATA FSR_2       0x0200:0x0202
area BSS  UNUSED      0x0202:0x0300
area DATA EPROM       0x0300:0x0D00
area BSS  UNUSED      0x0D00:0x0E00
area DATA BOOT_ROM    0x0E00:0x0FF0
area DATA USER_VEC    0x0FF0:0x1000


; Interrupt and reset vector assignments
interrupt __RESET           0x0FFE      Reset  
interrupt SWI               0x0FFC      SWI               
interrupt IRQ               0x0FFA      IRQ/IRQ2        
interrupt MFT               0x0FF8      MFT         
interrupt Timer1            0x0FF6      Timer1 Interrupt


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001    Port B data
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
T1CC           0x0002   Timer Capture Control
T1CC.TCAPS      7   Timer Input Capture Comparator Enable
UNUSED0003     0x0003   UNUSED
DDRA           0x0004   Port A data direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005   Port B data direction
DDRB.SLOWEA     7   Slow Transition Enable
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
UNUSED0006     0x0006   UNUSED
UNUSED0007     0x0007   UNUSED
TCSR           0x0008  MFT Ctrl/Status
TCSR.TOF        7   Timer Overflow Flag
TCSR.RTIF       6   Real Time Interrupt Flag
TCSR.TOFE       5   Timer Overflow Enable
TCSR.RTIE       4   Real Time Interrupt Enable
TCSR.TOFR       3   Timer Overflow Acknowledge
TCSR.RTIFR      2   Real Time Interrupt Acknowledge
TCSR.RT1        1   Real Time Interrupt Rate Select 1
TCSR.RT0        0   Real Time Interrupt Rate Select 0
TCR            0x0009   MFT Counter
TCR.TMR7        7
TCR.TMR6        6
TCR.TMR5        5
TCR.TMR4        4
TCR.TMR3        3
TCR.TMR2        2
TCR.TMR1        1
TCR.TMR0        0
ICSR           0x000A   IRQ Control/Status
ICSR.IRQE       7   IRQ Interrupt Enable
ICSR.IRQE1      6   PA7 Interrupt Enable
ICSR.IRQF       3   IRQ Interrupt Request Flag
ICSR.IRQF1      2   PA7 Interrupt Request Flag
ICSR.IRQR       1   IRQ Interrupt Acknowledge
ICSR.IRQR1      0   PA7 Interrupt Acknowledge
UNUSED000B     0x000B   UNUSED
UNUSED000C     0x000C   UNUSED
UNUSED000D     0x000D   UNUSED
UNUSED000E     0x000E   UNUSED
UNUSED000F     0x000F   UNUSED
PDURA          0x0010    Port A Pull Down/Up
PDURA.PURA7     7
PDURA.PURA6     6
PDURA.PURA5     5
PDURA.PURA4     4
PDURA.PURA3     3
PDURA.PURA2     2
PDURA.PURA1     1
PDURA.PURA0     0
PDURB          0x0011   Port B Pull Down/Up
PDURB.PURB5     5
PDURB.PURB4     4
PDURB.PURB3     3
PDURB.PURB2     2
PDURB.PURB1     1
PDURB.PURB0     0
T1CR           0x0012    Timer1 Control
T1CR.ICIE       7   INPUT CAPTURE INTERRUPT ENABLE
T1CR.T1OIE      5   TIMER OVERFLOW INTERRUPT ENABLE
T1CR.IEDGE      1   INPUT CAPTURE EDGE SELECT
T1SR           0x0013    Timer1 Status
T1SR.ICF        7   INPUT CAPTURE FLAG
T1SR.T1OF       5   TIMER1 OVERFLOW FLAG
ICH            0x0014    Input Capture High
ICL            0x0015    Input Capture Low
UNUSED0016     0x0016    UNUSED
UNUSED0017     0x0017    UNUSED
TCNTH          0x0018    Timer1 Counter High
TCNTL          0x0019    Timer1 Counter Low
ACNTH          0x001A    Alt Counter High
ACNTL          0x001B    Alt Counter Low
UNUSED001C     0x001C    UNUSED
UNUSED001D     0x001D    UNUSED
PCR            0x001E    EPROM Program Control Register
PCR.MORON       2   Mask Option Register ON
PCR.ELAT        1   EPROM LATch control
PCR.PGM         0   EPROM ProGraM command
RESERV001F     0x001F    RESERVED
COP            0x0FF0    COP Watchdog Timer
COP.COPR        0
RESERV0FF1     0x0FF1    RESERVED
RESERV0FF2     0x0FF2    RESERVED
RESERV0FF3     0x0FF3    RESERVED
RESERV0FF4     0x0FF4    RESERVED
RESERV0FF5     0x0FF5    RESERVED


.68HC705JB2
; HC705JB2GRS/H  http://
; HC705JB2GRS.pdf

; RAM=128
; ROM=0
; EPROM=2048
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area BSS  UNUSED      0x0040:0x0080
area DATA RAM         0x0080:0x0100
area BSS  UNUSED      0x0100:0x01FF
area DATA _MOR_       0x01FF:0x0200
area BSS  UNUSED      0x0200:0x1600
area CODE EPROM       0x1600:0x1E00
area DATA BootROM     0x1E00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      SWI               
interrupt IRQ               0x1FFA      IRQ/IRQ2        
interrupt USB               0x1FF8      USB         
interrupt TIMER1            0x1FF6      Timer1 
interrupt MFT               0x1FF4      MFT


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     PORT A DATA
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     PORT B DATA
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
UNUSED0002            0x0002     UNUSED
UNUSED0003            0x0003     UNUSED
DDRA                  0x0004     PORT A DATA DIR
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     PORT B DATA DIR
DDRB.SLOWE             7   Slow Transition Enable
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
UNUSED0006            0x0006     UNUSED
UNUSED0007            0x0007     UNUSED
TCSR                  0x0008     MFT CONTROL & STATUS
TCSR.TOF               7   Timer Overflow Flag
TCSR.RTIF              6   Real Time Interrupt Flag
TCSR.TOFE              5   Timer Overflow Enable
TCSR.RTIE              4   Real Time Interrupt Enable
TCSR.TOFR              3   Timer Overflow Acknowledge
TCSR.RTIFR             2   Real Time Interrupt Acknowledge
TCSR.RT1               1   Real Time Interrupt period select bits 1
TCSR.RT0               0   Real Time Interrupt period select bits 0
TCNT                  0x0009     MFT COUNTER
TCNT.TMR7              7
TCNT.TMR6              6
TCNT.TMR5              5
TCNT.TMR4              4
TCNT.TMR3              3
TCNT.TMR2              2
TCNT.TMR1              1
TCNT.TMR0              0
ICSR                  0x000A     IRQ CONTROL & STATUS
ICSR.IRQE              7   IRQ Interrupt Enable
ICSR.IRQF              3   IRQ Interrupt Request Flag
ICSR.IRQR              1   IRQ Interrupt Acknowledge
UNUSED000B            0x000B     UNUSED
UNUSED000C            0x000C     UNUSED
UNUSED000D            0x000D     UNUSED
UNUSED000E            0x000E     UNUSED
UNUSED000F            0x000F     UNUSED
PDURA                 0x0010     PORT A PULLDOWN/UP
PDURA.PDRA7            7
PDURA.PDRA6            6
PDURA.PDRA5            5
PDURA.PDRA4            4
PDURA.PDRA3            3
PDURA.PDRA2            2
PDURA.PDRA1            1
PDURA.PDRA0            0
PDURB                 0x0011     PORT B PULLDOWN_UP
PDURB.PURB2            2
PDURB.PURB1            1
PDURB.PURB0            0
TCR                   0x0012     TIMER CONTROL
TCR.ICIE               7   INPUT CAPTURE INTERRUPT ENABLE
TCR.OCIE               6   OUTPUT COMPARE INTERRUPT ENABLE
TCR.TOIE               5   TIMER OVERFLOW INTERRUPT ENABLE
TCR.IEDG               1   INPUT CAPTURE EDGE SELECT
TSR                   0x0013     TIMER STATUS
TSR.ICF                7   INPUT CAPTURE FLAG
TSR.OCF                6   OUTPUT COMPARE FLAG
TSR.TOF                5   TIMER OVERFLOW FLAG
ICH                   0x0014     INPUT CAPTURE HIGH
ICL                   0x0015     INPUT CAPTURE LOW
OCH                   0x0016     OUTPUT COMPARE HIGH
OCL                   0x0017     OUTPUT COMPARE LOW
TCNTH                 0x0018     TIMER HIGH
TCNTL                 0x0019     TIMER LOW
ACNTH                 0x001A     ALT COUNTER HIGH
ACNTL                 0x001B     ALT COUNTER LOW
UNUSED001C            0x001C     UNUSED
UNUSED001D            0x001D     UNUSED
UNUSED001E            0x001E     UNUSED
UNUSED001F            0x001F     UNUSED
UD0R0                 0x0020     USB ENDPOINT0 DATA REG0
UD0R0.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R0.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R0.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R0.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R0.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R0.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R0.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R0.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R1                 0x0021     USB ENDPOINT0 DATA REG1
UD0R1.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R1.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R1.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R1.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R1.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R1.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R1.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R1.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R2                 0x0022     USB ENDPOINT0 DATA REG2
UD0R2.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R2.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R2.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R2.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R2.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R2.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R2.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R2.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R3                 0x0023     USB ENDPOINT0 DATA REG3
UD0R3.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R3.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R3.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R3.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R3.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R3.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R3.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R3.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R4                 0x0024     USB ENDPOINT0 DATA REG4
UD0R4.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R4.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R4.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R4.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R4.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R4.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R4.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R4.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R5                 0x0025     USB ENDPOINT0 DATA REG5
UD0R5.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R5.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R5.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R5.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R5.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R5.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R5.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R5.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R6                 0x0026     USB ENDPOINT0 DATA REG6
UD0R6.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R6.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R6.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R6.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R6.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R6.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R6.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R6.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R7                 0x0027     USB ENDPOINT0 DATA REG7
UD0R7.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R7.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R7.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R7.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R7.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R7.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R7.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R7.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD1R0                 0x0028     USB ENDPOINT1 DATA REG0
UD1R0.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R0.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R0.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R0.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R0.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R0.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R0.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R0.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R1                 0x0029     USB ENDPOINT1 DATA REG1
UD1R1.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R1.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R1.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R1.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R1.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R1.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R1.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R1.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R2                 0x002A     USB ENDPOINT1 DATA REG2
UD1R2.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R2.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R2.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R2.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R2.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R2.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R2.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R2.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R3                 0x002B     USB ENDPOINT1 DATA REG3
UD1R3.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R3.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R3.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R3.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R3.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R3.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R3.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R3.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R4                 0x002C     USB ENDPOINT1 DATA REG4
UD1R4.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R4.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R4.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R4.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R4.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R4.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R4.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R4.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R5                 0x002D     USB ENDPOINT1 DATA REG5
UD1R5.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R5.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R5.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R5.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R5.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R5.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R5.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R5.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R6                 0x002E     USB ENDPOINT1 DATA REG6
UD1R6.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R6.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R6.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R6.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R6.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R6.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R6.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R6.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R7                 0x002F     USB ENDPOINT1 DATA REG7
UD1R7.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R7.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R7.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R7.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R7.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R7.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R7.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R7.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UNUSED0030            0x0030     UNUSED
UNUSED0031            0x0031     UNUSED
UNUSED0032            0x0032     UNUSED
UNUSED0033            0x0033     UNUSED
UNUSED0034            0x0034     UNUSED
UNUSED0035            0x0035     UNUSED
UNUSED0036            0x0036     UNUSED
UCR2                  0x0037     USB CONTROL2
UCR2.TX1STR            6   Clear Transmit First Flag
UCR2.TX1ST             5   Transmit First Flag
UCR2.ENABLE2           3   Endpoint 2 Enable
UCR2.ENABLE1           2   Endpoint 1 Enable
UCR2.STALL2            1   Endpoint 2 Force Stall Bit
UCR2.STALL1            0   Endpoint 1 Force Stall Bit
UADR                  0x0038     USB ADDRESS
UADR.USBEN             7   USB Module Enable
UADR.UADD6             6   USB Function Address 6
UADR.UADD5             5   USB Function Address 5
UADR.UADD4             4   USB Function Address 4
UADR.UADD3             3   USB Function Address 3
UADR.UADD2             2   USB Function Address 2
UADR.UADD1             1   USB Function Address 1
UADR.UADD0             0   USB Function Address 0
UIR0                  0x0039     USB INTERRUPT0
UIR0.TXD0F             7   Endpoint 0 Data Transmit Flag
UIR0.RXD0F             6   Endpoint 0 Data Receive Flag
UIR0.RSTF              5   USB Reset Flag
UIR0.SUSPND            4   USB Suspend Flag
UIR0.TXD0IE            3   Endpoint 0 Transmit Interrupt Enable
UIR0.RXD0IE            2   Endpoint 0 Receive Interrupt Enable
UIR0.TXD0FR            1   Endpoint 0 Transmit Flag Reset
UIR0.RXD0FR            0   Endpoint 0 Receive Flag Reset
UIR1                  0x003A     USB INTERRUPT1
UIR1.TXD1F             7   Endpoint 1/Endpoint 2 Data Transmit Flag
UIR1.EOPF              6   End of Packet Detect Flag
UIR1.RESUMF            5   Resume Flag
UIR1.RESUMFR           4   Resume Flag Reset
UIR1.TXD1IE            3   Endpoint 1/Endpoint 2 Transmit Interrupt Enable
UIR1.EOPIE             2   End of Packet Detect Interrupt Enable
UIR1.TXD1FR            1   Endpoint 1/Endpoint 2 Transmit Flag Reset
UIR1.EOPFR             0   End of Packet Flag Reset
UCR0                  0x003B     USB CONTROL0
UCR0.T0SEQ             7   Endpoint 0 Transmit Sequence Bit
UCR0.STALL0            6   Endpoint 0 Force Stall Bit
UCR0.TX0E              5   Endpoint 0 Transmit Enable
UCR0.RX0E              4   Endpoint 0 Receive Enable
UCR0.TP0SIZ3           3   Endpoint 0 Transmit Data Packet Size 3
UCR0.TP0SIZ2           2   Endpoint 0 Transmit Data Packet Size 2
UCR0.TP0SIZ1           1   Endpoint 0 Transmit Data Packet Size 1
UCR0.TP0SIZ0           0   Endpoint 0 Transmit Data Packet Size 0
UCR1                  0x003C     USB CONTROL1
UCR1.T1SEQ             7   Endpoint1/Endpoint 2 Transmit Sequence Bit
UCR1.ENDADD            6   Endpoint Address Select
UCR1.TX1E              5   Endpoint 1/Endpoint 2 Transmit Enable
UCR1.FRESUM            4   Force Resume
UCR1.TP1SIZ3           3   Endpoint 1/Endpoint 2 Transmit Data Packet Size 3
UCR1.TP1SIZ2           2   Endpoint 1/Endpoint 2 Transmit Data Packet Size 2
UCR1.TP1SIZ1           1   Endpoint 1/Endpoint 2 Transmit Data Packet Size 1
UCR1.TP1SIZ0           0   Endpoint 1/Endpoint 2 Transmit Data Packet Size 0
USR                   0x003D     USB STATUS
USR.RSEQ               7   Endpoint 0 Receive Sequence Bit
USR.SETUP              6   SETUP Token Detect Bit
USR.RPSIZ3             3   Endpoint 0 Receive Data Packet Size 3
USR.RPSIZ2             2   Endpoint 0 Receive Data Packet Size 2
USR.RPSIZ1             1   Endpoint 0 Receive Data Packet Size 1
USR.RPSIZ0             0   Endpoint 0 Receive Data Packet Size 0
PCR                   0x003E     PROG. CONTROL
PCR.MORON              2   Mask Option Register ON
PCR.ELAT               1   EPROM LATch control
PCR.PGM                0   EPROM ProGraM command
RESERV003F            0x003F     RESERVED
MOR                   0x01FF     MASK OPTION
MOR.IRQTRIG            4   IRQ, PA0-PA3 Interrupt Options
MOR.PULLREN            3   Port A and B Pullup/Pulldown Options
MOR.PAINTEN            2   PA0-PA3 External Interrupt Options
MOR.OSCDLY             1   Oscillator Delay Option
MOR.LVREN              0   LVR Option
RESERV1FFO            0x1FF0    RESERVED
RESERV1FF1            0x1FF1    RESERVED
RESERV1FF2            0x1FF2    RESERVED
RESERV1FF3            0x1FF3    RESERVED


.68HC705JB3
; HC05JB3GRS/H  http://
; HC05JB3GRS.pdf

; RAM=144
; ROM=0K
; EPROM=2.5K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area BSS  UNUSED      0x0040:0x0070
area DATA RAM         0x0070:0x0100
area BSS  UNUSED      0x0100:0x01FF
area DATA MOR         0x01FF:0x0200
area BSS  UNUSED      0x0200:0x1400
area CODE EPROM       0x1400:0x1E00
area DATA BootROM     0x1E00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      SWI               
interrupt IRQ               0x1FFA      IRQ/IRQ2        
interrupt USB               0x1FF8      USB         
interrupt TIMER1            0x1FF6      Timer1 
interrupt MFT               0x1FF4      MFT


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003     UNUSED
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.SLOWE             3   Slow Transition Enable         
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.OCMPO             7   OCMP Output Enable
DDRC.VROFF             6   USB 3.3V Voltage Reference
DDRC.DDRC3             3   PC3 Data Direction
DDRC.DDRC2             2   PC2 Data Direction
DDRC.DDRC1             1   PC1 Data Direction
DDRC.DDRC0             0   PC0 Data Direction
UNUSED0007            0x0007     UNUSED
TCSR                  0x0008     MFT Ctrl_Status
TCSR.TOF               7   Timer Overflow Flag
TCSR.RTIF              6   Real Time Interrupt Flag
TCSR.TOFE              5   Timer Overflow Enable
TCSR.RTIE              4   Real Time Interrupt Enable
TCSR.TOFR              3   Timer Overflow Acknowledge
TCSR.RTIFR             2   Real Time Interrupt Acknowledge
TCSR.RT1               1   Real-Time Interrupt period select bits 1
TCSR.RT0               0   Real-Time Interrupt period select bits 0
TCNT                  0x0009     MFT Counter
TCNT.TMR7              7
TCNT.TMR6              6
TCNT.TMR5              5
TCNT.TMR4              4
TCNT.TMR3              3
TCNT.TMR2              2
TCNT.TMR1              1
TCNT.TMR0              0
ICSR                  0x000A     IRQ Control_Status
ICSR.IRQE              7   IRQ Interrupt Enable
ICSR.IRQF              3   IRQ Interrupt Request Flag
ICSR.IRQR              1   IRQ Interrupt Acknowledge
ICSR.IRQPU             0   IRQ pin PUll-up resistor enable
UNUSED000B            0x000B     UNUSED
UNUSED000C            0x000C     UNUSED
UNUSED000D            0x000D     UNUSED
OIER                  0x000E     Optical Interface En.
OIER.TCMPE             7   Timer Input Capture Comparator Enable
OIER.VREF2             6   Reference Voltage Selection 3
OIER.VREF1             5   Reference Voltage Selection 1
OIER.VREF0             4   Reference Voltage Selection 0
OIER.OIE3              3   Optical Interface pair 3 Enable
OIER.OIE2              2   Optical Interface pair 2 Enable
OIER.OIE1              1   Optical Interface pair 1 Enable
OIER.OIE0              0   Optical Interface pair 0 Enable
PDURC                 0x000F     Port C Pull-down_up
PDURC.PDRC3            3   PC3 Pin Pull-down Enable
PDURC.PDRC2            2   PC2 Pin Pull-down Enable
PDURC.PDRC1            1   PC1 Pin Pull-down Enable
PDURC.PDRC0            0   PC0 Pin Pull-down Enable
PDURA                 0x0010     Port A Pull-down_up
PDURA.PDRA7            7   PA7 Pin Pull-down enable
PDURA.PDRA6            6   PA6 Pin Pull-down enable
PDURA.PDRA5            5   PA5 Pin Pull-down enable
PDURA.PDRA4            4   PA4 Pin Pull-down enable
PDURA.PDRA3            3   PA3 Pin Pull-down enable
PDURA.PDRA2            2   PA2 Pin Pull-down enable
PDURA.PDRA1            1   PA1 Pin Pull-down enable
PDURA.PDRA0            0   PA0 Pin Pull-down enable
PDURB                 0x0011     Port B Pull-down_up
PDURB.PDRB7            7   PB7 Pin Pull-down enable
PDURB.PDRB6            6   PB6 Pin Pull-down enable
PDURB.PDRB5            5   PB5 Pin Pull-down enable
PDURB.PDRB4            4   PB4 Pin Pull-down enable
PDURB.PURB2            2   PB2 Pin Pull-up enable  
PDURB.PURB1            1   PB1 Pin Pull-up enable  
PDURB.PDRB0            0   PB0 Pin Pull-up enable  
TCR                   0x0012     Timer1 Control
TCR.ICIE               7   INPUT CAPTURE INTERRUPT ENABLE
TCR.OCIE               6   OUTPUT COMPARE INTERRUPT ENABLE
TCR.TOIE               5   TIMER OVERFLOW INTERRUPT ENABLE
TCR.IEDG               1   INPUT CAPTURE EDGE SELECT
TSR                   0x0013     Timer1 Status
TSR.ICF                7   INPUT CAPTURE FLAG
TSR.OCF                6   OUTPUT COMPARE FLAG
TSR.TOF                5   TIMER OVERFLOW FLAG
ICH                   0x0014     Input Capture MSB
ICH.ICH7               7
ICH.ICH6               6
ICH.ICH5               5
ICH.ICH4               4
ICH.ICH3               3
ICH.ICH2               2
ICH.ICH1               1
ICH.ICH0               0
ICL                   0x0015     Input Capture LSB
ICL.ICL7               7
ICL.ICL6               6
ICL.ICL5               5
ICL.ICL4               4
ICL.ICL3               3
ICL.ICL2               2
ICL.ICL1               1
ICL.ICL0               0
OCH                   0x0016     Output Compare MSB
OCH.OCH7               7
OCH.OCH6               6
OCH.OCH5               5
OCH.OCH4               4
OCH.OCH3               3
OCH.OCH2               2
OCH.OCH1               1
OCH.OCH0               0
OCL                   0x0017     Output Compare LSB
OCL.OCL7               7
OCL.OCL6               6
OCL.OCL5               5
OCL.OCL4               4
OCL.OCL3               3
OCL.OCL2               2
OCL.OCL1               1
OCL.OCL0               0
TCNTH                 0x0018     Timer1 Counter MSB
TCNTH.TCNTH7           7
TCNTH.TCNTH6           6
TCNTH.TCNTH5           5
TCNTH.TCNTH4           4
TCNTH.TCNTH3           3
TCNTH.TCNTH2           2
TCNTH.TCNTH1           1
TCNTH.TCNTH0           0
TCNTL                 0x0019     Timer1 Counter LSB
TCNTL.TCNTL7           7
TCNTL.TCNTL6           6
TCNTL.TCNTL5           5
TCNTL.TCNTL4           4
TCNTL.TCNTL3           3
TCNTL.TCNTL2           2
TCNTL.TCNTL1           1
TCNTL.TCNTL0           0
ACNTH                 0x001A     Alter. Counter MSB
ACNTH.ACNTH7           7
ACNTH.ACNTH6           6
ACNTH.ACNTH5           5
ACNTH.ACNTH4           4
ACNTH.ACNTH3           3
ACNTH.ACNTH2           2
ACNTH.ACNTH1           1
ACNTH.ACNTH0           0
ACNTL                 0x001B     Alter. Counter LSB
ACNTL.ACNTL7           7
ACNTL.ACNTL6           6
ACNTL.ACNTL5           5
ACNTL.ACNTL4           4
ACNTL.ACNTL3           3
ACNTL.ACNTL2           2
ACNTL.ACNTL1           1
ACNTL.ACNTL0           0
UNUSED001C            0x001C     UNUSED
UNUSED001D            0x001D     UNUSED
UNUSED001E            0x001E     UNUSED
UNUSED001F            0x001F     UNUSED
UD0R0                 0x0020     USB Endpoint 0 Data 0
UD0R0.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R0.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R0.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R0.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R0.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R0.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R0.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R0.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R1                 0x0021     USB Endpoint 0 Data 1
UD0R1.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R1.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R1.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R1.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R1.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R1.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R1.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R1.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R2                 0x0022     USB Endpoint 0 Data 2
UD0R2.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R2.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R2.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R2.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R2.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R2.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R2.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R2.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R3                 0x0023     USB Endpoint 0 Data 3
UD0R3.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R3.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R3.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R3.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R3.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R3.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R3.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R3.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R4                 0x0024     USB Endpoint 0 Data 4
UD0R4.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R4.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R4.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R4.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R4.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R4.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R4.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R4.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R5                 0x0025     USB Endpoint 0 Data 5
UD0R5.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R5.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R5.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R5.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R5.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R5.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R5.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R5.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R6                 0x0026     USB Endpoint 0 Data 6
UD0R6.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R6.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R6.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R6.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R6.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R6.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R6.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R6.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R7                 0x0027     USB Endpoint 0 Data 7
UD0R7.UE0RD7_UE0TD7    7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R7.UE0RD6_UE0TD6    6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R7.UE0RD5_UE0TD5    5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R7.UE0RD4_UE0TD4    4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R7.UE0RD3_UE0TD3    3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R7.UE0RD2_UE0TD2    2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R7.UE0RD1_UE0TD1    1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R7.UE0RD0_UE0TD0    0   Endpoint 0 Receive/Transmit Data Buffer 0
UD1R0                 0x0028     USB Endpoint 1 Data 0
UD1R0.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R0.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R0.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R0.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R0.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R0.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R0.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R0.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R1                 0x0029     USB Endpoint 1 Data 1
UD1R1.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R1.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R1.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R1.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R1.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R1.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R1.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R1.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R2                 0x002A     USB Endpoint 1 Data 2
UD1R2.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R2.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R2.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R2.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R2.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R2.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R2.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R2.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R3                 0x002B     USB Endpoint 1 Data 3
UD1R3.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R3.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R3.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R3.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R3.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R3.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R3.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R3.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R4                 0x002C     USB Endpoint 1 Data 4
UD1R4.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R4.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R4.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R4.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R4.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R4.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R4.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R4.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R5                 0x002D     USB Endpoint 1 Data 5
UD1R5.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R5.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R5.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R5.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R5.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R5.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R5.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R5.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R6                 0x002E     USB Endpoint 1 Data 6
UD1R6.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R6.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R6.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R6.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R6.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R6.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R6.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R6.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R7                 0x002F     USB Endpoint 1 Data 7
UD1R7.UE1TD7           7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R7.UE1TD6           6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R7.UE1TD5           5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R7.UE1TD4           4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R7.UE1TD3           3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R7.UE1TD2           2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R7.UE1TD1           1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R7.UE1TD0           0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UNUSED0030            0x0030     UNUSED
UNUSED0031            0x0031     UNUSED
UNUSED0032            0x0032     UNUSED
UNUSED0033            0x0033     UNUSED
UNUSED0034            0x0034     UNUSED
UNUSED0035            0x0035     UNUSED
UNUSED0036            0x0036     UNUSED
UCR2                  0x0037     USB Control 2
UCR2.TX1STR            6   Clear Transmit First Flag
UCR2.TX1ST             5   Transmit First Flag
UCR2.ENABLE2           3   Endpoint 2 Enable
UCR2.ENABLE1           2   Endpoint 1 Enable
UCR2.STALL2            1   Endpoint 2 Force Stall Bit
UCR2.STALL1            0   Endpoint 1 Force Stall Bit
UADR                  0x0038     USB Address
UADR.USBEN             7   USB Module Enable
UADR.UADD6             6   USB Function Address 6
UADR.UADD5             5   USB Function Address 5
UADR.UADD4             4   USB Function Address 4
UADR.UADD3             3   USB Function Address 3
UADR.UADD2             2   USB Function Address 2
UADR.UADD1             1   USB Function Address 1
UADR.UADD0             0   USB Function Address 0
UIR0                  0x0039     USB Interrupt 0
UIR0.TXD0F             7   Endpoint 0 Data Transmit Flag
UIR0.RXD0F             6   Endpoint 0 Data Receive Flag
UIR0.RSTF              5   USB Reset Flag
UIR0.SUSPND            4   USB Suspend Flag
UIR0.TXD0IE            3   Endpoint 0 Transmit Interrupt Enable
UIR0.RXD0IE            2   Endpoint 0 Receive Interrupt Enable
UIR0.TXD0FR            1   Endpoint 0 Transmit Flag Reset
UIR0.RXD0FR            0   Endpoint 0 Receive Flag Reset
UIR1                  0x003A     USB Interrupt 1
UIR1.TXD1F             7   Endpoint 1/Endpoint 2 Data Transmit Flag
UIR1.EOPF              6   End of Packet Detect Flag
UIR1.RESUMF            5   Resume Flag
UIR1.RESUMFR           4   Resume Flag Reset
UIR1.TXD1IE            3   Endpoint 1/Endpoint 2 Transmit Interrupt Enable
UIR1.EOPIE             2   End of Packet Detect Interrupt Enable
UIR1.TXD1FR            1   Endpoint 1/Endpoint 2 Transmit Flag Reset
UIR1.EOPFR             0   End of Packet Flag Reset
UCR0                  0x003B     USB Control 0
UCR0.T0SEQ             7   Endpoint 0 Transmit Sequence Bit
UCR0.STALL0            6   Endpoint 0 Force Stall Bit
UCR0.TX0E              5   Endpoint 0 Transmit Enable
UCR0.RX0E              4   Endpoint 0 Receive Enable
UCR0.TP0SIZ3           3   Endpoint 0 Transmit Data Packet Size 3
UCR0.TP0SIZ2           2   Endpoint 0 Transmit Data Packet Size 2
UCR0.TP0SIZ1           1   Endpoint 0 Transmit Data Packet Size 1
UCR0.TP0SIZ0           0   Endpoint 0 Transmit Data Packet Size 0
UCR1                  0x003C     USB Control 1
UCR1.T1SEQ             7   Endpoint1/Endpoint 2 Transmit Sequence Bit
UCR1.ENDADD            6   Endpoint Address Select
UCR1.TX1E              5   Endpoint 1/Endpoint 2 Transmit Enable
UCR1.FRESUM            4   Force Resume
UCR1.TP1SIZ3           3   Endpoint 1/Endpoint 2 Transmit Data Packet Size 3
UCR1.TP1SIZ2           2   Endpoint 1/Endpoint 2 Transmit Data Packet Size 2
UCR1.TP1SIZ1           1   Endpoint 1/Endpoint 2 Transmit Data Packet Size 1
UCR1.TP1SIZ0           0   Endpoint 1/Endpoint 2 Transmit Data Packet Size 0
USR                   0x003D     USB Status
USR.RSEQ               7   Endpoint 0 Receive Sequence Bit
USR.SETUP              6   SETUP Token Detect Bit
USR.RPSIZ3             3   Endpoint 0 Receive Data Packet Size 3
USR.RPSIZ2             2   Endpoint 0 Receive Data Packet Size 2
USR.RPSIZ1             1   Endpoint 0 Receive Data Packet Size 1
USR.RPSIZ0             0   Endpoint 0 Receive Data Packet Size 0
PCR                   0x003E     EPROM Program Control Register
PCR.MORON              2   Mask Option Register ON
PCR.ELAT               1   EPROM LATch control
PCR.PGM                0   EPROM ProGraM command
Reserv003F            0x003F     Reserved
MOR                   0x01FF     MASK OPTION REGISTER
MOR.COPEN              5   COP Enable
MOR.IRQTRIG            4   IRQ, PA0-PA3 Interrupt Option
MOR.PULLREN            3   Port A, B, and C Pull-up/down Option
MOR.PAINTEN            2   PA0-PA3 External Interrupt Option
MOR.OSCDLY             1   Oscillator Delay Option
MOR.LVREN              0   LVR Option
RESERV1FF0            0x1FF0    RESERVED
RESERV1FF1            0x1FF1    RESERVED
RESERV1FF2            0x1FF2    RESERVED
RESERV1FF3            0x1FF3    RESERVED


.68HC705JB4
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705JB4&nodeId=01M98633
; HC05JB4GRS.pdf

; RAM=176
; ROM=0K
; EPROM=3.5K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area BSS  UNUSED      0x0040:0x007F
area DATA MOR         0x007F:0x0080
area DATA RAM         0x0080:0x0130
area BSS  UNUSED      0x0130:0x1000
area CODE EPROM       0x1000:0x1E00
area DATA BootROM     0x1E00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      SWI               
interrupt IRQ               0x1FFA      IRQ/IRQ2        
interrupt USB               0x1FF8      USB         
interrupt TIMER1            0x1FF6      Timer1 
interrupt MFT               0x1FF4      MFT


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003   UNUSED
DDRA                  0x0004   Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005   Port B data direction
DDRB.SLOWEA            7   Enable/Disable slow falling-edge output transition feature on PA6 and PA7
DDRB.SLOWEB            6   Enable/Disable slow falling-edge output transition feature on PB0 to PB4 
DDRB.DDRB4             4   Data Direction for Port B Bit 4                                          
DDRB.DDRB3             3   Data Direction for Port B Bit 3                                          
DDRB.DDRB2             2   Data Direction for Port B Bit 2                                          
DDRB.DDRB1             1   Data Direction for Port B Bit 1                                          
DDRB.DDRB0             0   Data Direction for Port B Bit 0                                          
DDRC                  0x0006   Port C data direction
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007   UNUSED
TCSR                  0x0008   MFT Ctrl/Status
TCSR.TOF               7   Timer Overflow Flag
TCSR.RTIF              6   Real Time Interrupt Flag
TCSR.TOFE              5   Timer Overflow Enable
TCSR.RTIE              4   Real Time Interrupt Enable
TCSR.TOFR              3   Timer Overflow Acknowledge
TCSR.RTIFR             2   Real Time Interrupt Acknowledge
TCSR.RT1               1   Real-Time Interrupt period select bits 1
TCSR.RT0               0   Real-Time Interrupt period select bits 0
TCNT                  0x0009   MFT Counter
TCNT.TMR7              7
TCNT.TMR6              6
TCNT.TMR5              5
TCNT.TMR4              4
TCNT.TMR3              3
TCNT.TMR2              2
TCNT.TMR1              1 
TCNT.TMR0              0
ICSR                  0x000A   IRQ Control/Status
ICSR.IRQE              7   IRQ Interrupt Enable
ICSR.IRQ2E             6   IRQ2 Interrupt Enable
ICSR.IRQF              3   IRQ Interrupt Request Flag
ICSR.IRQ2F             2   IRQ2 Interrupt Request Flag
ICSR.IRQR              1   IRQ Interrupt Acknowledge
ICSR.IRQ2R             0   IRQ2 Interrupt Acknowledge
UNUSED000B            0x000B   UNUSED
UNUSED000C            0x000C   UNUSED
UNUSED000D            0x000D   UNUSED
ADSCR                 0x000E   ADC Control/Status
ADSCR.COCO             7   COnversion COmplete
ADSCR.ADRC             6   ADC RC Oscillator Control
ADSCR.ADON             5   ADC On
ADSCR.CH3              3   Channel Select Bits 3
ADSCR.CH2              2   Channel Select Bits 2
ADSCR.CH1              1   Channel Select Bits 1
ADSCR.CH0              0   Channel Select Bits 0
ADDR                  0x000F   ADC Data
ADDR.ADDR7             7
ADDR.ADDR6             6
ADDR.ADDR5             5
ADDR.ADDR4             4
ADDR.ADDR3             3
ADDR.ADDR2             2
ADDR.ADDR1             1 
ADDR.ADDR0             0
PURA                  0x0010   Port A Pull-Up
PURA.PURA7             7
PURA.PURA6             6
PURA.PURA5             5
PURA.PURA4             4
PURA.PURA3             3
PURA.PURA2             2
PURA.PURA1             1
PURA.PURA0             0
PURB                  0x0011   Port B Pull-Up
PURB.PURB4             4
PURB.PURB3             3
PURB.PURB2             2
PURB.PURB1             1
PURB.PURB0             0
TCR                   0x0012   Timer1 control
TCR.ICIE               7   INPUT CAPTURE INTERRUPT ENABLE
TCR.OCIE               6   OUTPUT COMPARE INTERRUPT ENABLE
TCR.TOIE               5   TIMER OVERFLOW INTERRUPT ENABLE
TCR.IEDG               1   INPUT CAPTURE EDGE SELECT
TSR                   0x0013   Timer1 status
TSR.ICF                7   INPUT CAPTURE FLAG
TSR.OCF                6   OUTPUT COMPARE FLAG
TSR.TOF                5   TIMER OVERFLOW FLAG
ICH                   0x0014   Input capture MSB
ICH.ICH7               7
ICH.ICH6               6 
ICH.ICH5               5
ICH.ICH4               4
ICH.ICH3               3
ICH.ICH2               2
ICH.ICH1               1
ICH.ICH0               0
ICL                   0x0015   Input capture LSB
ICL.ICL7               7
ICL.ICL6               6
ICL.ICL5               5
ICL.ICL4               4
ICL.ICL3               3
ICL.ICL2               2
ICL.ICL1               1
ICL.ICL0               0
OCH                   0x0016   Output compare MSB
OCH.OCH7               7
OCH.OCH6               6
OCH.OCH5               5
OCH.OCH4               4
OCH.OCH3               3
OCH.OCH2               2
OCH.OCH1               1
OCH.OCH0               0
OCL                   0x0017   Output compare LSB
OCL.OCL7               7
OCL.OCL6               6
OCL.OCL5               5
OCL.OCL4               4
OCL.OCL3               3
OCL.OCL2               2
OCL.OCL1               1
OCL.OCL0               0
TCNTH                 0x0018   Timer1 Counter MSB
TCNTH.TCNTH7           7
TCNTH.TCNTH6           6
TCNTH.TCNTH5           5
TCNTH.TCNTH4           4
TCNTH.TCNTH3           3
TCNTH.TCNTH2           2
TCNTH.TCNTH1           1
TCNTH.TCNTH0           0
TCNTL                 0x0019   Timer1 Cunter LSB
TCNTL.TCNTL7           7
TCNTL.TCNTL6           6
TCNTL.TCNTL5           5
TCNTL.TCNTL4           4
TCNTL.TCNTL3           3
TCNTL.TCNTL2           2
TCNTL.TCNTL1           1
TCNTL.TCNTL0           0
ACNTH                 0x001A   Alternate counter MSB
ACNTH.ACNTH7           7
ACNTH.ACNTH6           6
ACNTH.ACNTH5           5
ACNTH.ACNTH4           4
ACNTH.ACNTH3           3
ACNTH.ACNTH2           2
ACNTH.ACNTH1           1
ACNTH.ACNTH0           0
ACNTL                 0x001B   Alternate counter LSB
ACNTL.ACNTL7           7
ACNTL.ACNTL6           6
ACNTL.ACNTL5           5
ACNTL.ACNTL4           4
ACNTL.ACNTL3           3
ACNTL.ACNTL2           2
ACNTL.ACNTL1           1
ACNTL.ACNTL0           0
UNUSED001C            0x001C   UNUSED
UNUSED001D            0x001D   UNUSED
UNUSED001E            0x001E   UNUSED
UNUSED001F            0x001F   UNUSED
UD0R0                 0x0020   USB Endpoint 0 Data 0
UD0R0.UE0D7            7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R0.UE0D6            6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R0.UE0D5            5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R0.UE0D4            4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R0.UE0D3            3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R0.UE0D2            2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R0.UE0D1            1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R0.UE0D0            0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R1                 0x0021   USB Endpoint 0 Data 1
UD0R1.UE0D7            7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R1.UE0D6            6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R1.UE0D5            5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R1.UE0D4            4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R1.UE0D3            3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R1.UE0D2            2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R1.UE0D1            1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R1.UE0D0            0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R2                 0x0022   USB Endpoint 0 Data 2
UD0R2.UE0D7            7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R2.UE0D6            6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R2.UE0D5            5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R2.UE0D4            4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R2.UE0D3            3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R2.UE0D2            2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R2.UE0D1            1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R2.UE0D0            0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R3                 0x0023   USB Endpoint 0 Data 3
UD0R3.UE0D7            7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R3.UE0D6            6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R3.UE0D5            5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R3.UE0D4            4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R3.UE0D3            3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R3.UE0D2            2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R3.UE0D1            1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R3.UE0D0            0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R4                 0x0024   USB Endpoint 0 Data 4
UD0R4.UE0D7            7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R4.UE0D6            6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R4.UE0D5            5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R4.UE0D4            4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R4.UE0D3            3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R4.UE0D2            2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R4.UE0D1            1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R4.UE0D0            0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R5                 0x0025   USB Endpoint 0 Data 5
UD0R5.UE0D7            7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R5.UE0D6            6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R5.UE0D5            5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R5.UE0D4            4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R5.UE0D3            3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R5.UE0D2            2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R5.UE0D1            1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R5.UE0D0            0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R6                 0x0026   USB Endpoint 0 Data 6
UD0R6.UE0D7            7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R6.UE0D6            6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R6.UE0D5            5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R6.UE0D4            4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R6.UE0D3            3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R6.UE0D2            2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R6.UE0D1            1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R6.UE0D0            0   Endpoint 0 Receive/Transmit Data Buffer 0
UD0R7                 0x0027   USB Endpoint 0 Data 7
UD0R7.UE0D7            7   Endpoint 0 Receive/Transmit Data Buffer 7
UD0R7.UE0D6            6   Endpoint 0 Receive/Transmit Data Buffer 6
UD0R7.UE0D5            5   Endpoint 0 Receive/Transmit Data Buffer 5
UD0R7.UE0D4            4   Endpoint 0 Receive/Transmit Data Buffer 4
UD0R7.UE0D3            3   Endpoint 0 Receive/Transmit Data Buffer 3
UD0R7.UE0D2            2   Endpoint 0 Receive/Transmit Data Buffer 2
UD0R7.UE0D1            1   Endpoint 0 Receive/Transmit Data Buffer 1
UD0R7.UE0D0            0   Endpoint 0 Receive/Transmit Data Buffer 0
UD1R0                 0x0028   USB Endpoint 1 Data 0
UD1R0.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R0.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R0.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R0.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R0.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R0.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R0.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R0.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R1                 0x0029   USB Endpoint 1 Data 1
UD1R1.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R1.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R1.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R1.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R1.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R1.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R1.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R1.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R2                 0x002A   USB Endpoint 1 Data 2
UD1R2.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R2.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R2.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R2.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R2.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R2.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R2.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R2.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R3                 0x002B   USB Endpoint 1 Data 3
UD1R3.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R3.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R3.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R3.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R3.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R3.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R3.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R3.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R4                 0x002C   USB Endpoint 1 Data 4
UD1R4.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R4.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R4.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R4.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R4.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R4.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R4.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R4.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R5                 0x002D   USB Endpoint 1 Data 5
UD1R5.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R5.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R5.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R5.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R5.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R5.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R5.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R5.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R6                 0x002E   USB Endpoint 1 Data 6
UD1R6.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R6.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R6.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R6.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R6.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R6.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R6.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R6.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UD1R7                 0x002F   USB Endpoint 1 Data 7
UD1R7.UE0D7            7   Endpoint 1/ Endpoint 2 Transmit Data Buffer 7
UD1R7.UE0D6            6   Endpoint 1/ Endpoint 2 Transmit Data Buffer 6
UD1R7.UE0D5            5   Endpoint 1/ Endpoint 2 Transmit Data Buffer 5
UD1R7.UE0D4            4   Endpoint 1/ Endpoint 2 Transmit Data Buffer 4
UD1R7.UE0D3            3   Endpoint 1/ Endpoint 2 Transmit Data Buffer 3
UD1R7.UE0D2            2   Endpoint 1/ Endpoint 2 Transmit Data Buffer 2
UD1R7.UE0D1            1   Endpoint 1/ Endpoint 2 Transmit Data Buffer 1
UD1R7.UE0D0            0   Endpoint 1/ Endpoint 2 Transmit Data Buffer 0
UNUSED0030            0x0030   UNUSED
UNUSED0031            0x0031   UNUSED
UNUSED0032            0x0032   UNUSED
UNUSED0033            0x0033   UNUSED
UNUSED0034            0x0034   UNUSED
UNUSED0035            0x0035   UNUSED
UNUSED0036            0x0036   UNUSED
UCR2                  0x0037   USB Control 2
UCR2.TX1STR            6   Clear Transmit First Flag
UCR2.TX1ST             5   Transmit First Flag
UCR2.ENABLE2           3   Endpoint 2 Enable
UCR2.ENABLE1           2   Endpoint 1 Enable
UCR2.STALL2            1   Endpoint 2 Force Stall Bit
UCR2.STALL1            0   Endpoint 1 Force Stall Bit
UADR                  0x0038   USB Address
UADR.USBEN             7   USB Module Enable
UADR.UADD6             6   USB Function Address 6
UADR.UADD5             5   USB Function Address 5
UADR.UADD4             4   USB Function Address 4
UADR.UADD3             3   USB Function Address 3
UADR.UADD2             2   USB Function Address 2
UADR.UADD1             1   USB Function Address 1
UADR.UADD0             0   USB Function Address 0
UIR0                  0x0039   USB Interrupt 0
UIR0.TXD0F             7   Endpoint 0 Data Transmit Flag
UIR0.RXD0F             6   Endpoint 0 Data Receive Flag
UIR0.RSTF              5   USB Reset Flag
UIR0.SUSPND            4   USB Suspend Flag
UIR0.TXD0IE            3   Endpoint 0 Transmit Interrupt Enable
UIR0.RXD0IE            2   Endpoint 0 Receive Interrupt Enable
UIR0.TXD0FR            1   Endpoint 0 Transmit Flag Reset
UIR0.RXD0FR            0   Endpoint 0 Receive Flag Reset
UIR1                  0x003A   USB Interrupt 1
UIR1.TXD1F             7   Endpoint 1/Endpoint 2 Data Transmit Flag
UIR1.EOPF              6   End of Packet Detect Flag
UIR1.RESUMF            5   Resume Flag
UIR1.RESUMFR           4   Resume Flag Reset
UIR1.TXD1IE            3   Endpoint 1/Endpoint 2 Transmit Interrupt Enable
UIR1.EOPIE             2   End of Packet Detect Interrupt Enable
UIR1.TXD1FR            1   Endpoint 1/Endpoint 2 Transmit Flag Reset
UIR1.EOPFR             0   End of Packet Flag Reset
UCR0                  0x003B   USB Control 0
UCR0.T0SEQ             7   Endpoint 0 Transmit Sequence Bit
UCR0.STALL             6   Endpoint 0 Force Stall Bit
UCR0.TX0E              5   Endpoint 0 Transmit Enable
UCR0.RX0E              4   Endpoint 0 Receive Enable
UCR0.TP0SIZ3           3   Endpoint 0 Transmit Data Packet Size 3
UCR0.TP0SIZ2           2   Endpoint 0 Transmit Data Packet Size 2
UCR0.TP0SIZ1           1   Endpoint 0 Transmit Data Packet Size 1
UCR0.TP0SIZ0           0   Endpoint 0 Transmit Data Packet Size 0
UCR1                  0x003C   USB Control 1
UCR1.T1SEQ             7   Endpoint1/Endpoint 2 Transmit Sequence Bit
UCR1.ENDADD            6   Endpoint Address Select
UCR1.TX1E              5   Endpoint 1/Endpoint 2 Transmit Enable
UCR1.FRESUM            4   Force Resume
UCR1.TP1SIZ3           3   Endpoint 1/Endpoint 2 Transmit Data Packet Size 3
UCR1.TP1SIZ2           2   Endpoint 1/Endpoint 2 Transmit Data Packet Size 2
UCR1.TP1SIZ1           1   Endpoint 1/Endpoint 2 Transmit Data Packet Size 1
UCR1.TP1SIZ0           0   Endpoint 1/Endpoint 2 Transmit Data Packet Size 0
USR                   0x003D   USB Status
USR.RSEQ               7   Endpoint 0 Receive Sequence Bit
USR.SETUP              6   SETUP Token Detect Bit
USR.RPSIZ3             3   Endpoint 0 Receive Data Packet Size 3
USR.RPSIZ2             2   Endpoint 0 Receive Data Packet Size 2
USR.RPSIZ1             1   Endpoint 0 Receive Data Packet Size 1
USR.RPSIZ0             0   Endpoint 0 Receive Data Packet Size 0
PCR                   0x003E   EPROM Program Control Register
PCR.MORON              2   Mask Option Register ON
PCR.ELAT               1   EPROM LATch control
PCR.PGM                0   EPROM ProGraM command
RESERV003F            0x003F   RESERVED
MOR                   0x007F   MASK OPTION REGISTER
MOR.COPEN              5   COP Enable
MOR.IRQTRIG            4   IRQ, PA0-PA3 Interrupt Options
MOR.HIGHCURRA          3   PA6 and PA7 High Current Enable
MOR.PAINTEN            2   PA0-PA3 External Interrupt Options
MOR.OSCDLY             1   Oscillator Delay Option
MOR.LVREN              0   LVR Option
RESERV1FF0            0x1FF0   RESERVED
RESERV1FF1            0x1FF1   RESERVED
RESERV1FF2            0x1FF2   RESERVED
RESERV1FF3            0x1FF3   RESERVED


.68HC705JJ7
; MC68HC705JJ7/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705JJ7&nodeId=01M98633
; MC68HC705JJ7.pdf

; RAM=224
; ROM=0
; EPROM=6K
; EEPROM=0


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA RAM		0x0020:0x0100
area DATA EPROM		0x0700:0x1FF0
area DATA USER_VEC	0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET 	0x1FFE       Reset Vector
interrupt SWI 		0x1FFC       SWI Vector
interrupt E_IRQ		0x1FFA       External IRQ Vector
interrupt CTIMER	0x1FF8       Core Timer Interrupt Vector
interrupt TIMER 	0x1FF6       Timer Interrupt Vector
interrupt SPIF 		0x1FF4       Serial Interrupt Vector
interrupt ANALOG	0x1FF2       Analog Interrupt Vector


; INPUT/ OUTPUT PORTS
PORTA           0x0000   Port A Data Register
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB           0x0001   Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
RESERV0002      0x0002   RESERVED
AMUX            0x0003   Analog Multiplex Register
AMUX.HOLD         7
AMUX.DHOLD        6
AMUX.INV          5
AMUX.VREF         4
AMUX.MUX4         3
AMUX.MUX3         2
AMUX.MUX2         1
AMUX.MUX1         0
DDRA            0x0004   Data Direction Register A
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB            0x0005   Data Direction Register B
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
RESERV0006      0x0006   RESERVED
UNUSED0007      0x0007   UNUSED
CTSCR           0x0008   Core Timer Status and Control Register
CTSCR.CTOF        7  Core Timer Overflow Flag
CTSCR.RTIF        6  Real-Time Interrupt Flag
CTSCR.CTOFE       5  Core Timer Overflow Interrupt Enable Bit
CTSCR.RTIE        4  Real-Time Interrupt Enable Bit
CTSCR.CTOFR       3  Core Timer Overflow Flag Reset Bit
CTSCR.RTIFR       2  Real-Time Interrupt Flag Reset Bit
CTSCR.RT1         1  Real-Time Interrupt Select Bits 1
CTSCR.RT0         0  Real-Time Interrupt Select Bits 0
CTCR            0x0009   Core Timer Counter Register
SCR             0x000A   SIOP Control Register
SCR.SPIE          7  Serial Peripheral Interrupt Enable Bit
SCR.SPE           6  Serial Peripheral Enable Bit
SCR.LSBF          5  Least Significant Bit First Bit
SCR.MSTR          4  Master Mode Select Bit
SCR.SPIR          3  Serial Peripheral Interrupt Reset Bit
SCR.CPHA          2  Clock Phase Bit
SCR.SPR1          1  Serial Peripheral Clock Rate Select Bits 1
SCR.SPR0          0  Serial Peripheral Clock Rate Select Bits 0
SSR             0x000B   SIOP Status Register
SSR.SPIF         7   Serial Port Interrupt Flag
SSR.DCOL         6   Data Collision Bit
SDR             0x000C   SIOP Data Register
ISCR            0x000D   IRQ Status and Control Register
ISCR.IRQE         7  External Interrupt Request Enable Bit
ISCR.OM2          6  Oscillator Select Bits 2
ISCR.OM1          5  Oscillator Select Bits 1
ISCR.IRQF         3  External Interrupt Request Flag
ISCR.IRQR         1  Interrupt Request Reset Bit
PEBSR           0x000E   PEPROM Bit Select Register
PEBSR.PEB7        7  Not connected to the PEPROM array 7
PEBSR.PEB6        6  Not connected to the PEPROM array 6
PEBSR.PEB5        5  PEPROM Bit Selects 5
PEBSR.PEB4        4  PEPROM Bit Selects 4
PEBSR.PEB3        3  PEPROM Bit Selects 3
PEBSR.PEB2        2  PEPROM Bit Selects 2
PEBSR.PEB1        1  PEPROM Bit Selects 1
PEBSR.PEB0        0  PEPROM Bit Selects 0
PESCR           0x000F   PEPROM Status and Control Register
PESCR.PEDATA      7  PEPROM Data Bit
PESCR.PEPGM       5  PEPROM Program Control Bit
PESCR.PEPRZF      0  PEPROM Row Zero Flag
PDRA            0x0010   Pulldown Register Port A
PDRA.PDIA5        5  Port A Pulldown Inhibit Bit 5
PDRA.PDIA4        4  Port A Pulldown Inhibit Bit 4
PDRA.PDIA3        3  Port A Pulldown Inhibit Bit 3
PDRA.PDIA2        2  Port A Pulldown Inhibit Bit 2
PDRA.PDIA1        1  Port A Pulldown Inhibit Bit 1
PDRA.PDIA0        0  Port A Pulldown Inhibit Bit 0
PDRB            0x0011   Pulldown Register B
PDRB.PDIB7        7  Port B Pulldown Inhibit Bit 7
PDRB.PDIB6        6  Port B Pulldown Inhibit Bit 6
PDRB.PDIB5        5  Port B Pulldown Inhibit Bit 5
PDRB.PDIB4        4  Port B Pulldown Inhibit Bit 4
PDRB.PDIB3        3  Port B Pulldown Inhibit Bit 3
PDRB.PDIB2        2  Port B Pulldown Inhibit Bit 2
PDRB.PDIB1        1  Port B Pulldown Inhibit Bit 1
PDRB.PDIB0        0  Port B Pulldown Inhibit Bit 0
TCR             0x0012   Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable
TCR.IEDG          1  Input Capture Edge Select
TCR.OLVL          0  Output Compare Output Level Select
TSR             0x0013   Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Flag
TSR.TOF           5  Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TMRH            0x0018   Programmable Timer Register High
TMRL            0x0019   Programmable Timer Register Low
ACRH            0x001A   Alternate Counter Register High
ACRL            0x001B   Alternate Counter Register Low
EPROG           0x001C   EPROM Programming Register
EPROG.ELAT        2  EPROM Bus Latch Bit
EPROG.MPGM        1  Mask Option Register (MOR) Programming Bit
EPROG.EPGM        0  EPROM Programming Bit
ACR             0x001D   Analog Counter Register
ACR.CHG           7
ACR.ATD2          6
ACR.ATD1          5
ACR.ICEN          4
ACR.CPIE          3
ACR.CP2EN         2
ACR.CP1EN         1
ACR.ISEN          0
ASR             0x001E   Analog Status Register
ASR.CPF2          7
ASR.CPF1          6
ASR.CPFR2         5
ASR.CPFR1         4
ASR.COE1          3
ASR.VOFF          2
ASR.CMP2          1
ASR.CMP1          0
Reserv001F      0x001F   RESERVED
Reserv1FEF      0x1FEF   RESERVED
COPR            0x1FF0   COP and Security Register
COPR.EPMSEC       7  EPROM Security Bit
COPR.OPT          6  Optional Features Bit
COPR.COPC         0  COP Clear Bit


.68HC705JP7
; MC68HC705JJ7/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705JP7&nodeId=01M98633
; MC68HC705JJ7.pdf

; RAM=224
; ROM=0
; EPROM=6K + 64 Bit PEP
; EEPROM=0


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA RAM		0x0020:0x0200
area DATA EPROM		0x0700:0x1FF0
area DATA USER_VEC	0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      ...
interrupt CTIMER            0x1FF8      Core timer interrupts
interrupt PTIMER            0x1FF6      Programmable
interrupt SPIF              0x1FF4      Serial interrupt
interrupt ANALOG            0x1FF2        

; INPUT/ OUTPUT PORTS
PORTA           0x0000   Port A Data Register
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB           0x0001   Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
PORTC           0x0002   Port C Data Register
PORTC.PC7         7  Port C Data Bits 7
PORTC.PC6         6  Port C Data Bits 6
PORTC.PC5         5  Port C Data Bits 5
PORTC.PC4         4  Port C Data Bits 4
PORTC.PC3         3  Port C Data Bits 3
PORTC.PC2         2  Port C Data Bits 2
PORTC.PC1         1  Port C Data Bits 1
PORTC.PC0         0  Port C Data Bits 0
AMUX            0x0003   Analog Multiplex Register
AMUX.HOLD         7
AMUX.DHOLD        6
AMUX.INV          5
AMUX.VREF         4
AMUX.MUX4         3
AMUX.MUX3         2
AMUX.MUX2         1
AMUX.MUX1         0
DDRA            0x0004   Data Direction Register A
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB            0x0005   Data Direction Register B
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
DDRC            0x0006   Data Direction Register C
DDRC.DDRC7        7  Data Direction for Port C Bit 7
DDRC.DDRC6        6  Data Direction for Port C Bit 6
DDRC.DDRC5        5  Data Direction for Port C Bit 5
DDRC.DDRC4        4  Data Direction for Port C Bit 4
DDRC.DDRC3        3  Data Direction for Port C Bit 3
DDRC.DDRC2        2  Data Direction for Port C Bit 2
DDRC.DDRC1        1  Data Direction for Port C Bit 1
DDRC.DDRC0        0  Data Direction for Port C Bit 0
UNUSED0007      0x0007   UNUSED
CTSCR           0x0008   Core Timer Status and Control Register
CTSCR.CTOF        7  Core Timer Overflow Flag
CTSCR.RTIF        6  Real-Time Interrupt Flag
CTSCR.CTOFE       5  Core Timer Overflow Interrupt Enable Bit
CTSCR.RTIE        4  Real-Time Interrupt Enable Bit
CTSCR.CTOFR       3  Core Timer Overflow Flag Reset Bit
CTSCR.RTIFR       2  Real-Time Interrupt Flag Reset Bit
CTSCR.RT1         1  Real-Time Interrupt Select Bits 1
CTSCR.RT0         0  Real-Time Interrupt Select Bits 0
CTCR            0x0009   Core Timer Counter Register
SCR             0x000A   SIOP Control Register
SCR.SPIE          7  Serial Peripheral Interrupt Enable Bit
SCR.SPE           6  Serial Peripheral Enable Bit
SCR.LSBF          5  Least Significant Bit First Bit
SCR.MSTR          4  Master Mode Select Bit
SCR.SPIR          3  Serial Peripheral Interrupt Reset Bit
SCR.CPHA          2  Clock Phase Bit
SCR.SPR1          1  Serial Peripheral Clock Rate Select Bits 1
SCR.SPR0          0  Serial Peripheral Clock Rate Select Bits 0
SSR             0x000B   SIOP Status Register
SSR.SPIF         7   Serial Port Interrupt Flag
SSR.DCOL         6   Data Collision Bit
SDR             0x000C   SIOP Data Register
ISCR            0x000D   IRQ Status and Control Register
ISCR.IRQE         7  External Interrupt Request Enable Bit
ISCR.OM2          6  Oscillator Select Bits 2
ISCR.OM1          5  Oscillator Select Bits 1
ISCR.IRQF         3  External Interrupt Request Flag
ISCR.IRQR         1  Interrupt Request Reset Bit
PEBSR           0x000E   PEPROM Bit Select Register
PEBSR.PEB7        7  Not connected to the PEPROM array 7
PEBSR.PEB6        6  Not connected to the PEPROM array 6
PEBSR.PEB5        5  PEPROM Bit Selects 5
PEBSR.PEB4        4  PEPROM Bit Selects 4
PEBSR.PEB3        3  PEPROM Bit Selects 3
PEBSR.PEB2        2  PEPROM Bit Selects 2
PEBSR.PEB1        1  PEPROM Bit Selects 1
PEBSR.PEB0        0  PEPROM Bit Selects 0
PESCR           0x000F   PEPROM Status and Control Register
PESCR.PEDATA      7  PEPROM Data Bit
PESCR.PEPGM       5  PEPROM Program Control Bit
PESCR.PEPRZF      0  PEPROM Row Zero Flag
PDRA            0x0010   Pulldown Register Port A and Port C
PDRA.PDICH        7  Upper Port C Pulldown Inhibit Bits
PDRA.PDICL        6  Lower Port C Pulldown Inhibit Bits
PDRA.PDIA5        5  Port A Pulldown Inhibit Bit 5
PDRA.PDIA4        4  Port A Pulldown Inhibit Bit 4
PDRA.PDIA3        3  Port A Pulldown Inhibit Bit 3
PDRA.PDIA2        2  Port A Pulldown Inhibit Bit 2
PDRA.PDIA1        1  Port A Pulldown Inhibit Bit 1
PDRA.PDIA0        0  Port A Pulldown Inhibit Bit 0
PDRB            0x0011   Pulldown Register B
PDRB.PDIB7        7  Port B Pulldown Inhibit Bit 7
PDRB.PDIB6        6  Port B Pulldown Inhibit Bit 6
PDRB.PDIB5        5  Port B Pulldown Inhibit Bit 5
PDRB.PDIB4        4  Port B Pulldown Inhibit Bit 4
PDRB.PDIB3        3  Port B Pulldown Inhibit Bit 3
PDRB.PDIB2        2  Port B Pulldown Inhibit Bit 2
PDRB.PDIB1        1  Port B Pulldown Inhibit Bit 1
PDRB.PDIB0        0  Port B Pulldown Inhibit Bit 0
TCR             0x0012   Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable
TCR.IEDG          1  Input Capture Edge Select
TCR.OLVL          0  Output Compare Output Level Select
TSR             0x0013   Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Flag
TSR.TOF           5  Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TMRH            0x0018   Programmable Timer Register High
TMRL            0x0019   Programmable Timer Register Low
ACRH            0x001A   Alternate Counter Register High
ACRL            0x001B   Alternate Counter Register Low
EPROG           0x001C   EPROM Programming Register
EPROG.ELAT        2  EPROM Bus Latch Bit
EPROG.MPGM        1  Mask Option Register (MOR) Programming Bit
EPROG.EPGM        0  EPROM Programming Bit
ACR             0x001D   Analog Counter Register
ACR.CHG           7
ACR.ATD2          6
ACR.ATD1          5
ACR.ICEN          4
ACR.CPIE          3
ACR.CP2EN         2
ACR.CP1EN         1
ACR.ISEN          0
ASR             0x001E   Analog Status Register
ASR.CPF2          7
ASR.CPF1          6
ASR.CPFR2         5
ASR.CPFR1         4
ASR.COE1          3
ASR.VOFF          2
ASR.CMP2          1
ASR.CMP1          0
Reserv001F      0x001F   RESERVED
Reserv1FEF      0x1FEF   RESERVED
COPR            0x1FF0   COP and Security Register
COPR.EPMSEC       7  EPROM Security Bit
COPR.OPT          6  Optional Features Bit
COPR.COPC         0  COP Clear Bit


.68HC705K1
; MC68HC705K1/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC705K1.pdf
; MC68HC705K1.pdf

; RAM=32
; ROM=0
; EPROM=496
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x00E0
area DATA RAM         0x00E0:0x0100
area BSS  UNUSED      0x0100:0x0200
area CODE EPROM       0x0200:0x03F0
area DATA ROM_TEST    0x03F0:0x03F8
area DATA USER_VEC    0x03F8:0x0400


; Interrupt and reset vector assignments
interrupt __RESET           0x03FE      Processor reset
interrupt SWI               0x03FC      Software interrupt
interrupt IRQ               0x03FA      ...
interrupt TIMER             0x03F8


; INPUT/ OUTPUT PORTS
PORTA           0x0000    Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001    Port B data
PORTB.PB1	 1   Port B Data Bits 1
PORTB.PB0	 0   Port B Data Bits 0	
UNUSED0002      0x0002    UNUSED
UNUSED0003      0x0003    UNUSED
DDRA            0x0004    Port A data direction
DDRA.DDRA7	 7   Data Direction for Port A Bit 7
DDRA.DDRA6	 6   Data Direction for Port A Bit 6
DDRA.DDRA5	 5   Data Direction for Port A Bit 5
DDRA.DDRA4	 4   Data Direction for Port A Bit 4
DDRA.DDRA3	 3   Data Direction for Port A Bit 3
DDRA.DDRA2	 2   Data Direction for Port A Bit 2
DDRA.DDRA1	 1   Data Direction for Port A Bit 1
DDRA.DDRA0	 0   Data Direction for Port A Bit 0
DDRB            0x0005    Port B data direction
DDRB.DDRB1	 1   Data Direction for Port B Bit 1
DDRB.DDRB0	 0   Data Direction for Port B Bit 0
UNUSED0006      0x0006    UNUSED
UNUSED0007      0x0007    UNUSED
TSCR            0x0008    Timer Status and Control Register
TSCR.TOF	 7   Timer Overflow Flag	
TSCR.RTIF        6   Real-Time Interrupt Flag
TSCR.TOIE        5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE        4   Real-Time Interrupt Enable Bit
TSCR.TOFR        3   Timer Overflow Flag Reset
TSCR.RTIFR       2   Real-Time Interrupt Flag Reset
TSCR.RT1	 1   Real-Time Interrupt Select Bit 1
TSCR.RT0	 0   Real-Time Interrupt Select Bit 0
TCNTR           0x0009    Timer Counter Register
ISCR            0x000A    IRQ Status and Control Register
ISCR.IRQE        7   External Interrupt Request Enable Bit
ISCR.IRQF        3   External Interrupt Request Flag
ISCR.IRQR        0   Interrupt Request Reset Bit
UNUSED000B      0x000B    UNUSED
UNUSED000C      0x000C    UNUSED
UNUSED000D      0x000D    UNUSED
PEBSR           0x000E    PERROM Bit Select Register
PEBSR.PEB7       7   Not Connected to the PEPROM Array 7
PEBSR.PEB6       6   Not Connected to the PEPROM Array 6
PEBSR.PEB5       5   PEPROM Bit Select Bit 5
PEBSR.PEB4       4   PEPROM Bit Select Bit 4
PEBSR.PEB3       3   PEPROM Bit Select Bit 3
PEBSR.PEB2       2   PEPROM Bit Select Bit 2
PEBSR.PEB1       1   PEPROM Bit Select Bit 1
PEBSR.PEB0       0   PEPROM Bit Select Bit 0
PESCR           0x000F    PERROM Status and Control Register
PESCR.PEDATA     7   PEPROM Data Bit
PESCR.PEPGM      5   PEPROM Program Control Bit
PESCR.PEPRZF     0   PEPROM Row Zero Flag
PDRA            0x0010    Pulldown Register A
PDRA.PDIA7       7   Port A Pulldown Inhibit Bit 7
PDRA.PDIA6       6   Port A Pulldown Inhibit Bit 6
PDRA.PDIA5       5   Port A Pulldown Inhibit Bit 5
PDRA.PDIA4       4   Port A Pulldown Inhibit Bit 4
PDRA.PDIA3       3   Port A Pulldown Inhibit Bit 3
PDRA.PDIA2       2   Port A Pulldown Inhibit Bit 2
PDRA.PDIA1       1   Port A Pulldown Inhibit Bit 1
PDRA.PDIA0       0   Port A Pulldown Inhibit Bit 0
PDRB            0x0011    Pulldown Register B
PDRB.PDIB1       1   Port B Pulldown Inhibit Bit 1
PDRB.PDIB0       0   Port B Pulldown Inhibit Bit 0
UNUSED0012      0x0012    UNUSED
UNUSED0013      0x0013    UNUSED
UNUSED0014      0x0014    UNUSED
UNUSED0015      0x0015    UNUSED
UNUSED0016      0x0016    UNUSED
MOR             0x0017    Mask Option Register
MOR.SWPDI        7   Software Pulldown Inhibit Bit
MOR.PIN3         6   3-Pin RC Oscillator Bit
MOR.RC           5   RC Oscillator Bit
MOR.SWAIT        4   STOP Conversion to WAIT Bit
MOR.LVRE         3   Low-Voltage Reset Enable Bit
MOR.PIRQ         2   Port A IRQ Enable Bit
MOR.LEVEL        1   External Interrupt Sensitivity Bit
MOR.COPEN        0   COP Watchdog Enable Bit
EPROG           0x0018    EPROM Programming Register
EPROG.ELAT       2   EPROM Bus Latch Bit
EPROG.MPGM       1   Mask Option Register (MOR) Programming Bit
EPROG.EPGM       0   EPROM Programming Bit
UNUSED0019      0x0019    UNUSED
UNUSED001A      0x001A    UNUSED
UNUSED001B      0x001B    UNUSED
UNUSED001C      0x001C    UNUSED
UNUSED001D      0x001D    UNUSED
UNUSED001E      0x001E    UNUSED
TEST            0x001F    Test Registe
TEST.LVRF        1
COPR            0x03F0    COP Register
COPR.COPC        0   COP Clear Bit
RESERV03F1      0x03F1    RESERVED
RESERV03F2      0x03F2    RESERVED
RESERV03F3      0x03F3    RESERVED
RESERV03F4      0x03F4    RESERVED
RESERV03F5      0x03F5    RESERVED
RESERV03F6      0x03F6    RESERVED
RESERV03F7      0x03F7    RESERVED


.68HC705KJ1
; MC68HC705KJ1/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705KJ1&nodeId=01M98633
; MC68HC705KJ1.pdf

; RAM=64
; ROM=0
; EPROM=1.2K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x00C0
area DATA RAM         0x00C0:0x0100
area BSS  UNUSED      0x0100:0x0300
area DATA EPROM       0x0300:0x07D0
area BSS  UNUSED      0x07D0:0x07EE
area DATA ROM_TEST    0x07EE:0x07F0
area DATA USER_VEC    0x07F0:0x0800


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Processor reset
interrupt SWI               0x07FC      Software interrupt
interrupt IRQ               0x07FA      External Interrupt
interrupt TIMER             0x07F8      Timer Interupt


; INPUT/ OUTPUT PORTS
PORTA           0x0000    Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001    Port B data
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
UNUSED0002      0x0002    UNUSED
UNUSED0003      0x0003    UNUSED
DDRA            0x0004    Port A data direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005    Port B data direction
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
UNUSED0006      0x0006    UNUSED
UNUSED0007      0x0007    UNUSED
TSCR            0x0008  Timer Status and Control
TSCR.TOF         7   Timer Overflow Flag
TSCR.RTIF        6   Real-Time Interrupt Flag
TSCR.TOIE        5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE        4   Real-Time Interrupt Enable Bit
TSCR.TOFR        3   Timer Overflow Flag Reset Bit
TSCR.RTIFR       2   Real-Time Interrupt Flag Reset Bit
TSCR.RT1         1   Real-Time Interrupt Select Bits 1
TSCR.RT0         0   Real-Time Interrupt Select Bits 0
TCR             0x0009  Timer Counter
TCR.TCR7         7
TCR.TCR6         6
TCR.TCR5         5
TCR.TCR4         4
TCR.TCR3         3
TCR.TCR2         2
TCR.TCR1         1
TCR.TCR0         0
ISCR            0x000A  IRQ Status and Control
ISCR.IRQE        7   External Interrupt Request Enable Bit
ISCR.IRQF        3   External Interrupt Request Flag
ISCR.IRQR        1   Interrupt Request Reset Bit
UNUSED000B      0x000B    UNUSED
UNUSED000C      0x000C    UNUSED
UNUSED000D      0x000D    UNUSED
UNUSED000E      0x000E    UNUSED
UNUSED000F      0x000F    UNUSED
PDRA            0x0010    Pulldown Register Port A
PDRA.PDRA7       7   Port A Pulldown Inhibit Bit 7
PDRA.PDRA6       6   Port A Pulldown Inhibit Bit 6
PDRA.PDRA5       5   Port A Pulldown Inhibit Bit 5
PDRA.PDRA4       4   Port A Pulldown Inhibit Bit 4
PDRA.PDRA3       3   Port A Pulldown Inhibit Bit 3
PDRA.PDRA2       2   Port A Pulldown Inhibit Bit 2
PDRA.PDRA1       1   Port A Pulldown Inhibit Bit 1
PDRA.PDRA0       0   Port A Pulldown Inhibit Bit 0
PDRB            0x0011     Pulldown Register Port B
PDRB.PDIB3       3   Port B Pulldown Inhibit Bit 3
PDRB.PDIB2       2   Port B Pulldown Inhibit Bit 2
UNUSED0012      0x0012    UNUSED
UNUSED0013      0x0013    UNUSED
UNUSED0014      0x0014    UNUSED
UNUSED0015      0x0015    UNUSED
UNUSED0016      0x0016    UNUSED
UNUSED0017      0x0017    UNUSED
EPROG           0x0018    EPROM Programming
EPROG.ELAT       2   EPROM Bus Latch Bit
EPROG.MPGM       1   MOR Programming Bit
EPROG.EPGM       0   EPROM Programming Bit
UNUSED0019      0x0019    UNUSED
UNUSED001A      0x001A    UNUSED
UNUSED001B      0x001B    UNUSED
UNUSED001C      0x001C    UNUSED
UNUSED001D      0x001D    UNUSED
UNUSED001E      0x001E    UNUSED
RESERV001F      0x001F   RESERVED
COPR            0x07F0   COP Register
COPR.COPC        0   COP Clear Bit
MOR             0x07F1   Mask Options
MOR.SOSCD        7   Short Oscillator Delay Bit
MOR.EPMSEC       6   EPROM Security Bit
MOR.OSCRES       5   Oscillator Internal Resistor Bit
MOR.SWAIT        4   Stop-to-Wait Conversion Bit
MOR.PDI          3   Software Pulldown Inhibit Bit
MOR.PIRQ         2   Port A External Interrupt Bit
MOR.LEVEL        1   External Interrupt Sensitivity Bit
MOR.COPEN        0   COP Enable Bit
RESERV07F2      0x07F2            RESERVED
RESERV07F3      0x07F3            RESERVED
RESERV07F4      0x07F4            RESERVED
RESERV07F5      0x07F5            RESERVED
RESERV07F6      0x07F6            RESERVED
RESERV07F7      0x07F7            RESERVED


.68HC705L16
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705L16&nodeId=01M98633
; HC05L16GRS.pdf

; RAM=512
; ROM=0
; EPROM=16K
; EEPROM=0      


; MEMORY MAP
area DATA FSR         0x0000:0x0040
area DATA RAM         0x0040:0x0240
area BSS  UNUSED      0x0240:0x1000
area DATA EPROM       0x1000:0x5000
area BSS  UNUSED      0x5000:0xFE00
area DATA BootROM     0xFE00:0xFFE0
area DATA TEST_VEC    0xFFE0:0xFFF0
area DATA USER_VEC    0xFFF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt SWI               0xFFFC      Software interrupt
interrupt IRQ               0xFFFA      ...
interrupt KWI               0xFFF8
interrupt TIMER1            0xFFF6
interrupt TIMER2            0xFFF4
interrupt SSPI              0xFFF2
interrupt TIMEBASE          0xFFF0


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTE                 0x0004   Port E data
PORTE.PE7              7   Port E Data Bits 7
PORTE.PE6              6   Port E Data Bits 6
PORTE.PE5              5   Port E Data Bits 5
PORTE.PE4              4   Port E Data Bits 4
PORTE.PE3              3   Port E Data Bits 3
PORTE.PE2              2   Port E Data Bits 2
PORTE.PE1              1   Port E Data Bits 1
PORTE.PE0              0   Port E Data Bits 0
RESERV0005            0x0005   RESERVED
RESERV0006            0x0006   RESERVED
RESERV0007            0x0007   RESERVED
INTCR                 0x0008   Interrupt Control
INTCR.IRQ1E            7   IRQ1 Interrupt Enable
INTCR.IRQ2E            6   IRQ2 Interrupt Enable
INTCR.KWIE             4   Key Wakeup Interrupt (KWI) Enable
INTCR.IRQ1S            3   IRQ1 Select Edge Sensitive Only
INTCR.IRQ2S            2   IRQ2 Select Edge Sensitive Only
INTSR                 0x0009   Interrupt Status
INTSR.IRQ1F            7   IRQ1 Interrupt Flag
INTSR.IRQ2F            6   IRQ2 Interrupt Flag
INTSR.KWIF             4   Key Wakeup Interrupt Flag
INTSR.RIRQ1            3   Reset IRQ1 Flag
INTSR.RIRQ2            2   Reset IRQ2 Flag
INTSR.RKWIF            0   Reset KWI Flag
SPCR                  0x000A   Serial Peripheral Control
SPCR.SPIE              7   SSPI Interrupt Enable
SPCR.SPE               6   SSPI Enable
SPCR.DORD              5   Data Transmission ORDer
SPCR.MSTR              4   MaSTeR Mode Select
SPCR.SPR               0   SSPI Clock Rate Select
SPSR                  0x000B   Serial peripheral Status
SPSR.SPIF              7   Serial Transfer Complete Flag
SPSR.DCOL              6   Data COLlision
SPDR                  0x000C   Serial Peripheral Data
SPDR.MSB               7
SPDR.LSB               0
PCR                   0x000D   Program Control Register
PCR.ELAT               1   EPROM LATch control
PCR.PGM                0   EPROM ProGraM command
RESERV000E            0x000E   RESERVED
RESERV000F            0x000F   RESERVED
TBCR1                 0x0010   Timer Base Control Register 1
TBCR1.TBCLK            7   Timebase Clock
TBCR1.LCLK             5   LCD Clock
TBCR1.T2R1             1   Timer 2 Prescale Rate Select Bits 1
TBCR1.T2R0             0   Timer 2 Prescale Rate Select Bits 0
TBCR2                 0x0011   Timer Base Control Register 2
TBCR2.TBIF             7   Timebase Interrupt Flag
TBCR2.TBIE             6   Timebase Interrupt Enable
TBCR2.TBR1             5   Timebase Interrupt Rate Select 1
TBCR2.TBR0             4   Timebase Interrupt Rate Select 0
TBCR2.RTBIF            3   Reset TBS Interrupt Flag
TBCR2.COPE             1   COP Enable
TBCR2.COPC             0   COP Clear
TCR                   0x0012   Timer  control
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare 1 Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.IEDG               1   Input Edge
TCR.OLVL               0   Not Used
TSR                   0x0013   Timer  status
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare 1 Flag
TSR.TOF                5   Timer Overflow Flag
ICH                   0x0014   Input capture
ICL                   0x0015   Input capture
OC1H                  0x0016   Output compare
OC1L                  0x0017   Output compare
TCNTH                 0x0018   Timer  Counter
TCNTL                 0x0019   Timer  Cunter
ACNTH                 0x001A   Alternate Timer Counter
ACNTL                 0x001B   Alternate Timer Counter
TCR2                  0x001C   Timer Control Register 2
TCR2.TI2IE             7   Timer Input 2 Interrupt Enable
TCR2.OC2IE             6   Compare 2 Interrupt Enable
TCR2.T2CLK             4   Timer 2 Clock Select
TCR2.IM2               3   Timer Input 2 Mode Select
TCR2.IL2               2   Timer Input 2 Active Edge (Level) Select
TCR2.OE2               1   Timer Output 2 (EVO) Output Enable
TCR2.OL2               0   Timer Output 2 Edge Select for Synchronization
TSR2                  0x001D   Timer Status Register 2
TSR2.TI2F              7   Timer Input 2 (EVI) Interrupt Flag
TSR2.OC2F              6   Compare 2 Interrupt Flag
TSR2.RTI2F             3   Reset Timer Input 2 Flag
TSR2.ROC2F             2   Reset Output Compare 2 Flag
OC2                   0x001E   Output Compare Register 2
TCNT2                 0x001F   Timer Conter Register 2
LCDCR                 0x0020   LCD Control
LCDCR.LCDE             7   LCD Output Enable
LCDCR.DUTY1            6   LCD Duty Select 1
LCDCR.DUTY0            5   LCD Duty Select 0
LCDCR.PEH              3   Select Port E (H)
LCDCR.PEL              2   Select Port E (L)
LCDCR.PDH              1   Select Port D (H)
LCDR1                 0x0021   LCD Data Register 1
LCDR1.F1B3             7
LCDR1.F1B2             6
LCDR1.F1B1             5
LCDR1.F1B0             4
LCDR1.F0B3             3
LCDR1.F0B2             2
LCDR1.F0B1             1
LCDR1.F0B0             0
LCDR2                 0x0022   LCD Data Register 2
LCDR2.F3B3             7
LCDR2.F3B2             6
LCDR2.F3B1             5
LCDR2.F3B0             4
LCDR2.F2B3             3
LCDR2.F2B2             2
LCDR2.F2B1             1
LCDR2.F2B0             0
LCDR3                 0x0023   LCD Data Register 3
LCDR3.F5B3             7
LCDR3.F5B2             6
LCDR3.F5B1             5
LCDR3.F5B0             4
LCDR3.F4B3             3
LCDR3.F4B2             2
LCDR3.F4B1             1
LCDR3.F4B0             0
LCDR4                 0x0024   LCD Data Register 4
LCDR4.F7B3             7
LCDR4.F7B2             6
LCDR4.F7B1             5
LCDR4.F7B0             4
LCDR4.F6B3             3
LCDR4.F6B2             2
LCDR4.F6B1             1
LCDR4.F6B0             0
LCDR5                 0x0025   LCD Data Register 5
LCDR5.F9B3             7
LCDR5.F9B2             6
LCDR5.F9B1             5
LCDR5.F9B0             4
LCDR5.F8B3             3
LCDR5.F8B2             2
LCDR5.F8B1             1
LCDR5.F8B0             0
LCDR6                 0x0026   LCD Data Register 6
LCDR6.F11B3            7
LCDR6.F11B2            6
LCDR6.F11B1            5
LCDR6.F11B0            4
LCDR6.F10B3            3
LCDR6.F10B2            2
LCDR6.F10B1            1
LCDR6.F10B0            0
LCDR7                 0x0027   LCD Data Register 7
LCDR7.F13B3            7
LCDR7.F13B2            6
LCDR7.F13B1            5
LCDR7.F13B0            4
LCDR7.F12B3            3
LCDR7.F12B2            2
LCDR7.F12B1            1
LCDR7.F12B0            0
LCDR8                 0x0028   LCD Data Register 8
LCDR8.F15B3            7
LCDR8.F15B2            6
LCDR8.F15B1            5
LCDR8.F15B0            4
LCDR8.F14B3            3
LCDR8.F14B2            2
LCDR8.F14B1            1
LCDR8.F14B0            0
LCDR9                 0x0029   LCD Data Register 9
LCDR9.F17B3            7
LCDR9.F17B2            6
LCDR9.F17B1            5
LCDR9.F17B0            4
LCDR9.F16B3            3
LCDR9.F16B2            2
LCDR9.F16B1            1
LCDR9.F16B0            0
LCDR10                0x002A   LCD Data Register 10
LCDR10.F19B3           7
LCDR10.F19B2           6
LCDR10.F19B1           5
LCDR10.F19B0           4
LCDR10.F18B3           3
LCDR10.F18B2           2
LCDR10.F18B1           1
LCDR10.F18B0           0
LCDR11                0x002B   LCD Data Register 11
LCDR11.F21B3           7
LCDR11.F21B2           6
LCDR11.F21B1           5
LCDR11.F21B0           4
LCDR11.F20B3           3
LCDR11.F20B2           2
LCDR11.F20B1           1
LCDR11.F20B0           0
LCDR12                0x002C   LCD Data Register 12
LCDR12.F23B3           7
LCDR12.F23B2           6
LCDR12.F23B1           5
LCDR12.F23B0           4
LCDR12.F22B3           3
LCDR12.F22B2           2
LCDR12.F22B1           1
LCDR12.F22B0           0
LCDR13                0x002D   LCD Data Register 13
LCDR13.F25B3           7
LCDR13.F25B2           6
LCDR13.F25B1           5
LCDR13.F25B0           4
LCDR13.F25B3           3
LCDR13.F25B2           2
LCDR13.F25B1           1
LCDR13.F25B0           0
LCDR14                0x002E   LCD Data Register 14
LCDR14.F27B3           7
LCDR14.F27B2           6
LCDR14.F27B1           5
LCDR14.F27B0           4
LCDR14.F26B3           3
LCDR14.F26B2           2
LCDR14.F26B1           1
LCDR14.F26B0           0
LCDR15                0x002F   LCD Data Register 15
LCDR15.F29B3           7
LCDR15.F29B2           6
LCDR15.F29B1           5
LCDR15.F29B0           4
LCDR15.F28B3           3
LCDR15.F28B2           2
LCDR15.F28B1           1
LCDR15.F28B0           0
LCDR16                0x0030   LCD Data Register 16
LCDR16.F31B3           7
LCDR16.F31B2           6
LCDR16.F31B1           5
LCDR16.F31B0           4
LCDR16.F30B3           3
LCDR16.F30B2           2
LCDR16.F30B1           1
LCDR16.F30B0           0
LCDR17                0x0031   LCD Data Register 17
LCDR17.F33B3           7
LCDR17.F33B2           6
LCDR17.F33B1           5
LCDR17.F33B0           4
LCDR17.F32B3           3
LCDR17.F32B2           2
LCDR17.F32B1           1
LCDR17.F32B0           0
LCDR18                0x0032   LCD Data Register 18
LCDR18.F35B3           7
LCDR18.F35B2           6
LCDR18.F35B1           5
LCDR18.F35B0           4
LCDR18.F34B3           3
LCDR18.F34B2           2
LCDR18.F34B1           1
LCDR18.F34B0           0
LCDR19                0x0033   LCD Data Register 19
LCDR19.F37B3           7
LCDR19.F37B2           6
LCDR19.F37B1           5
LCDR19.F37B0           4
LCDR19.F36B3           3
LCDR19.F36B2           2
LCDR19.F36B1           1
LCDR19.F36B0           0
LCDR20                0x0034   LCD Data Register 20
LCDR20.F38B3           3
LCDR20.F38B2           2
LCDR20.F38B1           1
LCDR20.F38B0           0
RESERV0035            0x0035   RESERVED
RESERV0036            0x0036   RESERVED
RESERV0037            0x0037   RESERVED
RESERV0038            0x0038   RESERVED
RESERV0039            0x0039   RESERVED
RESERV003A            0x003A   RESERVED
RESERV003B            0x003B   RESERVED
RESERV003C            0x003C   RESERVED
RESERV003D            0x003D   RESERVED
MISC                  0x003E   Miscellaneous
MISC.FTUP              7   OSC Time Up Flag
MISC.STUP              6   XOSC Time Up Flag
MISC.SYS1              3   System Clock Select 1
MISC.SYS0              2   System Clock Select 0
MISC.FORCE             1   Fast (Main) Oscillator Enable
MISC.OPTM              0   Option Map Select
RESERV003F            0x003F   RESERVED


.68HC705L28
; http://
; MC68HC05L28.pdf

; RAM=256
; ROM=0
; EPROM=8128
; EEPROM=240


; MEMORY MAP
area DATA FSR        0x0000:0x0040
area DATA LCD_RAM    0x0040:0x004C
area BSS  RESERVED   0x004C:0x0080
area DATA RAM        0x0080:0x0180
area BSS  RESERVED   0x0180:0x0300
area CODE EEPROM     0x0300:0x03F0
area BSS  RESERVED   0x03F0:0x1000
area CODE EPROM      0x1000:0x2FC0
area BSS  RESERVED   0x2FC0:0x3F00
area CODE BootROM    0x3F00:0x3FF0
area DATA USER_VEC   0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET 	0x3FFE       Reset
interrupt SWI 		0x3FFC       Software interrupt
interrupt IRQ 		0x3FFA       External interrupt
interrupt CTIMER	0x3FF8       Core timer
interrupt I2C 		0x3FF6       I2C
interrupt PTIMER 	0x3FF4       Programmable timer


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
RESERV0002            0x0002    RESERVED
RESERV0003            0x0003    RESERVED
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005   Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
RESERV0006            0x0006   RESERVED
RESERV0007            0x0007   RESERVED
CTCSR                 0x0008   Core timer control/status
CTCSR.CTOF             7   Core timer overflow
CTCSR.RTIF             6   Real time interrupt flag
CTCSR.CTOFE            5   Core timer overflow enable
CTCSR.RTIE             4   Real time interrupt enable
CTCSR.RT1              1   Real time interrupt rate select 1
CTCSR.RT0              0   Real time interrupt rate select 0
CTCR                  0x0009   Core timer counter
IRQ1                  0x000A   IRQ1
IRQ1.IRQ1INT           5   IRQ1 interrupt flag            
IRQ1.IRQ1ENA           4   IRQ1 interrupt enable          
IRQ1.IRQ1LV            3   IRQ1 interrupt sensitivity bits
IRQ1.IRQ1EDG           2   IRQ1 interrupt sensitivity bits
IRQ1.IRQ1RST           1   IRQ1 reset                     
IRQ1.IRQ1VAL           0   IRQ1 pin status                
IRQ2                  0x000B   IRQ2
IRQ2.IRQ2INT           5   IRQ2 interrupt flag
IRQ2.IRQ2ENA           4   IRQ2 interrupt enable
IRQ2.IRQ2LV            3   IRQ2 interrupt sensitivity bits
IRQ2.IRQ2EDG           2   IRQ2 interrupt sensitivity bits
IRQ2.IRQ2RST           1   IRQ2 reset
IRQ2.IRQ2VAL           0   IRQ2 pin status
RESERV000C            0x000C   RESERVED
RESERV000D            0x000D   RESERVED
RESERV000E            0x000E   RESERVED
RESERV000F            0x000F   RESERVED
MADR                  0x0010   I2 address
MADR.ADR7              7   Slave address bit 7
MADR.ADR6              6   Slave address bit 6
MADR.ADR5              5   Slave address bit 5
MADR.ADR4              4   Slave address bit 4
MADR.ADR3              3   Slave address bit 3
MADR.ADR2              2   Slave address bit 2
MADR.ADR1              1   Slave address bit 1
FDR                   0x0011   I2C frequency divide
FDR.MBC4               4   Clock rate select bit 4
FDR.MBC3               3   Clock rate select bit 3
FDR.MBC2               2   Clock rate select bit 2
FDR.MBC1               1   Clock rate select bit 1
FDR.MBC0               0   Clock rate select bit 0
MCR                   0x0012   I2C control
MCR.MEN                7   I2C-bus enable
MCR.MIEN               6   I2C-bus interrupt enable
MCR.MSTA               5   Master/slave mode select
MCR.MTX                4   Transmit/receive mode select
MCR.TXAK               3   Transmit acknowledge bit
MSR                   0x0013   I2C status
MSR.MCF                7   Data transferring
MSR.MAAS               6   I2C-bus addressed as a slave
MSR.MBB                5   Bus busy
MSR.MAL                4   Arbitration lost
MSR.SRW                2   Read/write command
MSR.MIF                1   I2C-bus interrupt flag
MSR.RXAK               0   Received acknowledge bit
MDR                   0x0014   I2C data
MDR.TRXD7              7
MDR.TRXD6              6
MDR.TRXD5              5
MDR.TRXD4              4 
MDR.TRXD3              3
MDR.TRXD2              2
MDR.TRXD1              1
MDR.TRXD0              0
ADSTAT                0x0015   A/D status control
ADSTAT.COCO            7   Conversion complete flag
ADSTAT.ADRC            6   A/D RC oscillator control
ADSTAT.ADON            5   A/D converter on
ADSTAT.CH3             3   A/D channels 3
ADSTAT.CH2             2   A/D channels 2
ADSTAT.CH1             1   A/D channels 1
ADSTAT.CH0             0   A/D channels 0
ADIN                  0x0016   A/D input
ADIN.AD1               1
ADIN.AD0               0
ADDATA                0x0017   A/D data
RESERV0018            0x0018   RESERVED
RESERV0019            0x0019   RESERVED
RESERV001A            0x001A   RESERVED
EEPROG                0x001B   EEPROM Program
EEPROG.CPEN            6   Charge pump enable
EEPROG.ER1             4   Erase select bits 1
EEPROG.ER0             3   Erase select bits 0
EEPROG.LATCH           2   EEPROM latch control
EEPROG.EERC            1   EEPROM RC oscillator control
EEPROG.EEPGM           0   EEPROM program control
PCR                   0x001C   EPROM program
PCR.ELAT               1   EPROM latch control
PCR.PGM                0   EPROM program control
OPT                   0x001D   Option
OPT.IRQED              1   IRQ edge sensitivity       
OPT.COPON              0   COP function enable/disable
LCD                   0x001E   LCD control
LCD.VLCDON             6   LCD voltage select
LCD.FDISP              3   Display frequency
LCD.MUX4               2   Multiplex ratio 4
LCD.MUX3               1   Multiplex ratio 3
LCD.DISON              0   Display ON/OFF
RESERV001F            0x001F   RESERVED
IC1H                  0x0020   Input capture1 HIGH
IC1L                  0x0021   Input capture1 LOW
OC1H                  0x0022   Output compare 1 HIGH
OC1L                  0x0023   Output compare 1 LOW
IC2H                  0x0024   Input capture2 HIGH
IC2L                  0x0025   Input capture2 LOW
OC2H                  0x0026   Output compare 2 HIGH
OC2L                  0x0027   Output compare 2 LOW
TCH                   0x0028   Timer counter HIGH
TCL                   0x0029   Timer counter LOW
ACH                   0x002A   Alternater counter HIGH
ACL                   0x002B   Alternater counter LOW
TCR1                  0x002C   Timer control 1
TCR1.IC1IE             7   Input capture 1 interrupt enable
TCR1.IC2IE             6   Input capture 2 interrupt enable
TCR1.OC1IE             5   Output compare 1 interrupt enable
TCR1.TOIE              4   Timer overflow interrupt enable
TCR1.CO1E              3   Timer compare 1 output enable
TCR1.IEDG1             2   Input edge 1
TCR1.IEDG2             1   Input edge 2
TCR1.OLV1              0   Output level 1
TCR2                  0x002D   Timer control 2
TCR2.OC2IE             5   Output compare 2 interrupt enable
TCR2.CO2E              3   Timer compare 2 output enable
TCR2.OLV2              0   Output level 2
TSR                   0x002E   Timer status
TSR.IC1F               7   Input capture 1 flag
TSR.IC2F               6   Input capture 2 flag
TSR.OC1F               5   Output compare 1 flag
TSR.TOF                4   Timer overflow flag
TSR.TCAP1              3   Timer capture 1
TSR.TCAP2              2   Timer capture 2
TSR.OC2F               1   Output compare 2 flag
RESERV002F            0x002F   RESERVED
PORTD                 0x0030   Port D Datat
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRD                  0x0031  Port D Data direction
DDRD.DDRD5             5   Data Direction for Port D Bit 5
DDRD.DDRD4             4   Data Direction for Port D Bit 4
DDRD.DDRD3             3   Data Direction for Port D Bit 3
DDRD.DDRD2             2   Data Direction for Port D Bit 2
DDRD.DDRD1             1   Data Direction for Port D Bit 1
DDRD.DDRD0             0   Data Direction for Port D Bit 0
COND                  0x0032   Port D control
COND.COND5             5
COND.COND4             4
COND.COND3             3
COND.COND2             2
COND.COND1             1
COND.COND0             0
SELD                  0x0033   Port D select
SELD.PD5_SCL0          5   Port D pin 5/SCL0 select
SELD.PD4_SDA0          4   Port D pin 4/SCL1 select
SELD.PD3_TCMP2         3   Port D pin 3/TCMP2 select
SELD.PD2_TCAP2         2   Port D pin 2/TCAP2 select
SELD.PD1_TCMP1         1   Port D pin 1/TCMP1 select
SELD.PD0_TCAP1         0   Port D pin 0/TCAP1 select
RESERV0034            0x0034   RESERVED
RESERV0035            0x0035   RESERVED
RESERV0036            0x0036   RESERVED
RESERV0037            0x0037   RESERVED
RESERV0038            0x0038   RESERVED
RESERV0039            0x0039   RESERVED
RESERV003A            0x003A   RESERVED
RESERV003B            0x003B   RESERVED
RESERV003C            0x003C   RESERVED
RESERV003D            0x003D   RESERVED
RESERV003E            0x003E   RESERVED
RESERV003F            0x003F   RESERVED
COP                   0x3FF0   COP
COP.COPR               0
RESERV3FF1            0x3FF1   RESERVED
RESERV3FF2            0x3FF2   RESERVED
RESERV3FF3            0x3FF3   RESERVED


.68HC705P3
; http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC05P3.pdf
; MC68HC05P3.pdf

; RAM=128
; ROM=2k 
; EPROM=0 
; EEPROM=128


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x0080
area DATA RAM         0x0080:0x0100
area DATA EEPROM      0x0100:0x0180
area BSS  UNUSED      0x0180:0x0300
area CODE _EPROM_     0x0300:0x0F00
area DATA BootROM     0x0F00:0x0FE0
area DATA BOOT_VEC    0x0FE0:0x0FF0
area BSS  RESERVED    0x0FF0:0x0FF6
area DATA USER_VEC    0x0FF6:0x1000


; Interrupt and reset vector assignments
interrupt __RESET           0x0FFE      Processor reset
interrupt SWI               0x0FFC      Software interrupt
interrupt IRQ_Keyboard      0x0FFA      ...
interrupt CoreTimer_RTI     0x0FF8
interrupt TIMER             0x0FF6


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0        
UNUSED0003            0x0003    UNUSED
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006    Port C data direction
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007    UNUSED
CTCSR                 0x0008    CTimer control and Status Register
CTCSR.CTOF             7   Timer Overflow Flag              
CTCSR.RTIF             6   Real Time Interrupt Flag         
CTCSR.CTOFE            5   Timer Overflow Enable            
CTCSR.RTIE             4   Real Time Interrupt Enable       
CTCSR.RT1              1   Real Time Interrupt Rate Select 1
CTCSR.RT0F             0   Real Time Interrupt Rate Select 0
CTCR                  0x0009    CTimer Counter Register
CTCR.CT7               7
CTCR.CT6               6
CTCR.CT5               5
CTCR.CT4               4
CTCR.CT3               3
CTCR.CT2               2
CTCR.CT1               1
CTCR.CT0               0
KEY_TIM               0x000A    Keyboard/timer
KEY_TIM.TIMEN          2
KEY_TIM.KSF            1
KEY_TIM.KIE            0        
UNUSED000B            0x000B    UNUSED
UNUSED000C            0x000C    UNUSED
UNUSED000D            0x000D    UNUSED
UNUSED000E            0x000E    UNUSED
OPT                   0x000F    IRQ status/control
OPT.OPTCOP             1
OPT.OPTIRQ             0
UNUSED0010            0x0010    UNUSED
UNUSED0011            0x0011    UNUSED
TCR                   0x0012    Timer control
TCR.ICIE               7
TCR.OCIE               6
TCR.TOIE               5
TCR.IEDG               1
TCR.OLVL               0
TSR                   0x0013    Timer status
TSR.ICF                7
TSR.OCF                6
TSR.TOF                5
ICH                   0x0014    Input capture high
ICH.IC15               7
ICH.IC14               6
ICH.IC13               5
ICH.IC12               4
ICH.IC11               3
ICH.IC10               2
ICH.IC9                1
ICH.IC8                0
ICL                   0x0015    Input capture low
ICL.IC7                7
ICL.IC6                6
ICL.IC5                5
ICL.IC4                4
ICL.IC3                3
ICL.IC2                2
ICL.IC1                1
ICL.IC0                0
OCH                   0x0016    Output compare high
OCH.OC15               7
OCH.OC14               6
OCH.OC13               5
OCH.OC12               4
OCH.OC11               3
OCH.OC10               2
OCH.OC9                1
OCH.OC8                0
OCL                   0x0017    Output compare low
OCL.OC7                7
OCL.OC6                6 
OCL.OC5                5 
OCL.OC4                4
OCL.OC3                3
OCL.OC2                2
OCL.OC1                1
OCL.OC0                0
TCH                   0x0018     Counter high
TCH.TC15               7
TCH.TC14               6
TCH.TC13               5
TCH.TC12               4
TCH.TC11               3
TCH.TC10               2
TCH.TC9                1
TCH.TC8                0
TCL                   0x0019     Counter low
TCL.TC7                7
TCL.TC6                6
TCL.TC5                5
TCL.TC4                4
TCL.TC3                3
TCL.TC2                2
TCL.TC1                1
TCL.TC0                0
ACH                   0x001A    Alternate counter high
ACH.AC15               7
ACH.AC14               6
ACH.AC13               5 
ACH.AC12               4
ACH.AC11               3
ACH.AC10               2
ACH.AC9                1
ACH.AC8                0
ACL                   0x001B    Alternate counter low
ACL.AC7                7
ACL.AC6                6
ACL.AC5                5
ACL.AC4                4
ACL.AC3                3
ACL.AC2                2
ACL.AC1                1
ACL.AC0                0
EEPROG                0x001C    EEPROM programming control
EEPROG.CPEN            6   Charge pump enable          
EEPROG.ER1             4   Erase select bit 1          
EEPROG.ER0             3   Erase select bit 0          
EEPROG.LATCH           2   EEPROM latch control        
EEPROG.EERC            1   EEPROM RC oscillator control
EEPROG.EEPGM           0   EEPROM program control      
PROG                  0x001D    EPROM programming
PROG.ELATCH            2
PROG.EPGM              0
RESERV001F            0x001F    RESERVED
RESERV0FF0            0x0FF0    RESERVED
RESERV0FF1            0x0FF1    RESERVED
RESERV0FF2            0x0FF2    RESERVED
RESERV0FF3            0x0FF3    RESERVED
RESERV0FF4            0x0FF4    RESERVED
RESERV0FF5            0x0FF5    RESERVED


.68HC705P6A
; MC68HC705P6A/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705P6A&nodeId=01M98633
; MC68HC705P6A.pdf

; RAM=176
; ROM=0K
; EPROM=4.5K
; EEPROM=0


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area DATA EPROM_P0     0x0020:0x0050
area DATA RAM          0x0050:0x0100
area DATA EPROM_P1     0x0100:0x1300
area BSS  RESERVED     0x1300:0x1EFF
area DATA MASK_OPT     0x1EFF:0x1F01
area DATA BootROM      0x1F01:0x1FF0
area DATA USER_VEC     0x1FF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Reset  
interrupt SWI               0x1FFC      SWI               
interrupt IRQ               0x1FFA      IRQ/IRQ2        
interrupt Timer             0x1FF8      Timer       


; INPUT/ OUTPUT PORTS
PORTA           0x0000    Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001    Port B data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTC           0x0002    Port C data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003    Port D data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD5        5   Port D Data Bits 6
DDRA            0x0004   Port A Data Direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005   Port B Data Direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRC            0x0006   Port C Data Direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007   Port D Data Direction
DDRD.DDRD5       5   Data Direction for Port D Bit 5
UNUSED0008      0x0008   UNUSED
UNUSED0009      0x0009   UNUSED
SCR             0x000A   SIOP Control
SCR.SPE          6   Serial Peripheral Enable
SCR.MSTR         4   Master Mode Select
SSR             0x000B   SIOP Status
SSR.SPIF         7   Serial Port Interface Flag
SSR.DCOL         6   Data Collision
SDR             0x000C   SIOP Data
SDR.SDR7         7
SDR.SDR6         6
SDR.SDR5         5
SDR.SDR4         4
SDR.SDR3         3
SDR.SDR2         2
SDR.SDR1         1
SDR.SDR0         0
RESERV000D      0x000D   RESERVED
UNUSED000E      0x000E   UNUSED
UNUSED000F      0x000F   UNUSED
UNUSED0010      0x0010   UNUSED
UNUSED0011      0x0011   UNUSED
TCR             0x0012   Timer  control
TCR.ICIE         7   Input Capture Interrupt Enable
TCR.OCIE         6   Output Compare Interrupt Enable
TCR.TOIE         5   Timer Overflow Interrupt Enable
TCR.IEDG         1   Input Edge
TCR.OLVL         0   Output Level
TSR             0x0013   Timer  status
TSR.ICF          7   Input Capture Flag
TSR.OCF          6   Output Compare Flag
TSR.TOF          5   Timer Overflow Flag
ICRH            0x0014   Input capture MSB
ICRH.ICRH7       7
ICRH.ICRH6       6
ICRH.ICRH5       5
ICRH.ICRH4       4
ICRH.ICRH3       3
ICRH.ICRH2       2
ICRH.ICRH1       1
ICRH.ICRH0       0
ICRL            0x0015   Input capture  LSB
ICRL.ICRL7       7
ICRL.ICRL6       6
ICRL.ICRL5       5
ICRL.ICRL4       4
ICRL.ICRL3       3
ICRL.ICRL2       2
ICRL.ICRL1       1
ICRL.ICRL0       0
OCRH            0x0016   Output compare MSB
OCRH.OCRH7       7
OCRH.OCRH6       6
OCRH.OCRH5       5
OCRH.OCRH4       4
OCRH.OCRH3       3
OCRH.OCRH2       2
OCRH.OCRH1       1
OCRH.OCRH0       0
OCRL            0x0017   Output compare LSB
OCRL.OCRL7       7
OCRL.OCRL6       6
OCRL.OCRL5       5
OCRL.OCRL4       4
OCRL.OCRL3       3
OCRL.OCRL2       2
OCRL.OCRL1       1
OCRL.OCRL0       0
TRH             0x0018   Timer  MSB
TRH.TMRH7        7
TRH.TMRH6        6
TRH.TMRH5        5
TRH.TMRH4        4
TRH.TMRH3        3
TRH.TMRH2        2
TRH.TMRH1        1
TRH.TMRH0        0
TRL             0x0019   Timer  LSB
TRL.TMRL7        7
TRL.TMRL6        6
TRL.TMRL5        5
TRL.TMRL4        4
TRL.TMRL3        3
TRL.TMRL2        2
TRL.TMRL1        1
TRL.TMRL0        0
ATRH            0x001A   Alternate  Counter MSB
ATRH.ACRH7       7
ATRH.ACRH6       6
ATRH.ACRH5       5
ATRH.ACRH4       4
ATRH.ACRH3       3
ATRH.ACRH2       2
ATRH.ACRH1       1
ATRH.ACRH0       0
ATRL            0x001B   Alternate  Counter LSB
ATRL.ACRL7       7
ATRL.ACRL6       6
ATRL.ACRL5       5
ATRL.ACRL4       4
ATRL.ACRL3       3
ATRL.ACRL2       2
ATRL.ACRL1       1
ATRL.ACRL0       0
EPROG           0x001C   EPROM Programming
EPROG.ELAT       2   EPROM Latch Control
EPROG.EPGM       0   EPROM Program Control
ADC             0x001D   A/D Conversion Data
ADC.AD7          7
ADC.AD6          6
ADC.AD5          5
ADC.AD4          4
ADC.AD3          3
ADC.AD2          2
ADC.AD1          1
ADC.AD0          0
ADSC            0x001E   A/D Status and Control
ADSC.CC          7   Conversion Complete
ADSC.ADRC        6   RC Oscillator Control
ADSC.ADON        5   A/D Subsystem On
ADSC.CH2         2   Channel Select Bits 2
ADSC.CH1         1   Channel Select Bits 1
ADSC.CH0         0   Channel Select Bits 0
RESERV001F      0x001F   RESERVED
MOR1            0x1EFF   Mask Option Register
MOR1.PA7PU       7   Port A Pullups/Interrupt Enable/Disable 7
MOR1.PA6PU       6   Port A Pullups/Interrupt Enable/Disable 6
MOR1.PA5PU       5   Port A Pullups/Interrupt Enable/Disable 5
MOR1.PA4PU       4   Port A Pullups/Interrupt Enable/Disable 4
MOR1.PA3PU       3   Port A Pullups/Interrupt Enable/Disable 3
MOR1.PA2PU       2   Port A Pullups/Interrupt Enable/Disable 2
MOR1.PA1PU       1   Port A Pullups/Interrupt Enable/Disable 1
MOR1.PA0PU       0   Port A Pullups/Interrupt Enable/Disable 0
MOR2            0x1F00   Mask Option Register
MOR2.SECURE      7   Security State
MOR2.SWAIT       5   STOP Instruction Mode
MOR2.SPR1        4   SIOP Clock Rate 1
MOR2.SPR0        3   SIOP Clock Rate 0
MOR2.LSBF        2   SIOP Least Significant Bit First
MOR2.LEVEL       1   IRQ Edge Sensitivity
MOR2.COP         0   COP Watchdog Enable
COP             0x1FF0   Computer Operating Properly
COP.COPR         0
UNUSED1FF1      0x1FF1   UNUSED
UNUSED1FF2      0x1FF2   UNUSED
UNUSED1FF3      0x1FF3   UNUSED
UNUSED1FF4      0x1FF4   UNUSED
UNUSED1FF5      0x1FF5   UNUSED
UNUSED1FF6      0x1FF6   UNUSED
UNUSED1FF7      0x1FF7   UNUSED


.68HC705RC17
; HC705RC17GRS/D  http://
; HC705RC17GRS.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA BOOT_ROM_1	0x0020:0x00B0
area DATA RAM_1		0x00B0:0x0100
area DATA BOOT_ROM_2	0x0100:0x0171
area DATA RAM_2		0x0171:0x0180
area DATA EPROM		0x0180:0x3FB0
area DATA BOOT_ROM_3	0x3FB0:0x3FF0
area DATA FSR_1         0x3FF0:0x3FF2
area DATA USER_VEC	0x3FF2:0x4000


; Interrupt and reset vector assignments
interrupt __RESET 	0x3FFE       Reset 
interrupt SWI 		0x3FFC       Software Interrupt 
interrupt IRQ 		0x3FFA       External Interrupts 
interrupt CMT 		0x3FF8       End-of-Cycle Interrupt 
interrupt CORE_TIMER 	0x3FF6       Real-Time Interrupt / Core Timer Overflow 


; INPUT/ OUTPUT PORTS
PORTA            0x0000     Port A Data Register
PORTA.PA7         7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
PORTB            0x0001     Port B Data Register
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTC            0x0002     Port C Data Register
PORTC.PC7         7   Port C Data Bits 7
PORTC.PC6         6   Port C Data Bits 6
PORTC.PC5         5   Port C Data Bits 5
PORTC.PC4         4   Port C Data Bits 4
PORTC.PC1         1   Port C Data Bits 1
PORTC.PC0         0   Port C Data Bits 0
RESERV0003       0x0003     RESERVED
DDRA             0x0004     Port A Data Direction Register
DDRA.DDRA7        7   Data Direction for Port A Bit 7
DDRA.DDRA6        6   Data Direction for Port A Bit 6
DDRA.DDRA5        5   Data Direction for Port A Bit 5
DDRA.DDRA4        4   Data Direction for Port A Bit 4
DDRA.DDRA3        3   Data Direction for Port A Bit 3
DDRA.DDRA2        2   Data Direction for Port A Bit 2
DDRA.DDRA1        1   Data Direction for Port A Bit 1
DDRA.DDRA0        0   Data Direction for Port A Bit 0
DDRB             0x0005     Port B Data Direction Register
DDRB.DDRB7        7   Data Direction for Port B Bit 7
DDRB.DDRB6        6   Data Direction for Port B Bit 6
DDRB.DDRB5        5   Data Direction for Port B Bit 5
DDRB.DDRB4        4   Data Direction for Port B Bit 4
DDRB.DDRB3        3   Data Direction for Port B Bit 3
DDRB.DDRB2        2   Data Direction for Port B Bit 2
DDRB.DDRB1        1   Data Direction for Port B Bit 1
DDRB.DDRB0        0   Data Direction for Port B Bit 0
DDRC             0x0006     Port C Data Direction Register
DDRC.DDRC7        7   Data Direction for Port C Bit 7
DDRC.DDRC6        6   Data Direction for Port C Bit 6
DDRC.DDRC5        5   Data Direction for Port C Bit 5
DDRC.DDRC4        4   Data Direction for Port C Bit 4
DDRC.DDRC1        1   Data Direction for Port C Bit 1
DDRC.DDRC0        0   Data Direction for Port C Bit 0
PLLCR            0x0007     Phase-Locked Loop Control Register
PLLCR.BCS         6   Bus Clock Select
PLLCR.BWC         4   Bandwidth Control
PLLCR.PLLON       3   PLL On
PLLCR.VCOTST      2   VCO Test
PLLCR.PS1         1   PLL Synthesizer Speed Select 1
PLLCR.PS0         0   PLL Synthesizer Speed Select 0
CTCSR            0x0008     Core Timer Control and Status Register
CTCSR.CTOF        7   Core Timer Overflow
CTCSR.RTIF        6   Real-Time Interrupt Flag
CTCSR.TOFE        5   Timer Overflow Enable
CTCSR.RTIE        4   Real-Time Interrupt Enable
CTCSR.TOFC        3   Timer Overflow Flag Clear
CTCSR.RTFC        2   Real-Time Interrupt Flag Clear
CTCSR.RT1         1   Real-Time Interrupt Rate Select 1
CTCSR.RT0         0   Real-Time Interrupt Rate Select 0
CTCR             0x0009     Core Timer Counter Register
CTCR.D7           7
CTCR.D6           6
CTCR.D5           5
CTCR.D4           4
CTCR.D3           3
CTCR.D2           2
CTCR.D1           1
CTCR.D0           0
RESERV000A       0x000A     RESERVED
RESERV000B       0x000B     RESERVED
RESERV000C       0x000C     RESERVED
RESERV000D       0x000D     RESERVED
RESERV000E       0x000E     RESERVED
RESERV000F       0x000F     RESERVED
CHR1             0x0010     Carrier Generator Data Registers primary high
CHR1.IROLN        7   IRO Latch Control
CHR1.CMTPOL       6
CHR1.PH5          5   Primary Carrier High Time Data Values 5
CHR1.PH4          4   Primary Carrier High Time Data Values 4
CHR1.PH3          3   Primary Carrier High Time Data Values 3
CHR1.PH2          2   Primary Carrier High Time Data Values 2
CHR1.PH1          1   Primary Carrier High Time Data Values 1
CHR1.PH0          0   Primary Carrier High Time Data Values 0
CLR1             0x0011     Carrier Generator Data Registers primary low
CLR1.IROLP        7   IRO Latch Control
CLR1.PL5          5   Primary Carrier Low Time Data Values 5
CLR1.PL4          4   Primary Carrier Low Time Data Values 4
CLR1.PL3          3   Primary Carrier Low Time Data Values 3
CLR1.PL2          2   Primary Carrier Low Time Data Values 2
CLR1.PL1          1   Primary Carrier Low Time Data Values 1
CLR1.PL0          0   Primary Carrier Low Time Data Values 0
CHR2             0x0012     Carrier Generator Data Registers secondary high
CHR2.SH5          5   Secondary Carrier High Time Data Values 5
CHR2.SH4          4   Secondary Carrier High Time Data Values 4
CHR2.SH3          3   Secondary Carrier High Time Data Values 3
CHR2.SH2          2   Secondary Carrier High Time Data Values 2
CHR2.SH1          1   Secondary Carrier High Time Data Values 1
CHR2.SH0          0   Secondary Carrier High Time Data Values 0
CLR2             0x0013     Carrier Generator Data Registers secondary low
CLR2.SL5          5   Secondary Carrier Low Time Data Values 5
CLR2.SL4          4   Secondary Carrier Low Time Data Values 4
CLR2.SL3          3   Secondary Carrier Low Time Data Values 3
CLR2.SL2          2   Secondary Carrier Low Time Data Values 2
CLR2.SL1          1   Secondary Carrier Low Time Data Values 1
CLR2.SL0          0   Secondary Carrier Low Time Data Values 0
MCSR             0x0014     Modulator Control and Status Register
MCSR.EOC          7   End-Of-Cycle Status Flag
MCSR.DIV2         6   Divide-by-two prescaler
MCSR.EIMSK        5   External Interrupt Mask
MCSR.EXSPC        4   Extended Space Enable
MCSR.BASE         3   Extended Space Enable
MCSR.MODE         2   Mode Select
MCSR.IE           1   Interrupt Enable
MCSR.MCGEN        0   Modulator and Carrier Generator Enable
MDR1             0x0015     Modulator Period Data Registers 1
MDR1.MB11         7
MDR1.MB10         6
MDR1.MB9          5
MDR1.MB8          4
MDR1.SB11         3
MDR1.SB10         2
MDR1.SB9          1
MDR1.SB8          0
MDR2             0x0016     Modulator Period Data Registers 2
MDR2.MB7          7
MDR2.MB6          6
MDR2.MB5          5
MDR2.MB4          4
MDR2.MB3          3
MDR2.MB2          2
MDR2.MB1          1
MDR2.MB0          0
MDR3             0x0017     Modulator Period Data Registers 3
MDR3.SB7          7
MDR3.SB6          6
MDR3.SB5          5
MDR3.SB4          4
MDR3.SB3          3
MDR3.SB2          2
MDR3.SB1          1
MDR3.SB0          0
RESERV0018       0x0018     RESERVED
RESERV0019       0x0019     RESERVED
RESERV001A       0x001A     RESERVED
RESERV001B       0x001B     RESERVED
RESERV001C       0x001C     RESERVED
RESERV001D       0x001D     RESERVED
PROG             0x001E     Programming Register
PROG.LATCH        2   EPROM Latch Control
PROG.EPGM         0   EPROM Program Control
RESERV001F       0x001F     RESERVED
MOR1             0x3FF0     Mask Option Register 1
MOR1.SECUR        3   SECURITY Enable
MOR1.IRQ          2   IRQ sensitivity
MOR1.STOP         1   STOP Enable
MOR1.COP          0   COP Enable
MOR2             0x3FF1     Mask Option Register 2
MOR2.PB7PU        7   Port B Pullup 7
MOR2.PB6PU        6   Port B Pullup 6
MOR2.PB5PU        5   Port B Pullup 5
MOR2.PB4PU        4   Port B Pullup 4
MOR2.PB3PU        3   Port B Pullup 3
MOR2.PB2PU        2   Port B Pullup 2
MOR2.PB1PU        1   Port B Pullup 1
MOR2.PB0PU        0   Port B Pullup 0
UNUSED3FF2       0x3FF2     UNUSED
UNUSED3FF3       0x3FF3     UNUSED
UNUSED3FF4       0x3FF4     UNUSED
UNUSED3FF5       0x3FF5     UNUSED


.68HC705SR3
; MC68HC05SR3D/H  http://
; MC68HC05SR3D.pdf


; MEMORY MAP
area DATA FSR         0x0000:0x0010
area DATA RAM         0x0010:0x0090
area BSS  UNUSED      0x0090:0x00C0
area DATA STACK       0x00C0:0x0100
area BSS  UNUSED      0x0100:0x1000
area DATA EPROM       0x1000:0x1F00
area DATA BOOT_ROM    0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt IRQ2              0x1FF8      External Interrupt 2
interrupt TIMER             0x1FF6      Timer Overflow
interrupt KBI               0x1FF4      Keyboard


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
DDRD                  0x0007     Port D Data Direction
DDRD.DDRD7             7   Data Direction for Port D Bit 7
DDRD.DDRD6             6   Data Direction for Port D Bit 6
DDRD.DDRD5             5   Data Direction for Port D Bit 5
DDRD.DDRD4             4   Data Direction for Port D Bit 4
DDRD.DDRD3             3   Data Direction for Port D Bit 3
DDRD.DDRD2             2   Data Direction for Port D Bit 2
DDRD.DDRD1             1   Data Direction for Port D Bit 1
DDRD.DDRD0             0   Data Direction for Port D Bit 0
TDR                   0x0008     Timer Data
TDR.TD7                7
TDR.TD6                6
TDR.TD5                5
TDR.TD4                4
TDR.TD3                3
TDR.TD2                2
TDR.TD1                1
TDR.TD0                0
TCR                   0x0009     Timer Control
TCR.TIF                7   Timer Interrupt Flag
TCR.TIM                6   Timer Interrupt Mask
TCR.TCEX               5   Timer Clock EXternal
TCR.TINE               4   Timer INput Enable
TCR.PRER               3   PREscaler Reset
TCR.PR2                2
TCR.PR1                1
TCR.PR0                0
POPR                  0x000A     Port Option
POPR.PIL               5   PB5:PB7 current drive select
POPR.PDP               4   Port D Pull-up              
POPR.PCP               3   Port C Pull-up              
POPR.PBP               2   PB2:PB7 Pull-up             
POPR.PB1               1   PB1 pull-up                 
POPR.PB0               0   PB0 pull-up                 
KBIM                  0x000B     KBI Mask
KBIM.KBE7              7   PA7 Keyboard Interrupt Enable
KBIM.KBE6              6   PA6 Keyboard Interrupt Enable
KBIM.KBE5              5   PA5 Keyboard Interrupt Enable
KBIM.KBE4              4   PA4 Keyboard Interrupt Enable
KBIM.KBE3              3   PA3 Keyboard Interrupt Enable
KBIM.KBE2              2   PA2 Keyboard Interrupt Enable
KBIM.KBE1              1   PA1 Keyboard Interrupt Enable
KBIM.KBE0              0   PA0 Keyboard Interrupt Enable
MCR                   0x000C     Miscellaneous Control
MCR.KBIE               7   KeyBoard Interrupt Enable
MCR.KBIC               6   KeyBoard Interrupt Clear
MCR.INTO               5   INTerrupt Option
MCR.INTE               4   INTerrupt Enable
MCR.LVRE               3   Low Voltage Reset Enable
MCR.SM                 2   Slow Mode
MCR.IRQ2F              1   IRQ2 Flag clear
MCR.IRQ2E              0   IRQ2 Enable
EPC                   0x000D     EPROM Programming Control (MC68HC705SR3)
EPC.ELAT               1   EPROM Latch Control
EPC.PGM                0   EPROM Program Command
ADSCR                 0x000E     ADC Status and Control
ADSCR.COCO             7   COnversion COmplete
ADSCR.ADRC             6   ADC RC Oscillator Control
ADSCR.ADON             5   ADC On
ADSCR.CH2              2   Channel Select Bits 2
ADSCR.CH1              1   Channel Select Bits 1
ADSCR.CH0              0   Channel Select Bits 0
ADDR                  0x000F     ADC Data
ADDR.AD7               7
ADDR.AD6               6
ADDR.AD5               5
ADDR.AD4               4
ADDR.AD3               3
ADDR.AD2               2
ADDR.AD1               1
ADDR.AD0               0
MOR                   0x0FFF     Mask Option (MC68HC705SR3)
MOR.SMD                5   SLOW Mode at Power-on
MOR.SEC                4   EPROM Security
MOR.TMR2               3   Power-on Reset Delay 2
MOR.TMR1               2   Power-on Reset Delay 1
MOR.TMR0               1   Power-on Reset Delay 0
MOR.RC                 0   RC or Crystal Oscillator Option
RESERV1FF0            0x1FF0     Reserved
RESERV1FF1            0x1FF1     Reserved
RESERV1FF2            0x1FF2     Reserved
RESERV1FF3            0x1FF3     Reserved


.68HC705V12
; MC68HC705V12/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC705V12.pdf
; MC68HC705V12.pdf

; RAM=512
; ROM=0
; EPROM=12032
; EEPROM=256


; MEMORY MAP
area DATA FSR        0x0000:0x0040
area DATA RAM_U1     0x0040:0x0100
area DATA RAM_U2     0x0100:0x01C0
area BSS  UNUSED     0x01C0:0x0240
area DATA EEPROM     0x0240:0x0340
area BSS  UNUSED     0x0340:0x0D00
area DATA EPROM      0x0D00:0x3C00
area CODE ROM_TEST   0x3C00:0x3FF0
area DATA USER_VEC   0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      IRQ
interrupt TIMER_16BIT       0x3FF8      16-BIT TIMER
interrupt BDLC              0x3FF6      BDLC
interrupt SPI               0x3FF4      SPI
interrupt TIMER_8BIT        0x3FF2	8-BIT TIMER
interrupt GAUGE             0x3FF0	Gauge synchronize


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data Register
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data Register
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data Register
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Data Register
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007     UNUSED
CTSCR                 0x0008     Core Timer Status and Control Register
CTSCR.CTOF             7   Core Timer Overflow Bit
CTSCR.RTIF             6   Real Time Interrupt Flag
CTSCR.TOFE             5   Timer Overflow Enable Bit
CTSCR.RTIE             4   Real-Time Interrupt Enable Bit
CTSCR.TOFC             3   Timer Overflow Flag Clear Bit
CTSCR.RTFC             2   Real-Time Interrupt Flag Clear Bit
CTSCR.RT1              1   Real-Time Interrupt Rate Select Bit 1
CTSCR.RT0              0   Real-Time Interrupt Rate Select Bit 0
CTCR                  0x0009     Core Timer Counter Register
CTCR.TMR7              7
CTCR.TMR6              6
CTCR.TMR5              5
CTCR.TMR4              4
CTCR.TMR3              3
CTCR.TMR2              2
CTCR.TMR1              1
CTCR.TMR0              0
SPCR                  0x000A     SPI Control Register
SPCR.SPIE              7   SPIE - Serial Peripheral Interrupt Enable Bit
SPCR.SPE               6   SPE - Serial Peripheral System Enable Bit
SPCR.MSTR              4   MSTR - Master Mode Select Bit
SPCR.CPOL              3   CPOL - Clock Polarity Bit
SPCR.CPHA              2   CPHA - Clock Phase Bit
SPCR.SPR1              1   SPR1 - SPI Clock Rate Select Bits
SPCR.SPR0              0   SPR0 - SPI Clock Rate Select Bits
SPSR                  0x000B     SPI Status Register
SPSR.SPIF              7   SPIF - SPI Transfer Complete Flag
SPSR.WCOL              6   WCOL - Write Collision Bit
SPSR.MODF              4   MODF - Mode Fault Bit
SPDR                  0x000C     SPI Data Register
SPDR.SPD7              7
SPDR.SPD6              6
SPDR.SPD5              5
SPDR.SPD4              4
SPDR.SPD3              3
SPDR.SPD2              2
SPDR.SPD1              1
SPDR.SPD0              0
EPROG                 0x000D     EPROM Programming Register
EPROG.MORON            7   Mask Option Register On Bit
EPROG.ELAT             2   EPROM Latch Control Bit
EPROG.EPGM             0   EPROM Program Control Bit
UNUSED000E            0x000E     UNUSED
UNUSED000F            0x000F     UNUSED
UNUSED0010            0x0010     UNUSED
UNUSED0011            0x0011     UNUSED
TMRCR                 0x0012     16-Bit Timer Control Register
TMRCR.ICIE             7   Input Capture Interrupt Enable Bit
TMRCR.OCIE             6   Output Compare Interrupt Enable Bit
TMRCR.TOIE             5   Timer Overflow Interrupt Enable Bit
TMRCR.TON              2   Timer On Bit
TMRCR.IEDG             1   Input Edge Bit
TMRCR.OLVL             0   Output Level Bit
TMRSR                 0x0013     16-Bit Timer Status Register
TMRSR.ICF              7   Input Capture Flag
TMRSR.OCF              6   Output Compare Flag
TMRSR.TOF              5   Timer Overflow Flag
TCAPH                 0x0014     Input Capture MSB Register
TCAPH.IC15             7
TCAPH.IC14             6
TCAPH.IC13             5
TCAPH.IC12             4
TCAPH.IC11             3
TCAPH.IC10             2
TCAPH.IC9              1
TCAPH.IC8              0
TCAPL                 0x0015     Input Capture LSB Register
TCAPL.IC7              7
TCAPL.IC6              6
TCAPL.IC5              5
TCAPL.IC4              4
TCAPL.IC3              3
TCAPL.IC2              2
TCAPL.IC1              1
TCAPL.IC0              0
TCMPH                 0x0016     Output Compare MSB Register
TCMPH.OC15             7
TCMPH.OC14             6
TCMPH.OC13             5
TCMPH.OC12             4
TCMPH.OC11             3
TCMPH.OC10             2
TCMPH.OC9              1
TCMPH.OC8              0
TCMPL                 0x0017     Output Compare Register
TCMPL.OC7              7
TCMPL.OC6              6
TCMPL.OC5              5
TCMPL.OC4              4
TCMPL.OC3              3
TCMPL.OC2              2
TCMPL.OC1              1
TCMPL.OC0              0
TCNTH                 0x0018     Timer Counter MSB Register
TCNTH.CNT15            7
TCNTH.CNT14            6
TCNTH.CNT13            5
TCNTH.CNT12            4
TCNTH.CNT11            3
TCNTH.CNT10            2
TCNTH.CNT9             1
TCNTH.CNT8             0
TCNTL                 0x0019     Timer Counter LSB Register
TCNTL.CNT7             7
TCNTL.CNT6             6
TCNTL.CNT5             5
TCNTL.CNT4             4
TCNTL.CNT3             3
TCNTL.CNT2             2
TCNTL.CNT1             1
TCNTL.CNT0             0
ALTCNTH               0x001A     Alternate Counter Register
ALTCNTH.AC15           7
ALTCNTH.AC14           6
ALTCNTH.AC13           5
ALTCNTH.AC12           4
ALTCNTH.AC11           3
ALTCNTH.AC10           2
ALTCNTH.AC9            1
ALTCNTH.AC8            0
ALTCNTL               0x001B     Alternate Counter Register
ALTCNTL.AC7            7
ALTCNTL.AC6            6
ALTCNTL.AC5            5
ALTCNTL.AC4            4
ALTCNTL.AC3            3
ALTCNTL.AC2            2
ALTCNTL.AC1            1
ALTCNTL.AC0            0
EEPROG                0x001C     EEPROM Programming Register
EEPROG.CPEN            6   Charge Pump Enable Bit
EEPROG.ER1             4   Erase Select Bits 1
EEPROG.ER0             3   Erase Select Bits 0
EEPROG.EELAT           2   EEPROM Programming Latch Bit
EEPROG.EERC            1   EEPROM RC Oscillator Control Bit
EEPROG.EEPGM           0   EEPROM Programming Power Enable Bit
ADDR                  0x001D     A/D Data Register
ADDR.D7                7
ADDR.D6                6
ADDR.D5                5
ADDR.D4                4
ADDR.D3                3
ADDR.D2                2
ADDR.D1                1
ADDR.D0                0
ADSCR                 0x001E     A_D Status and Control Register
ADSCR.COCO             7   Conversions Complete Bit
ADSCR.ADRC             6   RC Oscillator Control Bit
ADSCR.ADON             5   A/D On Bit
ADSCR.CH4              4   Channel Select Bits 4
ADSCR.CH3              3   Channel Select Bits 3
ADSCR.CH2              2   Channel Select Bits 2
ADSCR.CH1              1   Channel Select Bits 1
ADSCR.CH0              0   Channel Select Bits 0
ISCR                  0x001F     IRQ Status and Control Register
ISCR.IRQE              7   IRQ Interrupt Enable Bit
ISCR.IPCE              5   Port C IRQ Interrupt Enable Bit
ISCR.IRQF              3   IRQ Interrupt Request Bit
ISCR.IPCF              1   Port C IRQ Interrupt Request Bit
ISCR.IRQA              0   IRQ Interrupt Acknowledge Bit
GER                   0x0020     Gauge Enable Register
GER.MJAON              7   Major Gauge A On Bit
GER.MJBON              6   Major Gauge B On Bit
GER.MIAON              5   Minor Gauge A On Bit
GER.MIBON              4   Minor Gauge B On Bit
GER.MICON              3   Minor Gauge C On Bit
GER.MIDON              2   Minor Gauge D On Bit
GER.CMPS               1   Feedback Compensation Select
SSCR                  0x0021     Scan Status and Control Register
SSCR.SYNIE             7   Synchronize Interrupt Enable Bit
SSCR.SYNF              6   Synchronize Flag Bit
SSCR.SYNR              5   Synchronize Flag Reset Bit
SSCR.GCS1              3   Gauge Clock Select Bits 1
SSCR.GCS0              2   Gauge Clock Select Bits 0
SSCR.SCNS              1   Scan Start Bit
SSCR.AUTOS             0   Automatic Mode Select Bit
MAJA1                 0x0022     MAJA1 Magnitude Register
MAJA2                 0x0023     MAJA2 Magnitude Register
MAJB1                 0x0024     MAJB1 Magnitude Register
MAJB2                 0x0025     MAJB2 Magnitude Register
MINA1                 0x0026     MINA1 Magnitude Register
MINA2                 0x0027     MINA2 Magnitude Register
MINB1                 0x0028     MINB1 Magnitude Register
MINB2                 0x0029     MINB2 Magnitude Register
MINC1                 0x002A     MINC1 Magnitude Register
MINC2                 0x002B     MINC2 Magnitude Register
MIND1                 0x002C     MIND1 Magnitude Register
MIND2                 0x002D     MIND2 Magnitude Register
DMAJA                 0x002E     MAJA Current Direction Register
DMAJA.DMJA1            1   Current Direction Bits for Major Gauge A 1
DMAJA.DMJA2            0   Current Direction Bits for Major Gauge A 0
DMAJB                 0x002F     MAJB Current Direction Register
DMAJB.DMJB1            1   Current Direction Bits for Major Gauge B 1
DMAJB.DMJB2            0   Current Direction Bits for Major Gauge B 0
DMINA                 0x0030     MINA Current Direction Register
DMINA.DMIA             0   Current Direction Bit for Minor Gauge A
MINB                  0x0031     MINB Current Direction Register
MINB.DMIB              0   Current Direction Bit for Minor Gauge B
DMINC                 0x0032     MINC Current Direction Register
DMINC.DMIC             0   Current Direction Bit for Minor Gauge C
DMID                  0x0033     MIND Current Direction Register
DMID.DMID              0   Current Direction Bit for Minor Gauge D
Reserv0034            0x0034     RESERVED
MISC                  0x0035     Miscellaneous Register
MISC.OCE               6   Output Compare Enable Bit
PWMAD                 0x0036     PWMA Data Register
PWMAD.POLA             7   POLA - PWMA Polarity Bits
PWMAD.D5               5
PWMAD.D4               4
PWMAD.D3               3
PWMAD.D2               2
PWMAD.D1               1
PWMAD.D0               0
PWMAC                 0x0037     PWMA Control Register
PWMAC.PSA1A            7
PWMAC.PSA0A            6
PWMAC.PSB3A            3
PWMAC.PSB2A            2
PWMAC.PSB1A            1
PWMAC.PSB0A            0
PWMBD                 0x0038     PWMB Data Register
PWMBD.POLB             7   POLB - PWMB Polarity Bit
PWMBD.D5               5
PWMBD.D4               4
PWMBD.D3               3
PWMBD.D2               2
PWMBD.D1               1
PWMBD.D0               0
PWMBC                 0x0039     PWMB Control Register
PWMBC.PSA1B            7
PWMBC.PSA0B            6
PWMBC.PSB3B            3
PWMBC.PSB2B            2
PWMBC.PSB1B            1
PWMBC.PSB0B            0
BCR1                  0x003A     BDLC Control 1 Register
BCR1.IMSG              7   Ignore Message Bit
BCR1.CLKS              6   Clock Bit
BCR1.R1                5   Rate Select Bits 1
BCR1.R0                4   Rate Select Bits 0
BCR1.IE                1   Interrupt Enable Bit
BCR1.WCM               0   Wait Clock Mode Bit
BCR2                  0x003B     BDLC Control 2 Register
BCR2.ALOOP             7   Analog Loopback Mode Bit
BCR2.DLOOP             6   Digital Loopback Mode Bit
BCR2.RX4XE             5   Receive 4X Enable Bit
BCR2.NBFS              4   Normalization Bit Format Select Bit
BCR2.TEOD              3   Transmit End-of-Data Bit
BCR2.TSIFR             2   Transmit In-Frame Response Control Bits
BCR2.TMIFR1            1   Transmit In-Frame Response Control Bits 1
BCR2.TMIFR0            0   Transmit In-Frame Response Control Bits 0
BSVR                  0x003C     BDLC State Vector Register
BSVR.I3                5   Interrupt Source Bits 3
BSVR.I2                4   Interrupt Source Bits 2
BSVR.I1                3   Interrupt Source Bits 1
BSVR.I0                2   Interrupt Source Bits 0
BDR                   0x003D     BDLC Data Register
BDR.BD7                7
BDR.BD6                6
BDR.BD5                5
BDR.BD4                4
BDR.BD3                3
BDR.BD2                2
BDR.BD1                1
BDR.BD0                0
BARD                  0x003E     BDLC Analog and Roundtrip Delay Register
BARD.ATE               7   Analog Transceiver Enable Bit
BARD.RXPOL             6   Receive Pin Polarity Bit
BARD.BO3               3   BARD Offset Bits 3
BARD.BO2               2   BARD Offset Bits 2
BARD.BO1               1   BARD Offset Bits 1
BARD.BO0               0   BARD Offset Bits 0
Reserv003F            0x003F     RESERVED
MOR                   0x3C00     Mask Option Register (MOR)
MOR.LVRE               4   Low-Voltage Reset Enable Bit
MOR.STOPE              2   STOP Instruction Enable Bit
MOR.LEVEL              1   Interrupt Request Pin Sensitivity Bit
MOR.COPE               0   COP Timer Enable Bit


.68HC705V8
; HC705V8GRS/D  http://
; HC705V8GRS.pdf

; RAM=512
; ROM=0
; EPROM=12032
; EEPROM=128


; MEMORY MAP
area DATA FSR        0x0000:0x0040
area DATA RAM_U1     0x0040:0x0100
area DATA RAM_U2     0x0100:0x0240
area DATA EEPROM     0x0240:0x02C0
area BSS  UNUSED     0x02C0:0x0D00
area DATA EPROM      0x0D00:0x3C00
area DATA _MOR_      0x3C00:0x3C01
area CODE ROM_TEST   0x3C01:0x3FF0
area DATA USER_VEC   0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      IRQ
interrupt TIMER_16          0x3FF8      TIMER 16-BIT
interrupt MDLC              0x3FF6
interrupt SPI               0x3FF4
interrupt TIMER_8           0x3FF2	TIMER 8-BIT


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     PORT A DATA
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     PORT B DATA
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     PORT C DATA
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     PORT D DATA
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     PORT A DATA DIRECTION
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     PORT B DATA DIRECTION
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     PORT C DATA DIRECTION
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007     UNUSED
8BTSC                 0x0008     8 BIT TIMER STATUS_CONTROL
8BTSC.CTOF             7   Core Timer Over Flow
8BTSC.RTIF             6   Real Time Interrupt Flag
8BTSC.TOFE             5   Timer Over Flow Enable
8BTSC.RTIE             4   Real Time Interrupt Enable
8BTSC.TOFC             3   Timer Over Flow Flag Clear
8BTSC.RTFC             2   Real Time Interrupt Flag Clear
8BTSC.RT1              1   Real Time Interrupt Rate Select 1
8BTSC.RT0              0   Real Time Interrupt Rate Select 0
8BTC                  0x0009     8 BIT TIMER COUNTER
8BTC.D7                7
8BTC.D6                6
8BTC.D5                5
8BTC.D4                4
8BTC.D3                3
8BTC.D2                2
8BTC.D1                1
8BTC.D0                0
SCR                   0x000A     SPI CONTROL REGISTER
SCR.SPIE               7   Serial Peripheral Interrupt Enable
SCR.SPE                6   Serial Peripheral System Enable
SCR.MSTR               4   Master Mode Select
SCR.CPOL               3   Clock Polarity
SCR.CPHA               2   Clock Phase
SCR.SPR1               1   SPI Clock Rate Selects 1
SCR.SPR0               0   SPI Clock Rate Selects 0
SSR                   0x000B     SPI STATUS REGISTER
SSR.SPIF               7   SPI Transfer Complete Flag
SSR.WCOL               6   Write Collision
SSR.MODF               4   Mode Fault
SDR                   0x000C     SPI DATA REGISTER
SDR.SPD7               7
SDR.SPD6               6
SDR.SPD5               5
SDR.SPD4               4
SDR.SPD3               3
SDR.SPD2               2
SDR.SPD1               1
SDR.SPD0               0
EPROG                 0x000D     EPROM PROGRAM REGISTER
EPROG.MORON            7   Mask Option Register On
EPROG.LATCH            2   EPROM Latch Control
EPROG.EPGM             0   EPROM Program Control
MCR                   0x000E     MDLC CONTROL REGISTER
MCR.RXBM               7   Receive Block Mode
MCR.TXAB               6   Transmit Abort
MCR.R1                 5   Rate Select 1
MCR.R0                 4   Rate Select 0
MCR.IE                 1   Interrupt Enable
MCR.WCM                0   Wait Clock Mode
MSR                   0x000F     MDLC STATUS REGISTER
MSR.TXMS               3   Transmitted Message Successfully
MSR.RXMS               2   Received Message Successfully
MTCR                  0x0010     MDLC TX CONTROL REGISTER
MTCR.TC3               3
MTCR.TC2               2
MTCR.TC1               1
MTCR.TC0               0
MRSR                  0x0011     MDLC RX STATUS REGISTER
MRSR.RC3               3
MRSR.RC2               2
MRSR.RC1               1
MRSR.RC0               0
TCR                   0x0012     TIMER CONTROL REGISTER
TCR.ICIE               7   Input Capture Interrupt Enable
TCR.OCIE               6   Output Compare Interrupt Enable
TCR.TOIE               5   Timer Overflow Interrupt Enable
TCR.TON                2   Timer On
TCR.IEDG               1   Input Edge
TCR.OLVL               0   Output Level
TSR                   0x0013     TIMER STATUS REGISTER
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICH                   0x0014     INPUT CAPTURE HIGH
ICL                   0x0015     INPUT CAPTURE LOW
OCH                   0x0016     OUTPUT COMPARE HIGH
OCL                   0x0017     OUTPUT COMPARE LOW
TCH                   0x0018     TIMER COUNTER HIGH
TCL                   0x0019     TIMER COUNTER LOW
ACH                   0x001A     ALT. COUNTER HIGH
ACL                   0x001B     ALT. COUNTER LOW
EPROG                 0x001C     EEPROM PROGRAMMING
EPROG.CPEN             6   Charge Pump Enable
EPROG.ER1              4   Erase Select Bits 1
EPROG.ER0              3   Erase Select Bits 0
EPROG.LATCH            2
EPROG.EERC             1   EEPROM RC Oscillator Control
EPROG.EEPGM            0   EEPROM Programming Power Enable
ADD                   0x001D     A/D DATA
ADD.D7                 7
ADD.D6                 6
ADD.D5                 5
ADD.D4                 4
ADD.D3                 3
ADD.D2                 2
ADD.D1                 1
ADD.D0                 0
ADSC                  0x001E     A/D STATUS AND CONTROL
ADSC.COCO              7   Conversions Complete
ADSC.ADRC              6   RC Oscillator Control
ADSC.ADON              5   A/D On
ADSC.CH4               4   Channel Select Bits 4
ADSC.CH3               3   Channel Select Bits 3
ADSC.CH2               2   Channel Select Bits 2
ADSC.CH1               1   Channel Select Bits 1
ADSC.CH0               0   Channel Select Bits 0
ICS                   0x001F     IRQ CONTROL AND STATUS
ICS.IRQE               7   IRQ Interrupt Enable
ICS.IRQPAE             6   Port A IRQ Interrupt Enable
ICS.IRQPCE             5   Port C IRQ Interrupt Enable
ICS.IRQF               3   IRQ Interrupt Request
ICS.IRQPAF             2   Port A IRQ Interrupt Request
ICS.IRQPCF             1   Port C IRQ Interrupt Request
ICS.IRQA               0   IRQ Interrupt Acknowledge
MTDR0                 0x0020     MDLC TX DATA REGISTER 0
MTDR0.D7               7
MTDR0.D6               6
MTDR0.D5               5
MTDR0.D4               4
MTDR0.D3               3
MTDR0.D2               2
MTDR0.D1               1
MTDR0.D0               0
MTDR1                 0x0021     MDLC TX DATA REGISTER 1
MTDR1.D7               7
MTDR1.D6               6
MTDR1.D5               5
MTDR1.D4               4
MTDR1.D3               3
MTDR1.D2               2
MTDR1.D1               1
MTDR1.D0               0
MTDR2                 0x0022     MDLC TX DATA REGISTER 2
MTDR2.D7               7
MTDR2.D6               6
MTDR2.D5               5
MTDR2.D4               4
MTDR2.D3               3
MTDR2.D2               2
MTDR2.D1               1
MTDR2.D0               0
MTDR3                 0x0023     MDLC TX DATA REGISTER 3
MTDR3.D7               7
MTDR3.D6               6
MTDR3.D5               5
MTDR3.D4               4
MTDR3.D3               3
MTDR3.D2               2
MTDR3.D1               1
MTDR3.D0               0
MTDR4                 0x0024     MDLC TX DATA REGISTER 4
MTDR4.D7               7
MTDR4.D6               6
MTDR4.D5               5
MTDR4.D4               4
MTDR4.D3               3
MTDR4.D2               2
MTDR4.D1               1
MTDR4.D0               0
MTDR5                 0x0025     MDLC TX DATA REGISTER 5
MTDR5.D7               7
MTDR5.D6               6
MTDR5.D5               5
MTDR5.D4               4
MTDR5.D3               3
MTDR5.D2               2
MTDR5.D1               1
MTDR5.D0               0
MTDR6                 0x0026     MDLC TX DATA REGISTER 6
MTDR6.D7               7
MTDR6.D6               6
MTDR6.D5               5
MTDR6.D4               4
MTDR6.D3               3
MTDR6.D2               2
MTDR6.D1               1
MTDR6.D0               0
MTDR7                 0x0027     MDLC TX DATA REGISTER 7
MTDR7.D7               7
MTDR7.D6               6
MTDR7.D5               5
MTDR7.D4               4
MTDR7.D3               3
MTDR7.D2               2
MTDR7.D1               1
MTDR7.D0               0
MTDR8                 0x0028     MDLC TX DATA REGISTER 8
MTDR8.D7               7
MTDR8.D6               6
MTDR8.D5               5
MTDR8.D4               4
MTDR8.D3               3
MTDR8.D2               2
MTDR8.D1               1
MTDR8.D0               0
MTDR9                 0x0029     MDLC TX DATA REGISTER 9
MTDR9.D7               7
MTDR9.D6               6
MTDR9.D5               5
MTDR9.D4               4
MTDR9.D3               3
MTDR9.D2               2
MTDR9.D1               1
MTDR9.D0               0
MTDR10                0x002A     MDLC TX DATA REGISTER 10
MTDR10.D7              7
MTDR10.D6              6
MTDR10.D5              5
MTDR10.D4              4
MTDR10.D3              3
MTDR10.D2              2
MTDR10.D1              1
MTDR10.D0              0
PORTE                 0x002B     PORT E DATA
PORTE.PE7              7
PORTE.PE6              6
PORTE.PE5              5
PORTE.PE4              4
PORTE.PE3              3
PORTE.PE2              2
PORTE.PE1              1
PORTE.PE0              0
PORTF                 0x002C     PORT F DATA
PORTF.PF3              3   Port F Data Bits 3
PORTF.PF2              2   Port F Data Bits 2
PORTF.PF1              1   Port F Data Bits 1
PORTF.PF0              0   Port F Data Bits 0
DDRF                  0x002E     PORT F DATA DIRECTION
DDRF.DDRF3             3   Data Direction for Port F Bit 3
DDRF.DDRF2             2   Data Direction for Port F Bit 2
DDRF.DDRF1             1   Data Direction for Port F Bit 1
DDRF.DDRF0             0   Data Direction for Port F Bit 0
MISCELL               0x002F     MISCELLANEOUS
MISCELL.IGNS           7   Ignition status bit
MISCELL.OCE            6   Output compare enable
MISCELL.PDC            0   Power Down Control
PWMD                  0x0030     PWM DATA
PWMD.POL               7   PWM Polarity
PWMD.D5                5
PWMD.D4                4
PWMD.D3                3
PWMD.D2                2
PWMD.D1                1
PWMD.D0                0
PWMC                  0x0031     PWM CONTROL
PWMC.PSA1              7   PSA1 - PWM Clock Rate
PWMC.PSA0              6   PSA0 - PWM Clock Rate
PWMC.PSB3              3   PSB3 - PWM Clock Rate
PWMC.PSB2              2   PSB2 - PWM Clock Rate
PWMC.PSB1              1   PSB1 - PWM Clock Rate
PWMC.PSB0              0   PSB0 - PWM Clock Rate
UNUSED0032            0x0032     UNUSED
UNUSED0033            0x0033     UNUSED
MRDR0                 0x0034     MDLC RX DATA REGISTER 0
MRDR0.D7               7
MRDR0.D6               6
MRDR0.D5               5
MRDR0.D4               4
MRDR0.D3               3
MRDR0.D2               2
MRDR0.D1               1
MRDR0.D0               0
MRDR1                 0x0035     MDLC RX DATA REGISTER 1
MRDR1.D7               7
MRDR1.D6               6
MRDR1.D5               5
MRDR1.D4               4
MRDR1.D3               3
MRDR1.D2               2
MRDR1.D1               1
MRDR1.D0               0
MRDR2                 0x0036     MDLC RX DATA REGISTER 2
MRDR2.D7               7
MRDR2.D6               6
MRDR2.D5               5
MRDR2.D4               4
MRDR2.D3               3
MRDR2.D2               2
MRDR2.D1               1
MRDR2.D0               0
MRDR3                 0x0037     MDLC RX DATA REGISTER 3
MRDR3.D7               7
MRDR3.D6               6
MRDR3.D5               5
MRDR3.D4               4
MRDR3.D3               3
MRDR3.D2               2
MRDR3.D1               1
MRDR3.D0               0
MRDR4                 0x0038     MDLC RX DATA REGISTER 4
MRDR4.D7               7
MRDR4.D6               6
MRDR4.D5               5
MRDR4.D4               4
MRDR4.D3               3
MRDR4.D2               2
MRDR4.D1               1
MRDR4.D0               0
MRDR5                 0x0039     MDLC RX DATA REGISTER 5
MRDR5.D7               7
MRDR5.D6               6
MRDR5.D5               5
MRDR5.D4               4
MRDR5.D3               3
MRDR5.D2               2
MRDR5.D1               1
MRDR5.D0               0
MRDR6                 0x003A     MDLC RX DATA REGISTER 6
MRDR6.D7               7
MRDR6.D6               6
MRDR6.D5               5
MRDR6.D4               4
MRDR6.D3               3
MRDR6.D2               2
MRDR6.D1               1
MRDR6.D0               0
MRDR7                 0x003B     MDLC RX DATA REGISTER 7
MRDR7.D7               7
MRDR7.D6               6
MRDR7.D5               5
MRDR7.D4               4
MRDR7.D3               3
MRDR7.D2               2
MRDR7.D1               1
MRDR7.D0               0
MRDR8                 0x003C     MDLC RX DATA REGISTER 8
MRDR8.D7               7
MRDR8.D6               6
MRDR8.D5               5
MRDR8.D4               4
MRDR8.D3               3
MRDR8.D2               2
MRDR8.D1               1
MRDR8.D0               0
MRDR9                 0x003D     MDLC RX DATA REGISTER 9
MRDR9.D7               7
MRDR9.D6               6
MRDR9.D5               5
MRDR9.D4               4
MRDR9.D3               3
MRDR9.D2               2
MRDR9.D1               1
MRDR9.D0               0
MRDR10                0x003E     MDLC RX DATA REGISTER 10
MRDR10.D7              7
MRDR10.D6              6
MRDR10.D5              5
MRDR10.D4              4
MRDR10.D3              3
MRDR10.D2              2
MRDR10.D1              1
MRDR10.D0              0
RESERV003F            0x003F     RESERVED
MOR                   0x3C00     MASK OPTION REGISTER
MOR.REGEN              6   Regulator Enable or Disable
MOR.VDDC               5   V DD Clamp
MOR.MDLCPU             4   Enable the MDLC BUS pin to power up the on board regulator on a rising edge
MOR.LVR                3   Low Voltage Reset Enable or Disable
MOR.STOPEN             2   Enable the entry into STOP mode via the execution of the STOP
MOR.IRQ                1   Interrupt Request Pin Sensitivity
MOR.COPEN              0   COP Timer Enable or Disable
COP                   0x3FF0     COP REGISTER
UNUSED3FF1            0x3FF1     UNUSED


.68HC705X32
; MC68HC05X16/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705X32&nodeId=01M98633
; MC68HC05X16.pdf

; RAM=528
; ROM=0K
; EPROM=32K
; EEPROM=256


; MEMORY MAP
area DATA FSR           0x0000:0x0020
area DATA MCAN          0x0020:0x003E
area BSS  RESERVED      0x003E:0x0050
area DATA RAM_U1        0x0050:0x0100
area DATA EEPROM        0x0100:0x0200
area DATA BootROM_U1    0x0200:0x0250
area DATA RAM_U2        0x0250:0x03B0
area DATA BootROM_U2    0x03B0:0x0400
area CODE EPROM         0x0400:0x7E00
area DATA BootROM_U3    0x7E00:0x7FDE
area DATA _MOR_         0x7FDE:0x7FDF
area BSS  RESERVED      0x7FDF:0x7FE0
area DATA BOOT_VEC      0x7FE0:0x7FF0
area DATA USER_VEC      0x7FF0:0x8000


; Interrupt and reset vector assignments
interrupt __RESET           0x7FFE      Processor reset
interrupt SWI               0x7FFC      Software interrupt
interrupt IRQ               0x7FFA      WOI, External IRQ
interrupt TIMER_I           0x7FF8      Timer input capture
interrupt TIMER_O           0x7FF6      Timer output compare
interrupt TIMER_O           0x7FF4      Timer overflow
interrupt SCI               0x7FF2      Serial communications interface
interrupt MCAN              0x7FF0      MCAN


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2_ECLK         2   Port C Data Bit 2/ External clock option bit
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006    Port C data direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
C_EEPROM              0x0007    EEPROM/ECLK control
C_EEPROM.WOIE          7   Wired-OR interrupt enable bit
C_EEPROM.CAF           6   MCAN asleep flag
C_EEPROM.E6LAT         5   EPROM programming latch enable bit
C_EEPROM.E6PGM         4   EPROM program enable bit
C_EEPROM.ECLK          3   External clock output
C_EEPROM.E1ERA         2   EEPROM erase/programming bit
C_EEPROM.E1LAT         1   EEPROM programming latch enable bit
C_EEPROM.E1PGM         0   EEPROM charge pump enable/disable
ADDATA                0x0008    A/D data
ADSTAT                0x0009    A/D status/control
ADSTAT.COCO            7   Conversion complete flag
ADSTAT.ADRC            6   A/D RC oscillator control
ADSTAT.ADON            5   A/D converter on
ADSTAT.CH3             3   A/D channels 3
ADSTAT.CH2             2   A/D channels 2
ADSTAT.CH1             1   A/D channels 1
ADSTAT.CH0             0   A/D channels 0
PLMA                  0x000A    Pulse length modulation A
PLMB                  0x000B    Pulse length modulation B
Miscell               0x000C    Miscellaneous
Miscell.POR            7   Power-on reset bit
Miscell.INTP           6   External interrupt sensitivity options
Miscell.INTN           5   External interrupt sensitivity options
Miscell.INTE           4   External interrupt enable
Miscell.SFA            3   Slow or fast mode selection for PLMA
Miscell.SFB            2   Slow or fast mode selection for PLMB
Miscell.SM             1   Slow mode
Miscell.WDOG           0   Watchdog enable/disable
BAUD                  0x000D    SCI baud rate
BAUD.SCP1              7   Serial prescaler select bits 1
BAUD.SCP0              6   Serial prescaler select bits 0
BAUD.SCT2              5   SCI rate select bits 2 (transmitter)
BAUD.SCT1              4   SCI rate select bits 1 (transmitter)
BAUD.SCT0              3   SCI rate select bits 0 (transmitter)
BAUD.SCR2              2   SCI rate select bits (receiver) 2
BAUD.SCR1              1   SCI rate select bits (receiver) 1
BAUD.SCR0              0   SCI rate select bits (receiver) 0
SCCR1                 0x000E    SCI control 1
SCCR1.R8               7   Receive data bit 8
SCCR1.T8               6   Transmit data bit 8
SCCR1.M                4   Mode
SCCR1.WAKE             3   Wake-up mode select
SCCR1.CPOL             2   Clock polarity
SCCR1.CPHA             1   Clock phase
SCCR1.LBCL             0   Last bit clock
SCCR2                 0x000F    SCI control 2
SCCR2.TIE              7   Transmit interrupt enable
SCCR2.TCIE             6   Transmit complete interrupt enable
SCCR2.RIE              5   Receiver interrupt enable
SCCR2.ILIE             4   Idle line interrupt enable
SCCR2.TE               3   Transmitter enable
SCCR2.RE               2   Receiver enable
SCCR2.RWU              1   Receiver wake-up
SCCR2.SBK              0   Send break
SCSR                  0x0010    Serial communications status register
SCSR.TDRE              7   Transmit data register empty flag
SCSR.TC                6   Transmit complete flag
SCSR.RDRF              5   Receive data register full flag
SCSR.IDLE              4   Idle line detected flag
SCSR.OR                3   Overrun error flag
SCSR.NF                2   Noise error flag
SCSR.FE                1   Framing error flag
SCDR                  0x0011    SCI data
TCR                   0x0012    Timer control register
TCR.ICIE               7   Input captures interrupt enable
TCR.OCIE               6   Output compares interrupt enable
TCR.TOIE               5   Timer overflow interrupt enable
TCR.FOLV2              4   Force output compare 2
TCR.FOLV1              3   Force output compare 1
TCR.OLV2               2   Output level 2
TCR.IEDG1              1   Input edge 1
TCR.OLVL1              0   Output level 1
TSR                   0x0013    Timer status register
TSR.ICF1               7   Input capture flag 1
TSR.OCF1               6   Output compare flag 1
TSR.TOF                5   Timer overflow status flag
TSR.ICF2               4   Input capture flag 2
TSR.OCF2               3   Output compare flag 2
ICH1                  0x0014    Input capture high 1
ICL1                  0x0015    Input capture low 1
OCH1                  0x0016    Output compare high 1
OCL1                  0x0017    Output compare low 1
TCH                   0x0018    Timer counter high
TCL                   0x0019    Timer counter low
ACH                   0x001A    Alternate counter high
ACL                   0x001B    Alternate counter low
ICH2                  0x001C    Input capture high 2
ICL2                  0x001D    Input capture low 2
OCH2                  0x001E    Output compare high 2
OCL2                  0x001F    Output compare low 2
CANCTRL               0x0020   MCAN control register
CANCTRL.MODE           7   Undefined mode
CANCTRL.SPD            6   Speed mode
CANCTRL.OIE            4   Overrun interrupt enable
CANCTRL.EIE            3   Error interrupt enable
CANCTRL.TIE            2   Transmit interrupt enable
CANCTRL.RIE            1   Receive interrupt enable
CANCTRL.RR             0   Reset request
CANCOM                0x0021   MCAN command register
CANCOM.RX0             7   Receive pin 0 (passive)
CANCOM.RX1             6   Receive pin 1 (passive)
CANCOM.COMPSEL         5   Comparator selector
CANCOM.SLEEP           4   Go to sleep
CANCOM.COS             3   Clear overrun status
CANCOM.RRB             2   Release receive buffer
CANCOM.AT              1   Abort transmission
CANCOM.TR              0   Transmission request
CANSTAT               0x0022   MCAN status register
CANSTAT.BS             7   Bus status
CANSTAT.ES             6   Error status
CANSTAT.TS             5   Transmit status
CANSTAT.RS             4   Receive status
CANSTAT.TCS            3   Transmission complete status
CANSTAT.TBA            2   Transmit buffer access
CANSTAT.DO             1   Data overrun
CANSTAT.RBS            0   Receive buffer status
CANINT                0x0023   MCAN interrupt register
CANINT.WIF             4   Wake-up interrupt flag
CANINT.OIF             3   Overrun interrupt flag
CANINT.EIF             2   Error interrupt flag
CANINT.TIF             1   Transmit interrupt flag
CANINT.RIF             0   Receive interrupt flag
CANACC                0x0024   MCAN acceptance code register
CANACC.AC7             7   Acceptance code bits 7
CANACC.AC6             6   Acceptance code bits 6
CANACC.AC5             5   Acceptance code bits 5
CANACC.AC4             4   Acceptance code bits 4
CANACC.AC3             3   Acceptance code bits 3
CANACC.AC2             2   Acceptance code bits 2
CANACC.AC1             1   Acceptance code bits 1
CANACC.AC0             0   Acceptance code bits 0
CANACM                0x0025   Acceptance mask
CANACM.AM7             7   Acceptance mask bits 7
CANACM.AM6             6   Acceptance mask bits 6
CANACM.AM5             5   Acceptance mask bits 5
CANACM.AM4             4   Acceptance mask bits 4
CANACM.AM3             3   Acceptance mask bits 3
CANACM.AM2             2   Acceptance mask bits 2
CANACM.AM1             1   Acceptance mask bits 1
CANACM.AM0             0   Acceptance mask bits 0
CANBT0                0x0026   MCAN bus timing register 0
CANBT0.SJW1            7   Synchronization jump width bits 1
CANBT0.SJW0            6   Synchronization jump width bits 0
CANBT0.BRP5            5   Baud rate prescaler bits 5
CANBT0.BRP4            4   Baud rate prescaler bits 4
CANBT0.BRP3            3   Baud rate prescaler bits 3
CANBT0.BRP2            2   Baud rate prescaler bits 2
CANBT0.BRP1            1   Baud rate prescaler bits 1
CANBT0.BRP0            0   Baud rate prescaler bits 0
CANBT1                0x0027   MCAN bus timing register 1
CANBT1.SAMP            7   Sampling
CANBT1.TSEG22          6   Time segment bits 22
CANBT1.TSEG21          5   Time segment bits 21
CANBT1.TSEG20          4   Time segment bits 20
CANBT1.TSEG13          3   Time segment bits 13
CANBT1.TSEG12          2   Time segment bits 12
CANBT1.TSEG11          1   Time segment bits 11
CANBT1.TSEG10          0   Time segment bits 10
CANOPC                0x0028   MCAN output control register
CANOPC.OCTP1           7       
CANOPC.OCTN1           6       
CANOPC.OCPOL1          5
CANOPC.OCTP0           4
CANOPC.OCTN0           3
CANOPC.OCPOL0          2
CANOPC.OCM1            1   Output control mode bits 1
CANOPC.OCM0            0   Output control mode bits 0
Reserv0029            0x0029   reserved
CANTBI                0x002A   Transmit buffere identifiner
CANTBI.ID10            7   Identifier bits 10
CANTBI.ID9             6   Identifier bits 9
CANTBI.ID8             5   Identifier bits 8
CANTBI.ID7             4   Identifier bits 7
CANTBI.ID6             3   Identifier bits 6
CANTBI.ID5             2   Identifier bits 5
CANTBI.ID4             1   Identifier bits 4
CANTBI.ID3             0   Identifier bits 3
CANTRTDL              0x002B   RTR-bit data length code
CANTRTDL.ID2           7   Identifier bits 2
CANTRTDL.ID1           6   Identifier bits 1
CANTRTDL.ID0           5   Identifier bits 0
CANTRTDL.RTR           4   Remote transmission request
CANTRTDL.DLC3          3   Data length code bits 3
CANTRTDL.DLC2          2   Data length code bits 2
CANTRTDL.DLC1          1   Data length code bits 1
CANTRTDL.DLC0          0   Data length code bits 0
CANTDS1               0x002C    Transmit data segment 1
CANTDS1.DB7            7   data bit 7
CANTDS1.DB6            6   data bit 6
CANTDS1.DB5            5   data bit 5
CANTDS1.DB4            4   data bit 4
CANTDS1.DB3            3   data bit 3
CANTDS1.DB2            2   data bit 2
CANTDS1.DB1            1   data bit 1
CANTDS1.DB0            0   data bit 0
CANTDS2               0x002D    Transmit data segment 2
CANTDS2.DB7            7   data bit 7
CANTDS2.DB6            6   data bit 6
CANTDS2.DB5            5   data bit 5
CANTDS2.DB4            4   data bit 4
CANTDS2.DB3            3   data bit 3
CANTDS2.DB2            2   data bit 2
CANTDS2.DB1            1   data bit 1
CANTDS2.DB0            0   data bit 0
CANTDS3               0x002E    Transmit data segment 3
CANTDS3.DB7            7   data bit 7
CANTDS3.DB6            6   data bit 6
CANTDS3.DB5            5   data bit 5
CANTDS3.DB4            4   data bit 4
CANTDS3.DB3            3   data bit 3
CANTDS3.DB2            2   data bit 2
CANTDS3.DB1            1   data bit 1
CANTDS3.DB0            0   data bit 0
CANTDS4               0x002F    Transmit data segment 4
CANTDS4.DB7            7   data bit 7
CANTDS4.DB6            6   data bit 6
CANTDS4.DB5            5   data bit 5
CANTDS4.DB4            4   data bit 4
CANTDS4.DB3            3   data bit 3
CANTDS4.DB2            2   data bit 2
CANTDS4.DB1            1   data bit 1
CANTDS4.DB0            0   data bit 0
CANTDS5               0x0030    Transmit data segment 5
CANTDS5.DB7            7   data bit 7
CANTDS5.DB6            6   data bit 6
CANTDS5.DB5            5   data bit 5
CANTDS5.DB4            4   data bit 4
CANTDS5.DB3            3   data bit 3
CANTDS5.DB2            2   data bit 2
CANTDS5.DB1            1   data bit 1
CANTDS5.DB0            0   data bit 0
CANTDS6               0x0031    Transmit data segment 6
CANTDS6.DB7            7   data bit 7
CANTDS6.DB6            6   data bit 6
CANTDS6.DB5            5   data bit 5
CANTDS6.DB4            4   data bit 4
CANTDS6.DB3            3   data bit 3
CANTDS6.DB2            2   data bit 2
CANTDS6.DB1            1   data bit 1
CANTDS6.DB0            0   data bit 0
CANTDS7               0x0032    Transmit data segment 7
CANTDS7.DB7            7   data bit 7
CANTDS7.DB6            6   data bit 6
CANTDS7.DB5            5   data bit 5
CANTDS7.DB4            4   data bit 4
CANTDS7.DB3            3   data bit 3
CANTDS7.DB2            2   data bit 2
CANTDS7.DB1            1   data bit 1
CANTDS7.DB0            0   data bit 0
CANTDS8               0x0033    Transmit data segment 8
CANTDS8.DB7            7   data bit 7
CANTDS8.DB6            6   data bit 6
CANTDS8.DB5            5   data bit 5
CANTDS8.DB4            4   data bit 4
CANTDS8.DB3            3   data bit 3
CANTDS8.DB2            2   data bit 2
CANTDS8.DB1            1   data bit 1
CANTDS8.DB0            0   data bit 0
CANRBI                0x0034    Receive buffer idertifiner
CANRBI.ID10            7   Identifier bit 10
CANRBI.ID9             6   Identifier bit 9 
CANRBI.ID8             5   Identifier bit 8 
CANRBI.ID7             4   Identifier bit 7 
CANRBI.ID6             3   Identifier bit 6 
CANRBI.ID5             2   Identifier bit 5 
CANRBI.ID4             1   Identifier bit 4 
CANRBI.ID3             0   Identifier bit 3 
CANRRTDL              0x0035    RTR-bit , data length code
CANRRTDL.ID2           7   Identifier bit 2
CANRRTDL.ID1           6   Identifier bit 1
CANRRTDL.ID0           5   Identifier bit 0
CANRRTDL.RTR           4   Remote transmission request
CANRRTDL.DLC3          3   Data length code bits 3    
CANRRTDL.DLC2          2   Data length code bits 2    
CANRRTDL.DLC1          1   Data length code bits 1    
CANRRTDL.DLC0          0   Data length code bits 0    
CANRDS1               0x0036    Receive data segment 1
CANRDS1.DB7            7   data bit 7
CANRDS1.DB6            6   data bit 6
CANRDS1.DB5            5   data bit 5
CANRDS1.DB4            4   data bit 4
CANRDS1.DB3            3   data bit 3
CANRDS1.DB2            2   data bit 2
CANRDS1.DB1            1   data bit 1
CANRDS1.DB0            0   data bit 0
CANRDS2               0x0037    Receive data segment 2
CANRDS2.DB7            7   data bit 7
CANRDS2.DB6            6   data bit 6
CANRDS2.DB5            5   data bit 5
CANRDS2.DB4            4   data bit 4
CANRDS2.DB3            3   data bit 3
CANRDS2.DB2            2   data bit 2
CANRDS2.DB1            1   data bit 1
CANRDS2.DB0            0   data bit 0
CANRDS3               0x0038    Receive data segment 3
CANRDS3.DB7            7   data bit 7
CANRDS3.DB6            6   data bit 6
CANRDS3.DB5            5   data bit 5
CANRDS3.DB4            4   data bit 4
CANRDS3.DB3            3   data bit 3
CANRDS3.DB2            2   data bit 2
CANRDS3.DB1            1   data bit 1
CANRDS3.DB0            0   data bit 0
CANRDS4               0x0039    Receive data segment 4
CANRDS4.DB7            7   data bit 7
CANRDS4.DB6            6   data bit 6
CANRDS4.DB5            5   data bit 5
CANRDS4.DB4            4   data bit 4
CANRDS4.DB3            3   data bit 3
CANRDS4.DB2            2   data bit 2
CANRDS4.DB1            1   data bit 1
CANRDS4.DB0            0   data bit 0
CANRDS5               0x003A    Receive data segment 5
CANRDS5.DB7            7   data bit 7
CANRDS5.DB6            6   data bit 6
CANRDS5.DB5            5   data bit 5
CANRDS5.DB4            4   data bit 4
CANRDS5.DB3            3   data bit 3
CANRDS5.DB2            2   data bit 2
CANRDS5.DB1            1   data bit 1
CANRDS5.DB0            0   data bit 0
CANRDS6               0x003B    Receive data segment 6
CANRDS6.DB7            7   data bit 7
CANRDS6.DB6            6   data bit 6
CANRDS6.DB5            5   data bit 5
CANRDS6.DB4            4   data bit 4
CANRDS6.DB3            3   data bit 3
CANRDS6.DB2            2   data bit 2
CANRDS6.DB1            1   data bit 1
CANRDS6.DB0            0   data bit 0
CANRDS7               0x003C    Receive data segment 7
CANRDS7.DB7            7   data bit 7
CANRDS7.DB6            6   data bit 6
CANRDS7.DB5            5   data bit 5
CANRDS7.DB4            4   data bit 4
CANRDS7.DB3            3   data bit 3
CANRDS7.DB2            2   data bit 2
CANRDS7.DB1            1   data bit 1
CANRDS7.DB0            0   data bit 0
CANRDS8               0x003D    Receive data segment 8
CANRDS8.DB7            7   data bit 7
CANRDS8.DB6            6   data bit 6
CANRDS8.DB5            5   data bit 5
CANRDS8.DB4            4   data bit 4
CANRDS8.DB3            3   data bit 3
CANRDS8.DB2            2   data bit 2
CANRDS8.DB1            1   data bit 1
CANRDS8.DB0            0   data bit 0
OPTR                  0x0100    Options register
OPTR.EE1P              1   EEPROM protect bit
OPTR.SEC               0   Secure bit
MOR                   0x7FDE    Mask option register
MOR.WOI                7   Wired-OR interrupt enable
MOR.DIV2               6   DIV2 - Clock divide ratio selection
MOR.DIV8               5   DIV8 - Clock divide ratio selection
MOR.RTIM               4   Reset time
MOR.RWAT               3   Watchdog after reset
MOR.WWAT               2   Watchdog during WAIT mode
MOR.PBPD               1   Port B pull-down
MOR.PCPD               0   Port C pull-down


.68HC705X4
; MC68HC05X4/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705X4&nodeId=01M98633
; MC68HC05X4.pdf

; RAM=176
; ROM=0K
; EPROM=4K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA MCAN        0x0020:0x003E
area BSS  RESERVED    0x003E:0x0050
area DATA RAM         0x0050:0x0100
area BSS  RESERVED    0x0100:0x0F00
area DATA EPROM       0x0F00:0x1F00
area DATA _MOR_       0x1F00:0x1F01
area DATA BootROM     0x1F01:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt CIRQ              0x1FFA      WOI External IRQ
interrupt CTIMER            0x1FF8      Core_timer
interrupt WOI               0x1FF6
interrupt TIMER_16BIT       0x1FF4      16_bit_timer


; INPUT/ OUTPUT PORTS
PADAT               0x0000      Port A data
PADAT.PA7            7   Port A Data Bits 7
PADAT.PA6            6   Port A Data Bits 6
PADAT.PA5            5   Port A Data Bits 5
PADAT.PA4            4   Port A Data Bits 4
PADAT.PA3            3   Port A Data Bits 3
PADAT.PA2            2   Port A Data Bits 2
PADAT.PA1            1   Port A Data Bits 1
PADAT.PA0            0   Port A Data Bits 0
PBDAT               0x0001      Port B data
PBDAT.PB7            7   Port B Data Bits 7
PBDAT.PB6            6   Port B Data Bits 6
PBDAT.PB5            5   Port B Data Bits 5
PBDAT.PB4            4   Port B Data Bits 4
PBDAT.PB3            3   Port B Data Bits 3
PBDAT.PB2            2   Port B Data Bits 2
PBDAT.PB1            1   Port B Data Bits 1
PBDAT.PB0            0   Port B Data Bits 0
RESERV0002          0x0002      RESERVED
PCR                 0x0003      Port configuration
PCR.WOIF             5   Wired-OR interrupt flag
PCR.TIMEN            4   Timer enable
PCR.CAF              3   Indicates when MCAN is asleep
PCR.BPDE             2   Port B pull-down enable
PCR.BWIE             1   Port B WOI enable
PCR.AWPS             0   Port A WOI and pull-down select
PADDDR              0x0004      Port A DDR
PBDDDR              0x0005      Port B DDR
RESERV0006          0x0006      RESERVED
RESERV0007          0x0007      RESERVED
CTCSR               0x0008      Core timer control & status
CTCSR.CTOF           7   Core timer overflow
CTCSR.RTIF           6   Real time interrupt flag
CTCSR.CTOFE          5   Core timer overflow interrupt enable
CTCSR.RTIE           4   Real time interrupt enable
CTCSR.RT1            1   Real time interrupt rate select 1
CTCSR.RT0            0   Real time interrupt rate select 0
CTCR                0x0009      Core timer counter
RESERV000A          0x000A      RESERVED
RESERV000B          0x000B      RESERVED
RESERV000C          0x000C      RESERVED
RESERV000E          0x000E      RESERVED
RESERV000F          0x000F      RESERVED
RESERV0010          0x0010      RESERVED
RESERV0011          0x0011      RESERVED
TCR                 0x0012      Timer control
TCR.ICIE             7   Input capture interrupt enable
TCR.OCIE             6   Output compare interrupt enable
TCR.TOIE             5   Timer overflow interrupt enable
TCR.IEDG             1   Input edge
TCR.OLVL             0   Output level
TSR                 0x0013      Timer status
TSR.ICF              7   Input capture flag
TSR.OCF              6   Output compare flag
TSR.TOF              5   Timer overflow flag
ICH                 0x0014      Input capture high
ICL                 0x0015      Input capture low
OCH                 0x0016      Output compare high
OCL                 0x0017      Output compare low
COUNT_H             0x0018      Timer counter high
COUNT_L             0x0019      Timer counter low
ACH                 0x001A      Alternate counter high
ACL                 0x001B      Alternate counter low
EPROG               0x001C      EPROM programming (MC68HC705X4)
EPROG.ELAT           2   EPROM address and data latch
EPROG.EPGM           0   EPROM programming power control
RESERV001D          0x001D     RESERVED
RESERV001E          0x001E     RESERVED
RESERV001F          0x001F     RESERVED
CANCTRL             0x0020     Control
CANCTRL.MODE         7   Undefined mode
CANCTRL.SPD          6   Speed mode
CANCTRL.OIE          4   Overrun interrupt enable
CANCTRL.EIE          3   Error interrupt enable
CANCTRL.TIE          2   Transmit interrupt enable
CANCTRL.RIE          1   Receive interrupt enable
CANCTRL.RR           0   Reset request
CANCOM              0x0021     Command
CANCOM.RX0           7   Receive pin 0 (passive)
CANCOM.RX1           6   Receive pin 1 (passive)
CANCOM.COMPSEL       5   Comparator selector
CANCOM.SLEEP         4   Go to sleep
CANCOM.COS           3   Clear overrun status
CANCOM.RRB           2   Release receive buffer
CANCOM.AT            1   Abort transmission
CANCOM.TR            0   Transmission request
CANSTAT             0x0022     Status
CANSTAT.BS           7   Bus status
CANSTAT.ES           6   Error status
CANSTAT.TS           5   Transmit status
CANSTAT.RS           4   Receive status
CANSTAT.TCS          3   Transmission complete status
CANSTAT.TBA          2   Transmit buffer access
CANSTAT.DO           1   Data overrun
CANSTAT.RBS          0   Receive buffer status
CANINT              0x0023     Interrupt
CANINT.WIF           4   Wake-up interrupt flag
CANINT.OIF           3   Overrun interrupt flag
CANINT.EIF           2   Error interrupt flag
CANINT.TIF           1   Transmit interrupt flag
CANINT.RIF           0   Receive interrupt flag
CANACC              0x0024     Acceptance code
CANACC.AC7           7   Acceptance code bits 7
CANACC.AC6           6   Acceptance code bits 6
CANACC.AC5           5   Acceptance code bits 5
CANACC.AC4           4   Acceptance code bits 4
CANACC.AC3           3   Acceptance code bits 3
CANACC.AC2           2   Acceptance code bits 2
CANACC.AC1           1   Acceptance code bits 1
CANACC.AC0           0   Acceptance code bits 0
CANACM              0x0025     Acceptance mask
CANACM.AM7           7   Acceptance mask bit 7
CANACM.AM6           6   Acceptance mask bit 6
CANACM.AM5           5   Acceptance mask bit 5
CANACM.AM4           4   Acceptance mask bit 4
CANACM.AM3           3   Acceptance mask bit 3
CANACM.AM2           2   Acceptance mask bit 2
CANACM.AM1           1   Acceptance mask bit 1
CANACM.AM0           0   Acceptance mask bit 0
CANBT0              0x0026     Bus timing 0
CANBT0.SJW1          7   Synchronization jump width bits 1
CANBT0.SJW0          6   Synchronization jump width bits 0
CANBT0.BRP5          5   Baud rate prescaler bits 5
CANBT0.BRP4          4   Baud rate prescaler bits 4
CANBT0.BRP3          3   Baud rate prescaler bits 3
CANBT0.BRP2          2   Baud rate prescaler bits 2
CANBT0.BRP1          1   Baud rate prescaler bits 1
CANBT0.BRP0          0   Baud rate prescaler bits 0
CANBT1              0x0027     Bus timing 1
CANBT1.SAMP          7   Sampling
CANBT1.TSEG22        6   Time segment bits 22
CANBT1.TSEG21        5   Time segment bits 21
CANBT1.TSEG20        4   Time segment bits 20
CANBT1.TSEG13        3   Time segment bits 13
CANBT1.TSEG12        2   Time segment bits 12
CANBT1.TSEG11        1   Time segment bits 11
CANBT1.TSEG10        0   Time segment bits 10
CANOPC              0x0028     Output control
CANOPC.OCTP1         7
CANOPC.OCTN1         6
CANOPC.OCPOL1        5
CANOPC.OCTP0         4
CANOPC.OCTN0         3
CANOPC.OCPOL0        2
CANOPC.OCM1          1   Output control mode bits 1
CANOPC.OCM0          0   Output control mode bits 0
RESERV0029          0x0029     RESERVED
CANTBI              0x002A     Transmit buffere identifiner
CANTBI.ID10          7   Identifier bit 10
CANTBI.ID9           6   Identifier bit 9 
CANTBI.ID8           5   Identifier bit 8 
CANTBI.ID7           4   Identifier bit 7 
CANTBI.ID6           3   Identifier bit 6 
CANTBI.ID5           2   Identifier bit 5 
CANTBI.ID4           1   Identifier bit 4 
CANTBI.ID3           0   Identifier bit 3 
CANTRTDL            0x002B     RTR-bit data length code
CANTRTDL.ID2         7   Identifier bit 2
CANTRTDL.ID1         6   Identifier bit 1
CANTRTDL.ID0         5   Identifier bit 0
CANTRTDL.RTR         4   Remote transmission request
CANTRTDL.DLC3        3   Data length code bits 3
CANTRTDL.DLC2        2   Data length code bits 2
CANTRTDL.DLC1        1   Data length code bits 1
CANTRTDL.DLC0        0   Data length code bits 0
CANTDS1             0x002C      Transmit data segment 1
CANTDS1.DB7          7   data bit 7
CANTDS1.DB6          6   data bit 6
CANTDS1.DB5          5   data bit 5
CANTDS1.DB4          4   data bit 4
CANTDS1.DB3          3   data bit 3
CANTDS1.DB2          2   data bit 2
CANTDS1.DB1          1   data bit 1
CANTDS1.DB0          0   data bit 0
CANTDS2             0x002D      Transmit data segment 2
CANTDS2.DB7          7   data bit 7
CANTDS2.DB6          6   data bit 6
CANTDS2.DB5          5   data bit 5
CANTDS2.DB4          4   data bit 4
CANTDS2.DB3          3   data bit 3
CANTDS2.DB2          2   data bit 2
CANTDS2.DB1          1   data bit 1
CANTDS2.DB0          0   data bit 0
CANTDS3             0x002E      Transmit data segment 3
CANTDS3.DB7          7   data bit 7
CANTDS3.DB6          6   data bit 6
CANTDS3.DB5          5   data bit 5
CANTDS3.DB4          4   data bit 4
CANTDS3.DB3          3   data bit 3
CANTDS3.DB2          2   data bit 2
CANTDS3.DB1          1   data bit 1
CANTDS3.DB0          0   data bit 0
CANTDS4             0x002F      Transmit data segment 4
CANTDS4.DB7          7   data bit 7
CANTDS4.DB6          6   data bit 6
CANTDS4.DB5          5   data bit 5
CANTDS4.DB4          4   data bit 4
CANTDS4.DB3          3   data bit 3
CANTDS4.DB2          2   data bit 2
CANTDS4.DB1          1   data bit 1
CANTDS4.DB0          0   data bit 0
CANTDS5             0x0030      Transmit data segment 5
CANTDS5.DB7          7   data bit 7
CANTDS5.DB6          6   data bit 6
CANTDS5.DB5          5   data bit 5
CANTDS5.DB4          4   data bit 4
CANTDS5.DB3          3   data bit 3
CANTDS5.DB2          2   data bit 2
CANTDS5.DB1          1   data bit 1
CANTDS5.DB0          0   data bit 0
CANTDS6             0x0031      Transmit data segment 6
CANTDS6.DB7          7   data bit 7
CANTDS6.DB6          6   data bit 6
CANTDS6.DB5          5   data bit 5
CANTDS6.DB4          4   data bit 4
CANTDS6.DB3          3   data bit 3
CANTDS6.DB2          2   data bit 2
CANTDS6.DB1          1   data bit 1
CANTDS6.DB0          0   data bit 0
CANTDS7             0x0032      Transmit data segment 7
CANTDS7.DB7          7   data bit 7
CANTDS7.DB6          6   data bit 6
CANTDS7.DB5          5   data bit 5
CANTDS7.DB4          4   data bit 4
CANTDS7.DB3          3   data bit 3
CANTDS7.DB2          2   data bit 2
CANTDS7.DB1          1   data bit 1
CANTDS7.DB0          0   data bit 0
CANTDS8             0x0033      Transmit data segment 8
CANTDS8.DB7          7   data bit 7
CANTDS8.DB6          6   data bit 6
CANTDS8.DB5          5   data bit 5
CANTDS8.DB4          4   data bit 4
CANTDS8.DB3          3   data bit 3
CANTDS8.DB2          2   data bit 2
CANTDS8.DB1          1   data bit 1
CANTDS8.DB0          0   data bit 0
CANRBI              0x0034      Receive buffer idertifiner
CANRBI.ID10          7   Identifier bit 10
CANRBI.ID9           6   Identifier bit 9 
CANRBI.ID8           5   Identifier bit 8 
CANRBI.ID7           4   Identifier bit 7 
CANRBI.ID6           3   Identifier bit 6 
CANRBI.ID5           2   Identifier bit 5 
CANRBI.ID4           1   Identifier bit 4 
CANRBI.ID3           0   Identifier bit 3 
CANRRTDL            0x0035      RTR-bit , data length code
CANRRTDL.ID2         7   Identifier bit 2
CANRRTDL.ID1         6   Identifier bit 1
CANRRTDL.ID0         5   Identifier bit 0
CANRRTDL.RTR         4   Remote transmission request
CANRRTDL.DLC3        3   Data length code bits 3
CANRRTDL.DLC2        2   Data length code bits 2
CANRRTDL.DLC1        1   Data length code bits 1
CANRRTDL.DLC0        0   Data length code bits 0
CANRDS1             0x0036      Receive data segment 1
CANRDS1.DB7          7   data bit 7
CANRDS1.DB6          6   data bit 6
CANRDS1.DB5          5   data bit 5
CANRDS1.DB4          4   data bit 4
CANRDS1.DB3          3   data bit 3
CANRDS1.DB2          2   data bit 2
CANRDS1.DB1          1   data bit 1
CANRDS1.DB0          0   data bit 0
CANRDS2             0x0037      Receive data segment 2
CANRDS2.DB7          7   data bit 7
CANRDS2.DB6          6   data bit 6
CANRDS2.DB5          5   data bit 5
CANRDS2.DB4          4   data bit 4
CANRDS2.DB3          3   data bit 3
CANRDS2.DB2          2   data bit 2
CANRDS2.DB1          1   data bit 1
CANRDS2.DB0          0   data bit 0
CANRDS3             0x0038      Receive data segment 3
CANRDS3.DB7          7   data bit 7
CANRDS3.DB6          6   data bit 6
CANRDS3.DB5          5   data bit 5
CANRDS3.DB4          4   data bit 4
CANRDS3.DB3          3   data bit 3
CANRDS3.DB2          2   data bit 2
CANRDS3.DB1          1   data bit 1
CANRDS3.DB0          0   data bit 0
CANRDS4             0x0039      Receive data segment 4
CANRDS4.DB7          7   data bit 7
CANRDS4.DB6          6   data bit 6
CANRDS4.DB5          5   data bit 5
CANRDS4.DB4          4   data bit 4
CANRDS4.DB3          3   data bit 3
CANRDS4.DB2          2   data bit 2
CANRDS4.DB1          1   data bit 1
CANRDS4.DB0          0   data bit 0
CANRDS5             0x003A      Receive data segment 5
CANRDS5.DB7          7   data bit 7
CANRDS5.DB6          6   data bit 6
CANRDS5.DB5          5   data bit 5
CANRDS5.DB4          4   data bit 4
CANRDS5.DB3          3   data bit 3
CANRDS5.DB2          2   data bit 2
CANRDS5.DB1          1   data bit 1
CANRDS5.DB0          0   data bit 0
CANRDS6             0x003B      Receive data segment 6
CANRDS6.DB7          7   data bit 7
CANRDS6.DB6          6   data bit 6
CANRDS6.DB5          5   data bit 5
CANRDS6.DB4          4   data bit 4
CANRDS6.DB3          3   data bit 3
CANRDS6.DB2          2   data bit 2
CANRDS6.DB1          1   data bit 1
CANRDS6.DB0          0   data bit 0
CANRDS7             0x003C      Receive data segment 7
CANRDS7.DB7          7   data bit 7
CANRDS7.DB6          6   data bit 6
CANRDS7.DB5          5   data bit 5
CANRDS7.DB4          4   data bit 4
CANRDS7.DB3          3   data bit 3
CANRDS7.DB2          2   data bit 2
CANRDS7.DB1          1   data bit 1
CANRDS7.DB0          0   data bit 0
CANRDS8             0x003D      Receive data segment 8
CANRDS8.DB7          7   data bit 7
CANRDS8.DB6          6   data bit 6
CANRDS8.DB5          5   data bit 5
CANRDS8.DB4          4   data bit 4
CANRDS8.DB3          3   data bit 3
CANRDS8.DB2          2   data bit 2
CANRDS8.DB1          1   data bit 1
CANRDS8.DB0          0   data bit 0
RESERV1FF0          0x1FF0      RESERVED
RESERV1FF1          0x1FF1      RESERVED
RESERV1FF2          0x1FF2      RESERVED
RESERV1FF3          0x1FF3      RESERVED


.68HC805PV8
; MC68HC05PV8/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC805PV8&nodeId=01M98633   http://
; MC68HC05PV8.pdf

; RAM=192
; ROM=0K
; EPROM=0
; EEPROM=128


; MEMORY MAP
area DATA FSR      	0x0000:0x0020
area DATA FSR_1    	0x0020:0x0030
area DATA EM     	0x0030:0x0040          EXTERNALLY MAPPED 4-bit I/O If enabled
area DATA RAM      	0x0040:0x0100
area BSS  Unused   	0x0100:0x0180
area DATA EEPROM   	0x0180:0x0200
area BSS  Unused   	0x0200:0x2000
area DATA Mask_Opt 	0x2000:0x2001
area DATA EEPROM_ROM   	0x2001:0x3F00
area DATA Monitor_ROM 	0x3F00:0x3FF0
area DATA USER_VEC 	0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      External Interrupt
interrupt CTIMER            0x3FF8      CORE TIMER
interrupt TIMER             0x3FF6      16-BIT TIMER


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data
PORTB.TCAP1            5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
UNUSED0003            0x0003     UNUSED
DDRA                  0x0004     Port A Data Direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
UNUSED0007            0x0007     UNUSED
CTSCR                 0x0008     Core Timer Status and Control Register
CTSCR.TOF              7   Timer Over Flow
CTSCR.RTIF             6   Real Time Interrupt Flag
CTSCR.TOFE             5   Timer Over Flow Enable
CTSCR.RTIE             4   Real Time Interrupt Enable
CTSCR.RTOF             3   Reset TOF
CTSCR.RTIF             2   Reset RTIF
CTSCR.RT1              1   Real Time Interrupt Rate Select 1
CTSCR.RT0              0   Real Time Interrupt Rate Select 0
CTCR                  0x0009     Core Timer Counter Register
SYSCR                 0x000A     System Control
SYSCR.POR              7
SYSCR.INTP             6   External interrupt sensitivity options
SYSCR.INTN             5   External interrupt sensitivity options
SYSCR.INTE             4   External interrupt enable
SYSCR.WCOP             3
SYSCR.WCP              2
SYSCR.FPIE             1   Fast Peripheral Interface Enable
SYSCR.FPICLK           0   Fast Peripheral Clock
UNUSED000B            0x000B     UNUSED
EEPCR                 0x000C     EEPROM Control Register
EEPCR.EEOSC            4   EEPROM RC Oscillator Control
EEPCR.EER1             3   Erase Select Bits 1
EEPCR.EER0             2   Erase Select Bits 0
EEPCR.EELAT            1   EEPROM Programming Latch
EEPCR.EEPGM            0   EEPROM Programming Power Enable
PEECR                 0x000D     Program EEPROM Control
PEECR.RCON             4   RC Oscillator On
PEECR.BULK             3   Bulk Erase Enable
PEECR.EEPERA           2   Write/Erase Mode Selection
PEECR.EEPLAT           1   Programming Latch Enable
PEECR.EEPPGM           0   Programming enable
ADDR                  0x000E     A_D Data
ADSCR                 0x000F     A_D Status_Control
ADSCR.COCO             7   Conversion Complete
ADSCR.ADRC             6   RC Oscillator On
ADSCR.ADON             5   A/D On
ADSCR.ADTEST           4
ADSCR.CH3              3   Channel Select Bit 3
ADSCR.CH2              2   Channel Select Bit 2
ADSCR.CH1              1   Channel Select Bit 1
ADSCR.CH0              0   Channel Select Bit 0
TIC1H                 0x0010     Timer Input Capture1 High
TIC1L                 0x0011     Timer Input Capture1 Low
TOC1H                 0x0012     Timer Output Compare1 High
TOC1L                 0x0013     Timer Output Compare1 Low
TIC2H                 0x0014     Timer Input Capture2 High
TIC2L                 0x0015     Timer Input Capture2 Low
TOC2H                 0x0016     Timer Output Compare2 High
TOC2L                 0x0017     Timer Output Compare2 Low
TCH                   0x0018     Timer Counter High
TCL                   0x0019     Timer Counter Low
TACH                  0x001A     Timer Alternate Counter High
TACL                  0x001B     Timer Alternate Counter Low
TCR1                  0x001C     Timer Control1
TCR1.ICI1E             7   Input Capture 1 Interrupt Enable
TCR1.ICI2E             6   Input Capture 2 Interrupt Enable
TCR1.OCI1E             5   Output Compare 1 Interrupt Enable
TCR1.TOIE              4   Timer Overflow Interrupt Enable
TCR1.OCI2E             3   Output Compare 2 Interrupt Enable
TCR1.TOFF              0   Shut Off Timer
TCR2                  0x001D     Timer Control2
TCR2.IEDGE1            7   Input Edge
TCR2.IEDGE2            6   Input Edge
TCR2.CLK21             5   Output Compare 2 clocks output latch 1
TCR2.FOLV1             4   Force Output Level 1
TCR2.OLVL1             3   Output Level 1
TCR2.CLK12             2   Output Compare 1 clocks output latch 2
TCR2.FOLV2             1   Force Output Level 2
TCR2.OLVL2             0   Output Level 2
TSR                   0x001E     Timer Status
TSR.IC1F               7   Input Capture 1 Flag
TSR.IC2F               6   Input Capture 2 Flag
TSR.OC1F               5   Output Compare 1 Flag
TSR.TOF                4   Timer Overflow Flag
TSR.OC2F               3   Output Compare 2 Flag
TSR.SI1                2   Sample Input 1
TSR.SI2                1   Sample Input 2
TEST                  0x001F     TEST
PACFG                 0x0020     Port A Configuration
PACFG.VRHEN            7   Enable A/D High Reference Channel
PACFG.PUHEN            6   PA4-7 Pull-Up Resistor Enable Higher Nibble
PACFG.EDGEH            5   PA4-7 Interrupt Edge Higher Nibble
PACFG.PAHIE            4   PA4-7 Interrupt Enable Higher Nibble
PACFG.PULEN            3   PA0-3 Pull-Up Resistor Enable Lower Nibble
PACFG.EDGEL            2   PA0-3 Interrupt Edge Lower Nibble
PACFG.PALIE            1   PA0-3 Interrupt Enable Lower Nibble
PACFG.VRLEN            0   Enable A/D Low Reference Channel
IOCFG                 0x0021     I_O Configuration
IOCFG.TXOR             7   Timer EXOR Enable
IOCFG.OPAMP            6   Enable Operational Amplifier
IOCFG.PB4PW            4   PB4 PWM Enable
IOCFG.PB3OC            3   PB3 Output Compare Enable
IOCFG.PB2IC            2   PB2 Input Capture Enable
IOCFG.PB1OC            1   PB1 Output Compare Enable
IOCFG.PB0IC            0   PB0 Input Capture Enable
PCCFG0                0x0022     Port C Configuration
PCCFG0.ISOM            7   Driver Mode of PC4
PCCFG0.PC6PW           6   PC6 PWM Enable
PCCFG0.PWMS1           5   PWM Select Bits 1
PCCFG0.PWMS0           4   PWM Select Bits 0
PCCFG0.PC3OC           3   PC3 Output Compare Enable
PCCFG0.TS2             2   Timer Channel 1 Select Bits 2
PCCFG0.TS1             1   Timer Channel 1 Select Bits 1
PCCFG0.TS0             0   Timer Channel 1 Select Bits 0
UNUSED0023            0x0023     UNUSED
PAISR                 0x0024     Port A Interrupt Status
PAISR.PAIF7            7
PAISR.PAIF6            6
PAISR.PAIF5            5
PAISR.PAIF4            4
PAISR.PAIF3            3
PAISR.PAIF2            2
PAISR.PAIF1            1
PAISR.PAIF0            0
UNUSED0025            0x0025     UNUSED
PCCFG1                0x0026     Port C Configuration 1
PCCFG1.CSIE            7   Port C Contact Sense Interrupt Enable
PCCFG1.SCIE6           6   Low Side Driver Short Circuit Interrupt Enable
PCCFG1.SCIE5           5   Low Side Driver Short Circuit Interrupt Enable
PCCFG1.PC4CS           4   PC4 Contact Sense Enable
PCCFG1.PC3CS           3   PC3 Contact Sense Enable
PCCFG1.PC2CS           2   PC2 Contact Sense Enable
PCCFG1.PC1CS           1   PC1 Contact Sense Enable
PCCFG1.PC0CS           0   PC0 Contact Sense Enable
PCSTR                 0x0027     Port C Status
PCSTR.CSIF             7   Port C Contact Sense Interrupt Flag
PCSTR.SCIF6            6   Low Side Driver Short Circuit Interrupt Flag
PCSTR.SCIF5            5   Low Side Driver Short Circuit Interrupt Flag
PCSTR.CSD4             4   PC4 Contact Sense Data
PCSTR.CSD3             3   PC3 Contact Sense Data
PCSTR.CSD2             2   PC2 Contact Sense Data
PCSTR.CSD1             1   PC1 Contact Sense Data
PCSTR.CSD0             0   PC0 Contact Sense Data
INTCR                 0x0028     Interrupt Control Register
INTCR.HTIE             2   High Temperature Interrupt Enable
INTCR.HVIE             1   High Voltage Interrupt Enable
INTCR.LVIE             0   Low Voltage Interrupt Enable
INTSR                 0x0029     Interrupt Status Register
INTSR.RCON             7
INTSR.PC4CL            6
INTSR.HTIF             2   High Temperature Interrupt Flag
INTSR.HVIF             1   High Voltage Interrupt Flag
INTSR.LVIF             0   Low Voltage Interrupt Flag
RSR                   0x002A     Reset Status Register
RSR.PINR               7   External Reset Bit
RSR.STOPR              6   Illegal STOP Instruction Reset Bit
RSR.COPR               5   COP (Computer Operating Properly) Reset Bit
RSR.ILINR              4   Illegal Instruction Reset Bit
RSR.CMR                3   Clock Monitor Reset Bit
RSR.HTR                2   High Temperature Reset Bit
RSR.HVR                1   High Voltage Reset Bit
RSR.LVR                0   Low Voltage Reset Bit
UNUSED002B            0x002B     UNUSED
PWMPR                 0x002C     PWM Period
PWMCR                 0x002D     PWM Control
PWMCR.PWMON            7   PWM Module On
PWMCR.POL              6   PWM Polarity
PWMCR.CYCLE            4   PWM Cycle Completed
PWMCR.PRA3             3   PWM Clock Rate Bits 3
PWMCR.PRA2             2   PWM Clock Rate Bits 2
PWMCR.PRA1             1   PWM Clock Rate Bits 1
PWMCR.PRA0             0   PWM Clock Rate Bits 0
PWMDAT                0x002E     PWM Data
MFTEST                0x002F     MFTEST Register
MFTEST.HVTOFF          7   Disable of Port C Inputs
MFTEST.VSCAL           4   Disable of V SUP Scaler Circuit
MFTEST.LSOFF           3   Low Side Drivers Off
MFTEST.VT2             2   Voltage Regulator Trimming Bits 2
MFTEST.VT1             1   Voltage Regulator Trimming Bits 1
MFTEST.VT0             0   Voltage Regulator Trimming Bits 0
COPR                  0x3FF0    COP Watchdog Timer Location Register
COPR.COPR              0
RESERV3FF1            0x3FF1    RESERVED
RESERV3FF2            0x3FF2    RESERVED
RESERV3FF3            0x3FF3    RESERVED
RESERV3FF4            0x3FF4    RESERVED
RESERV3FF5            0x3FF5    RESERVED


.68HCL05C4A
; HC05C4AGRS/D  http://
; HC05C4AGRS.pdf

; RAM=176
; ROM=4144
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area DATA ROM_1        0x0020:0x0050
area DATA RAM          0x0050:0x0100
area DATA ROM_2        0x0100:0x1100
area BSS  UNUSED       0x1100:0x1F00
area DATA ROM_S_CH     0x1F00:0x1FF0
area DATA USER_VEC     0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt TIMER             0x1FF8      Timer Input Capture
interrupt SCI               0x1FF6      Serial Communications Interrupt
interrupt SPI               0x1FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A Data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001     Port B Data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002     Port C Data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003     Port D Data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004     Port A Data Direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005     Port B Data Direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006     Port C Data Direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
UNUSED07        0x0007     UNUSED
UNUSED08        0x0008     UNUSED
UNUSED09        0x0009     UNUSED
SPCR            0x000A     SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable
SPCR.MSTR        4   Master Mode Select
SPCR.CPOL        3   Clock Polarity
SPCR.CPHA        2   Clock Phase
SPCR.SPR1        1   SPI Clock Rate Selects 1
SPCR.SPR0        0   SPI Clock Rate Selects 0
SPSR            0x000B     SPI Status Register
SPSR.SPIF        7   SPI Transfer Complete Flag
SPSR.WCOL        6   Write Collision
SPSR.MODF        4   Mode Fault
SPDR            0x000C     SPI Data Register
SPDR.SPD7        7
SPDR.SPD6        6
SPDR.SPD5        5
SPDR.SPD4        4
SPDR.SPD3        3
SPDR.SPD2        2
SPDR.SPD1        1
SPDR.SPD0        0
BAUD            0x000D     SCI Baud Rate Register
BAUD.SCP1        5   SCI Prescaler Select Bits 1
BAUD.SCP0        3   SCI Prescaler Select Bits 0
BAUD.SCR2        2   SCI Baud Rate Select Bits 2
BAUD.SCR1        1   SCI Baud Rate Select Bits 1
BAUD.SCR0        0   SCI Baud Rate Select Bits 0
SCCR1           0x000E     SCI Control 1
SCCR1.R8         7   Bit 8 (Received)
SCCR1.T8         6   Bit 8 (Transmitted)
SCCR1.M          4   Character Length
SCCR1.WAKE       3   Wakeup Bit
SCCR2           0x000F     SCI Control 2
SCCR2.TIE        7   Transmit Interrupt Enable
SCCR2.TCIE       6   Transmission Complete Interrupt Enable
SCCR2.RIE        5   Receive Interrupt Enable
SCCR2.ILIE       4   Idle Line Interrupt Enable
SCCR2.TE         3   Transmit Enable
SCCR2.RE         2   Receive Enable
SCCR2.RMU        1   Receiver Wakeup Enable
SCCR2.SBK        0   Send Break
SCSR            0x0010     SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty
SCSR.TC          6   Transmission Complete
SCSR.RDRF        5   Receive Data Register Full
SCSR.IDLE        4   Receiver Idle
SCSR.OR          3   Receiver Overrun
SCSR.NF          2   Receiver Noise Flag
SCSR.FE          1   Receiver Framing Error
SCDAT           0x0011     SCI Data Register
SCDAT.SCD7       7   Serial Data Bit 7
SCDAT.SCD6       6   Serial Data Bit 6
SCDAT.SCD5       5   Serial Data Bit 5
SCDAT.SCD4       4   Serial Data Bit 4
SCDAT.SCD3       3   Serial Data Bit 3
SCDAT.SCD2       2   Serial Data Bit 2
SCDAT.SCD1       1   Serial Data Bit 1
SCDAT.SCD0       0   Serial Data Bit 0
TCR             0x0012     Timer Control Register
TCR.ICIE         7   Input Capture Interrupt Enable
TCR.OCIE         6   Output Compare Interrupt Enable
TCR.TOIE         5   Timer Overflow Interrupt Enable
TCR.IEDGE        1   Input Edge
TCR.OLVL         0   Output Level
TSR             0x0013     Timer Status Register
TSR.ICF          7   Input Capture Flag
TSR.OCF          6   Output Compare Flag
TSR.TOF          5   Timer Overflow Flag
ICRH            0x0014     Input Capture Register high
ICRL            0x0015     Input Capture Register low
OCRH            0x0016     Output Compare Register high
OCRL            0x0017     Output Compare Register low
TCNTH           0x0018     Timer Counter Register high
TCNTL           0x0019     Timer Counter Register low
ALTCNTH         0x001A     Alternate Counter Register high
ALTCNTL         0x001B     Alternate Counter Register low
UNUSED1C        0x001C     UNUSED
UNUSED1D        0x001D     UNUSED
UNUSED1E        0x001E     UNUSED
RESERV001F      0x001F     RESERVED
COPR            0x1FF0     COP Reset
COPR.COPC        0
RESERV1FF1      0x1FF1    RESERVED
RESERV1FF2      0x1FF2    RESERVED
RESERV1FF3      0x1FF3    RESERVED


.68HCL05C9A
; HC05C9AGRS/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05C9A&nodeId=01M98633 
; HC05C9AGRS.pdf

; RAM=0
; ROM=0
; EPROM=4608
; EEPROM=0


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area DATA ROM0_RAM0    0x0020:0x0050
area DATA RAM          0x0050:0x0100
area DATA ROM1_RAM1    0x0100:0x0180
area DATA ROM          0x0180:0x3F00
area DATA ROM_S_CH     0x3F00:0x3F00
area DATA USER_VEC     0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Reset  
interrupt SWI               0x3FFC      Software Interrupt               
interrupt IRQ               0x3FFA      IRQ/IRQ2        
interrupt Timer             0x3FF8      Timer Interrupt
interrupt SCI               0x3FF6      Serial Communications Interrupt
interrupt SPI               0x3FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001     Port B data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002    Port C data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003    Port D data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004   Port A Data Direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005   Port B Data Direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006   Port C Data Direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007   Port D Data Direction
DDRD.DDRD7       7   Data Direction for Port D Bit 7
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
RESERV0008      0x0008   RESERVED
RESERV0009      0x0009   RESERVED
SPCR            0x000A   SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable
SPCR.DWOM        5   Port D Wire-OR Mode Option
SPCR.MSTR        4   Master Mode Select
SPCR.CPOL        3   Clock Polarity
SPCR.CPHA        2   Clock Phase
SPCR.SPR1        1   SPI Clock Rate Selects 1
SPCR.SPR0        0   SPI Clock Rate Selects 0
SPSR            0x000B   SPI Status Register
SPSR.SPIF        7   SPI Transfer Complete Flag
SPSR.WCOL        6   Write Collision
SPSR.MODF        4   Mode Fault
SPDR            0x000C   SPI Data Register
SPDR.SPD7        7
SPDR.SPD6        6
SPDR.SPD5        5
SPDR.SPD4        4
SPDR.SPD3        3
SPDR.SPD2        2
SPDR.SPD1        1
SPDR.SPD0        0
BAUD            0x000D   SCI Baud Rate Register
BAUD.SCP1        5   SCI Prescaler Select Bits 1
BAUD.SCP0        4   SCI Prescaler Select Bits 0
BAUD.SCR2        2   SCR0-SCI Baud Rate Select Bits 2
BAUD.SCR1        1   SCR0-SCI Baud Rate Select Bits 1
BAUD.SCR0        0   SCR0-SCI Baud Rate Select Bits 0
SCCR1           0x000E   SCI Control Register 1
SCCR1.R8         7   Bit 8 (Received)
SCCR1.T8         6   Bit 8 (Transmitted)
SCCR1.M          4   Character Length
SCCR1.WAKE       3   Wakeup Method
SCCR2           0x000F   SCI Control Register 2
SCCR2.TIE        7   Transmit Interrupt Enable
SCCR2.TCIE       6   Transmission Complete Interrupt Enable
SCCR2.RIE        5   Receiver Interrupt Enable
SCCR2.ILIE       4   Idle Line Interrupt Enable
SCCR2.TE         3   Transmitter Enable
SCCR2.RE         2   Receiver Enable
SCCR2.RWU        1   Receiver Wakeup Enable
SCCR2.SBK        0   Send Break
SCSR            0x0010   SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty
SCSR.TC          6   Transmission Complete
SCSR.RDRF        5   Receive Data Register Full
SCSR.IDLE        4   Receiver Idle
SCSR.OR          3   Receiver Overrun
SCSR.NF          2   Receiver Noise Flag
SCSR.FE          1   Receiver Framing Error
SCDR            0x0011   SCI Data Register
SCDR.SCD7        7   Serial Data Bit 7
SCDR.SCD6        6   Serial Data Bit 6
SCDR.SCD5        5   Serial Data Bit 5
SCDR.SCD4        4   Serial Data Bit 4
SCDR.SCD3        3   Serial Data Bit 3
SCDR.SCD2        2   Serial Data Bit 2
SCDR.SCD1        1   Serial Data Bit 1
SCDR.SCD0        0   Serial Data Bit 0
TCR             0x0012   Timer  Control Register
TCR.ICIE         7   Input Capture Interrupt Enable
TCR.OCIE         6   Output Compare Interrupt Enable
TCR.TOIE         5   Timer Overflow Interrupt Enable
TCR.IEDG         1   Input Edge
TCR.OLVL         0   Output Level
TSR             0x0013   Timer  Status Register
TSR.ICF          7   Input Capture Flag
TSR.OCF          6   Output Compare Flag
TSR.TOF          5   Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TRH             0x0018   Timer Counter Register High
TRL             0x0019   Timer Counter Register Low
ATRH            0x001A   Alternate  Counter Register High
ATRL            0x001B   Alternate  Counter Register Low
UNUSED001C      0x001C   UNUSED
COPRST          0x001D   COP Reset Register
COPCR           0x001E   COP Control Register
COPCR.COPF       4   Computer Operating Properly Flag
COPCR.CME        3   Clock Monitor Enable
COPCR.COPE       2   COP Enable
COPCR.CM1        1   COP Mode Bit 1
COPCR.CM0        0   COP Mode Bit 0
RESERV001F      0x001F   RESERVED
RESERV03F0      0x03F0   RESERVED
RESERV03F1      0x03F1   RESERVED
RESERV03F2      0x03F2   RESERVED
RESERV03F3      0x03F3   RESERVED


.68HSC705C8A
; MC68HC705C8A/D   http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705C8A&nodeId=01M98633
; MC68HC705C8A.pdf

; RAM=304
; ROM=0K
; EPROM=8K
; EEPROM=0


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA RAM_PROM	0x0020:0x0050
area DATA RAM		0x0050:0x0100
area DATA PROM_RAM	0x0100:0x0160
area DATA PROM		0x0160:0x1F00
area DATA BOOT_ROM_1	0x1F00:0x1FDF
area DATA OPTION	0x1FDF:0x1FE0
area DATA BOOT_ROM_2	0x1FE0:0x1FF0
area DATA FSR_1		0x1FF0:0x1FF2
area DATA USER_VEC	0x1FF2:0x2000


; Interrupt and reset vector assignments
interrupt __RESET 	0x1FFE       Reset 
interrupt SWI 		0x1FFC       Software interrupt
interrupt IRQ 		0x1FFA       External interrupt
interrupt TIMER 	0x1FF8       Timer interrupts
interrupt SCI 		0x1FF6       SCI interrupts
interrupt SPI 		0x1FF4       SPI interrupts


; INPUT/ OUTPUT PORTS
PORTA		0x0000		Port A Data Register
PORTA.PA7         7  Port A Data Bits 7
PORTA.PA6         6  Port A Data Bits 6
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB		0x0001		Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
PORTC		0x0002		Port C Data Register
PORTC.PC7         7  Port C Data Bits 7
PORTC.PC6         6  Port C Data Bits 6
PORTC.PC5         5  Port C Data Bits 5
PORTC.PC4         4  Port C Data Bits 4
PORTC.PC3         3  Port C Data Bits 3
PORTC.PC2         2  Port C Data Bits 2
PORTC.PC1         1  Port C Data Bits 1
PORTC.PC0         0  Port C Data Bits 0
PORTD		0x0003		Port D Fixed Input Register
PORTD.PD7         7
PORTD.SS          5
PORTD.SCK         4
PORTD.MOSI        3
PORTD.MISO        2
PORTD.TDO         1
PORTD.RDI         0
DDRA		0x0004 		Port A Data Direction Register
DDRA.DDRA7        7  Data Direction for Port A Bit 7
DDRA.DDRA6        6  Data Direction for Port A Bit 6
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB		0x0005 		Port B Data Direction Register
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
DDRC		0x0006		Port C Data Direction
DDRC.DDRC7        7  Data Direction for Port C Bit 7
DDRC.DDRC6        6  Data Direction for Port C Bit 6
DDRC.DDRC5        5  Data Direction for Port C Bit 5
DDRC.DDRC4        4  Data Direction for Port C Bit 4
DDRC.DDRC3        3  Data Direction for Port C Bit 3
DDRC.DDRC2        2  Data Direction for Port C Bit 2
DDRC.DDRC1        1  Data Direction for Port C Bit 1
DDRC.DDRC0        0  Data Direction for Port C Bit 0
RESERV0007      0x0007          RESERVED
RESERV0008      0x0008          RESERVED
RESERV0009      0x0009          RESERVED
SPCR		0x000A		SPI Control Register
SPCR.SPIE         7  SPI Interrupt Enable Bit
SPCR.SPE          6  SPI Enable Bit
SPCR.MSTR         4  Master Bit
SPCR.CPOL         3  Clock Polarity Bit
SPCR.CPHA         2  Clock Phase Bit
SPCR.SPR1         1  SPI Clock Rate Bits 1
SPCR.SPR0         0  SPI Clock Rate Bits 0
SPSR		0x000B		SPI Status Register
SPSR.SPIF         7  SPI Flag
SPSR.WCOL         6  Write Collision Bit
SPSR.MODF         4  Mode Fault Bit
SPDR		0x000C		SPI Data Register
Baud		0x000D		Baud Rate Register
Baud.SCP1         5  SCI Prescaler Select Bit 1
Baud.SCP0         4  SCI Prescaler Select Bit 0
Baud.SCR2         2  SCI Baud Rate Select Bit 2
Baud.SCR1         1  SCI Baud Rate Select Bit 1
Baud.SCR0         0  SCI Baud Rate Select Bit 0
SCCR1		0x000E		SCI Control Register 1
SCCR1.R8          7  Bit 8 (Received)
SCCR1.T8          6  Bit 8 (Transmitted)
SCCR1.M           4  Character Length Bit
SCCR1.WAKE        3  Wakeup Bit
SCCR2		0x000F		SCI Control Register 2
SCCR2.TIE         7  Transmit Interrupt Enable Bit
SCCR2.TCIE        6  Transmission Complete Interrupt Enable Bit
SCCR2.RIE         5  Receive Interrupt Enable Bit
SCCR2.ILIE        4  Idle Line Interrupt Enable Bit
SCCR2.TE          3  Transmit Enable Bit
SCCR2.RE          2  Receive Enable Bit
SCCR2.RWU         1  Receiver Wakeup Enable Bit
SCCR2.SBK         0  Send Break Bit
SCSR		0x0010		SCI Status Register
SCSR.TDRE         7  Transmit Data Register Empty Bit
SCSR.TC           6  Transmission Complete Bit
SCSR.RDRF         5  Receive Data Register Full Bit
SCSR.IDLE         4  Receiver Idle Bit
SCSR.OR           3  Receiver Overrun Bit
SCSR.NF           2  Receiver Noise Flag Bit
SCSR.FE           1  Receiver Framing Error Bit
SCDR		0x0011		SCI Data Register
TCR		0x0012		Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable Bit
TCR.IEDG          1  Input Edge Bit
TCR.OLVL          0  Output Level Bit
TSR		0x0013		Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Flag
TSR.TOF           5  Timer Overflow Flag
ICRH		0x0014 		Input Capture Register High
ICRL		0x0015 		Input Capture Register Low
OCRH		0x0016 		Output Compare Register  High
OCRL		0x0017 		Output Compare Register Low
TRH		0x0018		Timer Register High
TRL		0x0019		Timer Register Low
ATRH		0x001A 		Alternate Timer Register High
ATRL		0x001B 		Alternate Timer Register Low
PROG		0x001C 		EPROM Programming Register
PROG.LAT          2  Latch Enable Bit
PROG.PGM          0  Program Bit
COPRST		0x001D 		Programmable COP Reset Register
COPCR		0x001E 		Programmable COP Control Register
COPCR.COPF        4  COP Flag
COPCR.CME         3  Clock Monitor Enable Bit
COPCR.PCOPE       2  Programmable COP Enable Bit
COPCR.CM1         1  COP Mode Bits 1
COPCR.CM0         0  COP Mode Bits 0
RESERV001F      0x001F          RESERVED
Option		0x1FDF		Option Register
Option.RAM0       7  Random-Access Memory Control Bit 0
Option.RAM1       6  Random-Access Memory Control Bit 1
Option.SEC        3  Security Bit
Option.IRQ        1  Interrupt Request Pin Sensitivity Bit
MOR1		0x1FF0		Mask Option Register 1
MOR1.PBPU7        7  Port B Pullup Enable Bit 7
MOR1.PBPU6        6  Port B Pullup Enable Bit 6
MOR1.PBPU5        5  Port B Pullup Enable Bit 5
MOR1.PBPU4        4  Port B Pullup Enable Bit 4
MOR1.PBPU3        3  Port B Pullup Enable Bit 3
MOR1.PBPU2        2  Port B Pullup Enable Bit 2
MOR1.PBPU1        1  Port B Pullup Enable Bit 1
MOR1.PBPU0_COPC   0  Port B Pullup Enable Bit 0
MOR2		0x1FF1		Mask Option Register 2
MOR2.NCOPE        0  Non-Programmable COP Watchdog Enable Bit
RESERV1FF2      0x1FF2          RESERVED
RESERV1FF3      0x1FF3          RESERVED


.68HLC705KJ1
; MC68HC705KJ1.pdf

; RAM=64
; ROM=0
; EPROM=1232
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x00C0
area DATA RAM         0x00C0:0x0100
area BSS  UNUSED      0x0100:0x0300
area DATA EPROM       0x0300:0x07D0
area BSS  UNUSED      0x07D0:0x07EE
area DATA ROM_TEST    0x07EE:0x07F0
area DATA USER_VEC    0x07F0:0x0800


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Processor reset
interrupt SWI               0x07FC      Software interrupt
interrupt IRQ               0x07FA      External Interrupt
interrupt TIMER             0x07F8      Timer Interupt


; INPUT/ OUTPUT PORTS
PORTA           0x0000    Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001    Port B data
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
UNUSED0002      0x0002    UNUSED
UNUSED0003      0x0003    UNUSED
DDRA            0x0004    Port A data direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005    Port B data direction
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
UNUSED0006      0x0006    UNUSED
UNUSED0007      0x0007    UNUSED
TSCR            0x0008  Timer Status and Control
TSCR.TOF         7   Timer Overflow Flag
TSCR.RTIF        6   Real-Time Interrupt Flag
TSCR.TOIE        5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE        4   Real-Time Interrupt Enable Bit
TSCR.TOFR        3   Timer Overflow Flag Reset Bit
TSCR.RTIFR       2   Real-Time Interrupt Flag Reset Bit
TSCR.RT1         1   Real-Time Interrupt Select Bits 1
TSCR.RT0         0   Real-Time Interrupt Select Bits 0
TCR             0x0009  Timer Counter
TCR.TCR7         7
TCR.TCR6         6
TCR.TCR5         5
TCR.TCR4         4
TCR.TCR3         3
TCR.TCR2         2
TCR.TCR1         1
TCR.TCR0         0
ISCR            0x000A  IRQ Status and Control
ISCR.IRQE        7   External Interrupt Request Enable Bit
ISCR.IRQF        3   External Interrupt Request Flag
ISCR.IRQR        1   Interrupt Request Reset Bit
UNUSED000B      0x000B    UNUSED
UNUSED000C      0x000C    UNUSED
UNUSED000D      0x000D    UNUSED
UNUSED000E      0x000E    UNUSED
UNUSED000F      0x000F    UNUSED
PDRA            0x0010    Pulldown Register Port A
PDRA.PDRA7       7   Port A Pulldown Inhibit Bit 7
PDRA.PDRA6       6   Port A Pulldown Inhibit Bit 6
PDRA.PDRA5       5   Port A Pulldown Inhibit Bit 5
PDRA.PDRA4       4   Port A Pulldown Inhibit Bit 4
PDRA.PDRA3       3   Port A Pulldown Inhibit Bit 3
PDRA.PDRA2       2   Port A Pulldown Inhibit Bit 2
PDRA.PDRA1       1   Port A Pulldown Inhibit Bit 1
PDRA.PDRA0       0   Port A Pulldown Inhibit Bit 0
PDRB            0x0011     Pulldown Register Port B
PDRB.PDIB3       3   Port B Pulldown Inhibit Bit 3
PDRB.PDIB2       2   Port B Pulldown Inhibit Bit 2
UNUSED0012      0x0012    UNUSED
UNUSED0013      0x0013    UNUSED
UNUSED0014      0x0014    UNUSED
UNUSED0015      0x0015    UNUSED
UNUSED0016      0x0016    UNUSED
UNUSED0017      0x0017    UNUSED
EPROG           0x0018    EPROM Programming
EPROG.ELAT       2   EPROM Bus Latch Bit
EPROG.MPGM       1   MOR Programming Bit
EPROG.EPGM       0   EPROM Programming Bit
UNUSED0019      0x0019    UNUSED
UNUSED001A      0x001A    UNUSED
UNUSED001B      0x001B    UNUSED
UNUSED001C      0x001C    UNUSED
UNUSED001D      0x001D    UNUSED
UNUSED001E      0x001E    UNUSED
RESERV001F      0x001F   RESERVED
COPR            0x07F0   COP Register
COPR.COPC        0   COP Clear Bit
MOR             0x07F1   Mask Options
MOR.SOSCD        7   Short Oscillator Delay Bit
MOR.EPMSEC       6   EPROM Security Bit
MOR.OSCRES       5   Oscillator Internal Resistor Bit
MOR.SWAIT        4   Stop-to-Wait Conversion Bit
MOR.PDI          3   Software Pulldown Inhibit Bit
MOR.PIRQ         2   Port A External Interrupt Bit
MOR.LEVEL        1   External Interrupt Sensitivity Bit
MOR.COPEN        0   COP Enable Bit
RESERV07F2      0x07F2            RESERVED
RESERV07F3      0x07F3            RESERVED
RESERV07F4      0x07F4            RESERVED
RESERV07F5      0x07F5            RESERVED
RESERV07F6      0x07F6            RESERVED
RESERV07F7      0x07F7            RESERVED


.68HRC705J1A
; MC68HC705J1A/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705J1A&nodeId=01M98633
; MC68HC705J1A.pdf

; RAM=64
; ROM=0
; EPROM=1232
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x00C0
area DATA RAM         0x00C0:0x0100
area BSS  UNUSED      0x0100:0x0300
area CODE EPROM       0x0300:0x07D0
area BSS  UNUSED      0x07D0:0x07EE
area DATA TES_TROM    0x07EE:0x07F0
area DATA USER_VEC    0x07F0:0x0800


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Processor reset
interrupt SWI               0x07FC      Software interrupt
interrupt EI                0x07FA      External Interrupt
interrupt TIMER_In          0x07F8      Timer Interupt


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001    Port B data
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
UNUSED0002     0x0002    UNUSED
UNUSED0003     0x0003    UNUSED
DDRA           0x0004    Port A data direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005    Port B data direction
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
UNUSED0006     0x0006    UNUSED
UNUSED0007     0x0007    UNUSED
TSCR           0x0008  Timer Status and Control
TSCR.TOF        7   Timer Overflow Flag
TSCR.RTIF       6   Real-Time Interrupt Flag
TSCR.TOIE       5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE       4   Real-Time Interrupt Enable Bit
TSCR.TOFR       3   Timer Overflow Flag Reset Bit
TSCR.RTIFR      2   Real-Time Interrupt Flag Reset Bit
TSCR.RT1        1   Real-Time Interrupt Select Bits 1
TSCR.RT0        0   Real-Time Interrupt Select Bits 0
TCR            0x0009  Timer Counter
TCR.TMR7        7
TCR.TMR6        6
TCR.TMR5        5
TCR.TMR4        4
TCR.TMR3        3
TCR.TMR2        2
TCR.TMR1        1
TCR.TMR0        0
ISCR           0x000A  IRQ Status and Control
ISCR.IRQE       7   External Interrupt Request Enable Bit
ISCR.IRQF       3   External Interrupt Request Flag
ISCR.IRQR       1   Interrupt Request Reset Bit
UNUSED000B     0x000B    UNUSED
UNUSED000C     0x000C    UNUSED
UNUSED000D     0x000D    UNUSED
UNUSED000E     0x000E    UNUSED
UNUSED000F     0x000F    UNUSED
PDRA           0x0010    Pulldown Register Port A
PDRA.PDIA7      7   Pulldown Inhibit A Bits 7
PDRA.PDIA6      6   Pulldown Inhibit A Bits 6
PDRA.PDIA5      5   Pulldown Inhibit A Bits 5
PDRA.PDIA4      4   Pulldown Inhibit A Bits 4
PDRA.PDIA3      3   Pulldown Inhibit A Bits 3
PDRA.PDIA2      2   Pulldown Inhibit A Bits 2
PDRA.PDIA1      1   Pulldown Inhibit A Bits 1
PDRA.PDIA0      0   Pulldown Inhibit A Bits 0
PDRB           0x0011     Pulldown Register Port B
PDRB.PDIB5      5   Pulldown Inhibit B Bits 5
PDRB.PDIB4      4   Pulldown Inhibit B Bits 4
PDRB.PDIB3      3   Pulldown Inhibit B Bits 3
PDRB.PDIB2      2   Pulldown Inhibit B Bits 2
PDRB.PDIB1      1   Pulldown Inhibit B Bits 1
PDRB.PDIB0      0   Pulldown Inhibit B Bits 0
UNUSED0012     0x0012    UNUSED
UNUSED0013     0x0013    UNUSED
UNUSED0014     0x0014    UNUSED
UNUSED0015     0x0015    UNUSED
UNUSED0016     0x0016    UNUSED
UNUSED0017     0x0017    UNUSED
EPROG          0x0018    EPROM Programming
EPROG.ELAT      2   EPROM Bus Latch Bit
EPROG.MPGM      1   MOR Programming Bit
EPROG.EPGM      0   EPROM Programming Bit
UNUSED0019     0x0019    UNUSED
UNUSED001A     0x001A    UNUSED
UNUSED001B     0x001B    UNUSED
UNUSED001C     0x001C    UNUSED
UNUSED001D     0x001D    UNUSED
UNUSED001E     0x001E    UNUSED
RESERV001F     0x001F    RESERVED
COPR           0x07F0    COP Register
COPR.COPC       0   COP Clear Bit
MOR            0x07F1    Mask Options
MOR.SOSCD       7   Short Oscillator Delay Bit
MOR.EPMSEC      6   EPROM Security Bit
MOR.OSCRES      5   Oscillator Internal Resistor Bit
MOR.SWAIT       4   Stop-to-Wait Conversion Bit
MOR.PDI         3   Software Pulldown Inhibit Bit
MOR.PIRQ        2   Port A External Interrupt Bit
MOR.LEVEL       1   External Interrupt Sensitivity Bit
MOR.COPEN       0   COP Enable Bit
RESERV07F2     0x07F2    RESERVED
RESERV07F3     0x07F3    RESERVED
RESERV07F4     0x07F4    RESERVED
RESERV07F5     0x07F5    RESERVED
RESERV07F6     0x07F6    RESERVED
RESERV07F7     0x07F7    RESERVED


.68HSC05C4A
; HC05C4AGRS/D  http://
; HC05C4AGRS.pdf

; RAM=176
; ROM=4144
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area DATA ROM_1        0x0020:0x0050
area DATA RAM          0x0050:0x0100
area DATA ROM_2        0x0100:0x1100
area BSS  UNUSED       0x1100:0x1F00
area DATA ROM_S_CH     0x1F00:0x1FF0
area DATA USER_VEC     0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt TIMER             0x1FF8      Timer Input Capture
interrupt SCI               0x1FF6      Serial Communications Interrupt
interrupt SPI               0x1FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA          0x0000     Port A Data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001     Port B Data
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
PORTC          0x0002     Port C Data
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
PORTD          0x0003     Port D Data
PORTD.PD7       7   Port D Data Bits 7
PORTD.PD5       5   Port D Data Bits 5
PORTD.PD4       4   Port D Data Bits 4
PORTD.PD3       3   Port D Data Bits 3
PORTD.PD2       2   Port D Data Bits 2
PORTD.PD1       1   Port D Data Bits 1
PORTD.PD0       0   Port D Data Bits 0
DDRA           0x0004     Port A Data Direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005     Port B Data Direction
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRC           0x0006     Port C Data Direction
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC6      6   Data Direction for Port C Bit 6
DDRC.DDRC5      5   Data Direction for Port C Bit 5
DDRC.DDRC4      4   Data Direction for Port C Bit 4
DDRC.DDRC3      3   Data Direction for Port C Bit 3
DDRC.DDRC2      2   Data Direction for Port C Bit 2
DDRC.DDRC1      1   Data Direction for Port C Bit 1
DDRC.DDRC0      0   Data Direction for Port C Bit 0
UNUSED07       0x0007     UNUSED
UNUSED08       0x0008     UNUSED
UNUSED09       0x0009     UNUSED
SPCR           0x000A     SPI Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable
SPCR.MSTR       4   Master Mode Select
SPCR.CPOL       3   Clock Polarity
SPCR.CPHA       2   Clock Phase
SPCR.SPR1       1   SPI Clock Rate Selects 1
SPCR.SPR0       0   SPI Clock Rate Selects 0
SPSR           0x000B     SPI Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision
SPSR.MODF       4   Mode Fault
SPDR           0x000C     SPI Data Register
SPDR.SPD7       7
SPDR.SPD6       6
SPDR.SPD5       5
SPDR.SPD4       4
SPDR.SPD3       3
SPDR.SPD2       2
SPDR.SPD1       1
SPDR.SPD0       0
BAUD           0x000D     SCI Baud Rate Register
BAUD.SCP1       5   SCI Prescaler Select Bits 1
BAUD.SCP0       3   SCI Prescaler Select Bits 0
BAUD.SCR2       2   SCI Baud Rate Select Bits 2
BAUD.SCR1       1   SCI Baud Rate Select Bits 1
BAUD.SCR0       0   SCI Baud Rate Select Bits 0
SCCR1          0x000E     SCI Control 1
SCCR1.R8        7   Bit 8 (Received)
SCCR1.T8        6   Bit 8 (Transmitted)
SCCR1.M         4   Character Length
SCCR1.WAKE      3   Wakeup Bit
SCCR2          0x000F     SCI Control 2
SCCR2.TIE       7   Transmit Interrupt Enable
SCCR2.TCIE      6   Transmission Complete Interrupt Enable
SCCR2.RIE       5   Receive Interrupt Enable
SCCR2.ILIE      4   Idle Line Interrupt Enable
SCCR2.TE        3   Transmit Enable
SCCR2.RE        2   Receive Enable
SCCR2.RMU       1   Receiver Wakeup Enable
SCCR2.SBK       0   Send Break
SCSR           0x0010     SCI Status Register
SCSR.TDRE       7   Transmit Data Register Empty
SCSR.TC         6   Transmission Complete
SCSR.RDRF       5   Receive Data Register Full
SCSR.IDLE       4   Receiver Idle
SCSR.OR         3   Receiver Overrun
SCSR.NF         2   Receiver Noise Flag
SCSR.FE         1   Receiver Framing Error
SCDAT          0x0011     SCI Data Register
SCDAT.SCD7      7   Serial Data Bit 7
SCDAT.SCD6      6   Serial Data Bit 6
SCDAT.SCD5      5   Serial Data Bit 5
SCDAT.SCD4      4   Serial Data Bit 4
SCDAT.SCD3      3   Serial Data Bit 3
SCDAT.SCD2      2   Serial Data Bit 2
SCDAT.SCD1      1   Serial Data Bit 1
SCDAT.SCD0      0   Serial Data Bit 0
TCR            0x0012     Timer Control Register
TCR.ICIE        7   Input Capture Interrupt Enable
TCR.OCIE        6   Output Compare Interrupt Enable
TCR.TOIE        5   Timer Overflow Interrupt Enable
TCR.IEDGE       1   Input Edge
TCR.OLVL        0   Output Level
TSR            0x0013     Timer Status Register
TSR.ICF         7   Input Capture Flag
TSR.OCF         6   Output Compare Flag
TSR.TOF         5   Timer Overflow Flag
ICRH           0x0014     Input Capture Register high
ICRL           0x0015     Input Capture Register low
OCRH           0x0016     Output Compare Register high
OCRL           0x0017     Output Compare Register low
TCNTH          0x0018     Timer Counter Register high
TCNTL          0x0019     Timer Counter Register low
ALTCNTH        0x001A     Alternate Counter Register high
ALTCNTL        0x001B     Alternate Counter Register low
UNUSED1C       0x001C     UNUSED
UNUSED1D       0x001D     UNUSED
UNUSED1E       0x001E     UNUSED
RESERV001F     0x001F     RESERVED
COPR           0x1FF0     COP Reset
COPR.COPC       0
RESERV1FF1     0x1FF1    RESERVED
RESERV1FF2     0x1FF2    RESERVED
RESERV1FF3     0x1FF3    RESERVED


.68HSC05C9A
; HC05C9AGRS/D http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05C9A&nodeId=01M98633 
; HC05C9AGRS.pdf

; RAM=0
; ROM=0
; EPROM=4608
; EEPROM=0


; MEMORY MAP
area DATA FSR          0x0000:0x0020
area DATA ROM0_RAM0    0x0020:0x0050
area DATA RAM          0x0050:0x0100
area DATA ROM1_RAM1    0x0100:0x0180
area DATA ROM          0x0180:0x3F00
area DATA ROM_S_CH     0x3F00:0x3F00
area DATA USER_VEC     0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Reset  
interrupt SWI               0x3FFC      Software Interrupt               
interrupt IRQ               0x3FFA      IRQ/IRQ2        
interrupt Timer             0x3FF8      Timer Interrupt
interrupt SCI               0x3FF6      Serial Communications Interrupt
interrupt SPI               0x3FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001     Port B data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002    Port C data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003    Port D data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004   Port A Data Direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005   Port B Data Direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006   Port C Data Direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007   Port D Data Direction
DDRD.DDRD7       7   Data Direction for Port D Bit 7
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
RESERV0008      0x0008   RESERVED
RESERV0009      0x0009   RESERVED
SPCR            0x000A   SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable
SPCR.DWOM        5   Port D Wire-OR Mode Option
SPCR.MSTR        4   Master Mode Select
SPCR.CPOL        3   Clock Polarity
SPCR.CPHA        2   Clock Phase
SPCR.SPR1        1   SPI Clock Rate Selects 1
SPCR.SPR0        0   SPI Clock Rate Selects 0
SPSR            0x000B   SPI Status Register
SPSR.SPIF        7   SPI Transfer Complete Flag
SPSR.WCOL        6   Write Collision
SPSR.MODF        4   Mode Fault
SPDR            0x000C   SPI Data Register
SPDR.SPD7        7
SPDR.SPD6        6
SPDR.SPD5        5
SPDR.SPD4        4
SPDR.SPD3        3
SPDR.SPD2        2
SPDR.SPD1        1
SPDR.SPD0        0
BAUD            0x000D   SCI Baud Rate Register
BAUD.SCP1        5   SCI Prescaler Select Bits 1
BAUD.SCP0        4   SCI Prescaler Select Bits 0
BAUD.SCR2        2   SCR0-SCI Baud Rate Select Bits 2
BAUD.SCR1        1   SCR0-SCI Baud Rate Select Bits 1
BAUD.SCR0        0   SCR0-SCI Baud Rate Select Bits 0
SCCR1           0x000E   SCI Control Register 1
SCCR1.R8         7   Bit 8 (Received)
SCCR1.T8         6   Bit 8 (Transmitted)
SCCR1.M          4   Character Length
SCCR1.WAKE       3   Wakeup Method
SCCR2           0x000F   SCI Control Register 2
SCCR2.TIE        7   Transmit Interrupt Enable
SCCR2.TCIE       6   Transmission Complete Interrupt Enable
SCCR2.RIE        5   Receiver Interrupt Enable
SCCR2.ILIE       4   Idle Line Interrupt Enable
SCCR2.TE         3   Transmitter Enable
SCCR2.RE         2   Receiver Enable
SCCR2.RWU        1   Receiver Wakeup Enable
SCCR2.SBK        0   Send Break
SCSR            0x0010   SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty
SCSR.TC          6   Transmission Complete
SCSR.RDRF        5   Receive Data Register Full
SCSR.IDLE        4   Receiver Idle
SCSR.OR          3   Receiver Overrun
SCSR.NF          2   Receiver Noise Flag
SCSR.FE          1   Receiver Framing Error
SCDR            0x0011   SCI Data Register
SCDR.SCD7        7   Serial Data Bit 7
SCDR.SCD6        6   Serial Data Bit 6
SCDR.SCD5        5   Serial Data Bit 5
SCDR.SCD4        4   Serial Data Bit 4
SCDR.SCD3        3   Serial Data Bit 3
SCDR.SCD2        2   Serial Data Bit 2
SCDR.SCD1        1   Serial Data Bit 1
SCDR.SCD0        0   Serial Data Bit 0
TCR             0x0012   Timer  Control Register
TCR.ICIE         7   Input Capture Interrupt Enable
TCR.OCIE         6   Output Compare Interrupt Enable
TCR.TOIE         5   Timer Overflow Interrupt Enable
TCR.IEDG         1   Input Edge
TCR.OLVL         0   Output Level
TSR             0x0013   Timer  Status Register
TSR.ICF          7   Input Capture Flag
TSR.OCF          6   Output Compare Flag
TSR.TOF          5   Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TRH             0x0018   Timer Counter Register High
TRL             0x0019   Timer Counter Register Low
ATRH            0x001A   Alternate  Counter Register High
ATRL            0x001B   Alternate  Counter Register Low
UNUSED001C      0x001C   UNUSED
COPRST          0x001D   COP Reset Register
COPCR           0x001E   COP Control Register
COPCR.COPF       4   Computer Operating Properly Flag
COPCR.CME        3   Clock Monitor Enable
COPCR.COPE       2   COP Enable
COPCR.CM1        1   COP Mode Bit 1
COPCR.CM0        0   COP Mode Bit 0
RESERV001F      0x001F   RESERVED
RESERV03F0      0x03F0   RESERVED
RESERV03F1      0x03F1   RESERVED
RESERV03F2      0x03F2   RESERVED
RESERV03F3      0x03F3   RESERVED


.68HSC705C4A
; MC68HC705C4A/D  http://
; MC68HC705C4A.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR			0x0000:0x0020
area DATA ROM_1			0x0020:0x0050
area DATA RAM			0x0050:0x0100
area DATA ROM_2			0x0100:0x1100
area BSS  UNUSED		0x1100:0x1F00
area DATA BOOT_ROM		0x1F00:0x1FF0
area DATA USER_VEC		0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      ...
interrupt TIMER             0x1FF8
interrupt SCI               0x1FF6
interrupt SPI               0x1FF4


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A Data Register
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B Data Register
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C Data Register
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D Fixed Input Register
PORTD.PD7              7
PORTD.SS               5
PORTD.SCK              4
PORTD.MOSI             3
PORTD.MISO             2
PORTD.TDO              1
PORTD.RDI              0
DDRA                  0x0004     Port A Data Direction Register
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B Data Direction Register
DDRB.DDRB7             7   Data Direction for Port B Bit 7
DDRB.DDRB6             6   Data Direction for Port B Bit 6
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C Data Direction Register
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
RESERV0007            0x0007     RESERVED
RESERV0008            0x0008     RESERVED
RESERV0009            0x0009     RESERVED
SPCR                  0x000A     SPI Control Register
SPCR.SPIE              7   SPI Interrupt Enable Bit
SPCR.SPE               6   SPI Enable Bit
SPCR.MSTR              4   Master Bit
SPCR.CPOL              3   Clock Polarity Bit
SPCR.CPHA              2   Clock Phase Bit
SPCR.SPR1              1   SPI Clock Rate Bits 1
SPCR.SPR0              0   SPI Clock Rate Bits 0
SPSR                  0x000B     SPI Status Register
SPSR.SPIF              7   SPI Flag
SPSR.WCOL              6   Write Collision Bit
SPSR.MODF              4   Mode Fault Bit
SPDR                  0x000C     SPI Data Register
Baud                  0x000D     Baud Rate Register
Baud.SCP1              5   SCI Prescaler Select Bit 1
Baud.SCP0              4   SCI Prescaler Select Bit 0
Baud.SCR2              2   SCI Baud Rate Select Bit 2
Baud.SCR1              1   SCI Baud Rate Select Bit 1
Baud.SCR0              0   SCI Baud Rate Select Bit 0
SCCR1                 0x000E     SCI Control Register 1
SCCR1.R8               7   Bit 8 (Received)
SCCR1.T8               6   Bit 8 (Transmitted)
SCCR1.M                4   Character Length Bit
SCCR1.WAKE             3   Wakeup Bit
SCCR2                 0x000F     SCI Control Register 2
SCCR2.TIE              7   Transmit Interrupt Enable Bit
SCCR2.TCIE             6   Transmission Complete Interrupt Enable Bit
SCCR2.RIE              5   Receive Interrupt Enable Bit
SCCR2.ILIE             4   Idle Line Interrupt Enable Bit
SCCR2.TE               3   Transmit Enable Bit
SCCR2.RE               2   Receive Enable Bit
SCCR2.RWU              1   Receiver Wakeup Enable Bit
SCCR2.SBK              0   Send Break Bit
SCSR                  0x0010     SCI Status Register
SCSR.TDRE              7   Transmit Data Register Empty Bit
SCSR.TC                6   Transmission Complete Bit
SCSR.RDRF              5   Receive Data Register Full Bit
SCSR.IDLE              4   Receiver Idle Bit
SCSR.OR                3   Receiver Overrun Bit
SCSR.NF                2   Receiver Noise Flag
SCSR.FE                1   Receiver Framing Error Bit
SCDR                  0x0011     SCI Data Register
TCR                   0x0012     Timer Control Register
TCR.ICIE               7   Input Capture Interrupt Enable Bit
TCR.OCIE               6   Output Compare Interrupt Enable Bit
TCR.TOIE               5   Timer Overflow Interrupt Enable Bit
TCR.IEDG               1   Input Edge Bit
TCR.OLVL               0   Output Level Bit
TSR                   0x0013     Timer Status Register
TSR.ICF                7   Input Capture Flag
TSR.OCF                6   Output Compare Flag
TSR.TOF                5   Timer Overflow Flag
ICRH                  0x0014     Input Capture Register High
ICRL                  0x0015     Input Capture Register Low
OCRH                  0x0016     Output Compare Register High
OCRL                  0x0017     Output Compare Register Low
TRH                   0x0018     Timer Register High
TRL                   0x0019     Timer Register Low
ATRH                  0x001A     Alternate Timer Register High
ATRL                  0x001B     Alternate Timer Register Low
PROG                  0x001C     EPROM Programming Register
PROG.LAT               2   Latch Enable Bit
PROG.PGM               0   Program Bit
RESERV001D            0x001D     RESERVED
RESERV001E            0x001E     RESERVED
RESERV001F            0x001F     RESERVED
Option                0x1FDF     Option Register
Option.SEC             3   Security Bit
Option.IRQ             1   Interrupt Request Pin Sensitivity Bit
MOR1                  0x1FF0     Mask Option Register 1
MOR1.PBPU7             7   Port B Pullup Enable Bit 7
MOR1.PBPU6             6   Port B Pullup Enable Bit 6
MOR1.PBPU5             5   Port B Pullup Enable Bit 5
MOR1.PBPU4             4   Port B Pullup Enable Bit 4
MOR1.PBPU3             3   Port B Pullup Enable Bit 3
MOR1.PBPU2             2   Port B Pullup Enable Bit 2
MOR1.PBPU1             1   Port B Pullup Enable Bit 1
MOR1.PBPU0_COPC        0   Port B Pullup Enable Bit 0
MOR2                  0x1FF1     Mask Option Register 2
MOR2.NCOPE             0   Non-Programmable COP Watchdog Enable Bit
RESERV1FF2            0x1FF2    RESERVED
RESERV1FF3            0x1FF3    RESERVED


.68HSC705J1A
; MC68HC705J1A/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705J1A&nodeId=01M98633
; MC68HC705J1A.pdf

; RAM=64
; ROM=0
; EPROM=1232
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x00C0
area DATA RAM         0x00C0:0x0100
area BSS  UNUSED      0x0100:0x0300
area CODE EPROM       0x0300:0x07D0
area BSS  UNUSED      0x07D0:0x07EE
area DATA TES_TROM    0x07EE:0x07F0
area DATA USER_VEC    0x07F0:0x0800


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Processor reset
interrupt SWI               0x07FC      Software interrupt
interrupt EI                0x07FA      External Interrupt
interrupt TIMER_In          0x07F8      Timer Interupt


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001    Port B data
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
UNUSED0002     0x0002    UNUSED
UNUSED0003     0x0003    UNUSED
DDRA           0x0004    Port A data direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0005    Port B data direction
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
UNUSED0006     0x0006    UNUSED
UNUSED0007     0x0007    UNUSED
TSCR           0x0008  Timer Status and Control
TSCR.TOF        7   Timer Overflow Flag
TSCR.RTIF       6   Real-Time Interrupt Flag
TSCR.TOIE       5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE       4   Real-Time Interrupt Enable Bit
TSCR.TOFR       3   Timer Overflow Flag Reset Bit
TSCR.RTIFR      2   Real-Time Interrupt Flag Reset Bit
TSCR.RT1        1   Real-Time Interrupt Select Bits 1
TSCR.RT0        0   Real-Time Interrupt Select Bits 0
TCR            0x0009  Timer Counter
TCR.TMR7        7
TCR.TMR6        6
TCR.TMR5        5
TCR.TMR4        4
TCR.TMR3        3
TCR.TMR2        2
TCR.TMR1        1
TCR.TMR0        0
ISCR           0x000A  IRQ Status and Control
ISCR.IRQE       7   External Interrupt Request Enable Bit
ISCR.IRQF       3   External Interrupt Request Flag
ISCR.IRQR       1   Interrupt Request Reset Bit
UNUSED000B     0x000B    UNUSED
UNUSED000C     0x000C    UNUSED
UNUSED000D     0x000D    UNUSED
UNUSED000E     0x000E    UNUSED
UNUSED000F     0x000F    UNUSED
PDRA           0x0010    Pulldown Register Port A
PDRA.PDIA7      7   Pulldown Inhibit A Bits 7
PDRA.PDIA6      6   Pulldown Inhibit A Bits 6
PDRA.PDIA5      5   Pulldown Inhibit A Bits 5
PDRA.PDIA4      4   Pulldown Inhibit A Bits 4
PDRA.PDIA3      3   Pulldown Inhibit A Bits 3
PDRA.PDIA2      2   Pulldown Inhibit A Bits 2
PDRA.PDIA1      1   Pulldown Inhibit A Bits 1
PDRA.PDIA0      0   Pulldown Inhibit A Bits 0
PDRB           0x0011     Pulldown Register Port B
PDRB.PDIB5      5   Pulldown Inhibit B Bits 5
PDRB.PDIB4      4   Pulldown Inhibit B Bits 4
PDRB.PDIB3      3   Pulldown Inhibit B Bits 3
PDRB.PDIB2      2   Pulldown Inhibit B Bits 2
PDRB.PDIB1      1   Pulldown Inhibit B Bits 1
PDRB.PDIB0      0   Pulldown Inhibit B Bits 0
UNUSED0012     0x0012    UNUSED
UNUSED0013     0x0013    UNUSED
UNUSED0014     0x0014    UNUSED
UNUSED0015     0x0015    UNUSED
UNUSED0016     0x0016    UNUSED
UNUSED0017     0x0017    UNUSED
EPROG          0x0018    EPROM Programming
EPROG.ELAT      2   EPROM Bus Latch Bit
EPROG.MPGM      1   MOR Programming Bit
EPROG.EPGM      0   EPROM Programming Bit
UNUSED0019     0x0019    UNUSED
UNUSED001A     0x001A    UNUSED
UNUSED001B     0x001B    UNUSED
UNUSED001C     0x001C    UNUSED
UNUSED001D     0x001D    UNUSED
UNUSED001E     0x001E    UNUSED
RESERV001F     0x001F    RESERVED
COPR           0x07F0    COP Register
COPR.COPC       0   COP Clear Bit
MOR            0x07F1    Mask Options
MOR.SOSCD       7   Short Oscillator Delay Bit
MOR.EPMSEC      6   EPROM Security Bit
MOR.OSCRES      5   Oscillator Internal Resistor Bit
MOR.SWAIT       4   Stop-to-Wait Conversion Bit
MOR.PDI         3   Software Pulldown Inhibit Bit
MOR.PIRQ        2   Port A External Interrupt Bit
MOR.LEVEL       1   External Interrupt Sensitivity Bit
MOR.COPEN       0   COP Enable Bit
RESERV07F2     0x07F2    RESERVED
RESERV07F3     0x07F3    RESERVED
RESERV07F4     0x07F4    RESERVED
RESERV07F5     0x07F5    RESERVED
RESERV07F6     0x07F6    RESERVED
RESERV07F7     0x07F7    RESERVED


.68HSR705J1A
; MC68HC705J1A/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705J1A&nodeId=01M98633
; MC68HC705J1A.pdf

; RAM=64
; ROM=0
; EPROM=1232
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x00C0
area DATA RAM         0x00C0:0x0100
area BSS  UNUSED      0x0100:0x0300
area CODE EPROM       0x0300:0x07D0
area BSS  UNUSED      0x07D0:0x07EE
area DATA TES_TROM    0x07EE:0x07F0
area DATA USER_VEC    0x07F0:0x0800


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Processor reset
interrupt SWI               0x07FC      Software interrupt
interrupt EI                0x07FA      External Interrupt
interrupt TIMER_In          0x07F8      Timer Interupt


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
UNUSED0002            0x0002    UNUSED
UNUSED0003            0x0003    UNUSED
DDRA                  0x0004    Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005    Port B data direction
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
UNUSED0006            0x0006    UNUSED
UNUSED0007            0x0007    UNUSED
TSCR                  0x0008  Timer Status and Control
TSCR.TOF               7   Timer Overflow Flag
TSCR.RTIF              6   Real-Time Interrupt Flag
TSCR.TOIE              5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE              4   Real-Time Interrupt Enable Bit
TSCR.TOFR              3   Timer Overflow Flag Reset Bit
TSCR.RTIFR             2   Real-Time Interrupt Flag Reset Bit
TSCR.RT1               1   Real-Time Interrupt Select Bits 1
TSCR.RT0               0   Real-Time Interrupt Select Bits 0
TCR                   0x0009  Timer Counter
TCR.TMR7               7
TCR.TMR6               6
TCR.TMR5               5
TCR.TMR4               4
TCR.TMR3               3
TCR.TMR2               2
TCR.TMR1               1
TCR.TMR0               0
ISCR                  0x000A  IRQ Status and Control
ISCR.IRQE              7   External Interrupt Request Enable Bit
ISCR.IRQF              3   External Interrupt Request Flag
ISCR.IRQR              1   Interrupt Request Reset Bit
UNUSED000B            0x000B    UNUSED
UNUSED000C            0x000C    UNUSED
UNUSED000D            0x000D    UNUSED
UNUSED000E            0x000E    UNUSED
UNUSED000F            0x000F    UNUSED
PDRA                  0x0010    Pulldown Register Port A
PDRA.PDIA7             7   Pulldown Inhibit A Bits 7
PDRA.PDIA6             6   Pulldown Inhibit A Bits 6
PDRA.PDIA5             5   Pulldown Inhibit A Bits 5
PDRA.PDIA4             4   Pulldown Inhibit A Bits 4
PDRA.PDIA3             3   Pulldown Inhibit A Bits 3
PDRA.PDIA2             2   Pulldown Inhibit A Bits 2
PDRA.PDIA1             1   Pulldown Inhibit A Bits 1
PDRA.PDIA0             0   Pulldown Inhibit A Bits 0
PDRB                  0x0011     Pulldown Register Port B
PDRB.PDIB5             5   Pulldown Inhibit B Bits 5
PDRB.PDIB4             4   Pulldown Inhibit B Bits 4
PDRB.PDIB3             3   Pulldown Inhibit B Bits 3
PDRB.PDIB2             2   Pulldown Inhibit B Bits 2
PDRB.PDIB1             1   Pulldown Inhibit B Bits 1
PDRB.PDIB0             0   Pulldown Inhibit B Bits 0
UNUSED0012            0x0012    UNUSED
UNUSED0013            0x0013    UNUSED
UNUSED0014            0x0014    UNUSED
UNUSED0015            0x0015    UNUSED
UNUSED0016            0x0016    UNUSED
UNUSED0017            0x0017    UNUSED
EPROG                 0x0018    EPROM Programming
EPROG.ELAT             2   EPROM Bus Latch Bit
EPROG.MPGM             1   MOR Programming Bit
EPROG.EPGM             0   EPROM Programming Bit
UNUSED0019            0x0019    UNUSED
UNUSED001A            0x001A    UNUSED
UNUSED001B            0x001B    UNUSED
UNUSED001C            0x001C    UNUSED
UNUSED001D            0x001D    UNUSED
UNUSED001E            0x001E    UNUSED
RESERV001F            0x001F    RESERVED
COPR                  0x07F0    COP Register
COPR.COPC              0   COP Clear Bit
MOR                   0x07F1    Mask Options
MOR.SOSCD              7   Short Oscillator Delay Bit
MOR.EPMSEC             6   EPROM Security Bit
MOR.OSCRES             5   Oscillator Internal Resistor Bit
MOR.SWAIT              4   Stop-to-Wait Conversion Bit
MOR.PDI                3   Software Pulldown Inhibit Bit
MOR.PIRQ               2   Port A External Interrupt Bit
MOR.LEVEL              1   External Interrupt Sensitivity Bit
MOR.COPEN              0   COP Enable Bit
RESERV07F2            0x07F2    RESERVED
RESERV07F3            0x07F3    RESERVED
RESERV07F4            0x07F4    RESERVED
RESERV07F5            0x07F5    RESERVED
RESERV07F6            0x07F6    RESERVED
RESERV07F7            0x07F7    RESERVED


.68HC805C4
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS


.68HC805K3
; http://
; AN1747.pdf

; RAM=64
; ROM=0
; EPROM=0
; EEPROM=920


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area CODE EEPROM_0    0x0020:0x00C0
area DATA SRAM        0x00C0:0x0100
area CODE EEPROM_1    0x0100:0x03F0
area DATA USER_VEC    0x03F0:0x0400


; Interrupt and reset vector assignments
interrupt __RESET           0x03FE      Processor reset
interrupt SWI               0x03FC      Software interrupt
interrupt IRQ               0x03FA      ...
interrupt TIMER             0x03F8


; INPUT/ OUTPUT PORTS
PORTA         0x0000   Port A Data
PORTB         0x0001   Port B Data
UNUSED0002    0x0002   UNUSED
UNUSED0003    0x0003   UNUSED
DDRA          0x0004   Port A Data Direction
DDRB          0x0005   Port B Data Direction
UNUSED0006    0x0006   UNUSED
UNUSED0007    0x0007   UNUSED
TSCR          0x0008   Timer Status_Control
TCNTR         0x0009   Timer Counter
ISCR          0x000A   IRQ Status_Control
UNUSED000B    0x000B   UNUSED
UNUSED000C    0x000C   UNUSED
UNUSED000D    0x000D   UNUSED
PEBSR         0x000E   Personality EEPROM Bit Select
PESCR         0x000F   Personality EEPROM Status_Control
PDRA          0x0010   Port A Pulldown Inhibit
PDRB          0x0011   Port B Pulldown Inhibit
MOR1          0x0012   MOR Register 1
MOR2          0x0013   MOR Register 2
RESERV0014    0x0014   RESERV
UNUSED0015    0x0015   UNUSED
UNUSED0016    0x0016   UNUSED
UNUSED0017    0x0017   UNUSED
UNUSED0018    0x0018   UNUSED
UNUSED0019    0x0019   UNUSED
UNUSED001A    0x001A   UNUSED
UNUSED001B    0x001B   UNUSED
UNUSED001C    0x001C   UNUSED
UNUSED001D    0x001D   UNUSED
UNUSED001E    0x001E   UNUSED
RESERV001F    0x001F   RESERVED
COP           0x03F0   COP
RESERV03F1    0x03F1   RESERVED
RESERV03F2    0x03F2   RESERVED
RESERV03F3    0x03F3   RESERVED
RESERV03F4    0x03F4   RESERVED
RESERV03F5    0x03F5   RESERVED
RESERV03F6    0x03F6   RESERVED
RESERV03F7    0x03F7   RESERVED


.68HSC05C8A
; MC68HC05C8A/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05C8A&nodeId=01M98633
; MC68HC05C8A.pdf

; RAM=176
; ROM=7744
; EPROM=0  
; EEPROM=0  


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_P1      0x0020:0x0050
area DATA RAM         0x0050:0x0100
area DATA ROM_P2      0x0100:0x1F00
area DATA ROM_S_CH    0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt TIMER             0x1FF8      Timer Interrupt
interrupt SCI               0x1FF6      Serial Communications Interrupt
interrupt SPI               0x1FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001    Port B data
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
PORTC          0x0002    Port C data
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
PORTD          0x0003    Port D data
PORTD.PD7       7   Port D Data Bits 7
PORTD.PD5       5   Port D Data Bits 5
PORTD.PD4       4   Port D Data Bits 4
PORTD.PD3       3   Port D Data Bits 3
PORTD.PD2       2   Port D Data Bits 2
PORTD.PD1       1   Port D Data Bits 1
PORTD.PD0       0   Port D Data Bits 0
DDRA           0x0004    Port A data direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA1      0   Data Direction for Port A Bit 0
DDRB           0x0005    Port B data direction
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRC           0x0006    Port C data direction
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC7      6   Data Direction for Port C Bit 6
DDRC.DDRC7      5   Data Direction for Port C Bit 5
DDRC.DDRC7      4   Data Direction for Port C Bit 4
DDRC.DDRC7      3   Data Direction for Port C Bit 3
DDRC.DDRC7      2   Data Direction for Port C Bit 2
DDRC.DDRC7      1   Data Direction for Port C Bit 1
DDRC.DDRC7      0   Data Direction for Port C Bit 0
UNUSED0007     0x0007    UNUSED
UNUSED0008     0x0008    UNUSED
UNUSED0009     0x0009    UNUSED
SPCR           0x000A    SPI Control
SPCR.SPIE       7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE        6   Serial Peripheral System Enable Bit
SPCR.MSTR       4   Master Mode Select Bit
SPCR.CPOL       3   Clock Polarity Bit
SPCR.CPHA       2   Clock Phase Bit
SPCR.SPR1       1   SPI Clock Rate Select Bits 1
SPCR.SPR0       0   SPI Clock Rate Select Bits 0
SPSR           0x000B    SPI Status
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Flag
SPDR           0x000C    SPI Data
SPDR.SPD7       7
SPDR.SPD6       6
SPDR.SPD5       5
SPDR.SPD4       4
SPDR.SPD3       3
SPDR.SPD2       2
SPDR.SPD1       1
SPDR.SPD0       0
BAUD           0x000D    SCI Baud Rate
BAUD.SCP1       5   SCI Prescaler Select Bits 1
BAUD.SCP0       4   SCI Prescaler Select Bits 0
BAUD.SCR2       2   SCI Baud Rate Select Bits 2
BAUD.SCR1       1   SCI Baud Rate Select Bits 1
BAUD.SCR0       0   SCI Baud Rate Select Bits 0
SCCR1          0x000E    SCI Control 1
SCCR1.R8        7   Bit 8 (Received)
SCCR1.T8        6   Bit 8 (Transmitted)
SCCR1.M         4   Character Length Bit
SCCR1.WAKE      3   Wakeup Bit
SCCR2          0x000F    SCI Control 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmission Complete Interrupt Enable Bit
SCCR2.RIE       5   Receive Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmit Enable Bit
SCCR2.RE        2   Receive Enable Bit
SCCR2.RMU       1   Receiver Wakeup Enable Bit
SCCR2.SBK       0   Send Break Bit
SCSR           0x0010    SCI Status
SCSR.TDRE       7   Transmit Data Register Empty Bit
SCSR.TC         6   Transmission Complete Bit
SCSR.RDRF       5   Receive Data Register Full Bit
SCSR.IDLE       4   Receiver Idle Bit
SCSR.OR         3   Receiver Overrun Bit
SCSR.NF         2   Receiver Noise Flag
SCSR.FE         1   Receiver Framing Error Flag
SCDAT          0x0011     SCI Data
SCDAT.SCD7      7   Serial Data Bit 7
SCDAT.SCD6      6   Serial Data Bit 6
SCDAT.SCD5      5   Serial Data Bit 5
SCDAT.SCD4      4   Serial Data Bit 4
SCDAT.SCD3      3   Serial Data Bit 3
SCDAT.SCD2      2   Serial Data Bit 2
SCDAT.SCD1      1   Serial Data Bit 1
SCDAT.SCD0      0   Serial Data Bit 0
TCR            0x0012    Timer Control
TCR.ICIE        7   Input Capture Interrupt Enable Bit
TCR.OCIE        6   Output Compare Interrupt Enable Bit
TCR.TOIE        5   Timer Overflow Interrupt Enable Bit
TCR.IEDGE       1   Input Edge Bit
TCR.OLVL1       0   Output Level Bit
TSR            0x0013    Timer Status
TSR.ICF         7   Input Capture Flag
TSR.OCF         6   Output Compare Flag
TSR.TOF         5   Timer Overflow Flag
ICH            0x0014    Input capture
ICL            0x0015    Input capture
OCH            0x0016    Output compare
OCL            0x0017    Output compare
TCNTH          0x0018    Timer counter
TCNTL          0x0019    Timer counter
ALTCNTH        0x001A    Alternate counter
ALTCNTL        0x001B    Alternate counter
UNUSED001C     0x001C    UNUSED
UNUSED001D     0x001D    UNUSED
UNUSED001E     0x001E    UNUSED
RESERV001F     0x001F    Reserved
COP            0x1FF0    COP
COP.COPR        0
UNUSED07F1     0x07F1   UNUSED
UNUSED07F2     0x07F2   UNUSED
UNUSED07F3     0x07F3   UNUSED


.68HC05F32
; http://
; MC68HC05F32.pdf
  
; RAM=920
; ROM=32512
; EPROM=0
; EEPROM=256


; MEMORY MAP
area DATA FSR		0x0000:0x0050
area BSS  UNUSED	0x0050:0x0054
area DATA LCD_RAM	0x0054:0x0068
area DATA RAM		0x0068:0x0400
area DATA EEPROM	0x0400:0x0500
area BSS  UNUSED	0x0500:0x8000
area DATA ROM		0x8000:0xFF00
area DATA Boot_ROM	0xFF00:0xFFF0
area DATA USER_VEC	0xFFF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       Reset 
interrupt SWI 		0xFFFC       Software interrupt 
interrupt IRQ 		0xFFFA       External interrupt 
interrupt CTIMER 	0xFFF8       CTIMER
interrupt TIMER 	0xFFF6       TIMER
interrupt KEYF 		0xFFFA       Keyboard interrupt 
interrupt LVI 		0xFFF4       Low voltage interrupt 
interrupt SPI 		0xFFF2       Serial peripheral interface
interrupt SCI 		0xFFF0       Serial communications interface


; INPUT/ OUTPUT PORTS
PORTA           0x0000     Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
; KISR            0x0000     Key interrupt status
PORTB           0x0001     Port B data
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTC           0x0002     Port C data
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTD           0x0003     Port D data
PORTD.PD7        7   Port D Data Bits 7
PORTD.PD6        6   Port D Data Bits 6
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRA            0x0004     Port A data direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005     Port B data direction
DDRB.DDRB7       7   Data Direction for Port B Bit 7
DDRB.DDRB6       6   Data Direction for Port B Bit 6
DDRB.DDRB5       5   Data Direction for Port B Bit 5
DDRB.DDRB4       4   Data Direction for Port B Bit 4
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
DDRB.DDRB1       1   Data Direction for Port B Bit 1
DDRB.DDRB0       0   Data Direction for Port B Bit 0
DDRC            0x0006     Port C data direction
DDRC.DDRC7       7   Data Direction for Port C Bit 7
DDRC.DDRC6       6   Data Direction for Port C Bit 6
DDRC.DDRC5       5   Data Direction for Port C Bit 5
DDRC.DDRC4       4   Data Direction for Port C Bit 4
DDRC.DDRC3       3   Data Direction for Port C Bit 3
DDRC.DDRC2       2   Data Direction for Port C Bit 2
DDRC.DDRC1       1   Data Direction for Port C Bit 1
DDRC.DDRC0       0   Data Direction for Port C Bit 0
DDRD            0x0007     Port D data direction
DDRD.DDRD7       7   Data Direction for Port D Bit 7
DDRD.DDRD6       6   Data Direction for Port D Bit 6
DDRD.DDRD5       5   Data Direction for Port D Bit 5
DDRD.DDRD4       4   Data Direction for Port D Bit 4
DDRD.DDRD3       3   Data Direction for Port D Bit 3
DDRD.DDRD2       2   Data Direction for Port D Bit 2
DDRD.DDRD1       1   Data Direction for Port D Bit 1
DDRD.DDRD0       0   Data Direction for Port D Bit 0
CTCSR           0x0008     Core timer control_status
CTCSR.TOF        7   Core timer overflow
CTCSR.RTIF       6   Real time interrupt flag
CTCSR.TOFE       5   Core timer overflow enable
CTCSR.RTIE       4   Real time interrupt enable
CTCSR.RTOF       3
CTCSR.RRTIF      2
CTCSR.RT1        1   Real time interrupt rate select 1
CTCSR.RT0        0   Real time interrupt rate select 0
CTCR            0x0009     Core timer counter
PORTE           0x000A     Port E data
PORTE.PE7        7   Port E Data Bits 7
PORTE.PE6        6   Port E Data Bits 6
PORTE.PE5        5   Port E Data Bits 5
PORTE.PE4        4   Port E Data Bits 4
PORTE.PE3        3   Port E Data Bits 3
PORTE.PE2        2   Port E Data Bits 2
PORTE.PE1        1   Port E Data Bits 1
PORTE.PE0        0   Port E Data Bits 0
DDRE            0x000B     Port E data direction
DDRE.DDRE7       7   Data Direction for Port E Bit 7
DDRE.DDRE6       6   Data Direction for Port E Bit 6
DDRE.DDRE5       5   Data Direction for Port E Bit 5
DDRE.DDRE4       4   Data Direction for Port E Bit 4
DDRE.DDRE3       3   Data Direction for Port E Bit 3
DDRE.DDRE2       2   Data Direction for Port E Bit 2
DDRE.DDRE1       1   Data Direction for Port E Bit 1
DDRE.DDRE0       0   Data Direction for Port E Bit 0
PECR            0x000C     Port E control
FCR             0x000D     DTMF row freq. control
FCR.FCR4         4
FCR.FCR3         3
FCR.FCR2         2
FCR.FCR1         1
FCR.FCR0         0
FCC             0x000E     DTMF column freq. control
FCC.FCC4         4
FCC.FCC3         3
FCC.FCC2         2
FCC.FCC1         1
FCC.FCC0         0
TNCR            0x000F     DTMF tone control
TNCR.MS1         7   Melody select for operation 1
TNCR.MS0         6   Melody select for operation 0
TNCR.TGER        5   Tone generator enable row path
TNCR.TGEC        4   Tone generator enable column path
TNCR.TNOE        3   Tone output enable
PORTF           0x0010     Port F data
PORTF.PF7        7   Port F Data Bits 7
PORTF.PF6        6   Port F Data Bits 6
PORTF.PF5        5   Port F Data Bits 5
PORTF.PF4        4   Port F Data Bits 4
PORTF.PF3        3   Port F Data Bits 3
PORTF.PF2        2   Port F Data Bits 2
PORTF.PF1        1   Port F Data Bits 1
PORTF.PF0        0   Port F Data Bits 0
PFCR            0x0011     Port F control
PORTG           0x0012     Port G data
PORTG.PG7        7   Port G Data Bits 7
PORTG.PG6        6   Port G Data Bits 6
PORTG.PG5        5   Port G Data Bits 5
PORTG.PG4        4   Port G Data Bits 4
PORTG.PG3        3   Port G Data Bits 3
PORTG.PG2        2   Port G Data Bits 2
PORTG.PG1        1   Port G Data Bits 1
PORTG.PG0        0   Port G Data Bits 0
PGCR            0x0013     Port G control
PORTH           0x0014     Port H data
PORTH.PH7        7   Port H Data Bits 7
PORTH.PH6        6   Port H Data Bits 6
PORTH.PH5        5   Port H Data Bits 5
PORTH.PH4        4   Port H Data Bits 4
PORTH.PH3        3   Port H Data Bits 3
PORTH.PH2        2   Port H Data Bits 2
PORTH.PH1        1   Port H Data Bits 1
PORTH.PH0        0   Port H Data Bits 0
PHCR            0x0015     Port H control
PORTI           0x0016     Port I data
PORTI.PI7        7   Port I Data Bits 7
PORTI.PI6        6   Port I Data Bits 6
PORTI.PI5        5   Port I Data Bits 5
PORTI.PI4        4   Port I Data Bits 4
PORTI.PI3        3   Port I Data Bits 3
PORTI.PI2        2   Port I Data Bits 2
PORTI.PI1        1   Port I Data Bits 1
PORTI.PI0        0   Port I Data Bits 0
PICR            0x0017     Port I control
PORTJ           0x0018     Port J data
PORTJ.PJ7        7   Port J Data Bits 7
PORTJ.PJ6        6   Port J Data Bits 6
PORTJ.PJ5        5   Port J Data Bits 5
PORTJ.PJ4        4   Port J Data Bits 4
PORTJ.PJ3        3   Port J Data Bits 3
PORTJ.PJ2        2   Port J Data Bits 2
PORTJ.PJ1        1   Port J Data Bits 1
PORTJ.PJ0        0   Port J Data Bits 0
PJCR            0x0019     Port J control
PDCR            0x001A     Port D control
KCR             0x001B     Key control
KCR.KF           7   Keyboard interrupt status flag
KCR.KIE          6   keyboard interrupt enable
KCR.EDG5         5   trigger edge control 5
KCR.EDG4         4   trigger edge control 4
KCR.EDG3         3   trigger edge control 3
KCR.EDG2         2   trigger edge control 2
KCR.EDG1         1   trigger edge control 1
KCR.EDG0         0   trigger edge control 0
EEPROG          0x001C     EEPROM prog.
EEPROG.CPEN      6   Charge pump enable
EEPROG.ER1       4   Erase select bits 1
EEPROG.ER0       3   Erase select bits 0
EEPROG.LATCH     2   EEPROM latch bit
EEPROG.EERC      1   EEPROM RC oscillator control
EEPROG.EEPGM     0   EEPROM programming power enable
Reserv001D      0x001D     RESERVED
LCD             0x001E     LCD control
LCD.WTLCDO       7   WAIT mode LCD only
LCD.FSEL1        6   LCD operation frequency 1
LCD.FSEL0        5   LCD operation frequency 0
LCD.NTVLCD       4   Internal voltage generator ON/OFF
LCD.FDISP        3   Display frequency
LCD.MUX4         2   Multiplex ratio 4
LCD.MUX3         1   Multiplex ratio 3
LCD.EXTVON       0   External LCD voltage ON/OFF
Reserv001F      0x001F     RESERVED
ICR1H           0x0020     Capture 1 high
ICR1L           0x0021     Capture 1 low
OCR1H           0x0022     Compare 1 high
OCR1L           0x0023     Compare 1 low
ICR2H           0x0024     Capture 2 high
ICR2L           0x0025     Capture 2 low
OCR2H           0x0026     Compare 2 high
OCR2L           0x0027     Compare 2 low
CNTH_1          0x0028     Counter 1 high
CNTL_1          0x0029     Counter 1 low
ACNTH_1         0x002A     Alternate counter 1 high
ACNTL_1         0x002B     Alternate counter 1 low
TCR1_1          0x002C     Timer1 control 1
TCR1_1.IC1IE     7   Input capture 1 interrupt enable
TCR1_1.IC2IE     6   Input capture 2 interrupt enable
TCR1_1.OC1IE     5   Output compare 1 interrupt enable
TCR1_1.TOIE      4   Timer overflow interrupt enable
TCR1_1.CO1E      3   Timer compare 1 output enable
TCR1_1.IEDG1     2   Input edge 1
TCR1_1.IEDG2     1   Input edge 2
TCR1_1.OLVL1     0   Output level 1
TCR2_1          0x002D     Timer1 control 2
TCR2_1.OC2IE     5   Output compare 2 interrupt enable
TCR2_1.CO2E      3   Timer compare 2 output enable
TCR2_1.OLVL2     0   Output level 2
TSR_1           0x002E     Timer1 status
TSR_1.IC1F       7   Input capture 1 flag
TSR_1.IC2F       6   Input capture 2 flag
TSR_1.OC1F       5   Output compare 1 flag
TSR_1.TOF        4   Timer overflow status flag
TSR_1.TCAP1      3   Timer capture 1 status flag
TSR_1.TCAP2      2   Timer capture 2 status flag
TSR_1.OC2F       1   Output compare 2 flag
Reserv002F      0x002F     RESERVED
ICR3H           0x0030     Capture 3 high
ICR3L           0x0031     Capture 3 low
OCR3H           0x0032     Compare 3 high
OCR3L           0x0033     Compare 3 low
ICR4H           0x0034     Capture 4 high
ICR4L           0x0035     Capture 4 low
OCR4H           0x0036     Compare 4 high
OCR4L           0x0037     Compare 4 low
CNTH_1          0x0038     Counter 1 high
CNTL_1          0x0039     Counter 1 low
ACNTH_1         0x003A     Alternate counter 2 high
ACNTL_1         0x003B     Alternate counter 2 low
TCR1_2          0x003C     Timer2 control 1
TCR1_2.ICI3E     7   
TCR1_2.ICI4E     6   
TCR1_2.OCI3E     5   
TCR1_2.TOIE      4   
TCR1_2.CO3E      3   
TCR1_2.IEDG3     2   
TCR1_2.IEDG4     1   
TCR2_2          0x003D     Timer2 control 2
TCR2_2.OCI4E     5
TCR2_2.CO4E      3
TSR_2           0x003E     Timer2 status
TSR_2.IC3F       7
TSR_2.IC4F       6
TSR_2.OC3F       5
TSR_2.TOF        4
TSR_2.TCAP3      3
TSR_2.TCAP4      2
TSR_2.OC4F       1
Reserv003F      0x003F     RESERVED
PWMCR           0x0040     PWM control
PWMCR.POL3       4   PWM3 polarity 3
PWMCR.POL2       3   PWM2 polarity 2
PWMCR.POL1       2   PWM1 polarity 1
PWMCR.RA1        1   PWM clock rate bits 1
PWMCR.RA0        0   PWM clock rate bits 0
PWMD1           0x0041     PWM data 1
PWMD2           0x0042     PWM data 2
PWMD3           0x0043     PWM data 3
SPCR            0x0044     SPI control
SPCR.SPIE        7   SPI interrupt enable
SPCR.SPE         6   SPI system enable
SPCR.DOD         5   Direction of data
SPCR.MSTR        4   Master/slave mode select
SPCR.CPOL        3   Clock polarity
SPCR.CPHA        2   Clock phase
SPCR.SPR1        1   SPI clock (SCK) rate select bits 1
SPCR.SPR0        0   SPI clock (SCK) rate select bits 0
SPSR            0x0045     SPI status
SPSR.SPIF        7   SPI interrupt request flag
SPSR.WCOL        6   Write collision
SPSR.MODF        4   SPI mode error interrupt status flag
SPDAT           0x0046     SPI data I_O
SCDAT           0x0047     SCI data
SCCR1           0x0048     SCI control 1
SCCR1.R8         7   Receive data bit 8
SCCR1.T8         6   Transmit data bit 8
SCCR1.M          4   Mode (select character format)
SCCR1.WAKE       3   Wake-up mode select
SCCR2           0x0049     SCI control 2
SCCR2.TIE        7   Transmit interrupt enable
SCCR2.TCIE       6   Transmit complete interrupt enable
SCCR2.RIE        5   Receiver interrupt enable
SCCR2.ILIE       4   Idle line interrupt enable
SCCR2.TE         3   Transmitter enable
SCCR2.RE         2   Receiver enable
SCCR2.RWU        1   Receiver wake-up
SCCR2.SBK        0   Send break
SCSR            0x004A     SCI status
SCSR.TDRE        7   Transmit data register empty flag
SCSR.TC          6   Transmit complete flag
SCSR.RDRF        5   Receive data register full flag
SCSR.IDLE        4   Idle line detected flag
SCSR.OR          3   Overrun error flag
SCSR.NF          2   Noise error flag
SCSR.FE          1   Framing error flag
BAUD            0x004B     SCI baud rate
BAUD.TCLR        7   Clear baud rate counters (test purposes only)
BAUD.SCP1        5   Serial prescaler select bits 1
BAUD.SCP0        4   Serial prescaler select bits 0
BAUD.RCKB        3   SCI receive baud rate clock test
BAUD.SCR2        2   SCI rate select bits 2
BAUD.SCR1        1   SCI rate select bits 1
BAUD.SCR0        0   SCI rate select bits 0
CPICSR          0x004C     CPI control status
CPICSR.CPIF      6   Custom periodic interrupt flag
CPICSR.CPIE      4   Custom periodic interrupt enable
CPICSR.RFQ1      1   Refresh frequency select 1
CPICSR.RFQ0      0   Refresh frequency select 0
SOR             0x004D     System options
SOR.LVIF         7   LVIF - Low voltage interrupt bit
SOR.LVIE         6   LVIE - Low voltage interrupt bit
SOR.LVION        5   LVION - Low voltage interrupt bit
SOR.SC           4   System clock option
SOR.IRQ          3   Interrupt sensitivity
SOR.KEYMUX       2   Multiplex bit for access of interrupt flag
SOR.KEYCLR       1   Keyboard interrupt clear
SOR.PUEN         0   PORTC pull-up enable
ADDATA          0x004E     A_D data
ADSCR           0x004F     A_D status_control
ADSCR.COCO       7   Conversion complete flag
ADSCR.ADRC       6   A/D RC oscillator control
ADSCR.ADON       5   A/D converter on
ADSCR.CH3        3   A/D channel selection 3
ADSCR.CH2        2   A/D channel selection 2
ADSCR.CH1        1   A/D channel selection 1
ADSCR.CH0        0   A/D channel selection 0


.68HC05B4
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05B4&nodeId=01M98633
; 6805b6r4.pdf

; RAM=176
; ROM=6K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_P0      0x0020:0x0050
area DATA RAM         0x0050:0x0100
area BSS  RESERVED    0x0100:0x0200
area DATA ROM_P1      0x0200:0x02C0
area BSS  RESERVED    0x02C0:0x0F00
area DATA ROM_P2      0x0F00:0x1FF0
area BSS  RESERVED    0x1FF0:0x1FF2
area DATA USER_VEC    0x1FF2:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x1FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x1FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x1FF4      Timer overflow
interrupt SCI               0x1FF2      SCI0


; INPUT/ OUTPUT PORTS
PORTA             0x0000    Port A data
PORTA.PA7          7   Port A Data Bits 7
PORTA.PA6          6   Port A Data Bits 6
PORTA.PA5          5   Port A Data Bits 5
PORTA.PA4          4   Port A Data Bits 4
PORTA.PA3          3   Port A Data Bits 3
PORTA.PA2          2   Port A Data Bits 2
PORTA.PA1          1   Port A Data Bits 1
PORTA.PA0          0   Port A Data Bits 0
PORTB             0x0001    Port B data
PORTB.PB7          7   Port B Data Bits 7
PORTB.PB6          6   Port B Data Bits 6
PORTB.PB5          5   Port B Data Bits 5
PORTB.PB4          4   Port B Data Bits 4
PORTB.PB3          3   Port B Data Bits 3
PORTB.PB2          2   Port B Data Bits 2
PORTB.PB1          1   Port B Data Bits 1
PORTB.PB0          0   Port B Data Bits 0
PORTC             0x0002    Port C data
PORTC.PC2_ECLK     2   Port C Data Bits 2
PORTD             0x0003    Port D data
PORTD.PD7_AN7      7   Port D Data Bits 7
PORTD.PD6_AN6      6   Port D Data Bits 6
PORTD.PD5_AN5      5   Port D Data Bits 5
PORTD.PD4_AN4      4   Port D Data Bits 4
PORTD.PD3_AN3      3   Port D Data Bits 3
PORTD.PD2_AN2      2   Port D Data Bits 2
PORTD.PD1_AN1      1   Port D Data Bits 1
PORTD.PD0_AN0      0   Port D Data Bits 0
DDRA              0x0004    Port A data direction
DDRA.DDA7          7   Data Direction for Port A Bit 7
DDRA.DDA6          6   Data Direction for Port A Bit 6
DDRA.DDA5          5   Data Direction for Port A Bit 5
DDRA.DDA4          4   Data Direction for Port A Bit 4
DDRA.DDA3          3   Data Direction for Port A Bit 3
DDRA.DDA2          2   Data Direction for Port A Bit 2
DDRA.DDA1          1   Data Direction for Port A Bit 1
DDRA.DDA0          0   Data Direction for Port A Bit 0
DDRB              0x0005    Port B data direction
DDRB.DDB2          2   Data Direction for Port B Bit 2
DDRC              0x0006    Port C data direction
DDRC.DDC7          7   Data Direction for Port C Bit 7
DDRC.DDC6          6   Data Direction for Port C Bit 6
DDRC.DDC5          5   Data Direction for Port C Bit 5
DDRC.DDC4          4   Data Direction for Port C Bit 4
DDRC.DDC3          3   Data Direction for Port C Bit 3
DDRC.DDC2          2   Data Direction for Port C Bit 2
DDRC.DDC1          1   Data Direction for Port C Bit 1
DDRC.DDC0          0   Data Direction for Port C Bit 0
ECLK              0x0007    ECLK control
ECLK.ECLK          3   External clock output bit
ADDATA            0x0008  A/D data
ADSTAT            0x0009  A/D ststus/control
ADSTAT.COCO        7   Conversion complete flag 
ADSTAT.ADRC        6   A/D RC oscillator control
ADSTAT.ADON        5   A/D converter on         
ADSTAT.CH3         3   A/D channel 3            
ADSTAT.CH2         2   A/D channel 2            
ADSTAT.CH1         1   A/D channel 1            
ADSTAT.CH0         0   A/D channel 0            
PLMA              0x000A  Pulse length modulation A
PLMB              0x000B  Pulse length modulation B
Miscell           0x000C  Miscellaneous
Miscell.POR        7   Power-on reset bit                    
Miscell.INTP       6   External interrupt sensitivity options
Miscell.INTN       5   External interrupt sensitivity options
Miscell.INTE       4   External interrupt enable             
Miscell.SFA        3   Slow or fast mode selection for PLMA  
Miscell.SFB        2   Slow or fast mode selection for PLMB  
Miscell.SM         1   Slow mode                             
Miscell.WDOG       0   Watchdog enable/disable               
BAUD              0x000D   SCI baud rate
BAUD.SPC1          7   Serial prescaler select bit 1       
BAUD.SPC0          6   Serial prescaler select bit 0       
BAUD.SCT2          5   SCI rate select bits (transmitter) 2
BAUD.SCT1          4   SCI rate select bits (transmitter) 1
BAUD.SCT0          3   SCI rate select bits (transmitter) 0
BAUD.SCR2          2   SCI rate select bits (receiver) 2   
BAUD.SCR1          1   SCI rate select bits (receiver) 1   
BAUD.SCR0          0   SCI rate select bits (receiver) 0   
SCCR1             0x000E   SCI control 1
SCCR1.R8           7   Receive Data Bit 8            
SCCR1.T8           6   Transmit Data Bit 8           
SCCR1.M            4   Mode (Select Character Format)
SCCR1.WAKE         3   Wake Up by Address Mark/Idle  
SCCR1.CPOL         2
SCCR1.CPHA         1
SCCR1.LBCL         0
SCCR2             0x000F    SCI control 2
SCCR2.TIE          7   Transmit interrupt enable         
SCCR2.TCIE         6   Transmit complete interrupt enable
SCCR2.RIE          5   Receiver interrupt enable         
SCCR2.ILIE         4   Idle line interrupt enable        
SCCR2.TE           3   Transmitter enable                
SCCR2.RE           2   Receiver enable                   
SCCR2.RWU          1   Receiver wake-up                  
SCCR2.SBK          0   Send break                        
SCSR              0x0010    SCI status
SCSR.TDRE          7   Transmit data register empty flag
SCSR.TC            6   Transmit complete flag           
SCSR.RDRF          5   Receive data register full flag  
SCSR.IDLE          4   Idle line detected flag          
SCSR.OR            3   Overrun error flag               
SCSR.NF            2   Noise error flag                 
SCSR.FE            1   Framing error flag               
SCDR              0x0011    SCI data
TCR               0x0012    Timer control
TCR.ICIE           7   Input captures interrupt enable 
TCR.OCIE           6   Output compares interrupt enable
TCR.TOIE           5   Timer overflow interrupt enable 
TCR.FOLV2          4   Force output compare 2          
TCR.FOLV1          3   Force output compare 1          
TCR.OLV2           2   Output level 2                  
TCR.IEDG1          1   Input edge 1                    
TCR.OLVL1          0   Output level 1                  
TSR               0x0013    Timer ststus
TSR.ICF1           7   Input capture flag 1      
TSR.OCF1           6   Output compare flag 1     
TSR.TOF            5   Timer overflow status flag
TSR.ICF2           4   Input capture flag 2      
TSR.OCF2           3   Output compare flag 2     
ICH1              0x0014    Input capture high 1
ICL1              0x0015    Input capture low 1
OCH1              0x0016    Output compare high 1
OCL1              0x0017    Output compare low 1
TCH               0x0018    Timer counter high
TCL               0x0019    Timer counter low
ACH               0x001A    Alternate counter high
ACL               0x001B    Alternate counter low
ICH2              0x001C   Input campare high 2
ICL2              0x001D   Input capture low 2
OCH2              0x001E   Output compare high 2
OCL2              0x001F   Output compare low 2


.68HC705B5
; http://
; 6805b6r4.pdf

; RAM=176
; ROM=496
; EPROM=6K
; EEPROM=0


; MEMORY MAP
area DATA FSR           0x0000:0x0020
area DATA EPROM_P0      0x0020:0x0050
area DATA RAM           0x0050:0x0100
area DATA EPROM_P1      0x0100:0x0200
area DATA BOOT_ROM_1    0x0200:0x0300
area BSS  RESERVED      0x0300:0x0800
area DATA _EPROM_       0x0800:0x1F00
area DATA BOOT_ROM_2    0x1F00:0x1FF0
area DATA USER_VEC      0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      WOI External IRQ
interrupt TIMER_In_Cap      0x1FF8      Timer input capture 1&2
interrupt TIMER_Out_Comp    0x1FF6      Timer output capture 1&2
interrupt TIMER_Overf       0x1FF4      Timer overflow
interrupt SCI               0x1FF2      SCI


; INPUT/ OUTPUT PORTS
PORTA                 0x0000    Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001    Port B data
PORTB.PB7              7   Port B Data Bits 7
PORTB.PB6              6   Port B Data Bits 6
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002    Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2_ECLK         2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003    Port D data
PORTD.PD7              7   Port D Data Bits 7
PORTD.PD6              6   Port D Data Bits 6
PORTD.PD5              5   Port D Data Bits 5
PORTD.PD4              4   Port D Data Bits 4
PORTD.PD3              3   Port D Data Bits 3
PORTD.PD2              2   Port D Data Bits 2
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004    Port A data direction
DDRB                  0x0005    Port B data direction
DDRC                  0x0006    Port C data direction
EPROM                 0x0007    EPROM/ECLK control
EPROM.EPPT             6   EPROM protect test bit
EPROM.ELAT             5   EPROM programming latch enable bit
EPROM.EPGM             4   EPROM programming bit
EPROM.ECLK             3   External clock option bit
ADDATA                0x0008  A/D data
ADSTAT                0x0009  A/D ststus/control
ADSTAT.COCO            7   Conversion complete flag 
ADSTAT.ADRC            6   A/D RC oscillator control
ADSTAT.ADON            5   A/D converter on         
ADSTAT.CH3             3   A/D channel 3            
ADSTAT.CH2             2   A/D channel 2            
ADSTAT.CH1             1   A/D channel 1            
ADSTAT.CH0             0   A/D channel 0                        
PLMA                  0x000A  Pulse length modulation A
PLMB                  0x000B  Pulse length modulation B
Miscell               0x000C  Miscellaneous
Miscell.POR            7   Power-on reset bit                    
Miscell.INTP           6   External interrupt sensitivity options
Miscell.INTN           5   External interrupt sensitivity options
Miscell.INTE           4   External interrupt enable             
Miscell.SFA            3   Slow or fast mode selection for PLMA  
Miscell.SFB            2   Slow or fast mode selection for PLMB  
Miscell.SM             1   Slow mode                             
Miscell.WDOG           0   Watchdog enable/disable               
BAUD                  0x000D   SCI baud rate
BAUD.SPC1              7   Serial prescaler select bit 1       
BAUD.SPC0              6   Serial prescaler select bit 0       
BAUD.SCT2              5   SCI rate select bits (transmitter) 2
BAUD.SCT1              4   SCI rate select bits (transmitter) 1
BAUD.SCT0              3   SCI rate select bits (transmitter) 0
BAUD.SCR2              2   SCI rate select bits (receiver) 2   
BAUD.SCR1              1   SCI rate select bits (receiver) 1   
BAUD.SCR0              0   SCI rate select bits (receiver) 0   
SCCR1                 0x000E   SCI control 1
SCCR1.R8               7   Receive Data Bit 8            
SCCR1.T8               6   Transmit Data Bit 8           
SCCR1.M                4   Mode (Select Character Format)
SCCR1.WAKE             3   Wake Up by Address Mark/Idle  
SCCR1.CPOL             2
SCCR1.CPHA             1
SCCR1.LBCL             0
SCCR2                 0x000F    SCI control 2
SCCR2.TIE              7   Transmit interrupt enable         
SCCR2.TCIE             6   Transmit complete interrupt enable
SCCR2.RIE              5   Receiver interrupt enable         
SCCR2.ILIE             4   Idle line interrupt enable        
SCCR2.TE               3   Transmitter enable                
SCCR2.RE               2   Receiver enable                   
SCCR2.RWU              1   Receiver wake-up                  
SCCR2.SBK              0   Send break                        
SCSR                  0x0010    SCI status
SCSR.TDRE              7   Transmit data register empty flag
SCSR.TC                6   Transmit complete flag           
SCSR.RDRF              5   Receive data register full flag  
SCSR.IDLE              4   Idle line detected flag          
SCSR.OR                3   Overrun error flag               
SCSR.NF                2   Noise error flag                 
SCSR.FE                1   Framing error flag               
SCDR                  0x0011    SCI data
TCR                   0x0012    Timer control
TCR.ICIE               7   Input captures interrupt enable 
TCR.OCIE               6   Output compares interrupt enable
TCR.TOIE               5   Timer overflow interrupt enable 
TCR.FOLV2              4   Force output compare 2          
TCR.FOLV1              3   Force output compare 1          
TCR.OLV2               2   Output level 2                  
TCR.IEDG1              1   Input edge 1                    
TCR.OLVL1              0   Output level 1                  
TSR                   0x0013    Timer ststus
TSR.ICF1               7   Input capture flag 1      
TSR.OCF1               6   Output compare flag 1     
TSR.TOF                5   Timer overflow status flag
TSR.ICF2               4   Input capture flag 2      
TSR.OCF2               3   Output compare flag 2     
ICH1                  0x0014    Input capture high 1
ICL1                  0x0015    Input capture low 1
OCH1                  0x0016    Output compare high 1
OCL1                  0x0017    Output compare low 1
TCH                   0x0018    Timer counter high
TCL                   0x0019    Timer counter low
ACH                   0x001A    Alternate counter high
ACL                   0x001B    Alternate counter low
ICH2                  0x001C   Input campare high 2
ICL2                  0x001D   Input capture low 2
OCH2                  0x001E   Output compare high 2
OCL2                  0x001F   Output compare low 2
OPTR                  0x1EFE   Options
OPTR.EPP               6   EPROM protect
OPTR.RTIM              4   Reset time
OPTR.RWAT              3   Watchdog after reset
OPTR.WWAT              2   Watchdog during WAIT mode
OPTR.PBPD              1   Port B pull-down resistors
OPTR.PCPD              0   Port C pull-down resistors
RESERV1FF0            0x1FF0    RESERVED
RESERV1FF1            0x1FF1    RESERVED


.68HCL05C8A
; MC68HC05C8A/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC05C8A&nodeId=01M98633
; MC68HC05C8A.pdf

; RAM=176
; ROM=7744
; EPROM=0  
; EEPROM=0  


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area DATA ROM_P1      0x0020:0x0050
area DATA RAM         0x0050:0x0100
area DATA ROM_P2      0x0100:0x1F00
area DATA ROM_S_CH    0x1F00:0x1FF0
area DATA USER_VEC    0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET           0x1FFE      Processor reset
interrupt SWI               0x1FFC      Software interrupt
interrupt IRQ               0x1FFA      External Interrupt
interrupt TIMER             0x1FF8      Timer Interrupt
interrupt SCI               0x1FF6      Serial Communications Interrupt
interrupt SPI               0x1FF4      Serial Peripheral Interrupt


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bits 7
PORTA.PA6       6   Port A Data Bits 6
PORTA.PA5       5   Port A Data Bits 5
PORTA.PA4       4   Port A Data Bits 4
PORTA.PA3       3   Port A Data Bits 3
PORTA.PA2       2   Port A Data Bits 2
PORTA.PA1       1   Port A Data Bits 1
PORTA.PA0       0   Port A Data Bits 0
PORTB          0x0001    Port B data
PORTB.PB7       7   Port B Data Bits 7
PORTB.PB6       6   Port B Data Bits 6
PORTB.PB5       5   Port B Data Bits 5
PORTB.PB4       4   Port B Data Bits 4
PORTB.PB3       3   Port B Data Bits 3
PORTB.PB2       2   Port B Data Bits 2
PORTB.PB1       1   Port B Data Bits 1
PORTB.PB0       0   Port B Data Bits 0
PORTC          0x0002    Port C data
PORTC.PC7       7   Port C Data Bits 7
PORTC.PC6       6   Port C Data Bits 6
PORTC.PC5       5   Port C Data Bits 5
PORTC.PC4       4   Port C Data Bits 4
PORTC.PC3       3   Port C Data Bits 3
PORTC.PC2       2   Port C Data Bits 2
PORTC.PC1       1   Port C Data Bits 1
PORTC.PC0       0   Port C Data Bits 0
PORTD          0x0003    Port D data
PORTD.PD7       7   Port D Data Bits 7
PORTD.PD5       5   Port D Data Bits 5
PORTD.PD4       4   Port D Data Bits 4
PORTD.PD3       3   Port D Data Bits 3
PORTD.PD2       2   Port D Data Bits 2
PORTD.PD1       1   Port D Data Bits 1
PORTD.PD0       0   Port D Data Bits 0
DDRA           0x0004    Port A data direction
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA1      0   Data Direction for Port A Bit 0
DDRB           0x0005    Port B data direction
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRC           0x0006    Port C data direction
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC7      6   Data Direction for Port C Bit 6
DDRC.DDRC7      5   Data Direction for Port C Bit 5
DDRC.DDRC7      4   Data Direction for Port C Bit 4
DDRC.DDRC7      3   Data Direction for Port C Bit 3
DDRC.DDRC7      2   Data Direction for Port C Bit 2
DDRC.DDRC7      1   Data Direction for Port C Bit 1
DDRC.DDRC7      0   Data Direction for Port C Bit 0
UNUSED0007     0x0007    UNUSED
UNUSED0008     0x0008    UNUSED
UNUSED0009     0x0009    UNUSED
SPCR           0x000A    SPI Control
SPCR.SPIE       7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE        6   Serial Peripheral System Enable Bit
SPCR.MSTR       4   Master Mode Select Bit
SPCR.CPOL       3   Clock Polarity Bit
SPCR.CPHA       2   Clock Phase Bit
SPCR.SPR1       1   SPI Clock Rate Select Bits 1
SPCR.SPR0       0   SPI Clock Rate Select Bits 0
SPSR           0x000B    SPI Status
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Flag
SPDR           0x000C    SPI Data
SPDR.SPD7       7
SPDR.SPD6       6
SPDR.SPD5       5
SPDR.SPD4       4
SPDR.SPD3       3
SPDR.SPD2       2
SPDR.SPD1       1
SPDR.SPD0       0
BAUD           0x000D    SCI Baud Rate
BAUD.SCP1       5   SCI Prescaler Select Bits 1
BAUD.SCP0       4   SCI Prescaler Select Bits 0
BAUD.SCR2       2   SCI Baud Rate Select Bits 2
BAUD.SCR1       1   SCI Baud Rate Select Bits 1
BAUD.SCR0       0   SCI Baud Rate Select Bits 0
SCCR1          0x000E    SCI Control 1
SCCR1.R8        7   Bit 8 (Received)
SCCR1.T8        6   Bit 8 (Transmitted)
SCCR1.M         4   Character Length Bit
SCCR1.WAKE      3   Wakeup Bit
SCCR2          0x000F    SCI Control 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmission Complete Interrupt Enable Bit
SCCR2.RIE       5   Receive Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmit Enable Bit
SCCR2.RE        2   Receive Enable Bit
SCCR2.RMU       1   Receiver Wakeup Enable Bit
SCCR2.SBK       0   Send Break Bit
SCSR           0x0010    SCI Status
SCSR.TDRE       7   Transmit Data Register Empty Bit
SCSR.TC         6   Transmission Complete Bit
SCSR.RDRF       5   Receive Data Register Full Bit
SCSR.IDLE       4   Receiver Idle Bit
SCSR.OR         3   Receiver Overrun Bit
SCSR.NF         2   Receiver Noise Flag
SCSR.FE         1   Receiver Framing Error Flag
SCDAT          0x0011     SCI Data
SCDAT.SCD7      7   Serial Data Bit 7
SCDAT.SCD6      6   Serial Data Bit 6
SCDAT.SCD5      5   Serial Data Bit 5
SCDAT.SCD4      4   Serial Data Bit 4
SCDAT.SCD3      3   Serial Data Bit 3
SCDAT.SCD2      2   Serial Data Bit 2
SCDAT.SCD1      1   Serial Data Bit 1
SCDAT.SCD0      0   Serial Data Bit 0
TCR            0x0012    Timer Control
TCR.ICIE        7   Input Capture Interrupt Enable Bit
TCR.OCIE        6   Output Compare Interrupt Enable Bit
TCR.TOIE        5   Timer Overflow Interrupt Enable Bit
TCR.IEDGE       1   Input Edge Bit
TCR.OLVL1       0   Output Level Bit
TSR            0x0013    Timer Status
TSR.ICF         7   Input Capture Flag
TSR.OCF         6   Output Compare Flag
TSR.TOF         5   Timer Overflow Flag
ICH            0x0014    Input capture
ICL            0x0015    Input capture
OCH            0x0016    Output compare
OCL            0x0017    Output compare
TCNTH          0x0018    Timer counter
TCNTL          0x0019    Timer counter
ALTCNTH        0x001A    Alternate counter
ALTCNTL        0x001B    Alternate counter
UNUSED001C     0x001C    UNUSED
UNUSED001D     0x001D    UNUSED
UNUSED001E     0x001E    UNUSED
RESERV001F     0x001F    Reserved
COP            0x1FF0    COP
COP.COPR        0
UNUSED07F1     0x07F1   UNUSED
UNUSED07F2     0x07F2   UNUSED
UNUSED07F3     0x07F3   UNUSED


.68HC05BD3
; MC68HC05BD3D/H  http://
; MC68HC05BD3D.pdf

; The user RAM consists of 128 bytes of memory, from 0x0080 to 0x00FF.
; The user ROM consists of 3.75K-bytes of memory, from 0x3000 to 0x3EFF

; RAM=128
; ROM=3.75K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR			0x0000:0x0030
area BSS  UNUSED		0x0030:0x0080
area DATA RAM			0x0080:0x0100
area BSS  UNUSED		0x0100:0x3000
area DATA ROM			0x3000:0x3F00
area DATA Self_Check_Prog	0x3F00:0x3FE0
area DATA Self_Check_Vect	0x3FE0:0x3FF0
area DATA USER_VEC		0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET    0x3FFE       Reset 
interrupt SWI        0x3FFC       Software
interrupt IRQ        0x3FFA       External Interrupt
interrupt SSP        0x3FF8       VSYNC
interrupt MBUS       0x3FF6       M-Bus
interrupt MFT        0x3FF4       Timer Overflow / Real Time Interrupt


; INPUT/ OUTPUT PORTS
PORTA              0x0000     Port A data
PORTA.PA7           7   Port A Data Bits 7
PORTA.PA6           6   Port A Data Bits 6
PORTA.PA5           5   Port A Data Bits 5
PORTA.PA4           4   Port A Data Bits 4
PORTA.PA3           3   Port A Data Bits 3
PORTA.PA2           2   Port A Data Bits 2
PORTA.PA1           1   Port A Data Bits 1
PORTA.PA0           0   Port A Data Bits 0
PORTB              0x0001     Port B data
PORTB.PB5           5   Port B Data Bits 5
PORTB.PB4           4   Port B Data Bits 4
PORTB.PB3           3   Port B Data Bits 3
PORTB.PB2           2   Port B Data Bits 2
PORTB.PB1           1   Port B Data Bits 1
PORTB.PB0           0   Port B Data Bits 0
PORTC              0x0002     Port C data
PORTC.PC7           7   Port C Data Bits 7
PORTC.PC6           6   Port C Data Bits 6
PORTC.PC5           5   Port C Data Bits 5
PORTC.PC4           4   Port C Data Bits 4
PORTC.PC3           3   Port C Data Bits 3
PORTC.PC2           2   Port C Data Bits 2
PORTC.PC1           1   Port C Data Bits 1
PORTC.PC0           0   Port C Data Bits 0
PORTD              0x0003     Port D data
PORTD.PD1           1   Port D Data Bits 1
PORTD.PD0           0   Port D Data Bits 0
DDRA               0x0004     Port A data direction
DDRA.DDRA7          7   Data Direction for Port A Bit 7
DDRA.DDRA6          6   Data Direction for Port A Bit 6
DDRA.DDRA5          5   Data Direction for Port A Bit 5
DDRA.DDRA4          4   Data Direction for Port A Bit 4
DDRA.DDRA3          3   Data Direction for Port A Bit 3
DDRA.DDRA2          2   Data Direction for Port A Bit 2
DDRA.DDRA1          1   Data Direction for Port A Bit 1
DDRA.DDRA0          0   Data Direction for Port A Bit 0
DDRB               0x0005     Port B data direction
DDRB.DDRB5          5   Data Direction for Port B Bit 5
DDRB.DDRB4          4   Data Direction for Port B Bit 4
DDRB.DDRB3          3   Data Direction for Port B Bit 3
DDRB.DDRB2          2   Data Direction for Port B Bit 2
DDRB.DDRB1          1   Data Direction for Port B Bit 1
DDRB.DDRB0          0   Data Direction for Port B Bit 0
DDRC               0x0006     Port C data direction
DDRC.DDRC7          7   Data Direction for Port C Bit 7
DDRC.DDRC6          6   Data Direction for Port C Bit 6
DDRC.DDRC5          5   Data Direction for Port C Bit 5
DDRC.DDRC4          4   Data Direction for Port C Bit 4
DDRC.DDRC3          3   Data Direction for Port C Bit 3
DDRC.DDRC2          2   Data Direction for Port C Bit 2
DDRC.DDRC1          1   Data Direction for Port C Bit 1
DDRC.DDRC0          0   Data Direction for Port C Bit 0
DDRD               0x0007     Port D data direction
DDRD.DDRD1          1   Data Direction for Port D Bit 1
DDRD.DDRD0          0   Data Direction for Port D Bit 0
MFTCS              0x0008     MFT control and status
MFTCS.TOF           7   Timer Overflow
MFTCS.RTIF          6   Real Time Interrupt Flag
MFTCS.TOFIE         5   Timer Overflow Interrupt Enable
MFTCS.RTIE          4   Real Time Interrupt Enable
MFTCS.IRQN          3   IRQ Pin Trigger Option
MFTCS.RT1           1   Rate Select for COP watchdog and RTI 1
MFTCS.RT0           0   Rate Select for COP watchdog and RTI 0
MFTTC              0x0009     MFT timer counter
MFTTC.MFTCR7        7
MFTTC.MFTCR6        6
MFTTC.MFTCR5        5
MFTTC.MFTCR4        4
MFTTC.MFTCR3        3
MFTTC.MFTCR2        2
MFTTC.MFTCR1        1
MFTTC.MFTCR0        0
CONFIG1            0x000A     Configuration 1
CONFIG1.PWM15       7
CONFIG1.PWM14       6
CONFIG1.PWM13       5
CONFIG1.PWM12       4
CONFIG1.PWM11       3
CONFIG1.PWM10       2
CONFIG1.PWM9        1
CONFIG1.PWM8        0
CONFIG2            0x000B     Configuration 2
CONFIG2.HTTL        7
CONFIG2.VTTL        6
CONFIG2.SCL         1
CONFIG2.SDA         0
SSPCS              0x000C     SSP control and status
SSPCS.VPOL          7   Vertical Sync Input Polarity
SSPCS.HPOL          6   Horizontal Sync Input Polarity
SSPCS.VDET          5   Vertical Sync Signal Detect
SSPCS.HDET          4   Horizontal Sync Signal Detect
SSPCS.SOUT          3   Sync Output Select
SSPCS.INSRTB        2   Hsync Insertion Bit
SSPCS.FOUT          1   Internal Hsync Frequency Select
SSPCS.VSIN          0   Vsync Input Source
VFH                0x000D     Vertical frequency high
VFH.VF12            4
VFH.VF11            3
VFH.VF10            2
VFH.VF9             1
VFH.VF8             0
VFL                0x000E     Vertical frequency low
VFL.VF7             7
VFL.VF6             6
VFL.VF5             5
VFL.VF4             4
VFL.VF3             3
VFL.VF2             2
VFL.VF1             1
VFL.VF0             0
LFH                0x000F     Line frequency high
LFH.HOVER           7
LFH.LF11            3
LFH.LF10            2
LFH.LF9             1
LFH.LF8             0
LFL                0x0010     Line frequency low
LFL.LF7             7
LFL.LF6             6
LFL.LF5             5
LFL.LF4             4
LFL.LF3             3
LFL.LF2             2
LFL.LF1             1
LFL.LF0             0
SSC                0x0011     Sync signal control
SSC.VSIE            7   Vsync Interrupt Enable
Unused12           0x0012     Unused
Unused13           0x0013     Unused
Unused14           0x0014     Unused
Unused15           0x0015     Unused
Unused16           0x0016     Unused
MAD                0x0017     MBUS address
MAD.MAD7            7
MAD.MAD6            6
MAD.MAD5            5
MAD.MAD4            4
MAD.MAD3            3
MAD.MAD2            2
MAD.MAD1            1
MFD                0x0018     MBUS frequency divider
MFD.FD4             4
MFD.FD3             3
MFD.FD2             2
MFD.FD1             1
MFD.FD0             0
MC                 0x0019     MBUS control
MC.MEN              7   M-Bus Enable
MC.MIEN             6   M-Bus Interrupt Enable
MC.MSTA             5   Master/Slave Select
MC.MTX              4   Transmit/Receive Mode Select
MC.TXAK             3   Acknowledge Enable
MS                 0x001A     MBUS status
MS.MCF              7   Data Transfer Complete
MS.MASS             6   Addressed as Slave
MS.MBB              5   Bus Busy
MS.MAL              4   Arbitration Lost
MS.SRW              2   Slave R/W Select
MS.MIF              1   M-Bus Interrupt
MS.RXAK             0   Receive Acknowledge
MD                 0x001B     MBUS data
MD.MD7              7
MD.MD6              6
MD.MD5              5
MD.MD4              4
MD.MD3              3
MD.MD2              2
MD.MD1              1
MD.MD0              0
Unused1C           0x001C     Unused
Unused1D           0x001D     Unused
HPW                0x001E     HSYNC period width
HPW.HPWR7           7
HPW.HPWR6           6
HPW.HPWR5           5
HPW.HPWR4           4
HPW.HPWR3           3
HPW.HPWR2           2
HPW.HPWR1           1
HPW.HPWR0           0
RESERV001F         0x001F    RESERVED
0PWM               0x0020    PWM Register 0
0PWM.0PWM4          7
0PWM.0PWM3          6
0PWM.0PWM2          5
0PWM.0PWM1          4
0PWM.0PWM0          3
0PWM.0BRM2          2
0PWM.0BRM1          1
0PWM.0BRM0          0
1PWM               0x0021    PWM Register 1
1PWM.1PWM4          7
1PWM.1PWM3          6
1PWM.1PWM2          5
1PWM.1PWM1          4
1PWM.1PWM0          3
1PWM.1BRM2          2
1PWM.1BRM1          1
1PWM.1BRM0          0
2PWM               0x0022    PWM Register 2
2PWM.2PWM4          7
2PWM.2PWM3          6
2PWM.2PWM2          5
2PWM.2PWM1          4
2PWM.2PWM0          3
2PWM.2BRM2          2
2PWM.2BRM1          1
2PWM.2BRM0          0
3PWM               0x0023    PWM Register 3
3PWM.3PWM4          7
3PWM.3PWM3          6
3PWM.3PWM2          5
3PWM.3PWM1          4
3PWM.3PWM0          3
3PWM.3BRM2          2
3PWM.3BRM1          1
3PWM.3BRM0          0
4PWM               0x0024    PWM Register 4
4PWM.4PWM4          7
4PWM.4PWM3          6
4PWM.4PWM2          5
4PWM.4PWM1          4
4PWM.4PWM0          3
4PWM.4BRM2          2
4PWM.4BRM1          1
4PWM.4BRM0          0
5PWM               0x0025    PWM Register 5
5PWM.5PWM4          7
5PWM.5PWM3          6
5PWM.5PWM2          5
5PWM.5PWM1          4
5PWM.5PWM0          3
5PWM.5BRM2          2
5PWM.5BRM1          1
5PWM.5BRM0          0
6PWM               0x0026    PWM Register 6
6PWM.6PWM4          7
6PWM.6PWM3          6
6PWM.6PWM2          5
6PWM.6PWM1          4
6PWM.6PWM0          3
6PWM.6BRM2          2
6PWM.6BRM1          1
6PWM.6BRM0          0
7PWM               0x0027    PWM Register 7
7PWM.7PWM4          7
7PWM.7PWM3          6
7PWM.7PWM2          5
7PWM.7PWM1          4
7PWM.7PWM0          3
7PWM.7BRM2          2
7PWM.7BRM1          1
7PWM.7BRM0          0
8PWM               0x0028    PWM Register 8
8PWM.8PWM4          7
8PWM.8PWM3          6
8PWM.8PWM2          5
8PWM.8PWM1          4
8PWM.8PWM0          3
8PWM.8BRM2          2
8PWM.8BRM1          1
8PWM.8BRM0          0
9PWM               0x0029    PWM Register 9
9PWM.9PWM4          7
9PWM.9PWM3          6
9PWM.9PWM2          5
9PWM.9PWM1          4
9PWM.9PWM0          3
9PWM.9BRM2          2
9PWM.9BRM1          1
9PWM.9BRM0          0
10PWM              0x002A    PWM Register 10
10PWM.10PWM4        7
10PWM.10PWM3        6
10PWM.10PWM2        5
10PWM.10PWM1        4
10PWM.10PWM0        3
10PWM.10BRM2        2
10PWM.10BRM1        1
10PWM.10BRM0        0
11PWM              0x002B    PWM Register 11
11PWM.11PWM4        7
11PWM.11PWM3        6
11PWM.11PWM2        5
11PWM.11PWM1        4
11PWM.11PWM0        3
11PWM.11BRM2        2
11PWM.11BRM1        1
11PWM.11BRM0        0
12PWM              0x002C    PWM Register 12
12PWM.12PWM4        7
12PWM.12PWM3        6
12PWM.12PWM2        5
12PWM.12PWM1        4
12PWM.12PWM0        3
12PWM.12BRM2        2
12PWM.12BRM1        1
12PWM.12BRM0        0
13PWM              0x002D    PWM Register 13
13PWM.13PWM4        7
13PWM.13PWM3        6
13PWM.13PWM2        5
13PWM.13PWM1        4
13PWM.13PWM0        3
13PWM.13BRM2        2
13PWM.13BRM1        1
13PWM.13BRM0        0
14PWM              0x002E    PWM Register 14
14PWM.14PWM4        7
14PWM.14PWM3        6
14PWM.14PWM2        5
14PWM.14PWM1        4
14PWM.14PWM0        3
14PWM.14BRM2        2
14PWM.14BRM1        1
14PWM.14BRM0        0
15PWM              0x002F    PWM Register 15
15PWM.15PWM4        7
15PWM.15PWM3        6
15PWM.15PWM2        5
15PWM.15PWM1        4
15PWM.15PWM0        3
15PWM.15BRM2        2
15PWM.15BRM1        1
15PWM.15BRM0        0
RESERV3FF0         0x3FF0    RESERVED
RESERV3FF1         0x3FF1    RESERVED
RESERV3FF2         0x3FF2    RESERVED
RESERV3FF3         0x3FF3    RESERVED


.68HC705BD3
; MC68HC05BD3D/H  http://
; MC68HC05BD3D.pdf

; RAM=256
; ROM=0
; EPROM=7.75K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0030
area BSS  UNUSED      0x0030:0x0080
area DATA RAM         0x0080:0x0180
area BSS  UNUSED      0x0180:0x1E00
area DATA BootROM     0x1E00:0x1FE0
area BSS  UNUSED      0x1FE0:0x2000
area DATA EPROM       0x2000:0x3F00
area BSS  UNUSED      0x3F00:0x3FE0
area DATA BOOT_VEC    0x3FE0:0x3FF0
area DATA USER_VEC    0x3FF0:0x4000


; Interrupt and reset vector assignments
interrupt __RESET           0x3FFE      Processor reset
interrupt SWI               0x3FFC      Software interrupt
interrupt IRQ               0x3FFA      ...
interrupt SSP               0x3FF8
interrupt M_BUS             0x3FF6
interrupt MFT               0x3FF4


; INPUT/ OUTPUT PORTS
PORTA                 0x0000     Port A data
PORTA.PA7              7   Port A Data Bits 7
PORTA.PA6              6   Port A Data Bits 6
PORTA.PA5              5   Port A Data Bits 5
PORTA.PA4              4   Port A Data Bits 4
PORTA.PA3              3   Port A Data Bits 3
PORTA.PA2              2   Port A Data Bits 2
PORTA.PA1              1   Port A Data Bits 1
PORTA.PA0              0   Port A Data Bits 0
PORTB                 0x0001     Port B data
PORTB.PB5              5   Port B Data Bits 5
PORTB.PB4              4   Port B Data Bits 4
PORTB.PB3              3   Port B Data Bits 3
PORTB.PB2              2   Port B Data Bits 2
PORTB.PB1              1   Port B Data Bits 1
PORTB.PB0              0   Port B Data Bits 0
PORTC                 0x0002     Port C data
PORTC.PC7              7   Port C Data Bits 7
PORTC.PC6              6   Port C Data Bits 6
PORTC.PC5              5   Port C Data Bits 5
PORTC.PC4              4   Port C Data Bits 4
PORTC.PC3              3   Port C Data Bits 3
PORTC.PC2              2   Port C Data Bits 2
PORTC.PC1              1   Port C Data Bits 1
PORTC.PC0              0   Port C Data Bits 0
PORTD                 0x0003     Port D data
PORTD.PD1              1   Port D Data Bits 1
PORTD.PD0              0   Port D Data Bits 0
DDRA                  0x0004     Port A data direction
DDRA.DDRA7             7   Data Direction for Port A Bit 7
DDRA.DDRA6             6   Data Direction for Port A Bit 6
DDRA.DDRA5             5   Data Direction for Port A Bit 5
DDRA.DDRA4             4   Data Direction for Port A Bit 4
DDRA.DDRA3             3   Data Direction for Port A Bit 3
DDRA.DDRA2             2   Data Direction for Port A Bit 2
DDRA.DDRA1             1   Data Direction for Port A Bit 1
DDRA.DDRA0             0   Data Direction for Port A Bit 0
DDRB                  0x0005     Port B data direction
DDRB.DDRB5             5   Data Direction for Port B Bit 5
DDRB.DDRB4             4   Data Direction for Port B Bit 4
DDRB.DDRB3             3   Data Direction for Port B Bit 3
DDRB.DDRB2             2   Data Direction for Port B Bit 2
DDRB.DDRB1             1   Data Direction for Port B Bit 1
DDRB.DDRB0             0   Data Direction for Port B Bit 0
DDRC                  0x0006     Port C data direction
DDRC.DDRC7             7   Data Direction for Port C Bit 7
DDRC.DDRC6             6   Data Direction for Port C Bit 6
DDRC.DDRC5             5   Data Direction for Port C Bit 5
DDRC.DDRC4             4   Data Direction for Port C Bit 4
DDRC.DDRC3             3   Data Direction for Port C Bit 3
DDRC.DDRC2             2   Data Direction for Port C Bit 2
DDRC.DDRC1             1   Data Direction for Port C Bit 1
DDRC.DDRC0             0   Data Direction for Port C Bit 0
DDRD                  0x0007     Port D data direction
DDRD.DDRD1             1   Data Direction for Port D Bit 1
DDRD.DDRD0             0   Data Direction for Port D Bit 0
MFTCS                 0x0008     MFT control and status
MFTCS.TOF              7   Timer Overflow
MFTCS.RTIF             6   Real Time Interrupt Flag
MFTCS.TOFIE            5   Timer Overflow Interrupt Enable       
MFTCS.RTIE             4   Real Time Interrupt Enable            
MFTCS.IRQN             3   IRQ Pin Trigger Option                
MFTCS.RT1              1   Rate Select for COP watchdog and RTI 1
MFTCS.RT0              0   Rate Select for COP watchdog and RTI 0
MFTTC                 0x0009     MFT timer counter
MFTTC.MFTCR7           7
MFTTC.MFTCR6           6
MFTTC.MFTCR5           5
MFTTC.MFTCR4           4
MFTTC.MFTCR3           3
MFTTC.MFTCR2           2
MFTTC.MFTCR1           1
MFTTC.MFTCR0           0
CONFIG1               0x000A     Configuration 1
CONFIG1.PWM15          7
CONFIG1.PWM14          6
CONFIG1.PWM13          5
CONFIG1.PWM12          4
CONFIG1.PWM11          3
CONFIG1.PWM10          2
CONFIG1.PWM9           1
CONFIG1.PWM8           0
CONFIG2               0x000B     Configuration 2
CONFIG2.HTTL           7
CONFIG2.VTTL           6
CONFIG2.SCL            1
CONFIG2.SDA            0
SSPCS                 0x000C     SSP control and status
SSPCS.VPOL             7   Vertical Sync Input Polarity
SSPCS.HPOL             6   Horizontal Sync Input Polarity
SSPCS.VDET             5   Vertical Sync Signal Detect
SSPCS.HDET             4   Horizontal Sync Signal Detect
SSPCS.SOUT             3   Sync Output Select
SSPCS.INSRTB           2   Hsync Insertion Bit
SSPCS.FOUT             1   Internal Hsync Frequency Select
SSPCS.VSIN             0   Vsync Input Source
VFH                   0x000D     Vertical frequency high
VFH.VF12               4
VFH.VF11               3
VFH.VF10               2
VFH.VF9                1
VFH.VF8                0
VFL                   0x000E     Vertical frequency low
VFL.VF7                7
VFL.VF6                6
VFL.VF5                5
VFL.VF4                4
VFL.VF3                3
VFL.VF2                2
VFL.VF1                1
VFL.VF0                0
LFH                   0x000F     Line frequency high
LFH.HOVER              7
LFH.LF11               3
LFH.LF10               2
LFH.LF9                1
LFH.LF8                0
LFL                   0x0010     Line frequency low
LFL.LF7                7
LFL.LF6                6
LFL.LF5                5
LFL.LF4                4
LFL.LF3                3
LFL.LF2                2
LFL.LF1                1
LFL.LF0                0
SSC                   0x0011     Sync signal control
SSC.VSIE               7   Vsync Input Source
Unused12              0x0012     Unused
Unused13              0x0013     Unused
Unused14              0x0014     Unused
Unused15              0x0015     Unused
Unused16              0x0016     Unused
MAD                   0x0017     MBUS address
MAD.MAD7               7
MAD.MAD6               6
MAD.MAD5               5
MAD.MAD4               4
MAD.MAD3               3
MAD.MAD2               2
MAD.MAD1               1
MFD                   0x0018     MBUS frequency divider
MFD.FD4                4
MFD.FD3                3
MFD.FD2                2
MFD.FD1                1
MFD.FD0                0
MC                    0x0019     MBUS control
MC.MEN                 7   M-Bus Enable
MC.MIEN                6   M-Bus Interrupt Enable
MC.MSTA                5   Master/Slave Select
MC.MTX                 4   Transmit/Receive Mode Select
MC.TXAK                3   Acknowledge Enable
MS                    0x001A     MBUS status
MS.MCF                 7   Data Transfer Complete
MS.MASS                6   Addressed as Slave
MS.MBB                 5   Bus Busy
MS.MAL                 4   Arbitration Lost
MS.SRW                 2   Slave R/W Select
MS.MIF                 1   M-Bus Interrupt
MS.RXAK                0   Receive Acknowledge
MD                    0x001B     MBUS data
MD.MD7                 7
MD.MD6                 6
MD.MD5                 5
MD.MD4                 4
MD.MD3                 3
MD.MD2                 2
MD.MD1                 1
MD.MD0                 0
Unused1C              0x001C     Unused
PCNR                  0x001D     Programming Control (MC68HC705BD3)
PCNR.ELAT              1
PCNR.PGM               0
HPW                   0x001E     HSYNC period width
HPW.HPWR7              7
HPW.HPWR6              6
HPW.HPWR5              5
HPW.HPWR4              4
HPW.HPWR3              3
HPW.HPWR2              2
HPW.HPWR1              1
HPW.HPWR0              0
RESERV001F            0x001F    RESERVED
0PWM                  0x0020 
0PWM.0PWM4             7
0PWM.0PWM3             6
0PWM.0PWM2             5
0PWM.0PWM1             4
0PWM.0PWM0             3
0PWM.0BRM2             2
0PWM.0BRM1             1
0PWM.0BRM0             0
1PWM                  0x0021 
1PWM.1PWM4             7
1PWM.1PWM3             6
1PWM.1PWM2             5
1PWM.1PWM1             4
1PWM.1PWM0             3
1PWM.1BRM2             2
1PWM.1BRM1             1
1PWM.1BRM0             0
2PWM                  0x0022 
2PWM.2PWM4             7
2PWM.2PWM3             6
2PWM.2PWM2             5
2PWM.2PWM1             4
2PWM.2PWM0             3
2PWM.2BRM2             2
2PWM.2BRM1             1
2PWM.2BRM0             0
3PWM                  0x0023 
3PWM.3PWM4             7
3PWM.3PWM3             6
3PWM.3PWM2             5
3PWM.3PWM1             4
3PWM.3PWM0             3
3PWM.3BRM2             2
3PWM.3BRM1             1
3PWM.3BRM0             0
4PWM                  0x0024 
4PWM.4PWM4             7
4PWM.4PWM3             6
4PWM.4PWM2             5
4PWM.4PWM1             4
4PWM.4PWM0             3
4PWM.4BRM2             2
4PWM.4BRM1             1
4PWM.4BRM0             0
5PWM                  0x0025 
5PWM.5PWM4             7
5PWM.5PWM3             6
5PWM.5PWM2             5
5PWM.5PWM1             4
5PWM.5PWM0             3
5PWM.5BRM2             2
5PWM.5BRM1             1
5PWM.5BRM0             0
6PWM                  0x0026 
6PWM.6PWM4             7
6PWM.6PWM3             6
6PWM.6PWM2             5
6PWM.6PWM1             4
6PWM.6PWM0             3
6PWM.6BRM2             2
6PWM.6BRM1             1
6PWM.6BRM0             0
7PWM                  0x0027 
7PWM.7PWM4             7
7PWM.7PWM3             6
7PWM.7PWM2             5
7PWM.7PWM1             4
7PWM.7PWM0             3
7PWM.7BRM2             2
7PWM.7BRM1             1
7PWM.7BRM0             0
8PWM                  0x0028 
8PWM.8PWM4             7
8PWM.8PWM3             6
8PWM.8PWM2             5
8PWM.8PWM1             4
8PWM.8PWM0             3
8PWM.8BRM2             2
8PWM.8BRM1             1
8PWM.8BRM0             0
9PWM                  0x0029 
9PWM.9PWM4             7
9PWM.9PWM3             6
9PWM.9PWM2             5
9PWM.9PWM1             4
9PWM.9PWM0             3
9PWM.9BRM2             2
9PWM.9BRM1             1
9PWM.9BRM0             0
10PWM                 0x002A 
10PWM.10PWM4           7
10PWM.10PWM3           6
10PWM.10PWM2           5
10PWM.10PWM1           4
10PWM.10PWM0           3
10PWM.10BRM2           2
10PWM.10BRM1           1
10PWM.10BRM0           0
11PWM                 0x002B 
11PWM.11PWM4           7
11PWM.11PWM3           6
11PWM.11PWM2           5
11PWM.11PWM1           4
11PWM.11PWM0           3
11PWM.11BRM2           2
11PWM.11BRM1           1
11PWM.11BRM0           0
12PWM                 0x002C 
12PWM.12PWM4           7
12PWM.12PWM3           6
12PWM.12PWM2           5
12PWM.12PWM1           4
12PWM.12PWM0           3
12PWM.12BRM2           2
12PWM.12BRM1           1
12PWM.12BRM0           0
13PWM                 0x002D 
13PWM.13PWM4           7
13PWM.13PWM3           6
13PWM.13PWM2           5
13PWM.13PWM1           4
13PWM.13PWM0           3
13PWM.13BRM2           2
13PWM.13BRM1           1
13PWM.13BRM0           0
14PWM                 0x002E 
14PWM.14PWM4           7
14PWM.14PWM3           6
14PWM.14PWM2           5
14PWM.14PWM1           4
14PWM.14PWM0           3
14PWM.14BRM2           2
14PWM.14BRM1           1
14PWM.14BRM0           0
15PWM                 0x002F 
15PWM.15PWM4           7
15PWM.15PWM3           6
15PWM.15PWM2           5
15PWM.15PWM1           4
15PWM.15PWM0           3
15PWM.15BRM2           2
15PWM.15BRM1           1
15PWM.15BRM0           0
RESERV3FF0            0x3FF0    RESERVED
RESERV3FF1            0x3FF1    RESERVED
RESERV3FF2            0x3FF2    RESERVED
RESERV3FF3            0x3FF3    RESERVED


.68HC705G4
; HC05G3GRS/D  http://
; HC05G3GRS.pdf

; RAM=1K
; ROM=0
; EPROM=32K
; EEPROM=0


; MEMORY MAP
area DATA FSR          0x0000:0x0040
area DATA RAM          0x0040:0x0440
area BSS  UNUSED       0x0440:0x1000
area DATA EEPROM       0x1000:0x9000
area BSS  UNUSED       0x9000:0xFE00
area DATA BootROM      0xFE00:0xFFE0
area DATA TEST_VEC     0xFFE0:0xFFF0
area DATA USER_VEC     0xFFF0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Reset  
interrupt SWI               0xFFFC      SWI               
interrupt IRQ               0xFFFA      IRQ       
interrupt KWI               0xFFF8      KWI        
interrupt TIMER_1           0xFFF6      Timer1 
interrupt TIMER_2           0xFFF4      Timer2
interrupt SPI               0xFFF2      SPI
interrupt TBI               0xFFF0      TBI


; INPUT/ OUTPUT PORTS
PORTA         0x0000   PORT A DATA
PORTA.PA7       7  Port A Data Bits 7
PORTA.PA6       6  Port A Data Bits 6
PORTA.PA5       5  Port A Data Bits 5
PORTA.PA4       4  Port A Data Bits 4
PORTA.PA3       3  Port A Data Bits 3
PORTA.PA2       2  Port A Data Bits 2
PORTA.PA1       1  Port A Data Bits 1
PORTA.PA0       0  Port A Data Bits 0
PORTB         0x0001   PORT B DATA
PORTB.PB7       7  Port B Data Bits 7
PORTB.PB6       6  Port B Data Bits 6
PORTB.PB5       5  Port B Data Bits 5
PORTB.PB4       4  Port B Data Bits 4
PORTB.PB3       3  Port B Data Bits 3
PORTB.PB2       2  Port B Data Bits 2
PORTB.PB1       1  Port B Data Bits 1
PORTB.PB0       0  Port B Data Bits 0
PORTC         0x0002   PORT C DATA
PORTC.PC7       7  Port C Data Bits 7
PORTC.PC6       6  Port C Data Bits 6
PORTC.PC5       5  Port C Data Bits 5
PORTC.PC4       4  Port C Data Bits 4
PORTC.PC3       3  Port C Data Bits 3
PORTC.PC2       2  Port C Data Bits 2
PORTC.PC1       1  Port C Data Bits 1
PORTC.PC0       0  Port C Data Bits 0
PORTD         0x0003   PORT D DATA
PORTD.PD7       7  Port D Data Bits 7
PORTD.PD6       6  Port D Data Bits 6
PORTD.PD5       5  Port D Data Bits 5
PORTD.PD4       4  Port D Data Bits 4
PORTD.PD3       3  Port D Data Bits 3
PORTD.PD2       2  Port D Data Bits 2
PORTD.PD1       1  Port D Data Bits 1
PORTD.PD0       0  Port D Data Bits 0
PORTE         0x0004   PORT E DATA
PORTE.PE7       7  Port E Data Bits 7
PORTE.PE6       6  Port E Data Bits 6
PORTE.PE5       5  Port E Data Bits 5
PORTE.PE4       4  Port E Data Bits 4
PORTE.PE3       3  Port E Data Bits 3
PORTE.PE2       2  Port E Data Bits 2
PORTE.PE1       1  Port E Data Bits 1
PORTE.PE0       0  Port E Data Bits 0
PORTF         0x0005   PORT F DATA
PORTF.PF7       7  Port H Data Bits 7
PORTF.PF6       6  Port H Data Bits 6
PORTF.PF5       5  Port H Data Bits 5
PORTF.PF4       4  Port H Data Bits 4
PORTF.PF3       3  Port H Data Bits 3
PORTF.PF2       2  Port H Data Bits 2
PORTF.PF1       1  Port H Data Bits 1
PORTF.PF0       0  Port H Data Bits 0
PORTG         0x0006   PORT G DATA
PORTG.PG7       7  Port G Data Bits 7
PORTG.PG6       6  Port G Data Bits 6
PORTG.PG5       5  Port G Data Bits 5
PORTG.PG4       4  Port G Data Bits 4
PORTG.PG3       3  Port G Data Bits 3
PORTG.PG2       2  Port G Data Bits 2
PORTG.PG1       1  Port G Data Bits 1
PORTG.PG0       0  Port G Data Bits 0
PORTH         0x0007   PORT H DATA
PORTH.PH7       7  Port H Data Bits 7
PORTH.PH6       6  Port H Data Bits 6
PORTH.PH5       5  Port H Data Bits 5
PORTH.PH4       4  Port H Data Bits 4
PORTH.PH3       3  Port H Data Bits 3
PORTH.PH2       2  Port H Data Bits 2
PORTH.PH1       1  Port H Data Bits 1
PORTH.PH0       0  Port H Data Bits 0
INTCR         0x0008   INTERRUPT CONTROL
INTCR.IRQ1E     7  IRQ1 Interrupt Enable
INTCR.IRQ2E     6  IRQ2 Interrupt Enable
INTCR.KWIE      4  Key Wakeup Interrupt (KWI) Enable
INTCR.IRQ1S     3  IRQ1 Select Edge-Sensitive Only
INTCR.IRQ2S     2  IRQ2 Select Edge Sensitive Only
INTSR         0x0009   INTERRUPT STATUS
INTSR.IRQ1F     7  IRQ1 Interrupt Flag
INTSR.IRQ2F     6  IRQ2 Interrupt Flag
INTSR.KWIF      4  Key Wakeup Interrupt Flag
INTSR.RIRQ1     3  Reset IRQ1 Flag
INTSR.RIRQ2     2  Reset IRQ2 Flag
INTSR.RKWIF     0  Reset KWI Flag
SPCR1         0x000A   SPI1 CONTROL
SPCR1.SPIE1     7  SPI Interrupt Enable
SPCR1.SPE1      6  SPI Enable
SPCR1.DORD1     5  Data transmission ORDer
SPCR1.MSTR1     4  MaSTeR mode select
SPCR1.SPR1      0  SPI 1 clock rate select
SPSR1         0x000B   SPI1 STATUS
SPSR1.SPIF1     7  Serial transfer complete flag
SPSR1.DCOL1     6  Data COLlision
SPDR1         0x000C   SPI1 DATA
SPCR2         0x000D   SPI2 CONTROL
SPCR2.SPIE2     7  SPI Interrupt Enable   
SPCR2.SPE2      6  SPI Enable             
SPCR2.DORD2     5  Data transmission ORDer
SPCR2.MSTR2     4  MaSTeR mode select     
SPCR2.SPR2      0  SPI 2 clock rate select
SPSR2         0x000E   SPI2 STATUS
SPSR2.SPIF2     7  Serial transfer complete flag
SPSR2.DCOL2     6  Data COLlision
SPDR2         0x000F   SPI2 DATA
TBCR1         0x0010   TIME BASE CONTROL REGISTER 1
TBCR1.TBCLK     7  Time Base Clock
TBCR1.T3R1      3  Prescale Rate or Clock select bits for PWM 1
TBCR1.T3R0      2  Prescale Rate or Clock select bits for PWM 0
TBCR1.T2R1      1  Preschool Rate Select bits for Timer 2 1
TBCR1.T2R0      0  Preschool Rate Select bits for Timer 2 0
TBCR2         0x0011   TIME BASE CONTROL REGISTER 2
TBCR2.TBIF      7  Time Base Interrupt Flag
TBCR2.TBIE      6  Time Base Interrupt Enable
TBCR2.TBR1      5  Time Base Interrupt Rate Select 1
TBCR2.TBR0      4  Time Base Interrupt Rate Select 0
TBCR2.RTBIF     3  Reset TB Interrupt Flag
TBCR2.COPE      1  COP Enable
TBCR2.COPC      0  COP Clear
TCR           0x0012   TIMER CONTROL
TCR.ICIE        7  Input Capture Interrupt Enable
TCR.OC1IE       6  Output Compare 1 Interrupt Enable
TCR.TOIE        5  Timer Overflow Interrupt Enable
TCR.IEDG        1  Input Edge
TCR.OLVL        0  Output Level
TSR           0x0013   TIMER STATUS
TSR.ICF         7  Input Capture Flag
TSR.OC1F        6  Output Compare 1 Flag
TSR.TOF         5  Timer Overflow Flag
ICH           0x0014   OUTPUT COMPARE REG0 (H)
ICL           0x0015   OUTPUT COMPARE REG0 (L)
OC1H          0x0016   OUTPUT COMPARE REG1 (H)
OC1L          0x0017   OUTPUT COMPARE REG1 (L)
TCNTH         0x0018   TIMER COUNTER (H)
TCNTL         0x0019   TIMER COUNTER (L)
ACNTH         0x001A   ALTERNATE COUNTER (H)
ACNTL         0x001B   ALTERNATE COUNTER (L)
TCR2          0x001C   TIMER CONTROL REG2
TCR2.TI2IE      7  Timer Input 2 Interrupt Enable
TCR2.OC2IE      6  Compare 2 Interrupt Enable
TCR2.T2CLK      4  Timer 2 Clock Select
TCR2.IM2        3  Timer Input 2 Mode Select
TCR2.IL2        2  Timer Input 2 active edge (Level) select
TCR2.OE2        1  Timer Output 2 (EVO) Output Enable
TCR2.OL2        0  Timer Output 2 Edge select for synchronization
TSR2          0x001D  TIMER STATUS REG2
TSR2.TI2F       7  Timer Input 2 (EVI) Interrupt Flag
TSR2.OC2F       6  Compare 2 Interrupt Flag
TSR2.RTI2F      3  Reset Timer Input 2 Flag
TSR2.ROC2F      2  Reset Output Compare 2 Flag
OC2           0x001E  OUTPUT COMPARE REG2
TCNT2         0x001F  TIMER COUNTER 2
Reserv0020    0x0020  RESERVED
Reserv0021    0x0021  RESERVED
Reserv0022    0x0022  RESERVED
Reserv0023    0x0023  RESERVED
Reserv0024    0x0024  RESERVED
Reserv0025    0x0025  RESERVED
Reserv0026    0x0026  RESERVED
Reserv0027    0x0027  RESERVED
Reserv0028    0x0028  RESERVED
Reserv0029    0x0029  RESERVED
Reserv002A    0x002A  RESERVED
Reserv002B    0x002B  RESERVED
Reserv002C    0x002C  RESERVED
Reserv002D    0x002D  RESERVED
Reserv002E    0x002E  RESERVED
Reserv002F    0x002F  RESERVED
Reserv0030    0x0030  RESERVED
Reserv0031    0x0031  RESERVED
Reserv0032    0x0032  RESERVED
Reserv0033    0x0033  RESERVED
PWMCR         0x0034  PWM OUT CONTROL
PWMCR.CH3       3
PWMCR.CH2       2
PWMCR.CH1       1
PWMCR.CH0       0
PWMCNT        0x0035  PWM COUNTER
PWMDR0        0x0036  PWM CHANNEL 0
PWMDR1        0x0037  PWM CHANNEL 1
PWMDR2        0x0038  PWM CHANNEL 2
PWMDR3        0x0039  PWM CHANNEL 3
ADR           0x003A  A/D DATA REG
ADSCR         0x003B  A/D STATUS/CONTROL REG
ADSCR.COCO      7  CONVERSIONS COMPLETE
ADSCR.ADRC      6  RC OSCILLATOR ON
ADSCR.ADON      5  A/D ON
ADSCR.CH3       3  CHANNEL SELECT BITS 3
ADSCR.CH2       2  CHANNEL SELECT BITS 2
ADSCR.CH1       1  CHANNEL SELECT BITS 1
ADSCR.CH0       0  CHANNEL SELECT BITS 0
PORTJ         0x003C  PORT J DATA
PORTJ.PJ3       3  Port J Data Bits 3
PORTJ.PJ2       2  Port J Data Bits 2
PORTJ.PJ1       1  Port J Data Bits 1
PORTJ.PJ0       0  Port J Data Bits 0
PCR           0x003D   PROGRAM CONTROL REG
PCR.ELAT        1  EPROM LATch control
PCR.PGM         0  EPROM Program Command
MISC          0x003E  MISCELLANEOUS REGISTER
MISC.FTUP       7  OSC Time Up Flag
MISC.STUP       6  XOSC Time Up Flag
MISC.SYS1       3  System Clock Select 1
MISC.SYS0       2  System Clock Select 0
MISC.FOSCE      1  Fast (Main) Oscillator Enable
MISC.OPTM       0  Option Map Select
Reserv003F    0x003F  RESERVED


.68HC705SJ7
; MC68HC705JJ7/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705JJ7&nodeId=01M98633
; MC68HC705JJ7.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA RAM		0x0020:0x0200
area DATA EPROM		0x0700:0x1FF0
area DATA USER_VEC	0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET 	0x1FFE       Reset Vector
interrupt SWI 		0x1FFC       SWI Vector
interrupt IRQ		0x1FFA       External IRQ Vector
interrupt CTIMER	0x1FF8       Core Timer Interrupt Vector
interrupt TIMER 	0x1FF6       Timer Interrupt Vector
interrupt SPIF 		0x1FF4       Serial Interrupt Vector
interrupt ANALOG	0x1FF2       Analog Interrupt Vector


; INPUT/ OUTPUT PORTS
PORTA           0x0000   Port A Data Register
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB           0x0001   Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
RESERV0002      0x0002   RESERVED
AMUX            0x0003   Analog Multiplex Register
AMUX.HOLD         7
AMUX.DHOLD        6
AMUX.INV          5
AMUX.VREF         4
AMUX.MUX4         3
AMUX.MUX3         2
AMUX.MUX2         1
AMUX.MUX1         0
DDRA            0x0004   Data Direction Register A
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB            0x0005   Data Direction Register B
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
RESERV0006      0x0006   RESERVED
UNUSED0007      0x0007   UNUSED
CTSCR           0x0008   Core Timer Status and Control Register
CTSCR.CTOF        7  Core Timer Overflow Flag
CTSCR.RTIF        6  Real-Time Interrupt Flag
CTSCR.CTOFE       5  Core Timer Overflow Interrupt Enable Bit
CTSCR.RTIE        4  Real-Time Interrupt Enable Bit
CTSCR.CTOFR       3  Core Timer Overflow Flag Reset Bit
CTSCR.RTIFR       2  Real-Time Interrupt Flag Reset Bit
CTSCR.RT1         1  Real-Time Interrupt Select Bits 1
CTSCR.RT0         0  Real-Time Interrupt Select Bits 0
CTCR            0x0009   Core Timer Counter Register
SCR             0x000A   SIOP Control Register
SCR.SPIE          7  Serial Peripheral Interrupt Enable Bit
SCR.SPE           6  Serial Peripheral Enable Bit
SCR.LSBF          5  Least Significant Bit First Bit
SCR.MSTR          4  Master Mode Select Bit
SCR.SPIR          3  Serial Peripheral Interrupt Reset Bit
SCR.CPHA          2  Clock Phase Bit
SCR.SPR1          1  Serial Peripheral Clock Rate Select Bits 1
SCR.SPR0          0  Serial Peripheral Clock Rate Select Bits 0
SSR             0x000B   SIOP Status Register
SSR.SPIF         7   Serial Port Interrupt Flag
SSR.DCOL         6   Data Collision Bit
SDR             0x000C   SIOP Data Register
ISCR            0x000D   IRQ Status and Control Register
ISCR.IRQE         7  External Interrupt Request Enable Bit
ISCR.OM2          6  Oscillator Select Bits 2
ISCR.OM1          5  Oscillator Select Bits 1
ISCR.IRQF         3  External Interrupt Request Flag
ISCR.IRQR         1  Interrupt Request Reset Bit
PEBSR           0x000E   PEPROM Bit Select Register
PEBSR.PEB7        7  Not connected to the PEPROM array 7
PEBSR.PEB6        6  Not connected to the PEPROM array 6
PEBSR.PEB5        5  PEPROM Bit Selects 5
PEBSR.PEB4        4  PEPROM Bit Selects 4
PEBSR.PEB3        3  PEPROM Bit Selects 3
PEBSR.PEB2        2  PEPROM Bit Selects 2
PEBSR.PEB1        1  PEPROM Bit Selects 1
PEBSR.PEB0        0  PEPROM Bit Selects 0
PESCR           0x000F   PEPROM Status and Control Register
PESCR.PEDATA      7  PEPROM Data Bit
PESCR.PEPGM       5  PEPROM Program Control Bit
PESCR.PEPRZF      0  PEPROM Row Zero Flag
PDRA            0x0010   Pulldown Register Port A
PDRA.PDIA5        5  Port A Pulldown Inhibit Bit 5
PDRA.PDIA4        4  Port A Pulldown Inhibit Bit 4
PDRA.PDIA3        3  Port A Pulldown Inhibit Bit 3
PDRA.PDIA2        2  Port A Pulldown Inhibit Bit 2
PDRA.PDIA1        1  Port A Pulldown Inhibit Bit 1
PDRA.PDIA0        0  Port A Pulldown Inhibit Bit 0
PDRB            0x0011   Pulldown Register B
PDRB.PDIB7        7  Port B Pulldown Inhibit Bit 7
PDRB.PDIB6        6  Port B Pulldown Inhibit Bit 6
PDRB.PDIB5        5  Port B Pulldown Inhibit Bit 5
PDRB.PDIB4        4  Port B Pulldown Inhibit Bit 4
PDRB.PDIB3        3  Port B Pulldown Inhibit Bit 3
PDRB.PDIB2        2  Port B Pulldown Inhibit Bit 2
PDRB.PDIB1        1  Port B Pulldown Inhibit Bit 1
PDRB.PDIB0        0  Port B Pulldown Inhibit Bit 0
TCR             0x0012   Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable
TCR.IEDG          1  Input Capture Edge Select
TCR.OLVL          0  Output Compare Output Level Select
TSR             0x0013   Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Flag
TSR.TOF           5  Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TMRH            0x0018   Programmable Timer Register High
TMRL            0x0019   Programmable Timer Register Low
ACRH            0x001A   Alternate Counter Register High
ACRL            0x001B   Alternate Counter Register Low
EPROG           0x001C   EPROM Programming Register
EPROG.ELAT        2  EPROM Bus Latch Bit
EPROG.MPGM        1  Mask Option Register (MOR) Programming Bit
EPROG.EPGM        0  EPROM Programming Bit
ACR             0x001D   Analog Counter Register
ACR.CHG           7
ACR.ATD2          6
ACR.ATD1          5
ACR.ICEN          4
ACR.CPIE          3
ACR.CP2EN         2
ACR.CP1EN         1
ACR.ISEN          0
ASR             0x001E   Analog Status Register
ASR.CPF2          7
ASR.CPF1          6
ASR.CPFR2         5
ASR.CPFR1         4
ASR.COE1          3
ASR.VOFF          2
ASR.CMP2          1
ASR.CMP1          0
Reserv001F      0x001F   RESERVED
Reserv1FEF      0x1FEF   RESERVED
COPR            0x1FF0   COP and Security Register
COPR.EPMSEC       7  EPROM Security Bit
COPR.OPT          6  Optional Features Bit
COPR.COPC         0  COP Clear Bit


.68HC705SP7
; MC68HC705JJ7/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705JJ7&nodeId=01M98633
; MC68HC705JJ7.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA RAM		0x0020:0x0200
area DATA EPROM		0x0700:0x1FF0
area DATA USER_VEC	0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET 	0x1FFE       Reset Vector
interrupt SWI 		0x1FFC       SWI Vector
interrupt IRQ		0x1FFA       External IRQ Vector
interrupt CTIMER	0x1FF8       Core Timer Interrupt Vector
interrupt TIMER 	0x1FF6       Timer Interrupt Vector
interrupt SPIF 		0x1FF4       Serial Interrupt Vector
interrupt ANALOG	0x1FF2       Analog Interrupt Vector


; INPUT/ OUTPUT PORTS
PORTA           0x0000   Port A Data Register
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB           0x0001   Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
PORTC           0x0002   Port C Data Register
PORTC.PC7         7  Port C Data Bits 7
PORTC.PC6         6  Port C Data Bits 6
PORTC.PC5         5  Port C Data Bits 5
PORTC.PC4         4  Port C Data Bits 4
PORTC.PC3         3  Port C Data Bits 3
PORTC.PC2         2  Port C Data Bits 2
PORTC.PC1         1  Port C Data Bits 1
PORTC.PC0         0  Port C Data Bits 0
AMUX            0x0003   Analog Multiplex Register
AMUX.HOLD         7
AMUX.DHOLD        6
AMUX.INV          5
AMUX.VREF         4
AMUX.MUX4         3
AMUX.MUX3         2
AMUX.MUX2         1
AMUX.MUX1         0
DDRA            0x0004   Data Direction Register A
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB            0x0005   Data Direction Register B
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
DDRC            0x0006   Data Direction Register C
DDRC.DDRC7        7  Data Direction for Port C Bit 7
DDRC.DDRC6        6  Data Direction for Port C Bit 6
DDRC.DDRC5        5  Data Direction for Port C Bit 5
DDRC.DDRC4        4  Data Direction for Port C Bit 4
DDRC.DDRC3        3  Data Direction for Port C Bit 3
DDRC.DDRC2        2  Data Direction for Port C Bit 2
DDRC.DDRC1        1  Data Direction for Port C Bit 1
DDRC.DDRC0        0  Data Direction for Port C Bit 0
UNUSED0007      0x0007   UNUSED
CTSCR           0x0008   Core Timer Status and Control Register
CTSCR.CTOF        7  Core Timer Overflow Flag
CTSCR.RTIF        6  Real-Time Interrupt Flag
CTSCR.CTOFE       5  Core Timer Overflow Interrupt Enable Bit
CTSCR.RTIE        4  Real-Time Interrupt Enable Bit
CTSCR.CTOFR       3  Core Timer Overflow Flag Reset Bit
CTSCR.RTIFR       2  Real-Time Interrupt Flag Reset Bit
CTSCR.RT1         1  Real-Time Interrupt Select Bits 1
CTSCR.RT0         0  Real-Time Interrupt Select Bits 0
CTCR            0x0009   Core Timer Counter Register
SCR             0x000A   SIOP Control Register
SCR.SPIE          7  Serial Peripheral Interrupt Enable Bit
SCR.SPE           6  Serial Peripheral Enable Bit
SCR.LSBF          5  Least Significant Bit First Bit
SCR.MSTR          4  Master Mode Select Bit
SCR.SPIR          3  Serial Peripheral Interrupt Reset Bit
SCR.CPHA          2  Clock Phase Bit
SCR.SPR1          1  Serial Peripheral Clock Rate Select Bits 1
SCR.SPR0          0  Serial Peripheral Clock Rate Select Bits 0
SSR             0x000B   SIOP Status Register
SSR.SPIF         7   Serial Port Interrupt Flag
SSR.DCOL         6   Data Collision Bit
SDR             0x000C   SIOP Data Register
ISCR            0x000D   IRQ Status and Control Register
ISCR.IRQE         7  External Interrupt Request Enable Bit
ISCR.OM2          6  Oscillator Select Bits 2
ISCR.OM1          5  Oscillator Select Bits 1
ISCR.IRQF         3  External Interrupt Request Flag
ISCR.IRQR         1  Interrupt Request Reset Bit
PEBSR           0x000E   PEPROM Bit Select Register
PEBSR.PEB7        7  Not connected to the PEPROM array 7
PEBSR.PEB6        6  Not connected to the PEPROM array 6
PEBSR.PEB5        5  PEPROM Bit Selects 5
PEBSR.PEB4        4  PEPROM Bit Selects 4
PEBSR.PEB3        3  PEPROM Bit Selects 3
PEBSR.PEB2        2  PEPROM Bit Selects 2
PEBSR.PEB1        1  PEPROM Bit Selects 1
PEBSR.PEB0        0  PEPROM Bit Selects 0
PESCR           0x000F   PEPROM Status and Control Register
PESCR.PEDATA      7  PEPROM Data Bit
PESCR.PEPGM       5  PEPROM Program Control Bit
PESCR.PEPRZF      0  PEPROM Row Zero Flag
PDRA            0x0010   Pulldown Register Port A and Port C
PDRA.PDICH        7  Upper Port C Pulldown Inhibit Bits
PDRA.PDICL        6  Lower Port C Pulldown Inhibit Bits
PDRA.PDIA5        5  Port A Pulldown Inhibit Bit 5
PDRA.PDIA4        4  Port A Pulldown Inhibit Bit 4
PDRA.PDIA3        3  Port A Pulldown Inhibit Bit 3
PDRA.PDIA2        2  Port A Pulldown Inhibit Bit 2
PDRA.PDIA1        1  Port A Pulldown Inhibit Bit 1
PDRA.PDIA0        0  Port A Pulldown Inhibit Bit 0
PDRB            0x0011   Pulldown Register B
PDRB.PDIB7        7  Port B Pulldown Inhibit Bit 7
PDRB.PDIB6        6  Port B Pulldown Inhibit Bit 6
PDRB.PDIB5        5  Port B Pulldown Inhibit Bit 5
PDRB.PDIB4        4  Port B Pulldown Inhibit Bit 4
PDRB.PDIB3        3  Port B Pulldown Inhibit Bit 3
PDRB.PDIB2        2  Port B Pulldown Inhibit Bit 2
PDRB.PDIB1        1  Port B Pulldown Inhibit Bit 1
PDRB.PDIB0        0  Port B Pulldown Inhibit Bit 0
TCR             0x0012   Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable
TCR.IEDG          1  Input Capture Edge Select
TCR.OLVL          0  Output Compare Output Level Select
TSR             0x0013   Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Flag
TSR.TOF           5  Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TMRH            0x0018   Programmable Timer Register High
TMRL            0x0019   Programmable Timer Register Low
ACRH            0x001A   Alternate Counter Register High
ACRL            0x001B   Alternate Counter Register Low
EPROG           0x001C   EPROM Programming Register
EPROG.ELAT        2  EPROM Bus Latch Bit
EPROG.MPGM        1  Mask Option Register (MOR) Programming Bit
EPROG.EPGM        0  EPROM Programming Bit
ACR             0x001D   Analog Counter Register
ACR.CHG           7
ACR.ATD2          6
ACR.ATD1          5
ACR.ICEN          4
ACR.CPIE          3
ACR.CP2EN         2
ACR.CP1EN         1
ACR.ISEN          0
ASR             0x001E   Analog Status Register
ASR.CPF2          7
ASR.CPF1          6
ASR.CPFR2         5
ASR.CPFR1         4
ASR.COE1          3
ASR.VOFF          2
ASR.CMP2          1
ASR.CMP1          0
Reserv001F      0x001F   RESERVED
Reserv1FEF      0x1FEF   RESERVED
COPR            0x1FF0   COP and Security Register
COPR.EPMSEC       7  EPROM Security Bit
COPR.OPT          6  Optional Features Bit
COPR.COPC         0  COP Clear Bit


.68HRC705JJ7
; MC68HC705JJ7/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705JJ7&nodeId=01M98633
; MC68HC705JJ7.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA RAM		0x0020:0x0200
area DATA EPROM		0x0700:0x1FF0
area DATA USER_VEC	0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET 	0x1FFE       Reset Vector
interrupt SWI 		0x1FFC       SWI Vector
interrupt E_IRQ		0x1FFA       External IRQ Vector
interrupt CTIMER	0x1FF8       Core Timer Interrupt Vector
interrupt TIMER 	0x1FF6       Timer Interrupt Vector
interrupt SPIF 		0x1FF4       Serial Interrupt Vector
interrupt ANALOG	0x1FF2       Analog Interrupt Vector


; INPUT/ OUTPUT PORTS
PORTA           0x0000   Port A Data Register
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB           0x0001   Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
RESERV0002      0x0002   RESERVED
AMUX            0x0003   Analog Multiplex Register
AMUX.HOLD         7
AMUX.DHOLD        6
AMUX.INV          5
AMUX.VREF         4
AMUX.MUX4         3
AMUX.MUX3         2
AMUX.MUX2         1
AMUX.MUX1         0
DDRA            0x0004   Data Direction Register A
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB            0x0005   Data Direction Register B
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
RESERV0006      0x0006   RESERVED
UNUSED0007      0x0007   UNUSED
CTSCR           0x0008   Core Timer Status and Control Register
CTSCR.CTOF        7  Core Timer Overflow Flag
CTSCR.RTIF        6  Real-Time Interrupt Flag
CTSCR.CTOFE       5  Core Timer Overflow Interrupt Enable Bit
CTSCR.RTIE        4  Real-Time Interrupt Enable Bit
CTSCR.CTOFR       3  Core Timer Overflow Flag Reset Bit
CTSCR.RTIFR       2  Real-Time Interrupt Flag Reset Bit
CTSCR.RT1         1  Real-Time Interrupt Select Bits 1
CTSCR.RT0         0  Real-Time Interrupt Select Bits 0
CTCR            0x0009   Core Timer Counter Register
SCR             0x000A   SIOP Control Register
SCR.SPIE          7  Serial Peripheral Interrupt Enable Bit
SCR.SPE           6  Serial Peripheral Enable Bit
SCR.LSBF          5  Least Significant Bit First Bit
SCR.MSTR          4  Master Mode Select Bit
SCR.SPIR          3  Serial Peripheral Interrupt Reset Bit
SCR.CPHA          2  Clock Phase Bit
SCR.SPR1          1  Serial Peripheral Clock Rate Select Bits 1
SCR.SPR0          0  Serial Peripheral Clock Rate Select Bits 0
SSR             0x000B   SIOP Status Register
SSR.SPIF         7   Serial Port Interrupt Flag
SSR.DCOL         6   Data Collision Bit
SDR             0x000C   SIOP Data Register
ISCR            0x000D   IRQ Status and Control Register
ISCR.IRQE         7  External Interrupt Request Enable Bit
ISCR.OM2          6  Oscillator Select Bits 2
ISCR.OM1          5  Oscillator Select Bits 1
ISCR.IRQF         3  External Interrupt Request Flag
ISCR.IRQR         1  Interrupt Request Reset Bit
PEBSR           0x000E   PEPROM Bit Select Register
PEBSR.PEB7        7  Not connected to the PEPROM array 7
PEBSR.PEB6        6  Not connected to the PEPROM array 6
PEBSR.PEB5        5  PEPROM Bit Selects 5
PEBSR.PEB4        4  PEPROM Bit Selects 4
PEBSR.PEB3        3  PEPROM Bit Selects 3
PEBSR.PEB2        2  PEPROM Bit Selects 2
PEBSR.PEB1        1  PEPROM Bit Selects 1
PEBSR.PEB0        0  PEPROM Bit Selects 0
PESCR           0x000F   PEPROM Status and Control Register
PESCR.PEDATA      7  PEPROM Data Bit
PESCR.PEPGM       5  PEPROM Program Control Bit
PESCR.PEPRZF      0  PEPROM Row Zero Flag
PDRA            0x0010   Pulldown Register Port A
PDRA.PDIA5        5  Port A Pulldown Inhibit Bit 5
PDRA.PDIA4        4  Port A Pulldown Inhibit Bit 4
PDRA.PDIA3        3  Port A Pulldown Inhibit Bit 3
PDRA.PDIA2        2  Port A Pulldown Inhibit Bit 2
PDRA.PDIA1        1  Port A Pulldown Inhibit Bit 1
PDRA.PDIA0        0  Port A Pulldown Inhibit Bit 0
PDRB            0x0011   Pulldown Register B
PDRB.PDIB7        7  Port B Pulldown Inhibit Bit 7
PDRB.PDIB6        6  Port B Pulldown Inhibit Bit 6
PDRB.PDIB5        5  Port B Pulldown Inhibit Bit 5
PDRB.PDIB4        4  Port B Pulldown Inhibit Bit 4
PDRB.PDIB3        3  Port B Pulldown Inhibit Bit 3
PDRB.PDIB2        2  Port B Pulldown Inhibit Bit 2
PDRB.PDIB1        1  Port B Pulldown Inhibit Bit 1
PDRB.PDIB0        0  Port B Pulldown Inhibit Bit 0
TCR             0x0012   Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable
TCR.IEDG          1  Input Capture Edge Select
TCR.OLVL          0  Output Compare Output Level Select
TSR             0x0013   Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Flag
TSR.TOF           5  Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TMRH            0x0018   Programmable Timer Register High
TMRL            0x0019   Programmable Timer Register Low
ACRH            0x001A   Alternate Counter Register High
ACRL            0x001B   Alternate Counter Register Low
EPROG           0x001C   EPROM Programming Register
EPROG.ELAT        2  EPROM Bus Latch Bit
EPROG.MPGM        1  Mask Option Register (MOR) Programming Bit
EPROG.EPGM        0  EPROM Programming Bit
ACR             0x001D   Analog Counter Register
ACR.CHG           7
ACR.ATD2          6
ACR.ATD1          5
ACR.ICEN          4
ACR.CPIE          3
ACR.CP2EN         2
ACR.CP1EN         1
ACR.ISEN          0
ASR             0x001E   Analog Status Register
ASR.CPF2          7
ASR.CPF1          6
ASR.CPFR2         5
ASR.CPFR1         4
ASR.COE1          3
ASR.VOFF          2
ASR.CMP2          1
ASR.CMP1          0
Reserv001F      0x001F   RESERVED
Reserv1FEF      0x1FEF   RESERVED
COPR            0x1FF0   COP and Security Register
COPR.EPMSEC       7  EPROM Security Bit
COPR.OPT          6  Optional Features Bit
COPR.COPC         0  COP Clear Bit


.68HRC705JP7
; MC68HC705JJ7/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC705JJ7&nodeId=01M98633
; MC68HC705JJ7.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=


; MEMORY MAP
area DATA FSR		0x0000:0x0020
area DATA RAM		0x0020:0x0200
area DATA EPROM		0x0700:0x1FF0
area DATA USER_VEC	0x1FF0:0x2000


; Interrupt and reset vector assignments
interrupt __RESET 	0x1FFE       Reset Vector
interrupt SWI 		0x1FFC       SWI Vector
interrupt E_IRQ		0x1FFA       External IRQ Vector
interrupt CTIMER	0x1FF8       Core Timer Interrupt Vector
interrupt TIMER 	0x1FF6       Timer Interrupt Vector
interrupt SPIF 		0x1FF4       Serial Interrupt Vector
interrupt ANALOG	0x1FF2       Analog Interrupt Vector


; INPUT/ OUTPUT PORTS
PORTA           0x0000   Port A Data Register
PORTA.PA5         5  Port A Data Bits 5
PORTA.PA4         4  Port A Data Bits 4
PORTA.PA3         3  Port A Data Bits 3
PORTA.PA2         2  Port A Data Bits 2
PORTA.PA1         1  Port A Data Bits 1
PORTA.PA0         0  Port A Data Bits 0
PORTB           0x0001   Port B Data Register
PORTB.PB7         7  Port B Data Bits 7
PORTB.PB6         6  Port B Data Bits 6
PORTB.PB5         5  Port B Data Bits 5
PORTB.PB4         4  Port B Data Bits 4
PORTB.PB3         3  Port B Data Bits 3
PORTB.PB2         2  Port B Data Bits 2
PORTB.PB1         1  Port B Data Bits 1
PORTB.PB0         0  Port B Data Bits 0
PORTC           0x0002   Port C Data Register
PORTC.PC7         7  Port C Data Bits 7
PORTC.PC6         6  Port C Data Bits 6
PORTC.PC5         5  Port C Data Bits 5
PORTC.PC4         4  Port C Data Bits 4
PORTC.PC3         3  Port C Data Bits 3
PORTC.PC2         2  Port C Data Bits 2
PORTC.PC1         1  Port C Data Bits 1
PORTC.PC0         0  Port C Data Bits 0
AMUX            0x0003   Analog Multiplex Register
AMUX.HOLD         7
AMUX.DHOLD        6
AMUX.INV          5
AMUX.VREF         4
AMUX.MUX4         3
AMUX.MUX3         2
AMUX.MUX2         1
AMUX.MUX1         0
DDRA            0x0004   Data Direction Register A
DDRA.DDRA5        5  Data Direction for Port A Bit 5
DDRA.DDRA4        4  Data Direction for Port A Bit 4
DDRA.DDRA3        3  Data Direction for Port A Bit 3
DDRA.DDRA2        2  Data Direction for Port A Bit 2
DDRA.DDRA1        1  Data Direction for Port A Bit 1
DDRA.DDRA0        0  Data Direction for Port A Bit 0
DDRB            0x0005   Data Direction Register B
DDRB.DDRB7        7  Data Direction for Port B Bit 7
DDRB.DDRB6        6  Data Direction for Port B Bit 6
DDRB.DDRB5        5  Data Direction for Port B Bit 5
DDRB.DDRB4        4  Data Direction for Port B Bit 4
DDRB.DDRB3        3  Data Direction for Port B Bit 3
DDRB.DDRB2        2  Data Direction for Port B Bit 2
DDRB.DDRB1        1  Data Direction for Port B Bit 1
DDRB.DDRB0        0  Data Direction for Port B Bit 0
DDRC            0x0006   Data Direction Register C
DDRC.DDRC7        7  Data Direction for Port C Bit 7
DDRC.DDRC6        6  Data Direction for Port C Bit 6
DDRC.DDRC5        5  Data Direction for Port C Bit 5
DDRC.DDRC4        4  Data Direction for Port C Bit 4
DDRC.DDRC3        3  Data Direction for Port C Bit 3
DDRC.DDRC2        2  Data Direction for Port C Bit 2
DDRC.DDRC1        1  Data Direction for Port C Bit 1
DDRC.DDRC0        0  Data Direction for Port C Bit 0
UNUSED0007      0x0007   UNUSED
CTSCR           0x0008   Core Timer Status and Control Register
CTSCR.CTOF        7  Core Timer Overflow Flag
CTSCR.RTIF        6  Real-Time Interrupt Flag
CTSCR.CTOFE       5  Core Timer Overflow Interrupt Enable Bit
CTSCR.RTIE        4  Real-Time Interrupt Enable Bit
CTSCR.CTOFR       3  Core Timer Overflow Flag Reset Bit
CTSCR.RTIFR       2  Real-Time Interrupt Flag Reset Bit
CTSCR.RT1         1  Real-Time Interrupt Select Bits 1
CTSCR.RT0         0  Real-Time Interrupt Select Bits 0
CTCR            0x0009   Core Timer Counter Register
SCR             0x000A   SIOP Control Register
SCR.SPIE          7  Serial Peripheral Interrupt Enable Bit
SCR.SPE           6  Serial Peripheral Enable Bit
SCR.LSBF          5  Least Significant Bit First Bit
SCR.MSTR          4  Master Mode Select Bit
SCR.SPIR          3  Serial Peripheral Interrupt Reset Bit
SCR.CPHA          2  Clock Phase Bit
SCR.SPR1          1  Serial Peripheral Clock Rate Select Bits 1
SCR.SPR0          0  Serial Peripheral Clock Rate Select Bits 0
SSR             0x000B   SIOP Status Register
SSR.SPIF         7   Serial Port Interrupt Flag
SSR.DCOL         6   Data Collision Bit
SDR             0x000C   SIOP Data Register
ISCR            0x000D   IRQ Status and Control Register
ISCR.IRQE         7  External Interrupt Request Enable Bit
ISCR.OM2          6  Oscillator Select Bits 2
ISCR.OM1          5  Oscillator Select Bits 1
ISCR.IRQF         3  External Interrupt Request Flag
ISCR.IRQR         1  Interrupt Request Reset Bit
PEBSR           0x000E   PEPROM Bit Select Register
PEBSR.PEB7        7  Not connected to the PEPROM array 7
PEBSR.PEB6        6  Not connected to the PEPROM array 6
PEBSR.PEB5        5  PEPROM Bit Selects 5
PEBSR.PEB4        4  PEPROM Bit Selects 4
PEBSR.PEB3        3  PEPROM Bit Selects 3
PEBSR.PEB2        2  PEPROM Bit Selects 2
PEBSR.PEB1        1  PEPROM Bit Selects 1
PEBSR.PEB0        0  PEPROM Bit Selects 0
PESCR           0x000F   PEPROM Status and Control Register
PESCR.PEDATA      7  PEPROM Data Bit
PESCR.PEPGM       5  PEPROM Program Control Bit
PESCR.PEPRZF      0  PEPROM Row Zero Flag
PDRA            0x0010   Pulldown Register Port A and Port C
PDRA.PDICH        7  Upper Port C Pulldown Inhibit Bits
PDRA.PDICL        6  Lower Port C Pulldown Inhibit Bits
PDRA.PDIA5        5  Port A Pulldown Inhibit Bit 5
PDRA.PDIA4        4  Port A Pulldown Inhibit Bit 4
PDRA.PDIA3        3  Port A Pulldown Inhibit Bit 3
PDRA.PDIA2        2  Port A Pulldown Inhibit Bit 2
PDRA.PDIA1        1  Port A Pulldown Inhibit Bit 1
PDRA.PDIA0        0  Port A Pulldown Inhibit Bit 0
PDRB            0x0011   Pulldown Register B
PDRB.PDIB7        7  Port B Pulldown Inhibit Bit 7
PDRB.PDIB6        6  Port B Pulldown Inhibit Bit 6
PDRB.PDIB5        5  Port B Pulldown Inhibit Bit 5
PDRB.PDIB4        4  Port B Pulldown Inhibit Bit 4
PDRB.PDIB3        3  Port B Pulldown Inhibit Bit 3
PDRB.PDIB2        2  Port B Pulldown Inhibit Bit 2
PDRB.PDIB1        1  Port B Pulldown Inhibit Bit 1
PDRB.PDIB0        0  Port B Pulldown Inhibit Bit 0
TCR             0x0012   Timer Control Register
TCR.ICIE          7  Input Capture Interrupt Enable Bit
TCR.OCIE          6  Output Compare Interrupt Enable Bit
TCR.TOIE          5  Timer Overflow Interrupt Enable
TCR.IEDG          1  Input Capture Edge Select
TCR.OLVL          0  Output Compare Output Level Select
TSR             0x0013   Timer Status Register
TSR.ICF           7  Input Capture Flag
TSR.OCF           6  Output Compare Flag
TSR.TOF           5  Timer Overflow Flag
ICRH            0x0014   Input Capture Register High
ICRL            0x0015   Input Capture Register Low
OCRH            0x0016   Output Compare Register High
OCRL            0x0017   Output Compare Register Low
TMRH            0x0018   Programmable Timer Register High
TMRL            0x0019   Programmable Timer Register Low
ACRH            0x001A   Alternate Counter Register High
ACRL            0x001B   Alternate Counter Register Low
EPROG           0x001C   EPROM Programming Register
EPROG.ELAT        2  EPROM Bus Latch Bit
EPROG.MPGM        1  Mask Option Register (MOR) Programming Bit
EPROG.EPGM        0  EPROM Programming Bit
ACR             0x001D   Analog Counter Register
ACR.CHG           7
ACR.ATD2          6
ACR.ATD1          5
ACR.ICEN          4
ACR.CPIE          3
ACR.CP2EN         2
ACR.CP1EN         1
ACR.ISEN          0
ASR             0x001E   Analog Status Register
ASR.CPF2          7
ASR.CPF1          6
ASR.CPFR2         5
ASR.CPFR1         4
ASR.COE1          3
ASR.VOFF          2
ASR.CMP2          1
ASR.CMP1          0
Reserv001F      0x001F   RESERVED
Reserv1FEF      0x1FEF   RESERVED
COPR            0x1FF0   COP and Security Register
COPR.EPMSEC       7  EPROM Security Bit
COPR.OPT          6  Optional Features Bit
COPR.COPC         0  COP Clear Bit


.68HRC705KJ1
; MC68HC705KJ1.pdf

; RAM=64
; ROM=0
; EPROM=1.2K
; EEPROM=0


; MEMORY MAP
area DATA FSR         0x0000:0x0020
area BSS  UNUSED      0x0020:0x00C0
area DATA RAM         0x00C0:0x0100
area BSS  UNUSED      0x0100:0x0300
area DATA EPROM       0x0300:0x07D0
area BSS  UNUSED      0x07D0:0x07EE
area DATA ROM_TEST    0x07EE:0x07F0
area DATA USER_VEC    0x07F0:0x0800


; Interrupt and reset vector assignments
interrupt __RESET           0x07FE      Processor reset
interrupt SWI               0x07FC      Software interrupt
interrupt IRQ               0x07FA      External Interrupt
interrupt TIMER             0x07F8      Timer Interupt


; INPUT/ OUTPUT PORTS
PORTA           0x0000    Port A data
PORTA.PA7        7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
PORTB           0x0001    Port B data
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
UNUSED0002      0x0002    UNUSED
UNUSED0003      0x0003    UNUSED
DDRA            0x0004    Port A data direction
DDRA.DDRA7       7   Data Direction for Port A Bit 7
DDRA.DDRA6       6   Data Direction for Port A Bit 6
DDRA.DDRA5       5   Data Direction for Port A Bit 5
DDRA.DDRA4       4   Data Direction for Port A Bit 4
DDRA.DDRA3       3   Data Direction for Port A Bit 3
DDRA.DDRA2       2   Data Direction for Port A Bit 2
DDRA.DDRA1       1   Data Direction for Port A Bit 1
DDRA.DDRA0       0   Data Direction for Port A Bit 0
DDRB            0x0005    Port B data direction
DDRB.DDRB3       3   Data Direction for Port B Bit 3
DDRB.DDRB2       2   Data Direction for Port B Bit 2
UNUSED0006      0x0006    UNUSED
UNUSED0007      0x0007    UNUSED
TSCR            0x0008  Timer Status and Control
TSCR.TOF         7   Timer Overflow Flag
TSCR.RTIF        6   Real-Time Interrupt Flag
TSCR.TOIE        5   Timer Overflow Interrupt Enable Bit
TSCR.RTIE        4   Real-Time Interrupt Enable Bit
TSCR.TOFR        3   Timer Overflow Flag Reset Bit
TSCR.RTIFR       2   Real-Time Interrupt Flag Reset Bit
TSCR.RT1         1   Real-Time Interrupt Select Bits 1
TSCR.RT0         0   Real-Time Interrupt Select Bits 0
TCR             0x0009  Timer Counter
TCR.TCR7         7
TCR.TCR6         6
TCR.TCR5         5
TCR.TCR4         4
TCR.TCR3         3
TCR.TCR2         2
TCR.TCR1         1
TCR.TCR0         0
ISCR            0x000A  IRQ Status and Control
ISCR.IRQE        7   External Interrupt Request Enable Bit
ISCR.IRQF        3   External Interrupt Request Flag
ISCR.IRQR        1   Interrupt Request Reset Bit
UNUSED000B      0x000B    UNUSED
UNUSED000C      0x000C    UNUSED
UNUSED000D      0x000D    UNUSED
UNUSED000E      0x000E    UNUSED
UNUSED000F      0x000F    UNUSED
PDRA            0x0010    Pulldown Register Port A
PDRA.PDRA7       7   Port A Pulldown Inhibit Bit 7
PDRA.PDRA6       6   Port A Pulldown Inhibit Bit 6
PDRA.PDRA5       5   Port A Pulldown Inhibit Bit 5
PDRA.PDRA4       4   Port A Pulldown Inhibit Bit 4
PDRA.PDRA3       3   Port A Pulldown Inhibit Bit 3
PDRA.PDRA2       2   Port A Pulldown Inhibit Bit 2
PDRA.PDRA1       1   Port A Pulldown Inhibit Bit 1
PDRA.PDRA0       0   Port A Pulldown Inhibit Bit 0
PDRB            0x0011     Pulldown Register Port B
PDRB.PDIB3       3   Port B Pulldown Inhibit Bit 3
PDRB.PDIB2       2   Port B Pulldown Inhibit Bit 2
UNUSED0012      0x0012    UNUSED
UNUSED0013      0x0013    UNUSED
UNUSED0014      0x0014    UNUSED
UNUSED0015      0x0015    UNUSED
UNUSED0016      0x0016    UNUSED
UNUSED0017      0x0017    UNUSED
EPROG           0x0018    EPROM Programming
EPROG.ELAT       2   EPROM Bus Latch Bit
EPROG.MPGM       1   MOR Programming Bit
EPROG.EPGM       0   EPROM Programming Bit
UNUSED0019      0x0019    UNUSED
UNUSED001A      0x001A    UNUSED
UNUSED001B      0x001B    UNUSED
UNUSED001C      0x001C    UNUSED
UNUSED001D      0x001D    UNUSED
UNUSED001E      0x001E    UNUSED
RESERV001F      0x001F   RESERVED
COPR            0x07F0   COP Register
COPR.COPC        0   COP Clear Bit
MOR             0x07F1   Mask Options
MOR.SOSCD        7   Short Oscillator Delay Bit
MOR.EPMSEC       6   EPROM Security Bit
MOR.OSCRES       5   Oscillator Internal Resistor Bit
MOR.SWAIT        4   Stop-to-Wait Conversion Bit
MOR.PDI          3   Software Pulldown Inhibit Bit
MOR.PIRQ         2   Port A External Interrupt Bit
MOR.LEVEL        1   External Interrupt Sensitivity Bit
MOR.COPEN        0   COP Enable Bit
RESERV07F2      0x07F2            RESERVED
RESERV07F3      0x07F3            RESERVED
RESERV07F4      0x07F4            RESERVED
RESERV07F5      0x07F5            RESERVED
RESERV07F6      0x07F6            RESERVED
RESERV07F7      0x07F7            RESERVED


