; The format of the input file:
; each device definition begins with a line like this:
;
;       .devicename
;
;  after it go the port definitions in this format:
;
;       portname        address
;
;  the bit definitions (optional) are represented like this:
;
;       portname.bitname  bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
;       .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
; MOTOROLA SPECIFIC LINES
;------------------------
;
; the processor definition may include the memory configuration.
; the line format is:

;       area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
;       START and END are addresses, the end address is not included

; Interrupt vectors are declared in the following way:

; interrupt NAME ADDRESS COMMENT

.default 68HC11A8


.68HC11A0        
; MC68HC11A8TS/D http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11A8.pdf

; RAM=256
; ROM=8K
; EPROM=0
; EEPROM=512


; MEMORY MAP
area DATA RAM         0x0000:0x0100
area BSS  RESERVED    0x0100:0x1000
area DATA FSR         0x1000:0x1040
area BSS  RESERVED    0x1040:0xB600
area DATA EEPROM      0xB600:0xB800
area BSS  RESERVED    0xB800:0xE000
area DATA ROM         0xE000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA           0x1000     Port A data
PORTA.PA7     	 7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
RESERV1001      0x1001     RESERVED01
PIOC            0x1002     Parallel I_O Control Register
PIOC.STAF        7   Strobe A Interrupt Status Flag
PIOC.STAI        6   Strobe A Interrupt Enable Mask
PIOC.CWOM        5   Port C Wire-OR Mode (affects all eight port C pins)
PIOC.HNDS        4   Handshake Mode
PIOC.OIN         3   Output or Input Handshake Select
PIOC.PLS         2   Pulse/Interlocked Handshake Operation
PIOC.EGA         1   Active Edge for Strobe A
PIOC.INVB        0   Invert Strobe B
PORTC           0x1003     I_O Port C
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTB           0x1004     Output Port B
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTCL          0x1005     Latched Port C
PORTCL.PCL7      7
PORTCL.PCL6      6
PORTCL.PCL5      5
PORTCL.PCL4      4
PORTCL.PCL3      3
PORTCL.PCL2      2
PORTCL.PCL1      1
PORTCL.PCL0      0
RESERV1006      0x1006     RESERVED06
DDRC            0x1007     Data Direction for Port C
DDRC.DDC7        7   Data Direction for Port C Bit 7
DDRC.DDC6        6   Data Direction for Port C Bit 6
DDRC.DDC5        5   Data Direction for Port C Bit 5
DDRC.DDC4        4   Data Direction for Port C Bit 4
DDRC.DDC3        3   Data Direction for Port C Bit 3
DDRC.DDC2        2   Data Direction for Port C Bit 2
DDRC.DDC1        1   Data Direction for Port C Bit 1
DDRC.DDC0        0   Data Direction for Port C Bit 0
PORTD           0x1008     I_O Port D
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRD            0x1009     Data Direction for Port D
DDRD.DDD5        5   Data Direction for Port D Bit 5
DDRD.DDD4        4   Data Direction for Port D Bit 4
DDRD.DDD3        3   Data Direction for Port D Bit 3
DDRD.DDD2        2   Data Direction for Port D Bit 2
DDRD.DDD1        1   Data Direction for Port D Bit 1
DDRD.DDD0        0   Data Direction for Port D Bit 0
PORTE           0x100A     Input Port E
PORTE.PE7        7   Port E Data Bits 7
PORTE.PE6        6   Port E Data Bits 6
PORTE.PE5        5   Port E Data Bits 5
PORTE.PE4        4   Port E Data Bits 4
PORTE.PE3        3   Port E Data Bits 3
PORTE.PE2        2   Port E Data Bits 2
PORTE.PE1        1   Port E Data Bits 1
PORTE.PE0        0   Port E Data Bits 0
CFORC           0x100B     Compare Force Register
CFORC.FOC1       7   Write ones to Force Compare 1
CFORC.FOC2       6   Write ones to Force Compare 2
CFORC.FOC3       5   Write ones to Force Compare 3
CFORC.FOC4       4   Write ones to Force Compare 4
CFORC.FOC5       3   Write ones to Force Compare 5
OC1M            0x100C     OC1 Action Mask Register
OC1M.OC1M7       7
OC1M.OC1M6       6
OC1M.OC1M5       5
OC1M.OC1M4       4
OC1M.OC1M3       3
OC1D            0x100D      OC1 Action Data Register
OC1D.OC1D7       7
OC1D.OC1D6       6
OC1D.OC1D5       5
OC1D.OC1D4       4
OC1D.OC1D3       3
TCNTH           0x100E     Timer Counter Register
TCNTL           0x100F     Timer Counter Register
TIC1H           0x1010     Input Capture 1 Register
TIC1L           0x1011     Input Capture 1 Register
TIC2H           0x1012     Input Capture 2 Register
TIC2L           0x1013     Input Capture 2 Register
TIC3H           0x1014     Input Capture 3 Register
TIC3L           0x1015     Input Capture 3 Register
TOC1H           0x1016     Output Compare 1 Register
TOC1L           0x1017     Output Compare 1 Register
TOC2H           0x1018     Output Compare 2 Register
TOC2L           0x1019     Output Compare 2 Register
TOC3H           0x101A     Output Compare 3 Register
TOC3L           0x101B     Output Compare 3 Register
TOC4H           0x101C     Output Compare 4 Register
TOC4L           0x101D     Output Compare 4 Register
TCO5H           0x101E     Output Compare 5 Register
TCO5L           0x101F     Output Compare 5 Register
TCTL1           0x1020     Timer Control Register 1
TCTL1.OM2        7   OM2 Output Mode
TCTL1.OL2        6   OL2 Output Level
TCTL1.OM3        5   OM3 Output Mode
TCTL1.OL3        4   OL3 Output Level
TCTL1.OM4        3   OM4 Output Mode
TCTL1.OL4        2   OL4 Output Level
TCTL1.OM5        1   OM5 Output Mode
TCTL1.OL5        0   OL5 Output Level
TCTL2           0x1021     Timer Control Register 2
TCTL2.EDG1B      5
TCTL2.EDG1A      4
TCTL2.EDG2B      3
TCTL2.EDG2A      2
TCTL2.EDG3B      1
TCTL2.EDG3A      0
TMSK1           0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I       7   Output Compare 1 Interrupt Enable
TMSK1.OC2I       6   Output Compare 2 Interrupt Enable
TMSK1.OC3I       5   Output Compare 3 Interrupt Enable
TMSK1.OC4I       4   Output Compare 4 Interrupt Enable
TMSK1.OC5I       3   Output Compare 5 Interrupt Enable
TMSK1.IC1I       2   Input Capture 1 Interrupt Enable
TMSK1.IC2I       1   Input Capture 2 Interrupt Enable
TMSK1.IC3I       0   Input Capture 3 Interrupt Enable
TFLG1           0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F       7   Output Compare 1 Flag
TFLG1.OC2F       6   Output Compare 2 Flag
TFLG1.OC3F       5   Output Compare 3 Flag
TFLG1.OC4F       4   Output Compare 4 Flag
TFLG1.OC5F       3   Output Compare 5 Flag
TFLG1.IC1F       2   Input Capture 1 Flag
TFLG1.IC2F       1   Input Capture 2 Flag
TFLG1.IC3F       0   Input Capture 3 Flag
TMSK2           0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI        7   Timer Overflow Interrupt Enable
TMSK2.RTII       6   Real-Time Interrupt Enable
TMSK2.PAOVI      5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII       4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1        1   Timer Prescaler Select 1
TMSK2.PR0        0   Timer Prescaler Select 0
TFLG2           0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF        7   Timer Overflow Flag
TFLG2.RTIF       6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF      5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF       4   Pulse Accumulator Input Edge Interrupt Flag
PACTL           0x1026     Pulse Accumulator Control Register
PACTL.DDRA7      7   Data Direction for Port A Bit 7
PACTL.PAEN       6   Pulse Accumulator System Enable
PACTL.PAMOD      5   Pulse Accumulator Mode
PACTL.PEDGE      4   Pulse Accumulator Edge Control
PACTL.RTR1       1   RTR1 - Real-Time Interrupt Rate
PACTL.RTR0       0   RTR0 - Real-Time Interrupt Rate
PACNT           0x1027     Pulse Accumulator Count Register
SPCR            0x1028     SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable
SPCR.DWOM        5   Port D Wired-OR Mode
SPCR.MSTR        4   Master Mode Select
SPCR.CPOL        3   Clock Polarity
SPCR.CPHA        2   Clock Phase
SPCR.SPR1        1   SPI Clock Rate Selects 1
SPCR.SPR0        0   SPI Clock Rate Selects 0
SPSR            0x1029     SPI Status Register
SPSR.SPIF        7   SPI Transfer Complete Flag
SPSR.WCOL        6   Write Collision
SPSR.MODF        4   Mode Fault (A Mode Fault Terminates SPI Operation)
SPDR            0x102A     SPI Data Register
BAUD            0x102B     SCI Baud Rate Control 3
BAUD.TCLR        7   Clear Baud Rate Counters (TEST)
BAUD.SCP1        5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0        4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB        3   SCI Baud Rate Clock Check (TEST)
BAUD.SCR2        2   SCI Baud Rate Selects 2
BAUD.SCR1        1   SCI Baud Rate Selects 1
BAUD.SCR0        0   SCI Baud Rate Selects 0
SCCR1           0x102C     SCI Control Register 1
SCCR1.R8         7   Receive Data Bit 8
SCCR1.T8         6   Transmit Data Bit 8
SCCR1.M          4   Mode (Select Character Format)
SCCR1.WAKE       3   Wake Up by Address Mark/Idle
SCCR2           0x102D     SCI Control Register 2
SCCR2.TIE        7   Transmit Interrupt Enable
SCCR2.TCIE       6   Transmit Complete Interrupt Enable
SCCR2.RIE        5   Receiver Interrupt Enable
SCCR2.ILIE       4   Idle Line Interrupt Enable
SCCR2.TE         3   Transmitter Enable
SCCR2.RE         2   Receiver Enable
SCCR2.RWU        1   Receiver Wake Up Control
SCCR2.SBK        0   Send Break
SCSR            0x102E     SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty Flag
SCSR.TC          6   Transmit Complete Flag
SCSR.RDRF        5   Receive Data Register Full Flag
SCSR.IDLE        4   Idle Line Detected Flag
SCSR.OR          3   Overrun Error Flag
SCSR.NF          2   Noise Error Flag
SCSR.FE          1   Framing Error
SCDR            0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7        7
SCDR.R6T6        6
SCDR.R5T5        5
SCDR.R4T4        4
SCDR.R3T3        3
SCDR.R2T2        2
SCDR.R1T1        1
SCDR.R0T0        0
ADCTL           0x1030     A_D Control Register
ADCTL.CCF        7   Conversions Complete Flag
ADCTL.SCAN       5   Continuous Scan Control
ADCTL.MULT       4   Multiple Channel/Single Channel Control
ADCTL.CD         3   Channel Select D
ADCTL.CC         2   Channel Select C
ADCTL.CB         1   Channel Select B
ADCTL.CA         0   Channel Select A
ADR1            0x1031     A_D Result Register 1
ADR2            0x1032     A_D Result Register 2
ADR3            0x1033     A_D Result Register 3
ADR4            0x1034     A_D Result Register 4
RESERV1035      0x1035     RESERVED35
RESERV1036      0x1036     RESERVED36
RESERV1037      0x1037     RESERVED37
RESERV1038      0x1038     RESERVED38
OPTION          0x1039     System Configuration Options
OPTION.ADPU      7   A/D Converter Power-up
OPTION.CSEL      6   Clock Select
OPTION.IRQE      5   IRQ Select Edge-Sensitive Only
OPTION.DLY       4   Enable Oscillator Start-Up Delay on Exit from STOP
OPTION.CME       3   Clock Monitor Enable
OPTION.CR1       1   COP Timer Rate Select 1
OPTION.CR0       0   COP Timer Rate Select 0
COPRST          0x103A     Arm_Reset COP Timer Circuitry
PPROG           0x103B     EEPROM Program Control Register
PPROG.ODD        7   Program Odd Rows in Half of EEPROM (TEST)
PPROG.EVEN       6   Program Even Rows in Half of EEPROM (TEST)
PPROG.BYTE       4   Byte/Other EEPROM Erase Mode
PPROG.ROW        3   Row/All EEPROM Erase Mode
PPROG.ERASE      2   Erase/Normal Control for EEPROM
PPROG.EELAT      1   EEPROM Latch Control
PPROG.EEPGM      0   EEPROM Program Command
HPRIO           0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT      7   Read Bootstrap ROM
HPRIO.SMOD       6   Special Mode Select
HPRIO.MDA        5   Mode Select A
HPRIO.IRV        4   Internal Read Visibility
HPRIO.PSEL3      3   Priority Select Bits 3
HPRIO.PSEL2      2   Priority Select Bits 2
HPRIO.PSEL1      1   Priority Select Bits 1
HPRIO.PSEL0      0   Priority Select Bits 0
INIT            0x103D     RAM and I_O Mapping Register
INIT.RAM3        7   256-Byte Internal RAM Map Position 3
INIT.RAM2        6   256-Byte Internal RAM Map Position 2
INIT.RAM1        5   256-Byte Internal RAM Map Position 1
INIT.RAM0        4   256-Byte Internal RAM Map Position 0
INIT.REG3        3   64-Byte Register Block Map Position 3
INIT.REG2        2   64-Byte Register Block Map Position 2
INIT.REG1        1   64-Byte Register Block Map Position 1
INIT.REG0        0   64-Byte Register Block Map Position 0
TEST1           0x103E     Factory TEST Control Register
TEST1.TILOP      7   Test Illegal Opcode
TEST1.OCCR       5   Output Condition Code Register to Timer Port
TEST1.CBYP       4   Timer Divider Chain Bypass
TEST1.DISR       3   Disable Resets from COP and Clock Monitor
TEST1.FCM        2   Force Clock Monitor Failure
TEST1.FCOP       1   Force COP Watchdog Failure
TEST1.TCON       0   Test Configuration Register
CONFIG          0x103F     COP, ROM, and EEPROM Enables
CONFIG.NOSEC     3   EEPROM Security Disable
CONFIG.NOCOP     2   COP System Disable
CONFIG.ROMON     1   ROM Enable
CONFIG.EEON      0   EEPROM Enable
RESERVFFC0      0xFFC0     RESERVED
RESERVFFC1      0xFFC1     RESERVED
RESERVFFC2      0xFFC2     RESERVED
RESERVFFC3      0xFFC3     RESERVED
RESERVFFC4      0xFFC4     RESERVED
RESERVFFC5      0xFFC5     RESERVED
RESERVFFC6      0xFFC6     RESERVED
RESERVFFC7      0xFFC7     RESERVED
RESERVFFC8      0xFFC8     RESERVED
RESERVFFC9      0xFFC9     RESERVED
RESERVFFCA      0xFFCA     RESERVED
RESERVFFCB      0xFFCB     RESERVED
RESERVFFCC      0xFFCC     RESERVED
RESERVFFCD      0xFFCD     RESERVED
RESERVFFCE      0xFFCE     RESERVED
RESERVFFCF      0xFFCF     RESERVED
RESERVFFD0      0xFFD0     RESERVED
RESERVFFD1      0xFFD1     RESERVED
RESERVFFD2      0xFFD2     RESERVED
RESERVFFD3      0xFFD3     RESERVED
RESERVFFD4      0xFFD4     RESERVED
RESERVFFD5      0xFFD5     RESERVED


.68HC11A1
; MC68HC11A8TS/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11A8.pdf

; RAM=256
; ROM=0
; EPROM=0
; EEPROM=512


; MEMORY MAP
area DATA RAM         0x0000:0x0100
area BSS  RESERVED    0x0100:0x1000
area DATA FSR         0x1000:0x1040
area BSS  RESERVED    0x1040:0xB600
area DATA EEPROM      0xB600:0xB800
area BSS  RESERVED    0xB800:0xE000
area DATA ROM         0xE000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA           0x1000  Port A data
PORTA.PA7     	 7   Port A Data Bits 7
PORTA.PA6        6   Port A Data Bits 6
PORTA.PA5        5   Port A Data Bits 5
PORTA.PA4        4   Port A Data Bits 4
PORTA.PA3        3   Port A Data Bits 3
PORTA.PA2        2   Port A Data Bits 2
PORTA.PA1        1   Port A Data Bits 1
PORTA.PA0        0   Port A Data Bits 0
RESERVED01      0x1001  RESERVED01
PIOC            0x1002  Parallel I_O Control Register
PIOC.STAF        7   Strobe A Interrupt Status Flag
PIOC.STAI        6   Strobe A Interrupt Enable Mask
PIOC.CWOM        5   Port C Wire-OR Mode (affects all eight port C pins)
PIOC.HNDS        4   Handshake Mode
PIOC.OIN         3   Output or Input Handshake Select
PIOC.PLS         2   Pulse/Interlocked Handshake Operation
PIOC.EGA         1   Active Edge for Strobe A
PIOC.INVB        0   Invert Strobe B
PORTC           0x1003  I_O Port C
PORTC.PC7        7   Port C Data Bits 7
PORTC.PC6        6   Port C Data Bits 6
PORTC.PC5        5   Port C Data Bits 5
PORTC.PC4        4   Port C Data Bits 4
PORTC.PC3        3   Port C Data Bits 3
PORTC.PC2        2   Port C Data Bits 2
PORTC.PC1        1   Port C Data Bits 1
PORTC.PC0        0   Port C Data Bits 0
PORTB           0x1004  Output Port B
PORTB.PB7        7   Port B Data Bits 7
PORTB.PB6        6   Port B Data Bits 6
PORTB.PB5        5   Port B Data Bits 5
PORTB.PB4        4   Port B Data Bits 4
PORTB.PB3        3   Port B Data Bits 3
PORTB.PB2        2   Port B Data Bits 2
PORTB.PB1        1   Port B Data Bits 1
PORTB.PB0        0   Port B Data Bits 0
PORTCL          0x1005  Alternate Latched Port C
PORTCL.PCL7      7
PORTCL.PCL6      6
PORTCL.PCL5      5
PORTCL.PCL4      4
PORTCL.PCL3      3
PORTCL.PCL2      2
PORTCL.PCL1      1
PORTCL.PCL0      0
RESERVED06      0x1006  RESERVED06
DDRC            0x1007  Data Direction for Port C
DDRC.DDC7        7   Data Direction for Port C Bit 7
DDRC.DDC6        6   Data Direction for Port C Bit 6
DDRC.DDC5        5   Data Direction for Port C Bit 5
DDRC.DDC4        4   Data Direction for Port C Bit 4
DDRC.DDC3        3   Data Direction for Port C Bit 3
DDRC.DDC2        2   Data Direction for Port C Bit 2
DDRC.DDC1        1   Data Direction for Port C Bit 1
DDRC.DDC0        0   Data Direction for Port C Bit 0
PORTD           0x1008  I_O Port D
PORTD.PD5        5   Port D Data Bits 5
PORTD.PD4        4   Port D Data Bits 4
PORTD.PD3        3   Port D Data Bits 3
PORTD.PD2        2   Port D Data Bits 2
PORTD.PD1        1   Port D Data Bits 1
PORTD.PD0        0   Port D Data Bits 0
DDRD            0x1009  Data Direction for Port D
DDRD.DDD5        5   Data Direction for Port D Bit 5
DDRD.DDD4        4   Data Direction for Port D Bit 4
DDRD.DDD3        3   Data Direction for Port D Bit 3
DDRD.DDD2        2   Data Direction for Port D Bit 2
DDRD.DDD1        1   Data Direction for Port D Bit 1
DDRD.DDD0        0   Data Direction for Port D Bit 0
PORTE           0x100A  Input Port E
PORTE.PE7        7   Port E Data Bits 7
PORTE.PE6        6   Port E Data Bits 6
PORTE.PE5        5   Port E Data Bits 5
PORTE.PE4        4   Port E Data Bits 4
PORTE.PE3        3   Port E Data Bits 3
PORTE.PE2        2   Port E Data Bits 2
PORTE.PE1        1   Port E Data Bits 1
PORTE.PE0        0   Port E Data Bits 0
CFORC           0x100B  Compare Force Register
CFORC.FOC1       7   Write ones to Force Compare 1
CFORC.FOC2       6   Write ones to Force Compare 2
CFORC.FOC3       5   Write ones to Force Compare 3
CFORC.FOC4       4   Write ones to Force Compare 4
CFORC.FOC5       3   Write ones to Force Compare 5
OC1M            0x100C  OC1 Action Mask Register
OC1M.OC1M7       7
OC1M.OC1M6       6
OC1M.OC1M5       5
OC1M.OC1M4       4
OC1M.OC1M3       3
OC1D            0x100D   OC1 Action Data Register
OC1D.OC1D7       7
OC1D.OC1D6       6
OC1D.OC1D5       5
OC1D.OC1D4       4
OC1D.OC1D3       3
TCNTH           0x100E  Timer Counter Register
TCNTL           0x100F  Timer Counter Register
TIC1H           0x1010  Input Capture 1 Register
TIC1L           0x1011  Input Capture 1 Register
TIC2H           0x1012  Input Capture 2 Register
TIC2L           0x1013  Input Capture 2 Register
TIC3H           0x1014  Input Capture 3 Register
TIC3L           0x1015  Input Capture 3 Register
TOC1H           0x1016  Output Compare 1 Register
TOC1L           0x1017  Output Compare 1 Register
TOC2H           0x1018  Output Compare 2 Register
TOC2L           0x1019  Output Compare 2 Register
TOC3H           0x101A  Output Compare 3 Register
TOC3L           0x101B  Output Compare 3 Register
TOC4H           0x101C  Output Compare 4 Register
TOC4L           0x101D  Output Compare 4 Register
TCO5H           0x101E  Output Compare 5 Register
TCO5L           0x101F  Output Compare 5 Register
TCTL1           0x1020  Timer Control Register 1
TCTL1.OM2        7   OM2 Output Mode
TCTL1.OL2        6   OL2 Output Level
TCTL1.OM3        5   OM3 Output Mode
TCTL1.OL3        4   OL3 Output Level
TCTL1.OM4        3   OM4 Output Mode
TCTL1.OL4        2   OL4 Output Level
TCTL1.OM5        1   OM5 Output Mode
TCTL1.OL5        0   OL5 Output Level
TCTL2           0x1021  Timer Control Register 2
TCTL2.EDG1B      5
TCTL2.EDG1A      4
TCTL2.EDG2B      3
TCTL2.EDG2A      2
TCTL2.EDG3B      1
TCTL2.EDG3A      0
TMSK1           0x1022  Timer Interrupt Mask Register 1
TMSK1.OC1I       7   Output Compare 1 Interrupt Enable
TMSK1.OC2I       6   Output Compare 2 Interrupt Enable
TMSK1.OC3I       5   Output Compare 3 Interrupt Enable
TMSK1.OC4I       4   Output Compare 4 Interrupt Enable
TMSK1.OC5I       3   Output Compare 5 Interrupt Enable
TMSK1.IC1I       2   Input Capture 1 Interrupt Enable
TMSK1.IC2I       1   Input Capture 2 Interrupt Enable
TMSK1.IC3I       0   Input Capture 3 Interrupt Enable
TFLG1           0x1023  Timer Interrupt Flag Register 1
TFLG1.OC1F       7   Output Compare 1 Flag
TFLG1.OC2F       6   Output Compare 2 Flag
TFLG1.OC3F       5   Output Compare 3 Flag
TFLG1.OC4F       4   Output Compare 4 Flag
TFLG1.OC5F       3   Output Compare 5 Flag
TFLG1.IC1F       2   Input Capture 1 Flag
TFLG1.IC2F       1   Input Capture 2 Flag
TFLG1.IC3F       0   Input Capture 3 Flag
TMSK2           0x1024  Timer Interrupt Mask Register 2
TMSK2.TOI        7   Timer Overflow Interrupt Enable
TMSK2.RTII       6   Real-Time Interrupt Enable
TMSK2.PAOVI      5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII       4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1        1   Timer Prescaler Select 1
TMSK2.PR0        0   Timer Prescaler Select 0
TFLG2           0x1025  Timer Interrupt Flag Register 2
TFLG2.TOF        7   Timer Overflow Flag
TFLG2.RTIF       6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF      5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF       4   Pulse Accumulator Input Edge Interrupt Flag
PACTL           0x1026  Pulse Accumulator Control Register
PACTL.DDRA7      7   Data Direction for Port A Bit 7
PACTL.PAEN       6   Pulse Accumulator System Enable
PACTL.PAMOD      5   Pulse Accumulator Mode
PACTL.PEDGE      4   Pulse Accumulator Edge Control
PACTL.RTR1       1   RTR1 - Real-Time Interrupt Rate
PACTL.RTR0       0   RTR0 - Real-Time Interrupt Rate
PACNT           0x1027  Pulse Accumulator Count Register
SPCR            0x1028  SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable
SPCR.DWOM        5   Port D Wired-OR Mode
SPCR.MSTR        4   Master Mode Select
SPCR.CPOL        3   Clock Polarity
SPCR.CPHA        2   Clock Phase
SPCR.SPR1        1   SPI Clock Rate Selects 1
SPCR.SPR0        0   SPI Clock Rate Selects 0
SPSR            0x1029  SPI Status Register
SPSR.SPIF        7   SPI Transfer Complete Flag
SPSR.WCOL        6   Write Collision
SPSR.MODF        4   Mode Fault (A Mode Fault Terminates SPI Operation)
SPDR            0x102A  SPI Data Register
BAUD            0x102B  SCI Baud Rate Control 3
BAUD.TCLR        7   Clear Baud Rate Counters (TEST)
BAUD.SCP1        5   SCI Baud Rate Prescaler Selects
BAUD.SCP0        4   SCI Baud Rate Prescaler Selects
BAUD.RCKB        3   SCI Baud Rate Clock Check (TEST)
BAUD.SCR2        2   SCI Baud Rate Selects
BAUD.SCR1        1   SCI Baud Rate Selects
BAUD.SCR0        0   SCI Baud Rate Selects
SCCR1           0x102C  SCI Control Register 1
SCCR1.R8         7   Receive Data Bit 8
SCCR1.T8         6   Transmit Data Bit 8
SCCR1.M          4   Mode (Select Character Format)
SCCR1.WAKE       3   Wake Up by Address Mark/Idle
SCCR2           0x102D  SCI Control Register 2
SCCR2.TIE        7   Transmit Interrupt Enable
SCCR2.TCIE       6   Transmit Complete Interrupt Enable
SCCR2.RIE        5   Receiver Interrupt Enable
SCCR2.ILIE       4   Idle Line Interrupt Enable
SCCR2.TE         3   Transmitter Enable
SCCR2.RE         2   Receiver Enable
SCCR2.RWU        1   Receiver Wake Up Control
SCCR2.SBK        0   Send Break
SCSR            0x102E  SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty Flag
SCSR.TC          6   Transmit Complete Flag
SCSR.RDRF        5   Receive Data Register Full Flag
SCSR.IDLE        4   Idle Line Detected Flag
SCSR.OR          3   Overrun Error Flag
SCSR.NF          2   Noise Error Flag
SCSR.FE          1   Framing Error
SCDR            0x102F  SCI Data (Read RDR, Write TDR)
SCDR.R7T7        7
SCDR.R6T6        6
SCDR.R5T5        5
SCDR.R4T4        4
SCDR.R3T3        3
SCDR.R2T2        2
SCDR.R1T1        1
SCDR.R0T0        0
ADCTL           0x1030  A_D Control Register
ADCTL.CCF        7   Conversions Complete Flag
ADCTL.SCAN       5   Continuous Scan Control
ADCTL.MULT       4   Multiple Channel/Single Channel Control
ADCTL.CD         3   Channel Select D
ADCTL.CC         2   Channel Select C
ADCTL.CB         1   Channel Select B
ADCTL.CA         0   Channel Select A
ADR1            0x1031  A_D Result Register 1
ADR2            0x1032  A_D Result Register 2
ADR3            0x1033  A_D Result Register 3
ADR4            0x1034  A_D Result Register 4
RESERVED35      0x1035  RESERVED35
RESERVED36      0x1036  RESERVED36
RESERVED37      0x1037  RESERVED37
RESERVED38      0x1038  RESERVED38
OPTION          0x1039  System Configuration Options
OPTION.ADPU      7   A/D Converter Power-up
OPTION.CSEL      6   Clock Select
OPTION.IRQE      5   IRQ Select Edge-Sensitive Only
OPTION.DLY       4   Enable Oscillator Start-Up Delay on Exit from STOP
OPTION.CME       3   Clock Monitor Enable
OPTION.CR1       1   COP Timer Rate Select 1
OPTION.CR0       0   COP Timer Rate Select 0
COPRST          0x103A  Arm_Reset COP Timer Circuitry
PPROG           0x103B  EEPROM Program Control Register
PPROG.ODD        7   Program Odd Rows in Half of EEPROM (TEST)
PPROG.EVEN       6   Program Even Rows in Half of EEPROM (TEST)
PPROG.BYTE       4   Byte/Other EEPROM Erase Mode
PPROG.ROW        3   Row/All EEPROM Erase Mode
PPROG.ERASE      2   Erase/Normal Control for EEPROM
PPROG.EELAT      1   EEPROM Latch Control
PPROG.EEPGM      0   EEPROM Program Command
HPRIO           0x103C  Highest Priority I-Bit Int and Misc
HPRIO.RBOOT      7   Read Bootstrap ROM
HPRIO.SMOD       6   Special Mode Select
HPRIO.MDA        5   Mode Select A
HPRIO.IRV        4   Internal Read Visibility
HPRIO.PSEL3      3   Priority Select Bits 3
HPRIO.PSEL2      2   Priority Select Bits 2
HPRIO.PSEL1      1   Priority Select Bits 1
HPRIO.PSEL0      0   Priority Select Bits 0
INIT            0x103D  RAM and I_O Mapping Register
INIT.RAM3        7   256-Byte Internal RAM Map Position 3
INIT.RAM2        6   256-Byte Internal RAM Map Position 2
INIT.RAM1        5   256-Byte Internal RAM Map Position 1
INIT.RAM0        4   256-Byte Internal RAM Map Position 0
INIT.REG3        3   64-Byte Register Block Map Position 3
INIT.REG2        2   64-Byte Register Block Map Position 2
INIT.REG1        1   64-Byte Register Block Map Position 1
INIT.REG0        0   64-Byte Register Block Map Position 0
TEST1           0x103E  Factory TEST Control Register
TEST1.TILOP      7   Test Illegal Opcode
TEST1.OCCR       5   Output Condition Code Register to Timer Port
TEST1.CBYP       4   Timer Divider Chain Bypass
TEST1.DISR       3   Disable Resets from COP and Clock Monitor
TEST1.FCM        2   Force Clock Monitor Failure
TEST1.FCOP       1   Force COP Watchdog Failure
TEST1.TCON       0   Test Configuration Register
CONFIG          0x103F  COP, ROM, and EEPROM Enables
CONFIG.NOSEC     3   EEPROM Security Disable
CONFIG.NOCOP     2   COP System Disable
CONFIG.ROMON     1   ROM Enable
CONFIG.EEON      0   EEPROM Enable
RESERVFFC0      0xFFC0  RESERVED
RESERVFFC1      0xFFC1  RESERVED
RESERVFFC2      0xFFC2  RESERVED
RESERVFFC3      0xFFC3  RESERVED
RESERVFFC4      0xFFC4  RESERVED
RESERVFFC5      0xFFC5  RESERVED
RESERVFFC6      0xFFC6  RESERVED
RESERVFFC7      0xFFC7  RESERVED
RESERVFFC8      0xFFC8  RESERVED
RESERVFFC9      0xFFC9  RESERVED
RESERVFFCA      0xFFCA  RESERVED
RESERVFFCB      0xFFCB  RESERVED
RESERVFFCC      0xFFCC  RESERVED
RESERVFFCD      0xFFCD  RESERVED
RESERVFFCE      0xFFCE  RESERVED
RESERVFFCF      0xFFCF  RESERVED
RESERVFFD0      0xFFD0  RESERVED
RESERVFFD1      0xFFD1  RESERVED
RESERVFFD2      0xFFD2  RESERVED
RESERVFFD3      0xFFD3  RESERVED
RESERVFFD4      0xFFD4  RESERVED
RESERVFFD5      0xFFD5  RESERVED


.68HC11A7     
; http://

; RAM=256
; ROM=8K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA RAM      0x0000:0x0100
area BSS  RESERVED 0x0100:0x1000
area DATA FSR      0x1000:0x1040
area BSS  RESERVED 0x1040:0xB600
area DATA EEPROM   0xB600:0xB800
area BSS  RESERVED 0xB800:0xE000
area DATA ROM      0xE000:0xFFBF
area DATA USER_VEC 0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS

RESERVFFC0           0xFFC0
RESERVFFC1           0xFFC1
RESERVFFC2           0xFFC2
RESERVFFC3           0xFFC3
RESERVFFC4           0xFFC4
RESERVFFC5           0xFFC5
RESERVFFC6           0xFFC6
RESERVFFC7           0xFFC7
RESERVFFC8           0xFFC8
RESERVFFC9           0xFFC9
RESERVFFCA           0xFFCA
RESERVFFCB           0xFFCB
RESERVFFCC           0xFFCC
RESERVFFCD           0xFFCD
RESERVFFCE           0xFFCE
RESERVFFCF           0xFFCF
RESERVFFD0           0xFFD0
RESERVFFD1           0xFFD1
RESERVFFD2           0xFFD2
RESERVFFD3           0xFFD3
RESERVFFD4           0xFFD4
RESERVFFD5           0xFFD5


.68HC11A8     
; MC68HC11A8TS/D http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11A8.pdf
; MC68HC11A8.pdf

; RAM=256
; ROM=8K
; EPROM=0
; EEPROM=512


; MEMORY MAP
area DATA RAM         0x0000:0x0100
area BSS  RESERVED    0x0100:0x1000
area DATA FSR         0x1000:0x1040
area BSS  RESERVED    0x1040:0xB600
area DATA EEPROM      0xB600:0xB800
area BSS  RESERVED    0xB800:0xE000
area DATA ROM         0xE000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA            0x1000     Port A data
PORTA.PA7     	  7   Port A Data Bits 7
PORTA.PA6         6   Port A Data Bits 6
PORTA.PA5         5   Port A Data Bits 5
PORTA.PA4         4   Port A Data Bits 4
PORTA.PA3         3   Port A Data Bits 3
PORTA.PA2         2   Port A Data Bits 2
PORTA.PA1         1   Port A Data Bits 1
PORTA.PA0         0   Port A Data Bits 0
RESERV1001       0x1001     RESERVED
PIOC             0x1002     Parallel I_O Control Register
PIOC.STAF         7   Strobe A Interrupt Status Flag
PIOC.STAI         6   Strobe A Interrupt Enable Mask
PIOC.CWOM         5   Port C Wire-OR Mode (affects all eight port C pins)
PIOC.HNDS         4   Handshake Mode
PIOC.OIN          3   Output or Input Handshake Select
PIOC.PLS          2   Pulse/Interlocked Handshake Operation
PIOC.EGA          1   Active Edge for Strobe A
PIOC.INVB         0   Invert Strobe B
PORTC            0x1003     Port C Data
PORTC.PC7         7   Port C Data Bits 7
PORTC.PC6         6   Port C Data Bits 6
PORTC.PC5         5   Port C Data Bits 5
PORTC.PC4         4   Port C Data Bits 4
PORTC.PC3         3   Port C Data Bits 3
PORTC.PC2         2   Port C Data Bits 2
PORTC.PC1         1   Port C Data Bits 1
PORTC.PC0         0   Port C Data Bits 0
PORTB            0x1004     Output Port B
PORTB.PB7         7   Port B Data Bits 7
PORTB.PB6         6   Port B Data Bits 6
PORTB.PB5         5   Port B Data Bits 5
PORTB.PB4         4   Port B Data Bits 4
PORTB.PB3         3   Port B Data Bits 3
PORTB.PB2         2   Port B Data Bits 2
PORTB.PB1         1   Port B Data Bits 1
PORTB.PB0         0   Port B Data Bits 0
PORTCL           0x1005     Alternate Latched Port C
PORTCL.PCL7       7
PORTCL.PCL6       6
PORTCL.PCL5       5
PORTCL.PCL4       4
PORTCL.PCL3       3
PORTCL.PCL2       2
PORTCL.PCL1       1
PORTCL.PCL0       0
RESERV1006       0x1006     RESERVED
DDRC             0x1007     Data Direction for Port C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x1008     I_O Port D
PORTD.PD5         5   Port D Data Bits 5
PORTD.PD4         4   Port D Data Bits 4
PORTD.PD3         3   Port D Data Bits 3
PORTD.PD2         2   Port D Data Bits 2
PORTD.PD1         1   Port D Data Bits 1
PORTD.PD0         0   Port D Data Bits 0
DDRD             0x1009     Data Direction for Port D
DDRD.DDD5         5   Data Direction for Port D Bit 5
DDRD.DDD4         4   Data Direction for Port D Bit 4
DDRD.DDD3         3   Data Direction for Port D Bit 3
DDRD.DDD2         2   Data Direction for Port D Bit 2
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
PORTE            0x100A     Input Port E
PORTE.PE7         7   Port E Data Bits 7
PORTE.PE6         6   Port E Data Bits 6
PORTE.PE5         5   Port E Data Bits 5
PORTE.PE4         4   Port E Data Bits 4
PORTE.PE3         3   Port E Data Bits 3
PORTE.PE2         2   Port E Data Bits 2
PORTE.PE1         1   Port E Data Bits 1
PORTE.PE0         0   Port E Data Bits 0
CFORC            0x100B     Compare Force Register
CFORC.FOC1        7   Write ones to Force Compare 1
CFORC.FOC2        6   Write ones to Force Compare 2
CFORC.FOC3        5   Write ones to Force Compare 3
CFORC.FOC4        4   Write ones to Force Compare 4
CFORC.FOC5        3   Write ones to Force Compare 5
OC1M             0x100C     OC1 Action Mask Register
OC1M.OC1M7        7
OC1M.OC1M6        6
OC1M.OC1M5        5
OC1M.OC1M4        4
OC1M.OC1M3        3
OC1D             0x100D      OC1 Action Data Register
OC1D.OC1D7        7
OC1D.OC1D6        6
OC1D.OC1D5        5
OC1D.OC1D4        4
OC1D.OC1D3        3
TCNTH            0x100E     Timer Counter Register
TCNTL            0x100F     Timer Counter Register
TIC1H            0x1010     Input Capture 1 Register
TIC1L            0x1011     Input Capture 1 Register
TIC2H            0x1012     Input Capture 2 Register
TIC2L            0x1013     Input Capture 2 Register
TIC3H            0x1014     Input Capture 3 Register
TIC3L            0x1015     Input Capture 3 Register
TOC1H            0x1016     Output Compare 1 Register
TOC1L            0x1017     Output Compare 1 Register
TOC2H            0x1018     Output Compare 2 Register
TOC2L            0x1019     Output Compare 2 Register
TOC3H            0x101A     Output Compare 3 Register
TOC3L            0x101B     Output Compare 3 Register
TOC4H            0x101C     Output Compare 4 Register
TOC4L            0x101D     Output Compare 4 Register
TCO5H            0x101E     Output Compare 5 Register
TCO5L            0x101F     Output Compare 5 Register
TCTL1            0x1020     Timer Control Register 1
TCTL1.OM2         7   OM2 Output Mode
TCTL1.OL2         6   OL2 Output Level
TCTL1.OM3         5   OM3 Output Mode
TCTL1.OL3         4   OL3 Output Level
TCTL1.OM4         3   OM4 Output Mode
TCTL1.OL4         2   OL4 Output Level
TCTL1.OM5         1   OM5 Output Mode
TCTL1.OL5         0   OL5 Output Level
TCTL2            0x1021     Timer Control Register 2
TCTL2.EDG1B       5
TCTL2.EDG1A       4
TCTL2.EDG2B       3
TCTL2.EDG2A       2
TCTL2.EDG3B       1
TCTL2.EDG3A       0
TMSK1            0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I        7   Output Compare 1 Interrupt Enable
TMSK1.OC2I        6   Output Compare 2 Interrupt Enable
TMSK1.OC3I        5   Output Compare 3 Interrupt Enable
TMSK1.OC4I        4   Output Compare 4 Interrupt Enable
TMSK1.OC5I        3   Output Compare 5 Interrupt Enable
TMSK1.IC1I        2   Input Capture 1 Interrupt Enable
TMSK1.IC2I        1   Input Capture 2 Interrupt Enable
TMSK1.IC3I        0   Input Capture 3 Interrupt Enable
TFLG1            0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F        7   Output Compare 1 Flag
TFLG1.OC2F        6   Output Compare 2 Flag
TFLG1.OC3F        5   Output Compare 3 Flag
TFLG1.OC4F        4   Output Compare 4 Flag
TFLG1.OC5F        3   Output Compare 5 Flag
TFLG1.IC1F        2   Input Capture 1 Flag
TFLG1.IC2F        1   Input Capture 2 Flag
TFLG1.IC3F        0   Input Capture 3 Flag
TMSK2            0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable
TMSK2.RTII        6   Real-Time Interrupt Enable
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII        4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1         1   Timer Prescaler Select bit 1
TMSK2.PR0         0   Timer Prescaler Select bit 0
TFLG2            0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF         7   Timer Overflow Flag
TFLG2.RTIF        6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Interrupt Flag
PACTL            0x1026     Pulse Accumulator Control Register
PACTL.DDRA7       7   Data Direction for Port A Bit 7
PACTL.PAEN        6   Pulse Accumulator System Enable
PACTL.PAMOD       5   Pulse Accumulator Mode
PACTL.PEDGE       4   Pulse Accumulator Edge Control
PACTL.RTR1        1   RTR1 - Real-Time Interrupt Rate
PACTL.RTR0        0   RTR0 - Real-Time Interrupt Rate
PACNT            0x1027     Pulse Accumulator Count Register
SPCR             0x1028     SPI Control Register
SPCR.SPIE         7   Serial Peripheral Interrupt Enable
SPCR.SPE          6   Serial Peripheral System Enable
SPCR.DWOM         5   Port D Wired-OR Mode
SPCR.MSTR         4   Master Mode Select
SPCR.CPOL         3   Clock Polarity
SPCR.CPHA         2   Clock Phase
SPCR.SPR1         1   SPI Clock Rate Selects bit 1
SPCR.SPR0         0   SPI Clock Rate Selects bit 0
SPSR             0x1029     SPI Status Register
SPSR.SPIF         7   SPI Transfer Complete Flag
SPSR.WCOL         6   Write Collision
SPSR.MODF         4   Mode Fault (A Mode Fault Terminates SPI Operation)
SPDR             0x102A     SPI Data Register
BAUD             0x102B     SCI Baud Rate Control 3
BAUD.TCLR         7    Clear Baud Rate Counters (TEST)
BAUD.SCP1         5    SCI Baud Rate Prescaler Selects
BAUD.SCP0         4    SCI Baud Rate Prescaler Selects
BAUD.RCKB         3    SCI Baud Rate Clock Check (TEST)
BAUD.SCR2         2    SCI Baud Rate Selects bit 2
BAUD.SCR1         1    SCI Baud Rate Selects bit 1
BAUD.SCR0         0    SCI Baud Rate Selects bit 0
SCCR1            0x102C     SCI Control Register 1
SCCR1.R8          7   Receive Data Bit 8
SCCR1.T8          6   Transmit Data Bit 8
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake Up by Address Mark/Idle
SCCR2            0x102D     SCI Control Register 2
SCCR2.TIE         7   Transmit Interrupt Enable
SCCR2.TCIE        6   Transmit Complete Interrupt Enable
SCCR2.RIE         5   Receiver Interrupt Enable
SCCR2.ILIE        4   Idle Line Interrupt Enable
SCCR2.TE          3   Transmitter Enable
SCCR2.RE          2   Receiver Enable
SCCR2.RWU         1   Receiver Wake Up Control
SCCR2.SBK         0   Send Break
SCSR             0x102E     SCI Status Register
SCSR.TDRE         7   Transmit Data Register Empty Flag
SCSR.TC           6   Transmit Complete Flag
SCSR.RDRF         5   Receive Data Register Full Flag
SCSR.IDLE         4   Idle Line Detected Flag
SCSR.OR           3   Overrun Error Flag
SCSR.NF           2   Noise Error Flag
SCSR.FE           1   Framing Error
SCDR             0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7         7
SCDR.R6T6         6
SCDR.R5T5         5
SCDR.R4T4         4
SCDR.R3T3         3
SCDR.R2T2         2
SCDR.R1T1         1
SCDR.R0T0         0
ADCTL            0x1030     A_D Control Register
ADCTL.CCF         7   Conversions Complete Flag
ADCTL.SCAN        5   Continuous Scan Control
ADCTL.MULT        4   Multiple Channel/Single Channel Control
ADCTL.CD          3   Channel Select D
ADCTL.CC          2   Channel Select C
ADCTL.CB          1   Channel Select B
ADCTL.CA          0   Channel Select A
ADR1             0x1031     A_D Result Register 1
ADR2             0x1032     A_D Result Register 2
ADR3             0x1033     A_D Result Register 3
ADR4             0x1034     A_D Result Register 4
RESERV1035       0x1035     RESERVED35
RESERV1036       0x1036     RESERVED36
RESERV1037       0x1037     RESERVED37
RESERV1038       0x1038     RESERVED38
OPTION           0x1039     System Configuration Options
OPTION.ADPU       7   A/D Converter Power-up
OPTION.CSEL       6   Clock Select
OPTION.IRQE       5   IRQ Select Edge-Sensitive Only
OPTION.DLY        4   Enable Oscillator Start-Up Delay on Exit from STOP
OPTION.CME        3   Clock Monitor Enable
OPTION.CR1        1   COP Timer Rate Select bit 1
OPTION.CR0        0   COP Timer Rate Select bit 0
COPRST           0x103A     Arm_Reset COP Timer Circuitry
PPROG            0x103B     EEPROM Program Control Register
PPROG.ODD         7   Program Odd Rows in Half of EEPROM (TEST)
PPROG.EVEN        6   Program Even Rows in Half of EEPROM (TEST)
PPROG.BYTE        4   Byte/Other EEPROM Erase Mode
PPROG.ROW         3   Row/All EEPROM Erase Mode
PPROG.ERASE       2   Erase/Normal Control for EEPROM
PPROG.EELAT       1   EEPROM Latch Control
PPROG.EEPGM       0   EEPROM Program Command
HPRIO            0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT       7   Read Bootstrap ROM
HPRIO.SMOD        6   Special Mode Select
HPRIO.MDA         5   Mode Select A
HPRIO.IRV         4   Internal Read Visibility
HPRIO.PSEL3       3   Priority Select Bit 3
HPRIO.PSEL2       2   Priority Select Bit 2
HPRIO.PSEL1       1   Priority Select Bit 1
HPRIO.PSEL0       0   Priority Select Bit 0
INIT             0x103D     RAM and I_O Mapping Register
INIT.RAM3         7   256-Byte Internal RAM Map Position Bit 3
INIT.RAM2         6   256-Byte Internal RAM Map Position Bit 2
INIT.RAM1         5   256-Byte Internal RAM Map Position Bit 1
INIT.RAM0         4   256-Byte Internal RAM Map Position Bit 0
INIT.REG3         3   64-Byte Register Block Map Position Bit 3
INIT.REG2         2   64-Byte Register Block Map Position Bit 2
INIT.REG1         1   64-Byte Register Block Map Position Bit 1
INIT.REG0         0   64-Byte Register Block Map Position Bit 0
TEST1            0x103E     Factory TEST Control Register
TEST1.TILOP       7   Test Illegal Opcode
TEST1.OCCR        5   Output Condition Code Register to Timer Port
TEST1.CBYP        4   Timer Divider Chain Bypass
TEST1.DISR        3   Disable Resets from COP and Clock Monitor
TEST1.FCM         2   Force Clock Monitor Failure
TEST1.FCOP        1   Force COP Watchdog Failure
TEST1.TCON        0   Test Configuration Register
CONFIG           0x103F     COP, ROM, and EEPROM Enables
CONFIG.NOSEC      3   EEPROM Security Disable
CONFIG.NOCOP      2   COP System Disable
CONFIG.ROMON      1   ROM Enable
CONFIG.EEON       0   EEPROM Enable
RESERVFFC0       0xFFC0     RESERVED
RESERVFFC1       0xFFC1     RESERVED
RESERVFFC2       0xFFC2     RESERVED
RESERVFFC3       0xFFC3     RESERVED
RESERVFFC4       0xFFC4     RESERVED
RESERVFFC5       0xFFC5     RESERVED
RESERVFFC6       0xFFC6     RESERVED
RESERVFFC7       0xFFC7     RESERVED
RESERVFFC8       0xFFC8     RESERVED
RESERVFFC9       0xFFC9     RESERVED
RESERVFFCA       0xFFCA     RESERVED
RESERVFFCB       0xFFCB     RESERVED
RESERVFFCC       0xFFCC     RESERVED
RESERVFFCD       0xFFCD     RESERVED
RESERVFFCE       0xFFCE     RESERVED
RESERVFFCF       0xFFCF     RESERVED
RESERVFFD0       0xFFD0     RESERVED
RESERVFFD1       0xFFD1     RESERVED
RESERVFFD2       0xFFD2     RESERVED
RESERVFFD3       0xFFD3     RESERVED
RESERVFFD4       0xFFD4     RESERVED
RESERVFFD5       0xFFD5     RESERVED


.68HC11C0
; MC68HC11C0TS/D http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11C0TS.pdf
; c0.pdf

; RAM=256
; ROM=1K
; EPROM=0
; EEPROM=0  


; MEMORY MAP
area DATA FSR         0x0000:0x0080
area BSS  RESERVED    0x0080:0x0400
area DATA RAM         0x0400:0x0500
area BSS  RESERVED    0x0500:0xBC00
area DATA BOOT_ROM_1  0xBC00:0xC000
area BSS  RESERVED    0xC000:0xFC00
area DATA BOOT_ROM_2  0xFC00:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA                0x0000     Port A data
PORTA.PA7             7   Port A Data Bit 7
PORTA.PA6             6   Port A Data Bit 6
PORTA.PA5             5   Port A Data Bit 5
PORTA.PA4             4   Port A Data Bit 4
PORTA.PA3             3   Port A Data Bit 3
PORTA.PA2             2   Port A Data Bit 2
PORTA.PA1             1   Port A Data Bit 1
PORTA.PA0             0   Port A Data Bit 0
DDRA                 0x0001     Data Direction Port A
DDRA.DDA7             7   Data Direction for Port A Bit 7
DDRA.DDA6             6   Data Direction for Port A Bit 6
DDRA.DDA5             5   Data Direction for Port A Bit 5
DDRA.DDA4             4   Data Direction for Port A Bit 4
DDRA.DDA3             3   Data Direction for Port A Bit 3
DDRA.DDA2             2   Data Direction for Port A Bit 2
DDRA.DDA1             1   Data Direction for Port A Bit 1
DDRA.DDA0             0   Data Direction for Port A Bit 0
PORTF                0x0002     Port F data
PORTF.PF6             6   Port F Data Bit 6
PORTF.PF5             5   Port F Data Bit 5
PORTF.PF4             4   Port F Data Bit 4
PORTF.PF3             3   Port F Data Bit 3
PORTF.PF2             2   Port F Data Bit 2
PORTF.PF1             1   Port F Data Bit 1
PORTF.PF0             0   Port F Data Bit 0
DDRF                 0x0003     Data Direction Port F
DDRF.DDF6             6   Data Direction for Port F Bit 6
DDRF.DDF5             5   Data Direction for Port F Bit 5
DDRF.DDF4             4   Data Direction for Port F Bit 4
DDRF.DDF3             3   Data Direction for Port F Bit 3
DDRF.DDF2             2   Data Direction for Port F Bit 2
DDRF.DDF1             1   Data Direction for Port F Bit 1
DDRF.DDF0             0   Data Direction for Port F Bit 0
FISTAT               0x0004     Port F Interrupt Status
FISTAT.IS7            7   IRQ7 Status
FISTAT.IS6            6   IRQ6 Status
FISTAT.IS5            5   IRQ5 Status
FISTAT.IS4            4   IRQ4 Status
FISTAT.IS3            3   IRQ3 Status
FISTAT.IS2            2   IRQ2 Status
FISTAT.IS1            1   IRQ1 Status
FISTAT.IS0            0   IRQ0 Status
FINTEN               0x0005     Port F Interrupt Enable
FINTEN.IE6            6   IRQ6 Enable
FINTEN.IE5            5   IRQ5 Enable
FINTEN.IE4            4   IRQ4 Enable
FINTEN.IE3            3   IRQ3 Enable
FINTEN.IE2            2   IRQ2 Enable
FINTEN.IE1            1   IRQ1 Enable
FINTEN.IE0            0   IRQ0 Enable
RESERV0006           0x0006     RESERVED
DIOCTL               0x0007     Port D I/O Control
DIOCTL.DIO5           5   Port D I/O Control for Port D Bits 5
DIOCTL.DIO4           4   Port D I/O Control for Port D Bits 4
DIOCTL.DIO3           3   Port D I/O Control for Port D Bits 3
DIOCTL.DIO2           2   Port D I/O Control for Port D Bits 2
DIOCTL.DIO0           0   Port D I/O Control for Port D Bits 0
PORTD                0x0008     Port D Data
PORTD.PD5             5   Port D Data Bit 5
PORTD.PD4             4   Port D Data Bit 4
PORTD.PD3             3   Port D Data Bit 3
PORTD.PD2             2   Port D Data Bit 2
PORTD.PD1             1   Port D Data Bit 1
PORTD.PD0             0   Port D Data Bit 0
DDRD                 0x0009     Data Direction Port D
DDRD.DDD5             5   Data Direction for Port D Bit 5
DDRD.DDD4             4   Data Direction for Port D Bit 4
DDRD.DDD3             3   Data Direction for Port D Bit 3
DDRD.DDD2             2   Data Direction for Port D Bit 2
DDRD.DDD1             1   Data Direction for Port D Bit 1
DDRD.DDD0             0   Data Direction for Port D Bit 0
PORTE                0x000A     Port E Data
PORTE.PE3             3   Port E Data Bit 3
PORTE.PE2             2   Port E Data Bit 2
PORTE.PE1             1   Port E Data Bit 1
PORTE.PE0             0   Port E Data Bit 0
CFORC                0x000B     Timer Compare Force
CFORC.FOC1            7   Force Output Compare 1
CFORC.FOC2            6   Force Output Compare 2
CFORC.FOC3            5   Force Output Compare 3
CFORC.FOC4            4   Force Output Compare 4
CFORC.FOC5            3   Force Output Compare 5
OC1M                 0x000C     Output Compare 1 Mask
OC1M.OC1M7            7
OC1M.OC1M6            6
OC1M.OC1M5            5
OC1M.OC1M4            4
OC1M.OC1M3            3 
OC1D                 0x000D     Output Compare 1 Data
OC1D.OC1D7            7
OC1D.OC1D6            6
OC1D.OC1D5            5
OC1D.OC1D4            4
OC1D.OC1D3            3
TCNTH                0x000E     Timer Count High
TCNTL                0x000F     Timer Count Low
TIC1H                0x0010     Timer Input Capture 1 High
TIC1L                0x0011     Timer Input Capture 1 Low
TIC2H                0x0012     Timer Input Capture 2 High
TIC2L                0x0013     Timer Input Capture 2 Low
TIC3H                0x0014     Timer Input Capture 3 High
TIC3L                0x0015     Timer Input Capture 3 Low
TOC1H                0x0016     Timer Output Compare 1 High
TOC1L                0x0017     Timer Output Compare 1 Low
TOC2H                0x0018     Timer Output Compare 2 High
TOC2L                0x0019     Timer Output Compare 2 Low
TOC3H                0x001A     Timer Output Compare 3 High
TOC3L                0x001B     Timer Output Compare 3 Low
TOC4H                0x001C     Timer Output Compare 4 High
TOC4L                0x001D     Timer Output Compare 4 Low
TI4O5H               0x001E     Timer Input Capture 4/Output Compare 5 High
TI4O5L               0x001F     Timer Input Capture 4/Output Compare 5 Low
TCTL1                0x0020     Timer Control 1
TCTL1.OM2             7   Output Mode 2
TCTL1.OL2             6   Output Level 2
TCTL1.OM3             5   Output Mode 3
TCTL1.OL3             4   Output Level 3
TCTL1.OM4             3   Output Mode 4
TCTL1.OL4             2   Output Level 4
TCTL1.OM5             1   Output Mode 5
TCTL1.OL5             0   Output Level 5
TCTL2                0x0021     Timer Control 2
TCTL2.EDG4B           7
TCTL2.EDG4A           6
TCTL2.EDG1B           5
TCTL2.EDG1A           4
TCTL2.EDG2B           3
TCTL2.EDG2A           2
TCTL2.EDG3B           1
TCTL2.EDG3A           0
TMSK1                0x0022     Timer Interrupt Mask 1
TMSK1.OC1I            7   Output Compare 1 Interrupt Enable
TMSK1.OC2I            6   Output Compare 2 Interrupt Enable
TMSK1.OC3I            5   Output Compare 3 Interrupt Enable
TMSK1.OC4I            4   Output Compare 4 Interrupt Enable
TMSK1.I4O5I           3   Input Capture 4 or Output Compare 5 Interrupt Enable
TMSK1.IC1I            2   Input Capture 1 Interrupt Enable
TMSK1.IC2I            1   Input Capture 2 Interrupt Enable
TMSK1.IC3I            0   Input Capture 3 Interrupt Enable
TFLG1                0x0023     Timer Interrupt Flag 1
TFLG1.OC1F            7   Output Compare 1 Flag
TFLG1.OC2F            6   Output Compare 2 Flag
TFLG1.OC3F            5   Output Compare 3 Flag
TFLG1.OC4F            4   Output Compare 4 Flag
TFLG1.I4O5F           3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F            2   Input Capture 1 Flag
TFLG1.IC2F            1   Input Capture 2 Flag
TFLG1.IC3F            0   Input Capture 3 Flag
TMSK2                0x0024     Timer Interrupt Mask 2
TMSK2.TOI             7   Timer Overflow Interrupt Enable
TMSK2.RTII            6   Real-time Interrupt Enable
TMSK2.PAOVI           5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII            4   Pulse Accumulator Input Interrupt Enable
TMSK2.PR1             1   Timer Prescaler Select
TMSK2.PR0             0   Timer Prescaler Select
TFLG2                0x0025     Timer Interrupt Flag 2
TFLG2.TOF             7   Timer Overflow Flag
TFLG2.RTIF            6   Real-Time Interrupt Flag
TFLG2.PAOVF           5   Pulse Accumulator Overflow Flag
TFLG2.PAIF            4   Pulse Accumulator Input Edge Flag
PACTL                0x0026     Pulse Accumulator Control
PACTL.PAEN            6   Pulse Accumulator System Enable
PACTL.PAMOD           5   Pulse Accumulator Mode
PACTL.PEDGE           4   Pulse Accumulator Edge Control
PACTL.I4O5            2   Input Capture 4/Output Compare 5
PACTL.RTR1            1   Real-Time Interrupt (RTI) Rate Bit 1
PACTL.RTR0            0   Real-Time Interrupt (RTI) Rate Bit 0
PACNT                0x0027     Pulse Accumulator Counter
SPCR                 0x0028     Serial Peripferal Control Register
SPCR.SPIE             7   Serial Peripheral Interrupt Enable
SPCR.SPE              6   Serial Peripheral System Enable
SPCR.MSTR             4   Master Mode Select
SPCR.CPOL             3   Clock Polarity
SPCR.CPHA             2   Clock Phase
SPCR.SPR1             1   SPI Clock Rate Selects Bit 1
SPCR.SPR0             0   SPI Clock Rate Selects Bit 0
SPSR                 0x0029     Serial Peripheral Status Register
SPSR.SPIF             7   SPI Transfer Complete Flag
SPSR.WCOL             6   Write Collision Error Flag
SPSR.MODF             4   Mode Fault (Mode fault terminates SPI operation)
SPDR                 0x002A     SPI Data Register
BAUD                 0x002B     Baud Rate Control Register
BAUD.TCLR             7   Clear Baud Rate Counters
BAUD.SCP1             5   SCI Baud Rate Prescaler Selects Bit 1
BAUD.SCP0             4   SCI Baud Rate Prescaler Selects Bit 0
BAUD.RCKB             3   SCI Baud Rate Clock Check
BAUD.SCR2             2   SCI Baud Rate Selects Bit 2
BAUD.SCR1             1   SCI Baud Rate Selects Bit 1
BAUD.SCR0             0   SCI Baud Rate Selects Bit 0
SCCR1                0x002C     SCI Control Register 1
SCCR1.R8              7   Receive Data Bit 8
SCCR1.T8              6   Transmit Data Bit 8
SCCR1.M               4   Mode (Select Character Format)
SCCR1.WAKE            3   Wakeup by Address Mark/Idle
SCCR2                0x002D     SCI Control Register 2
SCCR2.TIE             7   Transmit Interrupt Enable
SCCR2.TCIE            6   Transmit Complete Interrupt Enable
SCCR2.RIE             5   Receiver Interrupt Enable
SCCR2.ILIE            4   Idle Line Interrupt Enable
SCCR2.TE              3   Transmitter Enable
SCCR2.RE              2   Receiver Enable
SCCR2.RWU             1   Receiver Wakeup Control
SCCR2.SBK             0   Send Break
SCSR                 0x002E     SCI Status Register
SCSR.TDRE             7   Transmit Data Register Empty Flag
SCSR.TC               6   Transmit Complete Flag
SCSR.RDRF             5   Receive Data Register Full Flag
SCSR.IDLE             4   Idle Line Detected Flag
SCSR.OR               3   Overrun Error Flag
SCSR.NF               2   Noise Error Flag
SCSR.FE               1   Framing Error
SCDR                 0x002F     SCI Data Register
SCDR.R7T7             7
SCDR.R6T6             6
SCDR.R5T5             5
SCDR.R4T4             4
SCDR.R3T3             3
SCDR.R2T2             2
SCDR.R1T1             1
SCDR.R0T0             0
ADCTL                0x0030     A/D Control/Status
ADCTL.CCF             7   Conversions Complete Flag
ADCTL.SCAN            5   Continuous Scan Control
ADCTL.MULT            4   Multiple Channel/Single Channel Control
ADCTL.CD              3   Channel Select D
ADCTL.CC              2   Channel Select C
ADCTL.CB              1   Channel Select B
ADCTL.CA              0   Channel Select A
ADR1                 0x0031     A/D Results 1
ADR2                 0x0032     A/D Results 2
ADR3                 0x0033     A/D Results 3
ADR4                 0x0034     A/D Results 4
RESERV0035           0x0035     RESERVED
RESERV0036           0x0036     RESERVED
INIT2                0x0037     RAM Mapping
INIT2.RAM15           7   RAM15 - Internal RAM Map Position
INIT2.RAM14           6   RAM14 - Internal RAM Map Position
INIT2.RAM13           5   RAM13 - Internal RAM Map Position
INIT2.RAM12           4   RAM12 - Internal RAM Map Position
INIT2.RAM11           3   RAM11 - Internal RAM Map Position
INIT2.RAM10           2   RAM10 - Internal RAM Map Position
OPT2                 0x0038     System Configuration Options 2
OPT2.IRVNE            4   Internal Read Visibility/Not E
OPTION               0x0039     System Configuration Options
OPTION.ADPU           7   Analog-to-Digital Converter Power Up
OPTION.CSEL           6   Clock Select
OPTION.IRQE           5   IRQ Select Edge Sensitive Only
OPTION.DLY            4   Enable Oscillator Start-Up Delay on Exit from STOP
OPTION.CME            3   Clock Monitor Enable
OPTION.CR1            1   COP Timer Rate Select bit 1
OPTION.CR0            0   COP Timer Rate Select bit 0
COPRST               0x003A     Arm/Reset COP Timer Circuitry
HPRIO                0x003C     Highest Priority I-Bit Interrupt and Miscellaneous
HPRIO.RBOOT           7   Read Bootstrap ROM
HPRIO.SMOD            6   Special Mode Select
HPRIO.MDA             5   Mode Select A
HPRIO.PSEL3           3   Priority Select Bits 3
HPRIO.PSEL2           2   Priority Select Bits 2
HPRIO.PSEL1           1   Priority Select Bits 1
HPRIO.PSEL0           0   Priority Select Bits 0
INIT                 0x003D     Register Mapping
INIT.REG15            7   Internal Register Map Position 15
INIT.REG14            6   Internal Register Map Position 14
INIT.REG13            5   Internal Register Map Position 13
INIT.REG12            4   Internal Register Map Position 12
INIT.REG11            3   Internal Register Map Position 11
INIT.REG10            2   Internal Register Map Position 10
TEST1                0x003E     TEST1
TEST1.TILOP           7
TEST1.OCCR            5
TEST1.CBYP            4
TEST1.DISR            3
TEST1.FCM             2
TEST1.FCOP            1
TEST1.TCON            0
CONFIG               0x003F     System Configuration Register
CONFIG.RWMC           5   Read/Write Mode Strobe Mode Control
CONFIG.NOCOP          2   COP Watchdog Timer Disable
CONFIG.RAMON          1   RAM Enable
VCSADR               0x0040     Vector Chip Select Base Address
VCSADR.VA15           7   Vector Chip Select Address 15
VCSADR.VA14           6   Vector Chip Select Address 14
VCSADR.VA13           5   Vector Chip Select Address 13
VCSADR.VA12           4   Vector Chip Select Address 12
VCSADR.VA11           3   Vector Chip Select Address 11
VCSADR.VA10           2   Vector Chip Select Address 10
RESERV0041           0x0041     RESERVED
PGSADR               0x0042     Program Chip Select Starting Address
PGSADR.PSA15          7   Program Chip Select Starting Address 15
PGSADR.PSA14          6   Program Chip Select Starting Address 14
PGSADR.PSA13          5   Program Chip Select Starting Address 13
PGSADR.PSA12          4   Program Chip Select Starting Address 12
PGSADR.PSA11          3   Program Chip Select Starting Address 11
PGSADR.PSA10          2   Program Chip Select Starting Address 10
PGSADR.PSTHA          1   Program/Vector Chip Select Clock Stretch Select A
PGSADR.PSTHB          0   Program/Vector Chip Select Clock Stretch Select B
PGEADR               0x0043     Program Chip Select Ending Address
PGEADR.PEA15          7   Program Chip Select Ending Address 15
PGEADR.PEA14          6   Program Chip Select Ending Address 14
PGEADR.PEA13          5   Program Chip Select Ending Address 13
PGEADR.PEA12          4   Program Chip Select Ending Address 12
PGEADR.PEA11          3   Program Chip Select Ending Address 11
PGEADR.PEA10          2   Program Chip Select Ending Address 10
MXHADR               0x0044     Memory Expansion Address High
MXHADR.XA17           1   Memory Expansion Address 17
MXHADR.XA16           0   Memory Expansion Address 16
MXLADR               0x0045     Memory Expansion Address Low
MXLADR.XA15           7   Memory Expansion Address 15
MXLADR.XA14           6   Memory Expansion Address 14
MXLADR.XA13           5   Memory Expansion Address 13
MXLADR.XA12           4   Memory Expansion Address 12
MXLADR.XA11           3   Memory Expansion Address 11
MXLADR.XA10           2   Memory Expansion Address 10
GP1SADR              0x0046     General-Purpose Chip Select 1 Starting Address
GP1SADR.GS1A15        7   Program Chip Select Starting Address 15
GP1SADR.GS1A14        6   Program Chip Select Starting Address 14
GP1SADR.GS1A13        5   Program Chip Select Starting Address 13
GP1SADR.GS1A12        4   Program Chip Select Starting Address 12
GP1SADR.GS1A11        3   Program Chip Select Starting Address 11
GP1SADR.GS1A10        2   Program Chip Select Starting Address 10
GP1SADR.G1STHA        1   Program Chip Select Clock Stretch Select A
GP1SADR.G1STHB        0   Program Chip Select Clock Stretch Select B
GP1EADR              0x0047     General-Purpose Chip Select 1 Ending Address
GP1EADR.GE1A15        7   Program Chip Select Ending Address 15
GP1EADR.GE1A14        6   Program Chip Select Ending Address 14
GP1EADR.GE1A13        5   Program Chip Select Ending Address 13
GP1EADR.GE1A12        4   Program Chip Select Ending Address 12
GP1EADR.GE1A11        3   Program Chip Select Ending Address 11
GP1EADR.GE1A10        2   Program Chip Select Ending Address 10
GP2SADR              0x0048     General-Purpose Chip Select 2 Starting Address
GP2SADR.GS2A15        7   Program Chip Select Starting Address 15
GP2SADR.GS2A14        6   Program Chip Select Starting Address 14
GP2SADR.GS2A13        5   Program Chip Select Starting Address 13
GP2SADR.GS2A12        4   Program Chip Select Starting Address 12
GP2SADR.GS2A11        3   Program Chip Select Starting Address 11
GP2SADR.GS2A10        2   Program Chip Select Starting Address 10
GP2SADR.G2STHA        1   Program Chip Select Clock Stretch Select A
GP2SADR.G2STHB        0   Program Chip Select Clock Stretch Select B
GP2EADR              0x0049     General-Purpose Chip Select 2 Ending Address
GP2EADR.GE2A15        7   Program Chip Select Ending Address 15
GP2EADR.GE2A14        6   Program Chip Select Ending Address 14
GP2EADR.GE2A13        5   Program Chip Select Ending Address 13
GP2EADR.GE2A12        4   Program Chip Select Ending Address 12
GP2EADR.GE2A11        3   Program Chip Select Ending Address 11
GP2EADR.GE2A10        2   Program Chip Select Ending Address 10
GP3SADR              0x004A     General-Purpose Chip Select 3 Starting Address
GP3SADR.GS3A15        7   Program Chip Select Starting Address 15
GP3SADR.GS3A14        6   Program Chip Select Starting Address 14
GP3SADR.GS3A13        5   Program Chip Select Starting Address 13
GP3SADR.GS3A12        4   Program Chip Select Starting Address 12
GP3SADR.GS3A11        3   Program Chip Select Starting Address 11
GP3SADR.GS3A10        2   Program Chip Select Starting Address 10
GP3SADR.G3STHA        1   Program Chip Select Clock Stretch Select A
GP3SADR.G3STHB        0   Program Chip Select Clock Stretch Select B
GP3EADR              0x004B     General-Purpose Chip Select 3 Ending Address
GP3EADR.GE3A15        7   Program Chip Select Ending Address 15
GP3EADR.GE3A14        6   Program Chip Select Ending Address 14
GP3EADR.GE3A13        5   Program Chip Select Ending Address 13
GP3EADR.GE3A12        4   Program Chip Select Ending Address 12
GP3EADR.GE3A11        3   Program Chip Select Ending Address 11
GP3EADR.GE3A10        2   Program Chip Select Ending Address 10
GP4SADR              0x004C     General-Purpose Chip Select 4 Starting Address
GP4SADR.GS4A15        7   Program Chip Select Starting Address 15
GP4SADR.GS4A14        6   Program Chip Select Starting Address 14
GP4SADR.GS4A13        5   Program Chip Select Starting Address 13
GP4SADR.GS4A12        4   Program Chip Select Starting Address 12
GP4SADR.GS4A11        3   Program Chip Select Starting Address 11
GP4SADR.GS4A10        2   Program Chip Select Starting Address 10
GP4SADR.G4STHA        1   Program Chip Select Clock Stretch Select A
GP4SADR.G4STHB        0   Program Chip Select Clock Stretch Select B
GP4EADR              0x004D     General-Purpose Chip Select 4 Ending Address
GP4EADR.GE4A15        7   Program Chip Select Ending Address 15
GP4EADR.GE4A14        6   Program Chip Select Ending Address 14
GP4EADR.GE4A13        5   Program Chip Select Ending Address 13
GP4EADR.GE4A12        4   Program Chip Select Ending Address 12
GP4EADR.GE4A11        3   Program Chip Select Ending Address 11
GP4EADR.GE4A10        2   Program Chip Select Ending Address 10
GP5SADR              0x004E     General-Purpose Chip Select 5 Starting Address
GP5SADR.GS5A15        7   Program Chip Select Starting Address 15
GP5SADR.GS5A14        6   Program Chip Select Starting Address 14
GP5SADR.GS5A13        5   Program Chip Select Starting Address 13
GP5SADR.GS5A12        4   Program Chip Select Starting Address 12
GP5SADR.GS5A11        3   Program Chip Select Starting Address 11
GP5SADR.GS5A10        2   Program Chip Select Starting Address 10
GP5SADR.G5STHA        1   Program Chip Select Clock Stretch Select A
GP5SADR.G5STHB        0   Program Chip Select Clock Stretch Select B
GP5EADR              0x004F     General-Purpose Chip Select 5 Ending Address
GP5EADR.GE5A15        7   Program Chip Select Ending Address 15
GP5EADR.GE5A14        6   Program Chip Select Ending Address 14
GP5EADR.GE5A13        5   Program Chip Select Ending Address 13
GP5EADR.GE5A12        4   Program Chip Select Ending Address 12
GP5EADR.GE5A11        3   Program Chip Select Ending Address 11
GP5EADR.GE5A10        2   Program Chip Select Ending Address 10
RESERV0050           0x0050     RESERVED
RESERV0051           0x0051     RESERVED
RESERV0052           0x0052     RESERVED
RESERV0053           0x0053     RESERVED
RESERV0054           0x0054     RESERVED
RESERV0055           0x0055     RESERVED
RESERV0056           0x0056     RESERVED
RESERV0057           0x0057     RESERVED
RESERV0058           0x0058     RESERVED
RESERV0059           0x0059     RESERVED
RESERV005A           0x005A     RESERVED
RESERV005B           0x005B     RESERVED
RESERV005C           0x005C     RESERVED
RESERV005D           0x005D     RESERVED
RESERV005E           0x005E     RESERVED
RESERV005F           0x005F     RESERVED
PWCLK                0x0060     Pulse-Width Modulation Clock Select
PWCLK.CON12           6   Concatenate Channels One and Two
PWCLK.PCKA3           2   PCKA3 - Prescaler for Clock A
PWCLK.PCKA2           1   PCKA2 - Prescaler for Clock A
PWCLK.PCKA1           0   PCKA1 - Prescaler for Clock A
PWPOL                0x0061     Pulse-Width Modulation Timer Polarity
PWPOL.PCLK2           5   Pulse-Width Channel 2 Clock Select
PWPOL.PCLK1           4   Pulse-Width Channel 1 Clock Select
PWPOL.PPOL2           1   Pulse-Width Channel 2 Polarity
PWPOL.PPOL1           0   Pulse-Width Channel 1 Polarity
PWSCAL               0x0062     Pulse-Width Modulation Timer Prescaler
PWEN                 0x0063     Pulse-Width Modulation Timer Enable
PWEN.TPWSL            7   PWM Scaled Clock Test Bit (TEST)
PWEN.DISCP            6   Disable Compare Scaled E Clock (TEST)
PWEN.PWEN2            1   Pulse-Width Channel 2
PWEN.PWEN1            0   Pulse-Width Channel 1
RESERV0064           0x0064     RESERVED
RESERV0065           0x0065     RESERVED
PWCNT1               0x0066     Pulse-Width Modulation Timer Counter 1
PWCNT2               0x0067     Pulse-Width Modulation Timer Counter 2
RESERV0068           0x0068     RESERVED
RESERV0069           0x0069     RESERVED
PWPER1               0x006A     Pulse-Width Modulation Timer Period  1
PWPER2               0x006B     Pulse-Width Modulation Timer Period  2
RESERV006C           0x006C     RESERVED
RESERV006D           0x006D     RESERVED
PWDTY1               0x006E     Pulse-Width Modulation Timer Duty Cycle 1
PWDTY2               0x006F     Pulse-Width Modulation Timer Duty Cycle 2
PPAR                 0x0070     Port Pull-Up Assignment Register
PPAR.HPPUE            7   Port H Pull-Up Enable
PPAR.GPPUE            6   Port G Pull-Up Enable
PPAR.FPPUE            5   Port F Pull-Up Enable
PPAR.DPPUE            3   Port D Pull-Up Enable
PPAR.APPUE            0   Port A Pull-Up Enable
PGEN                 0x0071     Port G Enabled
PGEN.PGEN7            7   Port G Enable Bits 7
PGEN.PGEN6            6   Port G Enable Bits 6
PGEN.PGEN5            5   Port G Enable Bits 5
PGEN.PGEN4            4   Port G Enable Bits 4
PGEN.PGEN3            3   Port G Enable Bits 3
PGEN.MEM1             2   Memory Expansion Mode Select Bits
PGEN.MEM0             1   Memory Expansion Mode Select Bits
PGEN.PGEN0            0   Port G Enable Bits 0
RESERV0072           0x0072     RESERVED
RESERV0073           0x0073     RESERVED
RESERV0074           0x0074     RESERVED
DODM                 0x0075     Port D Open Drain Mode
DODM.DOD5             5   Port D Open Drain Bits 5
DODM.DOD4             4   Port D Open Drain Bits 4
DODM.DOD3             3   Port D Open Drain Bits 3
DODM.DOD2             2   Port D Open Drain Bits 2
DODM.DOD1             1   Port D Open Drain Bits 1
DODM.DOD0             0   Port D Open Drain Bits 0
RESERV0076           0x0076     RESERVED
RESERV0077           0x0077     RESERVED
RESERV0078           0x0078     RESERVED
RESERV0079           0x0079     RESERVED
RESERV007A           0x007A     RESERVED
RESERV007B           0x007B     RESERVED
PORTH                0x007C     Port H Data Register
PORTH.PH1             1   Port H Data Bit 1
PORTH.PH0             0   Port H Data Bit 0
DDRH                 0x007D     Data Direction Register Port H
DDRH.DDH1             1   Data Direction for Port H Bit 1
DDRH.DDH0             0   Data Direction for Port H Bit 0
PORTG                0x007E     Port G Data Register
PORTG.PG7             7   Port G Data Bit 7
PORTG.PG6             6   Port G Data Bit 6
PORTG.PG5             5   Port G Data Bit 5
PORTG.PG4             4   Port G Data Bit 4
PORTG.PG3             3   Port G Data Bit 3
PORTG.PG2             2   Port G Data Bit 2
PORTG.PG1             1   Port G Data Bit 1
PORTG.PG0             0   Port G Data Bit 0
DDRG                 0x007F     Data Direction Register Port G
DDRG.DDG7             7   Data Direction for Port G Bit 7
DDRG.DDG6             6   Data Direction for Port G Bit 6
DDRG.DDG5             5   Data Direction for Port G Bit 5
DDRG.DDG4             4   Data Direction for Port G Bit 4
DDRG.DDG3             3   Data Direction for Port G Bit 3
DDRG.DDG2             2   Data Direction for Port G Bit 2
DDRG.DDG1             1   Data Direction for Port G Bit 1
DDRG.DDG0             0   Data Direction for Port G Bit 0
RESERVFFC0           0xFFC0     RESERVED
RESERVFFC1           0xFFC1     RESERVED
RESERVFFC2           0xFFC2     RESERVED
RESERVFFC3           0xFFC3     RESERVED
RESERVFFC4           0xFFC4     RESERVED
RESERVFFC5           0xFFC5     RESERVED
RESERVFFC6           0xFFC6     RESERVED
RESERVFFC7           0xFFC7     RESERVED
RESERVFFC8           0xFFC8     RESERVED
RESERVFFC9           0xFFC9     RESERVED
RESERVFFCA           0xFFCA     RESERVED
RESERVFFCB           0xFFCB     RESERVED
RESERVFFCC           0xFFCC     RESERVED
RESERVFFCD           0xFFCD     RESERVED
RESERVFFCE           0xFFCE     RESERVED
RESERVFFCF           0xFFCF     RESERVED
RESERVFFD0           0xFFD0     RESERVED
RESERVFFD1           0xFFD1     RESERVED
RESERVFFD2           0xFFD2     RESERVED
RESERVFFD3           0xFFD3     RESERVED
RESERVFFD4           0xFFD4     RESERVED
RESERVFFD5           0xFFD5     RESERVED


.68HC11D0               
; 68HC11D0 http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11D0&nodeId=01M98635
; MC68HC11D3.pdf

; RAM=192
; ROM=4K
; EPROM=0
; EEPROM=0  


; MEMORY MAP
area DATA FSR      0x0000:0x0040
area DATA RAM      0x0040:0x0100
area BSS  RESERVED 0x0100:0xF000
area DATA ROM      0xF000:0xFFC0
area DATA USER_VEC 0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA            0x0000  Port A data
PORTA.PA7     	  7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
RESERVED01       0x0001  RESERVED01
PIOC             0x0002  Parallel I_O Control Register
PIOC.CWOM         5   Port C Wired-OR Mode (affects all eight port C pins)
PORTC            0x0003  I_O Port C
PORTC.PC7         7   Port C Data Bit 7
PORTC.PC6         6   Port C Data Bit 6
PORTC.PC5         5   Port C Data Bit 5
PORTC.PC4         4   Port C Data Bit 4
PORTC.PC3         3   Port C Data Bit 3
PORTC.PC2         2   Port C Data Bit 2
PORTC.PC1         1   Port C Data Bit 1
PORTC.PC0         0   Port C Data Bit 0
PORTB            0x0004  Output Port B
PORTB.PB7         7   Port B Data Bit 7
PORTB.PB6         6   Port B Data Bit 6
PORTB.PB5         5   Port B Data Bit 5
PORTB.PB4         4   Port B Data Bit 4
PORTB.PB3         3   Port B Data Bit 3
PORTB.PB2         2   Port B Data Bit 2
PORTB.PB1         1   Port B Data Bit 1
PORTB.PB0         0   Port B Data Bit 0
RESERVED05       0x0005  RESERVED
DDRB             0x0006  Data Direction PortB
DDRB.DDB7         7   Data Direction for Port B Bit 7
DDRB.DDB6         6   Data Direction for Port B Bit 6
DDRB.DDB5         5   Data Direction for Port B Bit 5
DDRB.DDB4         4   Data Direction for Port B Bit 4
DDRB.DDB3         3   Data Direction for Port B Bit 3
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRB.DDB1         1   Data Direction for Port B Bit 1
DDRB.DDB0         0   Data Direction for Port B Bit 0
DDRC             0x0007  Data Direction for Port C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x0008  Data Port D
PORTD.PD7         7   Port D Data Bit 7
PORTD.PD6         6   Port D Data Bit 6
PORTD.PD5         5   Port D Data Bit 5
PORTD.PD4         4   Port D Data Bit 4
PORTD.PD3         3   Port D Data Bit 3
PORTD.PD2         2   Port D Data Bit 2
PORTD.PD1         1   Port D Data Bit 1
PORTD.PD0         0   Port D Data Bit 0
DDRD             0x0009  Data Direction for Port D
DDRD.DDD7         7   Data Direction for Port D Bit 7
DDRD.DDD6         6   Data Direction for Port D Bit 6
DDRD.DDD5         5   Data Direction for Port D Bit 5
DDRD.DDD4         4   Data Direction for Port D Bit 4
DDRD.DDD3         3   Data Direction for Port D Bit 3
DDRD.DDD2         2   Data Direction for Port D Bit 2
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
RESERVED0A       0x000A  RESERVED
CFORC            0x000B  Compare Force Register
CFORC.FOC1        7   Write Ones to Force Compare 1
CFORC.FOC2        6   Write Ones to Force Compare 2
CFORC.FOC3        5   Write Ones to Force Compare 3
CFORC.FOC4        4   Write Ones to Force Compare 4
CFORC.FOC5        3   Write Ones to Force Compare 5
OC1M             0x000C  OC1 Action Mask Register
OC1M.OC1M7        7   Output Compare Masks 7
OC1M.OC1M6        6   Output Compare Masks 6
OC1M.OC1M5        5   Output Compare Masks 5
OC1M.OC1M4        4   Output Compare Masks 4
OC1M.OC1M3        3   Output Compare Masks 3
OC1D             0x000D   OC1 Action Data Register
OC1D.OC1D7        7
OC1D.OC1D6        6
OC1D.OC1D5        5
OC1D.OC1D4        4
OC1D.OC1D3        3
TCNTH            0x000E  Timer Counter Register (High)
TCNTL            0x000F  Timer Counter Register (Low)
TIC1H            0x0010  Input Capture 1 Register (High)
TIC1L            0x0011  Input Capture 1 Register (Low)
TIC2H            0x0012  Input Capture 2 Register (High)
TIC2L            0x0013  Input Capture 2 Register (Low)
TIC3H            0x0014  Input Capture 3 Register (High)
TIC3L            0x0015  Input Capture 3 Register (Low)
TOC1H            0x0016  Output Compare 1 Register (High)
TOC1L            0x0017  Output Compare 1 Register (Low)
TOC2H            0x0018  Output Compare 2 Register (High)
TOC2L            0x0019  Output Compare 2 Register (Low)
TOC3H            0x001A  Output Compare 3 Register (High)
TOC3L            0x001B  Output Compare 3 Register (Low)
TOC4H            0x001C  Output Compare 4 Register (High)
TOC4L            0x001D  Output Compare 4 Register (Low)
TI4O5H           0x001E  Timer Input Capture 4/Output Compare 5 (High)
TI4O5L           0x001F  Timer Input Capture 4/Output Compare 5 (Low)
TCTL1            0x0020  Timer Control 1
TCTL1.OM2         7   Output Mode 2
TCTL1.OL2         6   Output Level 2
TCTL1.OM3         5   Output Mode 3
TCTL1.OL3         4   Output Level 3
TCTL1.OM4         3   Output Mode 4
TCTL1.OL4         2   Output Level 4
TCTL1.OM5         1   Output Mode 5
TCTL1.OL5         0   Output Level 5
TCTL2            0x0021  Timer Control 2
TCTL2.EDG4B       7   EDG4B  Input Capture Edge Control
TCTL2.EDG4A       6   EDG4A  Input Capture Edge Control
TCTL2.EDG1B       5   EDG1B  Input Capture Edge Control
TCTL2.EDG1A       4   EDG1A  Input Capture Edge Control
TCTL2.EDG2B       3   EDG2B  Input Capture Edge Control
TCTL2.EDG2A       2   EDG2A  Input Capture Edge Control
TCTL2.EDG3B       1   EDG3B  Input Capture Edge Control
TCTL2.EDG3A       0   EDG3A  Input Capture Edge Control
TMSK1            0x0022  Timer Interrupt Mask 1
TMSK1.OC1I        7   Output Compare 1 Interrupt Enable
TMSK1.OC2I        6   Output Compare 2 Interrupt Enable
TMSK1.OC3I        5   Output Compare 3 Interrupt Enable
TMSK1.OC4I        4   Output Compare 4 Interrupt Enable
TMSK1.I4_O5I      3   Input Capture 4 or Output Compare 5 Interrupt Enable
TMSK1.IC1I        2   Input Capture 1 Interrupt Enable
TMSK1.IC2I        1   Input Capture 2 Interrupt Enable
TMSK1.IC3I        0   Input Capture 3 Interrupt Enable
TFLG1            0x0023  Timer Interrupt Flag Register 1
TFLG1.OC1F        7   Output Compare 1 Flag
TFLG1.OC2F        6   Output Compare 2 Flag
TFLG1.OC3F        5   Output Compare 3 Flag
TFLG1.OC4F        4   Output Compare 4 Flag
TFLG1.I4_O5F      3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F        2   Input Capture 1 Flag
TFLG1.IC2F        1   Input Capture 2 Flag
TFLG1.IC3F        0   Input Capture 3 Flag
TMSK2            0x0024  Timer Interrupt Mask Register 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable
TMSK2.RTII        6   Real-time Interrupt Enable
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII        4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1         1   Timer Prescaler Select 1
TMSK2.PR0         0   Timer Prescaler Select 0
TFLG2            0x0025  Timer Interrupt Flag Register 2
TFLG2.TOF         7   Timer Overflow Interrupt Flag
TFLG2.RTIF        6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Interrupt Flag
PACTL            0x0026  Pulse Accumulator Control Register
PACTL.DDRA7       7   Data Direction Control for Port A Bit 7
PACTL.PAEN        6   Pulse Accumulator System Enable
PACTL.PAMOD       5   Pulse Accumulator Mode
PACTL.PEDGE       4   Pulse Accumulator Edge Control
PACTL.DDRA3       3   Data Direction for Port A Bit 3
PACTL.I4_O5       2   Configure TI4/O5 register for IC4 or OC5
PACTL.RTR1        1   Real-Time Interrupt (RTI) Rate 1
PACTL.RTR0        0   Real-Time Interrupt (RTI) Rate 0
PACNT            0x0027  Pulse Accumulator Count Register
SPCR             0x0028  SPI Control Register
SPCR.SPIE         7   Serial Peripheral Interrupt Enable
SPCR.SPE          6   Serial Peripheral System Enable
SPCR.DWOM         5   Port D Wired-OR Mode
SPCR.MSTR         4   Master Mode Select
SPCR.CPOL         3   Clock Polarity
SPCR.CPHA         2   Clock Phase
SPCR.SPR1         1   SPI Clock Rate Selects 1
SPCR.SPR0         0   SPI Clock Rate Selects 0
SPSR             0x0029  SPI Status Register
SPSR.SPIF         7   SPI Transfer Complete Flag
SPSR.WCOL         6   Write Collision
SPSR.MODF         4   Mode Fault
SPDR             0x002A  SPI Data Register
BAUD             0x002B  SCI Baud Rate Control 3
BAUD.TCLR         7   Clear Baud Rate Counters (Test)
BAUD.SCP1         5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0         4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB         3   SCI Baud Rate Clock Check (Test)
BAUD.SCR2         2   SCI Baud Rate Selects 2
BAUD.SCR1         1   SCI Baud Rate Selects 1
BAUD.SCR0         0   SCI Baud Rate Selects 0
SCCR1            0x002C  SCI Control Register 1
SCCR1.R8          7   Receive Data Bit 8
SCCR1.T8          6   Transmit Data bit 8
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake-up by Address Mark/Idle
SCCR2            0x002D  SCI Control Register 2
SCCR2.TIE         7   Transmit Interrupt Enable
SCCR2.TCIE        6   Transmit Complete Interrupt Enable
SCCR2.RIE         5   Receiver Interrupt Enable
SCCR2.ILIE        4   Idle Line Interrupt Enable
SCCR2.TE          3   Transmitter Enable
SCCR2.RE          2   Receiver Enable
SCCR2.RWU         1   Receiver Wake-Up Control
SCCR2.SBK         0   Send Break
SCSR             0x002E  SCI Status Register
SCSR.TDRE         7   Transmit Data Register Empty Flag
SCSR.TC           6   Transmit Complete Flag
SCSR.RDRF         5   Receive Data Register Full Flag
SCSR.IDLE         4   Idle Line Detected Flag
SCSR.OR           3   Overrun Error Flag
SCSR.NF           2   Noise Error Flag
SCSR.FE           1   Framing Error
SCDR             0x002F  SCI Data (Read RDR, Write TDR)
SCDR.R7T7         7
SCDR.R6T6         6
SCDR.R5T5         5
SCDR.R4T4         4
SCDR.R3T3         3
SCDR.R2T2         2
SCDR.R1T1         1
SCDR.R0T0         0
RESERVED30       0x0030  RESERVED
RESERVED31       0x0031  RESERVED
RESERVED32       0x0032  RESERVED
RESERVED33       0x0033  RESERVED
RESERVED34       0x0034  RESERVED
RESERVED35       0x0035  RESERVED
RESERVED36       0x0036  RESERVED
RESERVED37       0x0037  RESERVED
RESERVED38       0x0038  RESERVED
OPTION           0x0039  System Configuration Options
OPTION.IRQE       5   IRQ Select Edge Sensitive only
OPTION.DLY        4   Enable Oscillator Startup Delay
OPTION.CME        3   Clock Monitor Enable
OPTION.CR1        1   COP Timer Rate Select Bits 1
OPTION.CR0        0   COP Timer Rate Select Bits 0
COPRST           0x003A  Arm_Reset COP Timer Circuitry
RESERVED3B       0x003B  RESERVED
HPRIO            0x003C  Highest Priority I-Bit Int and Misc
HPRIO.RBOOT       7   Read Bootstrap ROM
HPRIO.SMOD        6   Special Mode Select
HPRIO.MDA         5   Mode Select A
HPRIO.IRVNE       4   Internal Read Visibility/Not E
HPRIO.PSEL3       3   Priority Select Bits 3
HPRIO.PSEL2       2   Priority Select Bits 2
HPRIO.PSEL1       1   Priority Select Bits 1
HPRIO.PSEL0       0   Priority Select Bits 0
INIT             0x003D  RAM and I_O Mapping Register
INIT.RAM3         7   RAM Map Position 3
INIT.RAM2         6   RAM Map Position 2
INIT.RAM1         5   RAM Map Position 1
INIT.RAM0         4   RAM Map Position 0
INIT.REG3         3   64-Byte Register Block Position 3
INIT.REG2         2   64-Byte Register Block Position 2
INIT.REG1         1   64-Byte Register Block Position 1
INIT.REG0         0   64-Byte Register Block Position 0
TEST1            0x003E  Factory TEST Control Register
TEST1.TILOP       7
TEST1.OCCR        5
TEST1.CBYP        4
TEST1.DISR        3
TEST1.FCM         2
TEST1.FCOP        1
CONFIG           0x003F  COP, ROM, and EEPROM Enables
CONFIG.NOCOP      2   COP System Disable
CONFIG.ROMON      1   ROM Enable
RESERVFFC0       0xFFC0  RESERVED
RESERVFFC1       0xFFC1  RESERVED
RESERVFFC2       0xFFC2  RESERVED
RESERVFFC3       0xFFC3  RESERVED
RESERVFFC4       0xFFC4  RESERVED
RESERVFFC5       0xFFC5  RESERVED
RESERVFFC6       0xFFC6  RESERVED
RESERVFFC7       0xFFC7  RESERVED
RESERVFFC8       0xFFC8  RESERVED
RESERVFFC9       0xFFC9  RESERVED
RESERVFFCA       0xFFCA  RESERVED
RESERVFFCB       0xFFCB  RESERVED
RESERVFFCC       0xFFCC  RESERVED
RESERVFFCD       0xFFCD  RESERVED
RESERVFFCE       0xFFCE  RESERVED
RESERVFFCF       0xFFCF  RESERVED
RESERVFFD0       0xFFD0  RESERVED
RESERVFFD1       0xFFD1  RESERVED
RESERVFFD2       0xFFD2  RESERVED
RESERVFFD3       0xFFD3  RESERVED
RESERVFFD4       0xFFD4  RESERVED
RESERVFFD5       0xFFD5  RESERVED

                                        
.68HC11D3     
; MC68HC11D3  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11D3&nodeId=01M98635
; MC68HC11D3.pdf

; RAM=192
; ROM=4K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA FSR      0x0000:0x0040
area DATA RAM      0x0040:0x0100
area BSS  RESERVED 0x0100:0xF000
area DATA ROM      0xF000:0xFFC0
area DATA USER_VEC 0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA            0x0000  Port A data
PORTA.PA7     	  7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
RESERVED01       0x0001  RESERVED01
PIOC             0x0002  Parallel I_O Control Register
PIOC.CWOM         5   Port C Wired-OR Mode (affects all eight port C pins)
PORTC            0x0003  I_O Port C
PORTC.PC7         7   Port C Data Bit 7
PORTC.PC6         6   Port C Data Bit 6
PORTC.PC5         5   Port C Data Bit 5
PORTC.PC4         4   Port C Data Bit 4
PORTC.PC3         3   Port C Data Bit 3
PORTC.PC2         2   Port C Data Bit 2
PORTC.PC1         1   Port C Data Bit 1
PORTC.PC0         0   Port C Data Bit 0
PORTB            0x0004  Output Port B
PORTB.PB7         7   Port B Data Bit 7
PORTB.PB6         6   Port B Data Bit 6
PORTB.PB5         5   Port B Data Bit 5
PORTB.PB4         4   Port B Data Bit 4
PORTB.PB3         3   Port B Data Bit 3
PORTB.PB2         2   Port B Data Bit 2
PORTB.PB1         1   Port B Data Bit 1
PORTB.PB0         0   Port B Data Bit 0
RESERVED05       0x0005  RESERVED
DDRB             0x0006  Data Direction PortB
DDRB.DDB7         7   Data Direction for Port B Bit 7
DDRB.DDB6         6   Data Direction for Port B Bit 6
DDRB.DDB5         5   Data Direction for Port B Bit 5
DDRB.DDB4         4   Data Direction for Port B Bit 4
DDRB.DDB3         3   Data Direction for Port B Bit 3
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRB.DDB1         1   Data Direction for Port B Bit 1
DDRB.DDB0         0   Data Direction for Port B Bit 0
DDRC             0x0007  Data Direction for Port C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x0008  Data Port D
PORTD.PD7         7   Port D Data Bit 7
PORTD.PD6         6   Port D Data Bit 6
PORTD.PD5         5   Port D Data Bit 5
PORTD.PD4         4   Port D Data Bit 4
PORTD.PD3         3   Port D Data Bit 3
PORTD.PD2         2   Port D Data Bit 2
PORTD.PD1         1   Port D Data Bit 1
PORTD.PD0         0   Port D Data Bit 0
DDRD             0x0009  Data Direction for Port D
DDRD.DDD7         7   Data Direction for Port D Bit 7
DDRD.DDD6         6   Data Direction for Port D Bit 6
DDRD.DDD5         5   Data Direction for Port D Bit 5
DDRD.DDD4         4   Data Direction for Port D Bit 4
DDRD.DDD3         3   Data Direction for Port D Bit 3
DDRD.DDD2         2   Data Direction for Port D Bit 2
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
RESERVED0A       0x000A  RESERVED
CFORC            0x000B  Compare Force Register
CFORC.FOC1        7   Write Ones to Force Compare 1
CFORC.FOC2        6   Write Ones to Force Compare 2
CFORC.FOC3        5   Write Ones to Force Compare 3
CFORC.FOC4        4   Write Ones to Force Compare 4
CFORC.FOC5        3   Write Ones to Force Compare 5
OC1M             0x000C  OC1 Action Mask Register
OC1M.OC1M7        7   Output Compare Masks 7
OC1M.OC1M6        6   Output Compare Masks 6
OC1M.OC1M5        5   Output Compare Masks 5
OC1M.OC1M4        4   Output Compare Masks 4
OC1M.OC1M3        3   Output Compare Masks 3
OC1D             0x000D   OC1 Action Data Register
OC1D.OC1D7        7
OC1D.OC1D6        6
OC1D.OC1D5        5
OC1D.OC1D4        4
OC1D.OC1D3        3
TCNTH            0x000E  Timer Counter Register (High)
TCNTL            0x000F  Timer Counter Register (Low)
TIC1H            0x0010  Input Capture 1 Register (High)
TIC1L            0x0011  Input Capture 1 Register (Low)
TIC2H            0x0012  Input Capture 2 Register (High)
TIC2L            0x0013  Input Capture 2 Register (Low)
TIC3H            0x0014  Input Capture 3 Register (High)
TIC3L            0x0015  Input Capture 3 Register (Low)
TOC1H            0x0016  Output Compare 1 Register (High)
TOC1L            0x0017  Output Compare 1 Register (Low)
TOC2H            0x0018  Output Compare 2 Register (High)
TOC2L            0x0019  Output Compare 2 Register (Low)
TOC3H            0x001A  Output Compare 3 Register (High)
TOC3L            0x001B  Output Compare 3 Register (Low)
TOC4H            0x001C  Output Compare 4 Register (High)
TOC4L            0x001D  Output Compare 4 Register (Low)
TI4O5H           0x001E  Timer Input Capture 4/Output Compare 5 (High)
TI4O5L           0x001F  Timer Input Capture 4/Output Compare 5 (Low)
TCTL1            0x0020  Timer Control 1
TCTL1.OM2         7   Output Mode 2
TCTL1.OL2         6   Output Level 2
TCTL1.OM3         5   Output Mode 3
TCTL1.OL3         4   Output Level 3
TCTL1.OM4         3   Output Mode 4
TCTL1.OL4         2   Output Level 4
TCTL1.OM5         1   Output Mode 5
TCTL1.OL5         0   Output Level 5
TCTL2            0x0021  Timer Control 2
TCTL2.EDG4B       7   EDG4B  Input Capture Edge Control
TCTL2.EDG4A       6   EDG4A  Input Capture Edge Control
TCTL2.EDG1B       5   EDG1B  Input Capture Edge Control
TCTL2.EDG1A       4   EDG1A  Input Capture Edge Control
TCTL2.EDG2B       3   EDG2B  Input Capture Edge Control
TCTL2.EDG2A       2   EDG2A  Input Capture Edge Control
TCTL2.EDG3B       1   EDG3B  Input Capture Edge Control
TCTL2.EDG3A       0   EDG3A  Input Capture Edge Control
TMSK1            0x0022  Timer Interrupt Mask 1
TMSK1.OC1I        7   Output Compare 1 Interrupt Enable
TMSK1.OC2I        6   Output Compare 2 Interrupt Enable
TMSK1.OC3I        5   Output Compare 3 Interrupt Enable
TMSK1.OC4I        4   Output Compare 4 Interrupt Enable
TMSK1.I4_O5I      3   Input Capture 4 or Output Compare 5 Interrupt Enable
TMSK1.IC1I        2   Input Capture 1 Interrupt Enable
TMSK1.IC2I        1   Input Capture 2 Interrupt Enable
TMSK1.IC3I        0   Input Capture 3 Interrupt Enable
TFLG1            0x0023  Timer Interrupt Flag Register 1
TFLG1.OC1F        7   Output Compare 1 Flag
TFLG1.OC2F        6   Output Compare 2 Flag
TFLG1.OC3F        5   Output Compare 3 Flag
TFLG1.OC4F        4   Output Compare 4 Flag
TFLG1.I4_O5F      3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F        2   Input Capture 1 Flag
TFLG1.IC2F        1   Input Capture 2 Flag
TFLG1.IC3F        0   Input Capture 3 Flag
TMSK2            0x0024  Timer Interrupt Mask Register 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable
TMSK2.RTII        6   Real-time Interrupt Enable
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII        4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1         1   Timer Prescaler Select 1
TMSK2.PR0         0   Timer Prescaler Select 0
TFLG2            0x0025  Timer Interrupt Flag Register 2
TFLG2.TOF         7   Timer Overflow Interrupt Flag
TFLG2.RTIF        6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Interrupt Flag
PACTL            0x0026  Pulse Accumulator Control Register
PACTL.DDRA7       7   Data Direction Control for Port A Bit 7
PACTL.PAEN        6   Pulse Accumulator System Enable
PACTL.PAMOD       5   Pulse Accumulator Mode
PACTL.PEDGE       4   Pulse Accumulator Edge Control
PACTL.DDRA3       3   Data Direction for Port A Bit 3
PACTL.I4_O5       2   Configure TI4/O5 register for IC4 or OC5
PACTL.RTR1        1   Real-Time Interrupt (RTI) Rate 1
PACTL.RTR0        0   Real-Time Interrupt (RTI) Rate 0
PACNT            0x0027  Pulse Accumulator Count Register
SPCR             0x0028  SPI Control Register
SPCR.SPIE         7   Serial Peripheral Interrupt Enable
SPCR.SPE          6   Serial Peripheral System Enable
SPCR.DWOM         5   Port D Wired-OR Mode
SPCR.MSTR         4   Master Mode Select
SPCR.CPOL         3   Clock Polarity
SPCR.CPHA         2   Clock Phase
SPCR.SPR1         1   SPI Clock Rate Selects 1
SPCR.SPR0         0   SPI Clock Rate Selects 0
SPSR             0x0029  SPI Status Register
SPSR.SPIF         7   SPI Transfer Complete Flag
SPSR.WCOL         6   Write Collision
SPSR.MODF         4   Mode Fault
SPDR             0x002A  SPI Data Register
BAUD             0x002B  SCI Baud Rate Control 3
BAUD.TCLR         7   Clear Baud Rate Counters (Test)
BAUD.SCP1         5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0         4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB         3   SCI Baud Rate Clock Check (Test)
BAUD.SCR2         2   SCI Baud Rate Selects 2
BAUD.SCR1         1   SCI Baud Rate Selects 1
BAUD.SCR0         0   SCI Baud Rate Selects 0
SCCR1            0x002C  SCI Control Register 1
SCCR1.R8          7   Receive Data Bit 8
SCCR1.T8          6   Transmit Data bit 8
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake-up by Address Mark/Idle
SCCR2            0x002D  SCI Control Register 2
SCCR2.TIE         7   Transmit Interrupt Enable
SCCR2.TCIE        6   Transmit Complete Interrupt Enable
SCCR2.RIE         5   Receiver Interrupt Enable
SCCR2.ILIE        4   Idle Line Interrupt Enable
SCCR2.TE          3   Transmitter Enable
SCCR2.RE          2   Receiver Enable
SCCR2.RWU         1   Receiver Wake-Up Control
SCCR2.SBK         0   Send Break
SCSR             0x002E  SCI Status Register
SCSR.TDRE         7   Transmit Data Register Empty Flag
SCSR.TC           6   Transmit Complete Flag
SCSR.RDRF         5   Receive Data Register Full Flag
SCSR.IDLE         4   Idle Line Detected Flag
SCSR.OR           3   Overrun Error Flag
SCSR.NF           2   Noise Error Flag
SCSR.FE           1   Framing Error
SCDR             0x002F  SCI Data (Read RDR, Write TDR)
SCDR.R7T7         7
SCDR.R6T6         6
SCDR.R5T5         5
SCDR.R4T4         4
SCDR.R3T3         3
SCDR.R2T2         2
SCDR.R1T1         1
SCDR.R0T0         0
RESERVED30       0x0030  RESERVED
RESERVED31       0x0031  RESERVED
RESERVED32       0x0032  RESERVED
RESERVED33       0x0033  RESERVED
RESERVED34       0x0034  RESERVED
RESERVED35       0x0035  RESERVED
RESERVED36       0x0036  RESERVED
RESERVED37       0x0037  RESERVED
RESERVED38       0x0038  RESERVED
OPTION           0x0039  System Configuration Options
OPTION.IRQE       5   IRQ Select Edge Sensitive only
OPTION.DLY        4   Enable Oscillator Startup Delay
OPTION.CME        3   Clock Monitor Enable
OPTION.CR1        1   COP Timer Rate Select Bits 1
OPTION.CR0        0   COP Timer Rate Select Bits 0
COPRST           0x003A  Arm_Reset COP Timer Circuitry
RESERVED3B       0x003B  RESERVED
HPRIO            0x003C  Highest Priority I-Bit Int and Misc
HPRIO.RBOOT       7   Read Bootstrap ROM
HPRIO.SMOD        6   Special Mode Select
HPRIO.MDA         5   Mode Select A
HPRIO.IRVNE       4   Internal Read Visibility/Not E
HPRIO.PSEL3       3   Priority Select Bits 3
HPRIO.PSEL2       2   Priority Select Bits 2
HPRIO.PSEL1       1   Priority Select Bits 1
HPRIO.PSEL0       0   Priority Select Bits 0
INIT             0x003D  RAM and I_O Mapping Register
INIT.RAM3         7   RAM Map Position 3
INIT.RAM2         6   RAM Map Position 2
INIT.RAM1         5   RAM Map Position 1
INIT.RAM0         4   RAM Map Position 0
INIT.REG3         3   64-Byte Register Block Position 3
INIT.REG2         2   64-Byte Register Block Position 2
INIT.REG1         1   64-Byte Register Block Position 1
INIT.REG0         0   64-Byte Register Block Position 0
TEST1            0x003E  Factory TEST Control Register
TEST1.TILOP       7
TEST1.OCCR        5
TEST1.CBYP        4
TEST1.DISR        3
TEST1.FCM         2
TEST1.FCOP        1
CONFIG           0x003F  COP, ROM, and EEPROM Enables
CONFIG.NOCOP      2   COP System Disable
CONFIG.ROMON      1   ROM Enable
RESERVFFC0       0xFFC0  RESERVED
RESERVFFC1       0xFFC1  RESERVED
RESERVFFC2       0xFFC2  RESERVED
RESERVFFC3       0xFFC3  RESERVED
RESERVFFC4       0xFFC4  RESERVED
RESERVFFC5       0xFFC5  RESERVED
RESERVFFC6       0xFFC6  RESERVED
RESERVFFC7       0xFFC7  RESERVED
RESERVFFC8       0xFFC8  RESERVED
RESERVFFC9       0xFFC9  RESERVED
RESERVFFCA       0xFFCA  RESERVED
RESERVFFCB       0xFFCB  RESERVED
RESERVFFCC       0xFFCC  RESERVED
RESERVFFCD       0xFFCD  RESERVED
RESERVFFCE       0xFFCE  RESERVED
RESERVFFCF       0xFFCF  RESERVED
RESERVFFD0       0xFFD0  RESERVED
RESERVFFD1       0xFFD1  RESERVED
RESERVFFD2       0xFFD2  RESERVED
RESERVFFD3       0xFFD3  RESERVED
RESERVFFD4       0xFFD4  RESERVED
RESERVFFD5       0xFFD5  RESERVED


.68HC11E0
; M68HC11E/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11E0&nodeId=01M98635
; M68HC11E.pdf

; RAM=512
; ROM=0 
; EPROM=0
; EEPROM=0  


; MEMORY MAP
area DATA RAM         0x0000:0x0200
area BSS  RESERVED    0x0200:0x1000
area DATA FSR         0x1000:0x1040
area BSS  RESERVED    0x1040:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA                0x1000     Port A data
PORTA.PA7     	      7   Port A Data Bit 7
PORTA.PA6             6   Port A Data Bit 6
PORTA.PA5             5   Port A Data Bit 5
PORTA.PA4             4   Port A Data Bit 4
PORTA.PA3             3   Port A Data Bit 3
PORTA.PA2             2   Port A Data Bit 2
PORTA.PA1             1   Port A Data Bit 1
PORTA.PA0             0   Port A Data Bit 0
RESERV01             0x1001     RESERVED
PIOC                 0x1002     Parallel I_O Control Register
PIOC.STAF             7   Strobe A Interrupt Status Flag
PIOC.STAI             6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM             5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS             4   Handshake Mode Bit
PIOC.OIN              3   Output or Input Handshake Select Bit
PIOC.PLS              2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA              1   Active Edge for Strobe A Bit
PIOC.INVB             0   Invert Strobe B Bit
PORTC                0x1003      Port C Data
PORTC.PC7             7   Port C Data Bit 7
PORTC.PC6             6   Port C Data Bit 6
PORTC.PC5             5   Port C Data Bit 5
PORTC.PC4             4   Port C Data Bit 4
PORTC.PC3             3   Port C Data Bit 3
PORTC.PC2             2   Port C Data Bit 2
PORTC.PC1             1   Port C Data Bit 1
PORTC.PC0             0   Port C Data Bit 0
PORTB                0x1004     Output Port B
PORTB.PB7             7   Port B Data Bit 7
PORTB.PB6             6   Port B Data Bit 6
PORTB.PB5             5   Port B Data Bit 5
PORTB.PB4             4   Port B Data Bit 4
PORTB.PB3             3   Port B Data Bit 3
PORTB.PB2             2   Port B Data Bit 2
PORTB.PB1             1   Port B Data Bit 1
PORTB.PB0             0   Port B Data Bit 0
PORTCL               0x1005     Alternate Latched Port C
PORTCL.PCL7           7
PORTCL.PCL6           6
PORTCL.PCL5           5
PORTCL.PCL4           4
PORTCL.PCL3           3
PORTCL.PCL2           2
PORTCL.PCL1           1
PORTCL.PCL0           0
RESERV1006           0x1006     RESERVED06
DDRC                 0x1007     Data Direction for Port C
DDRC.DDC7             7   Data Direction for Port C Bit 7
DDRC.DDC6             6   Data Direction for Port C Bit 6
DDRC.DDC5             5   Data Direction for Port C Bit 5
DDRC.DDC4             4   Data Direction for Port C Bit 4
DDRC.DDC3             3   Data Direction for Port C Bit 3
DDRC.DDC2             2   Data Direction for Port C Bit 2
DDRC.DDC1             1   Data Direction for Port C Bit 1
DDRC.DDC0             0   Data Direction for Port C Bit 0
PORTD                0x1008     Port D Data
PORTD.PD5             5   Port D Data Bit 5
PORTD.PD4             4   Port D Data Bit 4
PORTD.PD3             3   Port D Data Bit 3
PORTD.PD2             2   Port D Data Bit 2
PORTD.PD1             1   Port D Data Bit 1
PORTD.PD0             0   Port D Data Bit 0
DDRD                 0x1009     Data Direction for Port D
DDRD.DDD5             5   Data Direction for Port D Bit 5
DDRD.DDD4             4   Data Direction for Port D Bit 4
DDRD.DDD3             3   Data Direction for Port D Bit 3
DDRD.DDD2             2   Data Direction for Port D Bit 2
DDRD.DDD1             1   Data Direction for Port D Bit 1
DDRD.DDD0             0   Data Direction for Port D Bit 0
PORTE                0x100A     Port E Data
PORTE.PE7             7   Port E Data Bit 7
PORTE.PE6             6   Port E Data Bit 6
PORTE.PE5             5   Port E Data Bit 5
PORTE.PE4             4   Port E Data Bit 4
PORTE.PE3             3   Port E Data Bit 3
PORTE.PE2             2   Port E Data Bit 2
PORTE.PE1             1   Port E Data Bit 1
PORTE.PE0             0   Port E Data Bit 0
CFORC                0x100B     Timer Compare Force Register
CFORC.FOC1            7   Force Output Comparison Bit 1
CFORC.FOC2            6   Force Output Comparison Bit 2
CFORC.FOC3            5   Force Output Comparison Bit 3
CFORC.FOC4            4   Force Output Comparison Bit 4
CFORC.FOC5            3   Force Output Comparison Bit 5
OC1M                 0x100C     Output Compare 1 Mask Register
OC1M.OC1M7            7   Output Compare Masks 7
OC1M.OC1M6            6   Output Compare Masks 6
OC1M.OC1M5            5   Output Compare Masks 5
OC1M.OC1M4            4   Output Compare Masks 4
OC1M.OC1M3            3   Output Compare Masks 3
OC1D                 0x100D     Output Compare 1 Data Register
OC1D.OC1D7            7
OC1D.OC1D6            6
OC1D.OC1D5            5
OC1D.OC1D4            4
OC1D.OC1D3            3
TCNTH                0x100E     Timer Counter Register
TCNTL                0x100F     Timer Counter Register
TIC1H                0x1010     Input Capture 1 Register
TIC1L                0x1011     Input Capture 1 Register
TIC2H                0x1012     Input Capture 2 Register
TIC2L                0x1013     Input Capture 2 Register
TIC3H                0x1014     Input Capture 3 Register
TIC3L                0x1015     Input Capture 3 Register
TOC1H                0x1016     Output Compare 1 Register
TOC1L                0x1017     Output Compare 1 Register
TOC2H                0x1018     Output Compare 2 Register
TOC2L                0x1019     Output Compare 2 Register
TOC3H                0x101A     Output Compare 3 Register
TOC3L                0x101B     Output Compare 3 Register
TOC4H                0x101C     Output Compare 4 Register
TOC4L                0x101D     Output Compare 4 Register
TCO5H                0x101E     Output Compare 5 Register
TCO5L                0x101F     Output Compare 5 Register
TCTL1                0x1020     Timer Control Register 1
TCTL1.OM2             7   Output Mode Bits 2
TCTL1.OL2             6   Output Level Bits 2
TCTL1.OM3             5   Output Mode Bits 3
TCTL1.OL3             4   Output Level Bits 3
TCTL1.OM4             3   Output Mode Bits 4
TCTL1.OL4             2   Output Level Bits 4
TCTL1.OM5             1   Output Mode Bits 5
TCTL1.OL5             0   Output Level Bits 5
TCTL2                0x1021     Timer Control Register 2
TCTL2.EDG4B           7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A           6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B           5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A           4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B           3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A           2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B           1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A           0   EDG3A  Input Capture Edge Control Bits
TMSK1                0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I            7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I            6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I            5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I            4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I          3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I            2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I            1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I            0   Input Capture 3 Interrupt Enable Bits
TFLG1                0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F            7   Output Compare 1 Flag
TFLG1.OC2F            6   Output Compare 2 Flag
TFLG1.OC3F            5   Output Compare 3 Flag
TFLG1.OC4F            4   Output Compare 4 Flag
TFLG1.I4_O5F          3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F            2   Input Capture 1 Flag
TFLG1.IC2F            1   Input Capture 2 Flag
TFLG1.IC3F            0   Input Capture 3 Flag
TMSK2                0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI             7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII            6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI           5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII            4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1             1   Timer Prescaler Select Bits 1
TMSK2.PR0             0   Timer Prescaler Select Bits 0
TFLG2                0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF             7   Timer Overflow Interrupt Flag
TFLG2.RTIF            6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF           5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF            4   Pulse Accumulator Input Edge Interrupt Flag
PACTL                0x1026     Pulse Accumulator Control Register
PACTL.DDRA7           7   Data Direction for Port A Bit 7
PACTL.PAEN            6   Pulse Accumulator System Enable Bit
PACTL.PAMOD           5   Pulse Accumulator Mode Bit
PACTL.PEDGE           4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3           3   Data Direction for Port A Bit 3
PACTL.I4_O5           2   Input Capture 4/Output Compare Bit
PACTL.RTR1            1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0            0   RTI Interrupt Rate Select Bits 0
PACNT                0x1027     Pulse Accumulator Count Register
SPCR                 0x1028     SPI Control Register
SPCR.SPIE             7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE              6   Serial Peripheral System Enable Bit
SPCR.DWOM             5   Port D Wired-OR Mode Bit
SPCR.MSTR             4   Master Mode Select Bit
SPCR.CPOL             3   Clock Polarity Bit
SPCR.CPHA             2   Clock Phase Bit
SPCR.SPR1             1   SPI Clock Rate Select Bits 1
SPCR.SPR0             0   SPI Clock Rate Select Bits 0
SPSR                 0x1029     SPI Status Register
SPSR.SPIF             7   SPI Interrupt Complete Flag
SPSR.WCOL             6   Write Collision Bit
SPSR.MODF             4   Mode Fault Bit
SPDR                 0x102A     SPI Data Register
BAUD                 0x102B     SCI Baud Rate Control 3
BAUD.TCLR             7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP1             5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0             4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB             3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2             2   SCI Baud Rate Select Bits 2
BAUD.SCR1             1   SCI Baud Rate Select Bits 1
BAUD.SCR0             0   SCI Baud Rate Select Bits 0
SCCR1                0x102C     SCI Control Register 1
SCCR1.R8              7   Receive Data Bit 8
SCCR1.T8              6   Transmit Data Bit 8
SCCR1.M               4   Mode Bit (select character format)
SCCR1.WAKE            3   Wakeup by Address Mark/Idle Bit
SCCR2                0x102D     Serial Communications Control Register 2
SCCR2.TIE             7   Transmit Interrupt Enable Bit
SCCR2.TCIE            6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE             5   Receiver Interrupt Enable Bit
SCCR2.ILIE            4   Idle-Line Interrupt Enable Bit
SCCR2.TE              3   Transmitter Enable Bit
SCCR2.RE              2   Receiver Enable Bit
SCCR2.RWU             1   Receiver Wakeup Control Bit
SCCR2.SBK             0   Send Break
SCSR                 0x102E     Serial Communications Status Register
SCSR.TDRE             7   Transmit Data Register Empty Flag
SCSR.TC               6   Transmit Complete Flag
SCSR.RDRF             5   Receive Data Register Full Flag
SCSR.IDLE             4   Idle Line Detected Flag
SCSR.OR               3   Overrun Error Flag
SCSR.NF               2   Noise Error Flag
SCSR.FE               1   Framing Error Flag
SCDR                 0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7             7
SCDR.R6T6             6
SCDR.R5T5             5
SCDR.R4T4             4
SCDR.R3T3             3
SCDR.R2T2             2
SCDR.R1T1             1
SCDR.R0T0             0
ADCTL                0x1030     A_D Control Register
ADCTL.CCF             7   Conversion Complete Flag
ADCTL.SCAN            5   Continuous Scan Control Bit
ADCTL.MULT            4   Multiple Channel/Single Channel Control Bit
ADCTL.CD              3   Channel Selects D Bits
ADCTL.CC              2   Channel Selects C Bits
ADCTL.CB              1   Channel Selects B Bits
ADCTL.CA              0   Channel Selects A Bits
ADR1                 0x1031     A_D Result Register 1
ADR2                 0x1032     A_D Result Register 2
ADR3                 0x1033     A_D Result Register 3
ADR4                 0x1034     A_D Result Register 4
BPROT                0x1035     Block Protect Register
BPROT.PTCON           4   Protect CONFIG Register Bit
BPROT.BPRT3           3   Block Protect Bits for EEPROM 3
BPROT.BPRT2           2   Block Protect Bits for EEPROM 2
BPROT.BPRT1           1   Block Protect Bits for EEPROM 1
BPROT.BPRT0           0   Block Protect Bits for EEPROM 0
RESERV1036           0x1036     RESERVED
RESERV1037           0x1037     RESERVED
RESERV1038           0x1038     RESERVED
OPTION               0x1039     System Configuration Options
OPTION.ADPU           7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL           6   Clock Select Bit
OPTION.IRQE           5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY            4   Enable Oscillator Startup Delay Bit
OPTION.CME            3   Clock Monitor Enable Bit
OPTION.CR1            1   COP Timer Rate Select Bits 1
OPTION.CR0            0   COP Timer Rate Select Bits 0
COPRST               0x103A     Arm_Reset COP Timer Circuitry
PPROG                0x103B     EEPROM Program Control Register
PPROG.ODD             7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN            6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE            4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW             3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE           2   Erase Mode Select Bit
PPROG.EELAT           1   EEPROM Latch Control Bit
PPROG.EEPGM           0   EPROM/OTPROM/EEPROM Programming
HPRIO                0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT           7   Read Bootstrap ROM Bit
HPRIO.SMOD            6   Special Mode Select
HPRIO.MDA             5   Mode Select A Bits
HPRIO.IRV             4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3           3   Priority Select Bits 3
HPRIO.PSEL2           2   Priority Select Bits 2
HPRIO.PSEL1           1   Priority Select Bits 1
HPRIO.PSEL0           0   Priority Select Bits 0
INIT                 0x103D     RAM and I_O Mapping Register
INIT.RAM3             7   RAM Map Position Bits 3
INIT.RAM2             6   RAM Map Position Bits 2
INIT.RAM1             5   RAM Map Position Bits 1
INIT.RAM0             4   RAM Map Position Bits 0
INIT.REG3             3   64-Byte Register Block Position 3
INIT.REG2             2   64-Byte Register Block Position 2
INIT.REG1             1   64-Byte Register Block Position 1
INIT.REG0             0   64-Byte Register Block Position 0
RESERV3E             0x103E     RESERVED
CONFIG               0x103F     System Configuration Register
CONFIG.NOSEC          3   Security Disable Bit
CONFIG.NOCOP          2   COP System Disable Bit
CONFIG.ROMON          1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON           0   EEPROM Enable Bit
RESERVFFC0           0xFFC0     RESERVED
RESERVFFC1           0xFFC1     RESERVED
RESERVFFC2           0xFFC2     RESERVED
RESERVFFC3           0xFFC3     RESERVED
RESERVFFC4           0xFFC4     RESERVED
RESERVFFC5           0xFFC5     RESERVED
RESERVFFC6           0xFFC6     RESERVED
RESERVFFC7           0xFFC7     RESERVED
RESERVFFC8           0xFFC8     RESERVED
RESERVFFC9           0xFFC9     RESERVED
RESERVFFCA           0xFFCA     RESERVED
RESERVFFCB           0xFFCB     RESERVED
RESERVFFCC           0xFFCC     RESERVED
RESERVFFCD           0xFFCD     RESERVED
RESERVFFCE           0xFFCE     RESERVED
RESERVFFCF           0xFFCF     RESERVED
RESERVFFD0           0xFFD0     RESERVED
RESERVFFD1           0xFFD1     RESERVED
RESERVFFD2           0xFFD2     RESERVED
RESERVFFD3           0xFFD3     RESERVED
RESERVFFD4           0xFFD4     RESERVED
RESERVFFD5           0xFFD5     RESERVED


.68HC11E1
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11E1&nodeId=01M98635
; M68HC11E.pdf

; RAM=512
; ROM=0 
; EPROM=0
; EEPROM=0  


; MEMORY MAP
area DATA RAM          0x0000:0x0200
area BSS  RESERVED     0x0200:0x1000
area DATA FSR          0x1000:0x1040
area BSS  RESERVED     0x1040:0xB600
area DATA EEPROM       0xB600:0xB800
area BSS  RESERVED     0xB800:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET   0xFFFE    Processor reset
interrupt CME       0xFFFC    Clock Monitor Fail
interrupt NOCOP     0xFFFA    COP Failure
interrupt OPC       0xFFF8    Illegal Opcode Trap
interrupt SOFT      0xFFF6    Software Interrupt
interrupt XIRQ      0xFFF4    XIRQ Pin
interrupt IRQ       0xFFF2    IRQ
interrupt RTII      0xFFF0    Real Time Interrupt
interrupt IC1I      0xFFEE    Timer Input Capture 1
interrupt IC2I      0xFFEC    Timer Input Capture 2
interrupt IC3I      0xFFEA    Timer Input Capture 3
interrupt OC1I      0xFFE8    Timer Output Compare 1
interrupt OC2I      0xFFE6    Timer Output Compare 2
interrupt OC3I      0xFFE4    Timer Output Compare 3
interrupt OC4I      0xFFE2    Timer Output Compare 4
interrupt I4_I5     0xFFE0    Timer Input Capture 4 / Output Compare 5
interrupt TOI       0xFFDE    Timer Overflow
interrupt PAOVI     0xFFDC    Pulse Accumulator Overflow
interrupt PAII      0xFFDA    Pulse Accumulator Input Edge
interrupt SPIE      0xFFD8    SPI Serial Transfer Complete
interrupt SCISS     0xFFD6    SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA            0x1000     Port A data
PORTA.PA7     	  7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
RESERV01         0x1001     RESERVED
PIOC             0x1002     Parallel I_O Control Register
PIOC.STAF         7   Strobe A Interrupt Status Flag
PIOC.STAI         6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM         5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS         4   Handshake Mode Bit
PIOC.OIN          3   Output or Input Handshake Select Bit
PIOC.PLS          2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA          1   Active Edge for Strobe A Bit
PIOC.INVB         0   Invert Strobe B Bit
PORTC            0x1003      Port C Data
PORTC.PC7         7   Port C Data Bit 7
PORTC.PC6         6   Port C Data Bit 6
PORTC.PC5         5   Port C Data Bit 5
PORTC.PC4         4   Port C Data Bit 4
PORTC.PC3         3   Port C Data Bit 3
PORTC.PC2         2   Port C Data Bit 2
PORTC.PC1         1   Port C Data Bit 1
PORTC.PC0         0   Port C Data Bit 0
PORTB            0x1004     Output Port B
PORTB.PB7         7   Port B Data Bit 7
PORTB.PB6         6   Port B Data Bit 6
PORTB.PB5         5   Port B Data Bit 5
PORTB.PB4         4   Port B Data Bit 4
PORTB.PB3         3   Port B Data Bit 3
PORTB.PB2         2   Port B Data Bit 2
PORTB.PB1         1   Port B Data Bit 1
PORTB.PB0         0   Port B Data Bit 0
PORTCL           0x1005     Alternate Latched Port C
PORTCL.PCL7       7
PORTCL.PCL6       6
PORTCL.PCL5       5
PORTCL.PCL4       4
PORTCL.PCL3       3
PORTCL.PCL2       2
PORTCL.PCL1       1
PORTCL.PCL0       0
RESERV1006       0x1006     RESERVED06
DDRC             0x1007     Data Direction for Port C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x1008     Port D Data
PORTD.PD5         5   Port D Data Bit 5
PORTD.PD4         4   Port D Data Bit 4
PORTD.PD3         3   Port D Data Bit 3
PORTD.PD2         2   Port D Data Bit 2
PORTD.PD1         1   Port D Data Bit 1
PORTD.PD0         0   Port D Data Bit 0
DDRD             0x1009     Data Direction for Port D
DDRD.DDD5         5   Data Direction for Port D Bit 5
DDRD.DDD4         4   Data Direction for Port D Bit 4
DDRD.DDD3         3   Data Direction for Port D Bit 3
DDRD.DDD2         2   Data Direction for Port D Bit 2
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
PORTE            0x100A     Port E Data
PORTE.PE7         7   Port E Data Bit 7
PORTE.PE6         6   Port E Data Bit 6
PORTE.PE5         5   Port E Data Bit 5
PORTE.PE4         4   Port E Data Bit 4
PORTE.PE3         3   Port E Data Bit 3
PORTE.PE2         2   Port E Data Bit 2
PORTE.PE1         1   Port E Data Bit 1
PORTE.PE0         0   Port E Data Bit 0
CFORC            0x100B     Timer Compare Force Register
CFORC.FOC1        7   Force Output Comparison Bit 1
CFORC.FOC2        6   Force Output Comparison Bit 2
CFORC.FOC3        5   Force Output Comparison Bit 3
CFORC.FOC4        4   Force Output Comparison Bit 4
CFORC.FOC5        3   Force Output Comparison Bit 5
OC1M             0x100C     Output Compare 1 Mask Register
OC1M.OC1M7        7   Output Compare Masks 7
OC1M.OC1M6        6   Output Compare Masks 6
OC1M.OC1M5        5   Output Compare Masks 5
OC1M.OC1M4        4   Output Compare Masks 4
OC1M.OC1M3        3   Output Compare Masks 3
OC1D             0x100D     Output Compare 1 Data Register
OC1D.OC1D7        7
OC1D.OC1D6        6
OC1D.OC1D5        5
OC1D.OC1D4        4
OC1D.OC1D3        3
TCNTH            0x100E     Timer Counter Register
TCNTL            0x100F     Timer Counter Register
TIC1H            0x1010     Input Capture 1 Register
TIC1L            0x1011     Input Capture 1 Register
TIC2H            0x1012     Input Capture 2 Register
TIC2L            0x1013     Input Capture 2 Register
TIC3H            0x1014     Input Capture 3 Register
TIC3L            0x1015     Input Capture 3 Register
TOC1H            0x1016     Output Compare 1 Register
TOC1L            0x1017     Output Compare 1 Register
TOC2H            0x1018     Output Compare 2 Register
TOC2L            0x1019     Output Compare 2 Register
TOC3H            0x101A     Output Compare 3 Register
TOC3L            0x101B     Output Compare 3 Register
TOC4H            0x101C     Output Compare 4 Register
TOC4L            0x101D     Output Compare 4 Register
TCO5H            0x101E     Output Compare 5 Register
TCO5L            0x101F     Output Compare 5 Register
TCTL1            0x1020     Timer Control Register 1
TCTL1.OM2         7   Output Mode Bits 2
TCTL1.OL2         6   Output Level Bits 2
TCTL1.OM3         5   Output Mode Bits 3
TCTL1.OL3         4   Output Level Bits 3
TCTL1.OM4         3   Output Mode Bits 4
TCTL1.OL4         2   Output Level Bits 4
TCTL1.OM5         1   Output Mode Bits 5
TCTL1.OL5         0   Output Level Bits 5
TCTL2            0x1021     Timer Control Register 2
TCTL2.EDG4B       7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A       6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B       5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A       4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B       3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A       2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B       1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A       0   EDG3A  Input Capture Edge Control Bits
TMSK1            0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I        7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I        6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I        5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I        4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I      3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I        2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I        1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I        0   Input Capture 3 Interrupt Enable Bits
TFLG1            0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F        7   Output Compare 1 Flag
TFLG1.OC2F        6   Output Compare 2 Flag
TFLG1.OC3F        5   Output Compare 3 Flag
TFLG1.OC4F        4   Output Compare 4 Flag
TFLG1.I4_O5F      3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F        2   Input Capture 1 Flag
TFLG1.IC2F        1   Input Capture 2 Flag
TFLG1.IC3F        0   Input Capture 3 Flag
TMSK2            0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII        6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII        4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1         1   Timer Prescaler Select Bits 1
TMSK2.PR0         0   Timer Prescaler Select Bits 0
TFLG2            0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF         7   Timer Overflow Interrupt Flag
TFLG2.RTIF        6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Interrupt Flag
PACTL            0x1026     Pulse Accumulator Control Register
PACTL.DDRA7       7   Data Direction for Port A Bit 7
PACTL.PAEN        6   Pulse Accumulator System Enable Bit
PACTL.PAMOD       5   Pulse Accumulator Mode Bit
PACTL.PEDGE       4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3       3   Data Direction for Port A Bit 3
PACTL.I4_O5       2   Input Capture 4/Output Compare Bit
PACTL.RTR1        1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0        0   RTI Interrupt Rate Select Bits 0
PACNT            0x1027     Pulse Accumulator Count Register
SPCR             0x1028     SPI Control Register
SPCR.SPIE         7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE          6   Serial Peripheral System Enable Bit
SPCR.DWOM         5   Port D Wired-OR Mode Bit
SPCR.MSTR         4   Master Mode Select Bit
SPCR.CPOL         3   Clock Polarity Bit
SPCR.CPHA         2   Clock Phase Bit
SPCR.SPR1         1   SPI Clock Rate Select Bits 1
SPCR.SPR0         0   SPI Clock Rate Select Bits 0
SPSR             0x1029     SPI Status Register
SPSR.SPIF         7   SPI Interrupt Complete Flag
SPSR.WCOL         6   Write Collision Bit
SPSR.MODF         4   Mode Fault Bit
SPDR             0x102A     SPI Data Register
BAUD             0x102B     SCI Baud Rate Control 3
BAUD.TCLR         7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP1         5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0         4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB         3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2         2   SCI Baud Rate Select Bits 2
BAUD.SCR1         1   SCI Baud Rate Select Bits 1
BAUD.SCR0         0   SCI Baud Rate Select Bits 0
SCCR1            0x102C     SCI Control Register 1
SCCR1.R8          7   Receive Data Bit 8
SCCR1.T8          6   Transmit Data Bit 8
SCCR1.M           4   Mode Bit (select character format)
SCCR1.WAKE        3   Wakeup by Address Mark/Idle Bit
SCCR2            0x102D     Serial Communications Control Register 2
SCCR2.TIE         7   Transmit Interrupt Enable Bit
SCCR2.TCIE        6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE         5   Receiver Interrupt Enable Bit
SCCR2.ILIE        4   Idle-Line Interrupt Enable Bit
SCCR2.TE          3   Transmitter Enable Bit
SCCR2.RE          2   Receiver Enable Bit
SCCR2.RWU         1   Receiver Wakeup Control Bit
SCCR2.SBK         0   Send Break
SCSR             0x102E     Serial Communications Status Register
SCSR.TDRE         7   Transmit Data Register Empty Flag
SCSR.TC           6   Transmit Complete Flag
SCSR.RDRF         5   Receive Data Register Full Flag
SCSR.IDLE         4   Idle Line Detected Flag
SCSR.OR           3   Overrun Error Flag
SCSR.NF           2   Noise Error Flag
SCSR.FE           1   Framing Error Flag
SCDR             0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7         7
SCDR.R6T6         6
SCDR.R5T5         5
SCDR.R4T4         4
SCDR.R3T3         3
SCDR.R2T2         2
SCDR.R1T1         1
SCDR.R0T0         0
ADCTL            0x1030     A_D Control Register
ADCTL.CCF         7   Conversion Complete Flag
ADCTL.SCAN        5   Continuous Scan Control Bit
ADCTL.MULT        4   Multiple Channel/Single Channel Control Bit
ADCTL.CD          3   Channel Selects D Bits
ADCTL.CC          2   Channel Selects C Bits
ADCTL.CB          1   Channel Selects B Bits
ADCTL.CA          0   Channel Selects A Bits
ADR1             0x1031     A_D Result Register 1
ADR2             0x1032     A_D Result Register 2
ADR3             0x1033     A_D Result Register 3
ADR4             0x1034     A_D Result Register 4
BPROT            0x1035     Block Protect Register
BPROT.PTCON       4   Protect CONFIG Register Bit
BPROT.BPRT3       3   Block Protect Bits for EEPROM 3
BPROT.BPRT2       2   Block Protect Bits for EEPROM 2
BPROT.BPRT1       1   Block Protect Bits for EEPROM 1
BPROT.BPRT0       0   Block Protect Bits for EEPROM 0
RESERV1036       0x1036     RESERVED
RESERV1037       0x1037     RESERVED
RESERV1038       0x1038     RESERVED
OPTION           0x1039     System Configuration Options
OPTION.ADPU       7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL       6   Clock Select Bit
OPTION.IRQE       5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY        4   Enable Oscillator Startup Delay Bit
OPTION.CME        3   Clock Monitor Enable Bit
OPTION.CR1        1   COP Timer Rate Select Bits 1
OPTION.CR0        0   COP Timer Rate Select Bits 0
COPRST           0x103A     Arm_Reset COP Timer Circuitry
PPROG            0x103B     EEPROM Program Control Register
PPROG.ODD         7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN        6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE        4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW         3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE       2   Erase Mode Select Bit
PPROG.EELAT       1   EEPROM Latch Control Bit
PPROG.EEPGM       0   EPROM/OTPROM/EEPROM Programming
HPRIO            0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT       7   Read Bootstrap ROM Bit
HPRIO.SMOD        6   Special Mode Select
HPRIO.MDA         5   Mode Select A Bits
HPRIO.IRV         4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3       3   Priority Select Bits 3
HPRIO.PSEL2       2   Priority Select Bits 2
HPRIO.PSEL1       1   Priority Select Bits 1
HPRIO.PSEL0       0   Priority Select Bits 0
INIT             0x103D     RAM and I_O Mapping Register
INIT.RAM3         7   RAM Map Position Bits 3
INIT.RAM2         6   RAM Map Position Bits 2
INIT.RAM1         5   RAM Map Position Bits 1
INIT.RAM0         4   RAM Map Position Bits 0
INIT.REG3         3   64-Byte Register Block Position 3
INIT.REG2         2   64-Byte Register Block Position 2
INIT.REG1         1   64-Byte Register Block Position 1
INIT.REG0         0   64-Byte Register Block Position 0
RESERV3E         0x103E     RESERVED
CONFIG           0x103F     System Configuration Register
CONFIG.NOSEC      3   Security Disable Bit
CONFIG.NOCOP      2   COP System Disable Bit
CONFIG.ROMON      1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON       0   EEPROM Enable Bit
RESERVFFC0       0xFFC0     RESERVED
RESERVFFC1       0xFFC1     RESERVED
RESERVFFC2       0xFFC2     RESERVED
RESERVFFC3       0xFFC3     RESERVED
RESERVFFC4       0xFFC4     RESERVED
RESERVFFC5       0xFFC5     RESERVED
RESERVFFC6       0xFFC6     RESERVED
RESERVFFC7       0xFFC7     RESERVED
RESERVFFC8       0xFFC8     RESERVED
RESERVFFC9       0xFFC9     RESERVED
RESERVFFCA       0xFFCA     RESERVED
RESERVFFCB       0xFFCB     RESERVED
RESERVFFCC       0xFFCC     RESERVED
RESERVFFCD       0xFFCD     RESERVED
RESERVFFCE       0xFFCE     RESERVED
RESERVFFCF       0xFFCF     RESERVED
RESERVFFD0       0xFFD0     RESERVED
RESERVFFD1       0xFFD1     RESERVED
RESERVFFD2       0xFFD2     RESERVED
RESERVFFD3       0xFFD3     RESERVED
RESERVFFD4       0xFFD4     RESERVED
RESERVFFD5       0xFFD5     RESERVED


.68HC11E2
; M68HC11E/D  http://
; M68HC11E.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       RESET 
interrupt CLOCK 	0xFFFC       Clock monitor fail 
interrupt COP 		0xFFFA       COP failure 
interrupt OPC	 	0xFFF8       Illegal opcode trap 
interrupt SOFT 		0xFFF6       Software interrupt 
interrupt XIRQ 		0xFFF4       XIRQ pin 
interrupt IRQ 		0xFFF2       IRQ (external pin) 
interrupt RTI 		0xFFF0       Real-time interrupt 
interrupt TIC1 		0xFFEE       Timer input capture 1 
interrupt TIC2 		0xFFEC       Timer input capture 2 
interrupt TIC3 		0xFFEA       Timer input capture 3 
interrupt TOC1 		0xFFE8       Timer output compare 1 
interrupt TOC2 		0xFFE6       Timer output compare 2 
interrupt TOC3 		0xFFE4       Timer output compare 3 
interrupt TOC4 		0xFFE2       Timer output compare 4 
interrupt TIC4_TOC5 	0xFFE0       Timer input capture 4/output compare 5 
interrupt TIMER 	0xFFDE       Timer overflow 
interrupt PAO 		0xFFDC       Pulse accumulator overflow 
interrupt PAIE 		0xFFDA       Pulse accumulator input edge 
interrupt SPI 		0xFFD8       SPI serial transfer complete 
interrupt SCI 		0xFFD6       SCI serial system


; INPUT/ OUTPUT PORTS
PORTA            0x1000     Port A data
PORTA.PA7     	  7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
RESERV01         0x1001     RESERVED
PIOC             0x1002     Parallel I_O Control Register
PIOC.STAF         7   Strobe A Interrupt Status Flag
PIOC.STAI         6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM         5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS         4   Handshake Mode Bit
PIOC.OIN          3   Output or Input Handshake Select Bit
PIOC.PLS          2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA          1   Active Edge for Strobe A Bit
PIOC.INVB         0   Invert Strobe B Bit
PORTC            0x1003      Port C Data
PORTC.PC7         7   Port C Data Bit 7
PORTC.PC6         6   Port C Data Bit 6
PORTC.PC5         5   Port C Data Bit 5
PORTC.PC4         4   Port C Data Bit 4
PORTC.PC3         3   Port C Data Bit 3
PORTC.PC2         2   Port C Data Bit 2
PORTC.PC1         1   Port C Data Bit 1
PORTC.PC0         0   Port C Data Bit 0
PORTB            0x1004     Output Port B
PORTB.PB7         7   Port B Data Bit 7
PORTB.PB6         6   Port B Data Bit 6
PORTB.PB5         5   Port B Data Bit 5
PORTB.PB4         4   Port B Data Bit 4
PORTB.PB3         3   Port B Data Bit 3
PORTB.PB2         2   Port B Data Bit 2
PORTB.PB1         1   Port B Data Bit 1
PORTB.PB0         0   Port B Data Bit 0
PORTCL           0x1005     Alternate Latched Port C
PORTCL.PCL7       7
PORTCL.PCL6       6
PORTCL.PCL5       5
PORTCL.PCL4       4
PORTCL.PCL3       3
PORTCL.PCL2       2
PORTCL.PCL1       1
PORTCL.PCL0       0
RESERV1006       0x1006     RESERVED06
DDRC             0x1007     Data Direction for Port C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x1008     Port D Data
PORTD.PD5         5   Port D Data Bit 5
PORTD.PD4         4   Port D Data Bit 4
PORTD.PD3         3   Port D Data Bit 3
PORTD.PD2         2   Port D Data Bit 2
PORTD.PD1         1   Port D Data Bit 1
PORTD.PD0         0   Port D Data Bit 0
DDRD             0x1009     Data Direction for Port D
DDRD.DDD5         5   Data Direction for Port D Bit 5
DDRD.DDD4         4   Data Direction for Port D Bit 4
DDRD.DDD3         3   Data Direction for Port D Bit 3
DDRD.DDD2         2   Data Direction for Port D Bit 2
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
PORTE            0x100A     Port E Data
PORTE.PE7         7   Port E Data Bit 7
PORTE.PE6         6   Port E Data Bit 6
PORTE.PE5         5   Port E Data Bit 5
PORTE.PE4         4   Port E Data Bit 4
PORTE.PE3         3   Port E Data Bit 3
PORTE.PE2         2   Port E Data Bit 2
PORTE.PE1         1   Port E Data Bit 1
PORTE.PE0         0   Port E Data Bit 0
CFORC            0x100B     Timer Compare Force Register
CFORC.FOC1        7   Force Output Comparison Bit 1
CFORC.FOC2        6   Force Output Comparison Bit 2
CFORC.FOC3        5   Force Output Comparison Bit 3
CFORC.FOC4        4   Force Output Comparison Bit 4
CFORC.FOC5        3   Force Output Comparison Bit 5
OC1M             0x100C     Output Compare 1 Mask Register
OC1M.OC1M7        7   Output Compare Masks 7
OC1M.OC1M6        6   Output Compare Masks 6
OC1M.OC1M5        5   Output Compare Masks 5
OC1M.OC1M4        4   Output Compare Masks 4
OC1M.OC1M3        3   Output Compare Masks 3
OC1D             0x100D     Output Compare 1 Data Register
OC1D.OC1D7        7
OC1D.OC1D6        6
OC1D.OC1D5        5
OC1D.OC1D4        4
OC1D.OC1D3        3
TCNTH            0x100E     Timer Counter Register
TCNTL            0x100F     Timer Counter Register
TIC1H            0x1010     Input Capture 1 Register
TIC1L            0x1011     Input Capture 1 Register
TIC2H            0x1012     Input Capture 2 Register
TIC2L            0x1013     Input Capture 2 Register
TIC3H            0x1014     Input Capture 3 Register
TIC3L            0x1015     Input Capture 3 Register
TOC1H            0x1016     Output Compare 1 Register
TOC1L            0x1017     Output Compare 1 Register
TOC2H            0x1018     Output Compare 2 Register
TOC2L            0x1019     Output Compare 2 Register
TOC3H            0x101A     Output Compare 3 Register
TOC3L            0x101B     Output Compare 3 Register
TOC4H            0x101C     Output Compare 4 Register
TOC4L            0x101D     Output Compare 4 Register
TCO5H            0x101E     Output Compare 5 Register
TCO5L            0x101F     Output Compare 5 Register
TCTL1            0x1020     Timer Control Register 1
TCTL1.OM2         7   Output Mode Bits 2
TCTL1.OL2         6   Output Level Bits 2
TCTL1.OM3         5   Output Mode Bits 3
TCTL1.OL3         4   Output Level Bits 3
TCTL1.OM4         3   Output Mode Bits 4
TCTL1.OL4         2   Output Level Bits 4
TCTL1.OM5         1   Output Mode Bits 5
TCTL1.OL5         0   Output Level Bits 5
TCTL2            0x1021     Timer Control Register 2
TCTL2.EDG4B       7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A       6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B       5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A       4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B       3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A       2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B       1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A       0   EDG3A  Input Capture Edge Control Bits
TMSK1            0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I        7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I        6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I        5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I        4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I      3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I        2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I        1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I        0   Input Capture 3 Interrupt Enable Bits
TFLG1            0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F        7   Output Compare 1 Flag
TFLG1.OC2F        6   Output Compare 2 Flag
TFLG1.OC3F        5   Output Compare 3 Flag
TFLG1.OC4F        4   Output Compare 4 Flag
TFLG1.I4_O5F      3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F        2   Input Capture 1 Flag
TFLG1.IC2F        1   Input Capture 2 Flag
TFLG1.IC3F        0   Input Capture 3 Flag
TMSK2            0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII        6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII        4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1         1   Timer Prescaler Select Bits 1
TMSK2.PR0         0   Timer Prescaler Select Bits 0
TFLG2            0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF         7   Timer Overflow Interrupt Flag
TFLG2.RTIF        6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Interrupt Flag
PACTL            0x1026     Pulse Accumulator Control Register
PACTL.DDRA7       7   Data Direction for Port A Bit 7
PACTL.PAEN        6   Pulse Accumulator System Enable Bit
PACTL.PAMOD       5   Pulse Accumulator Mode Bit
PACTL.PEDGE       4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3       3   Data Direction for Port A Bit 3
PACTL.I4_O5       2   Input Capture 4/Output Compare Bit
PACTL.RTR1        1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0        0   RTI Interrupt Rate Select Bits 0
PACNT            0x1027     Pulse Accumulator Count Register
SPCR             0x1028     SPI Control Register
SPCR.SPIE         7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE          6   Serial Peripheral System Enable Bit
SPCR.DWOM         5   Port D Wired-OR Mode Bit
SPCR.MSTR         4   Master Mode Select Bit
SPCR.CPOL         3   Clock Polarity Bit
SPCR.CPHA         2   Clock Phase Bit
SPCR.SPR1         1   SPI Clock Rate Select Bits 1
SPCR.SPR0         0   SPI Clock Rate Select Bits 0
SPSR             0x1029     SPI Status Register
SPSR.SPIF         7   SPI Interrupt Complete Flag
SPSR.WCOL         6   Write Collision Bit
SPSR.MODF         4   Mode Fault Bit
SPDR             0x102A     SPI Data Register
BAUD             0x102B     SCI Baud Rate Control 3
BAUD.TCLR         7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP1         5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0         4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB         3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2         2   SCI Baud Rate Select Bits 2
BAUD.SCR1         1   SCI Baud Rate Select Bits 1
BAUD.SCR0         0   SCI Baud Rate Select Bits 0
SCCR1            0x102C     SCI Control Register 1
SCCR1.R8          7   Receive Data Bit 8
SCCR1.T8          6   Transmit Data Bit 8
SCCR1.M           4   Mode Bit (select character format)
SCCR1.WAKE        3   Wakeup by Address Mark/Idle Bit
SCCR2            0x102D     Serial Communications Control Register 2
SCCR2.TIE         7   Transmit Interrupt Enable Bit
SCCR2.TCIE        6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE         5   Receiver Interrupt Enable Bit
SCCR2.ILIE        4   Idle-Line Interrupt Enable Bit
SCCR2.TE          3   Transmitter Enable Bit
SCCR2.RE          2   Receiver Enable Bit
SCCR2.RWU         1   Receiver Wakeup Control Bit
SCCR2.SBK         0   Send Break
SCSR             0x102E     Serial Communications Status Register
SCSR.TDRE         7   Transmit Data Register Empty Flag
SCSR.TC           6   Transmit Complete Flag
SCSR.RDRF         5   Receive Data Register Full Flag
SCSR.IDLE         4   Idle Line Detected Flag
SCSR.OR           3   Overrun Error Flag
SCSR.NF           2   Noise Error Flag
SCSR.FE           1   Framing Error Flag
SCDR             0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7         7
SCDR.R6T6         6
SCDR.R5T5         5
SCDR.R4T4         4
SCDR.R3T3         3
SCDR.R2T2         2
SCDR.R1T1         1
SCDR.R0T0         0
ADCTL            0x1030     A_D Control Register
ADCTL.CCF         7   Conversion Complete Flag
ADCTL.SCAN        5   Continuous Scan Control Bit
ADCTL.MULT        4   Multiple Channel/Single Channel Control Bit
ADCTL.CD          3   Channel Selects D Bits
ADCTL.CC          2   Channel Selects C Bits
ADCTL.CB          1   Channel Selects B Bits
ADCTL.CA          0   Channel Selects A Bits
ADR1             0x1031     A_D Result Register 1
ADR2             0x1032     A_D Result Register 2
ADR3             0x1033     A_D Result Register 3
ADR4             0x1034     A_D Result Register 4
BPROT            0x1035     Block Protect Register
BPROT.PTCON       4   Protect CONFIG Register Bit
BPROT.BPRT3       3   Block Protect Bits for EEPROM 3
BPROT.BPRT2       2   Block Protect Bits for EEPROM 2
BPROT.BPRT1       1   Block Protect Bits for EEPROM 1
BPROT.BPRT0       0   Block Protect Bits for EEPROM 0
RESERV1036       0x1036     RESERVED
RESERV1037       0x1037     RESERVED
RESERV1038       0x1038     RESERVED
OPTION           0x1039     System Configuration Options
OPTION.ADPU       7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL       6   Clock Select Bit
OPTION.IRQE       5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY        4   Enable Oscillator Startup Delay Bit
OPTION.CME        3   Clock Monitor Enable Bit
OPTION.CR1        1   COP Timer Rate Select Bits 1
OPTION.CR0        0   COP Timer Rate Select Bits 0
COPRST           0x103A     Arm_Reset COP Timer Circuitry
PPROG            0x103B     EEPROM Program Control Register
PPROG.ODD         7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN        6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE        4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW         3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE       2   Erase Mode Select Bit
PPROG.EELAT       1   EEPROM Latch Control Bit
PPROG.EEPGM       0   EPROM/OTPROM/EEPROM Programming
HPRIO            0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT       7   Read Bootstrap ROM Bit
HPRIO.SMOD        6   Special Mode Select
HPRIO.MDA         5   Mode Select A Bits
HPRIO.IRV         4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3       3   Priority Select Bits 3
HPRIO.PSEL2       2   Priority Select Bits 2
HPRIO.PSEL1       1   Priority Select Bits 1
HPRIO.PSEL0       0   Priority Select Bits 0
INIT             0x103D     RAM and I_O Mapping Register
INIT.RAM3         7   RAM Map Position Bits 3
INIT.RAM2         6   RAM Map Position Bits 2
INIT.RAM1         5   RAM Map Position Bits 1
INIT.RAM0         4   RAM Map Position Bits 0
INIT.REG3         3   64-Byte Register Block Position 3
INIT.REG2         2   64-Byte Register Block Position 2
INIT.REG1         1   64-Byte Register Block Position 1
INIT.REG0         0   64-Byte Register Block Position 0
RESERV3E         0x103E     RESERVED
CONFIG           0x103F     System Configuration Register
CONFIG.NOSEC      3   Security Disable Bit
CONFIG.NOCOP      2   COP System Disable Bit
CONFIG.ROMON      1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON       0   EEPROM Enable Bit
RESERVFFC0       0xFFC0     RESERVED
RESERVFFC1       0xFFC1     RESERVED
RESERVFFC2       0xFFC2     RESERVED
RESERVFFC3       0xFFC3     RESERVED
RESERVFFC4       0xFFC4     RESERVED
RESERVFFC5       0xFFC5     RESERVED
RESERVFFC6       0xFFC6     RESERVED
RESERVFFC7       0xFFC7     RESERVED
RESERVFFC8       0xFFC8     RESERVED
RESERVFFC9       0xFFC9     RESERVED
RESERVFFCA       0xFFCA     RESERVED
RESERVFFCB       0xFFCB     RESERVED
RESERVFFCC       0xFFCC     RESERVED
RESERVFFCD       0xFFCD     RESERVED
RESERVFFCE       0xFFCE     RESERVED
RESERVFFCF       0xFFCF     RESERVED
RESERVFFD0       0xFFD0     RESERVED
RESERVFFD1       0xFFD1     RESERVED
RESERVFFD2       0xFFD2     RESERVED
RESERVFFD3       0xFFD3     RESERVED
RESERVFFD4       0xFFD4     RESERVED
RESERVFFD5       0xFFD5     RESERVED


.68HC11E20
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11E20&nodeId=01M98635
; M68HC11E.pdf

; RAM=768
; ROM=20K
; EPROM=0
; EEPROM=512


; MEMORY MAP
area DATA RAM           0x0000:0x0300
area BSS  RESERVED      0x0300:0x1000
area DATA FSR           0x1000:0x1040
area BSS  RESERVED      0x1040:0x9000
area DATA ROM_EPROM_0   0x9000:0xB000
area BSS  RESERVED      0xB000:0xB600
area DATA EEPROM        0xB600:0xB800
area BSS  RESERVED      0xB800:0xD000
area DATA ROM_EPROM_1   0xD000:0xFFC0
area DATA USER_VEC      0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA                0x1000     Port A data
PORTA.PA7     	      7   Port A Data Bit 7
PORTA.PA6             6   Port A Data Bit 6
PORTA.PA5             5   Port A Data Bit 5
PORTA.PA4             4   Port A Data Bit 4
PORTA.PA3             3   Port A Data Bit 3
PORTA.PA2             2   Port A Data Bit 2
PORTA.PA1             1   Port A Data Bit 1
PORTA.PA0             0   Port A Data Bit 0
RESERV01             0x1001     RESERVED
PIOC                 0x1002     Parallel I_O Control Register
PIOC.STAF             7   Strobe A Interrupt Status Flag
PIOC.STAI             6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM             5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS             4   Handshake Mode Bit
PIOC.OIN              3   Output or Input Handshake Select Bit
PIOC.PLS              2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA              1   Active Edge for Strobe A Bit
PIOC.INVB             0   Invert Strobe B Bit
PORTC                0x1003      Port C Data
PORTC.PC7             7   Port C Data Bit 7
PORTC.PC6             6   Port C Data Bit 6
PORTC.PC5             5   Port C Data Bit 5
PORTC.PC4             4   Port C Data Bit 4
PORTC.PC3             3   Port C Data Bit 3
PORTC.PC2             2   Port C Data Bit 2
PORTC.PC1             1   Port C Data Bit 1
PORTC.PC0             0   Port C Data Bit 0
PORTB                0x1004     Output Port B
PORTB.PB7             7   Port B Data Bit 7
PORTB.PB6             6   Port B Data Bit 6
PORTB.PB5             5   Port B Data Bit 5
PORTB.PB4             4   Port B Data Bit 4
PORTB.PB3             3   Port B Data Bit 3
PORTB.PB2             2   Port B Data Bit 2
PORTB.PB1             1   Port B Data Bit 1
PORTB.PB0             0   Port B Data Bit 0
PORTCL               0x1005     Alternate Latched Port C
PORTCL.PCL7           7
PORTCL.PCL6           6
PORTCL.PCL5           5
PORTCL.PCL4           4
PORTCL.PCL3           3
PORTCL.PCL2           2
PORTCL.PCL1           1
PORTCL.PCL0           0
RESERV1006           0x1006     RESERVED06
DDRC                 0x1007     Data Direction for Port C
DDRC.DDC7             7   Data Direction for Port C Bit 7
DDRC.DDC6             6   Data Direction for Port C Bit 6
DDRC.DDC5             5   Data Direction for Port C Bit 5
DDRC.DDC4             4   Data Direction for Port C Bit 4
DDRC.DDC3             3   Data Direction for Port C Bit 3
DDRC.DDC2             2   Data Direction for Port C Bit 2
DDRC.DDC1             1   Data Direction for Port C Bit 1
DDRC.DDC0             0   Data Direction for Port C Bit 0
PORTD                0x1008     Port D Data
PORTD.PD5             5   Port D Data Bit 5
PORTD.PD4             4   Port D Data Bit 4
PORTD.PD3             3   Port D Data Bit 3
PORTD.PD2             2   Port D Data Bit 2
PORTD.PD1             1   Port D Data Bit 1
PORTD.PD0             0   Port D Data Bit 0
DDRD                 0x1009     Data Direction for Port D
DDRD.DDD5             5   Data Direction for Port D Bit 5
DDRD.DDD4             4   Data Direction for Port D Bit 4
DDRD.DDD3             3   Data Direction for Port D Bit 3
DDRD.DDD2             2   Data Direction for Port D Bit 2
DDRD.DDD1             1   Data Direction for Port D Bit 1
DDRD.DDD0             0   Data Direction for Port D Bit 0
PORTE                0x100A     Port E Data
PORTE.PE7             7   Port E Data Bit 7
PORTE.PE6             6   Port E Data Bit 6
PORTE.PE5             5   Port E Data Bit 5
PORTE.PE4             4   Port E Data Bit 4
PORTE.PE3             3   Port E Data Bit 3
PORTE.PE2             2   Port E Data Bit 2
PORTE.PE1             1   Port E Data Bit 1
PORTE.PE0             0   Port E Data Bit 0
CFORC                0x100B     Timer Compare Force Register
CFORC.FOC1            7   Force Output Comparison Bit 1
CFORC.FOC2            6   Force Output Comparison Bit 2
CFORC.FOC3            5   Force Output Comparison Bit 3
CFORC.FOC4            4   Force Output Comparison Bit 4
CFORC.FOC5            3   Force Output Comparison Bit 5
OC1M                 0x100C     Output Compare 1 Mask Register
OC1M.OC1M7            7   Output Compare Masks 7
OC1M.OC1M6            6   Output Compare Masks 6
OC1M.OC1M5            5   Output Compare Masks 5
OC1M.OC1M4            4   Output Compare Masks 4
OC1M.OC1M3            3   Output Compare Masks 3
OC1D                 0x100D     Output Compare 1 Data Register
OC1D.OC1D7            7
OC1D.OC1D6            6
OC1D.OC1D5            5
OC1D.OC1D4            4
OC1D.OC1D3            3
TCNTH                0x100E     Timer Counter Register
TCNTL                0x100F     Timer Counter Register
TIC1H                0x1010     Input Capture 1 Register
TIC1L                0x1011     Input Capture 1 Register
TIC2H                0x1012     Input Capture 2 Register
TIC2L                0x1013     Input Capture 2 Register
TIC3H                0x1014     Input Capture 3 Register
TIC3L                0x1015     Input Capture 3 Register
TOC1H                0x1016     Output Compare 1 Register
TOC1L                0x1017     Output Compare 1 Register
TOC2H                0x1018     Output Compare 2 Register
TOC2L                0x1019     Output Compare 2 Register
TOC3H                0x101A     Output Compare 3 Register
TOC3L                0x101B     Output Compare 3 Register
TOC4H                0x101C     Output Compare 4 Register
TOC4L                0x101D     Output Compare 4 Register
TCO5H                0x101E     Output Compare 5 Register
TCO5L                0x101F     Output Compare 5 Register
TCTL1                0x1020     Timer Control Register 1
TCTL1.OM2             7   Output Mode Bits 2
TCTL1.OL2             6   Output Level Bits 2
TCTL1.OM3             5   Output Mode Bits 3
TCTL1.OL3             4   Output Level Bits 3
TCTL1.OM4             3   Output Mode Bits 4
TCTL1.OL4             2   Output Level Bits 4
TCTL1.OM5             1   Output Mode Bits 5
TCTL1.OL5             0   Output Level Bits 5
TCTL2                0x1021     Timer Control Register 2
TCTL2.EDG4B           7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A           6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B           5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A           4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B           3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A           2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B           1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A           0   EDG3A  Input Capture Edge Control Bits
TMSK1                0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I            7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I            6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I            5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I            4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I          3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I            2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I            1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I            0   Input Capture 3 Interrupt Enable Bits
TFLG1                0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F            7   Output Compare 1 Flag
TFLG1.OC2F            6   Output Compare 2 Flag
TFLG1.OC3F            5   Output Compare 3 Flag
TFLG1.OC4F            4   Output Compare 4 Flag
TFLG1.I4_O5F          3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F            2   Input Capture 1 Flag
TFLG1.IC2F            1   Input Capture 2 Flag
TFLG1.IC3F            0   Input Capture 3 Flag
TMSK2                0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI             7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII            6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI           5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII            4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1             1   Timer Prescaler Select Bits 1
TMSK2.PR0             0   Timer Prescaler Select Bits 0
TFLG2                0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF             7   Timer Overflow Interrupt Flag
TFLG2.RTIF            6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF           5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF            4   Pulse Accumulator Input Edge Interrupt Flag
PACTL                0x1026     Pulse Accumulator Control Register
PACTL.DDRA7           7   Data Direction for Port A Bit 7
PACTL.PAEN            6   Pulse Accumulator System Enable Bit
PACTL.PAMOD           5   Pulse Accumulator Mode Bit
PACTL.PEDGE           4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3           3   Data Direction for Port A Bit 3
PACTL.I4_O5           2   Input Capture 4/Output Compare Bit
PACTL.RTR1            1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0            0   RTI Interrupt Rate Select Bits 0
PACNT                0x1027     Pulse Accumulator Count Register
SPCR                 0x1028     SPI Control Register
SPCR.SPIE             7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE              6   Serial Peripheral System Enable Bit
SPCR.DWOM             5   Port D Wired-OR Mode Bit
SPCR.MSTR             4   Master Mode Select Bit
SPCR.CPOL             3   Clock Polarity Bit
SPCR.CPHA             2   Clock Phase Bit
SPCR.SPR1             1   SPI Clock Rate Select Bits 1
SPCR.SPR0             0   SPI Clock Rate Select Bits 0
SPSR                 0x1029     SPI Status Register
SPSR.SPIF             7   SPI Interrupt Complete Flag
SPSR.WCOL             6   Write Collision Bit
SPSR.MODF             4   Mode Fault Bit
SPDR                 0x102A     SPI Data Register
BAUD                 0x102B     SCI Baud Rate Control 3
BAUD.TCLR             7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP2             6   SCI Baud Rate Prescaler Select Bits 2
BAUD.SCP1             5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0             4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB             3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2             2   SCI Baud Rate Select Bits 2
BAUD.SCR1             1   SCI Baud Rate Select Bits 1
BAUD.SCR0             0   SCI Baud Rate Select Bits 0
SCCR1                0x102C     SCI Control Register 1
SCCR1.R8              7   Receive Data Bit 8
SCCR1.T8              6   Transmit Data Bit 8
SCCR1.M               4   Mode Bit (select character format)
SCCR1.WAKE            3   Wakeup by Address Mark/Idle Bit
SCCR2                0x102D     Serial Communications Control Register 2
SCCR2.TIE             7   Transmit Interrupt Enable Bit
SCCR2.TCIE            6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE             5   Receiver Interrupt Enable Bit
SCCR2.ILIE            4   Idle-Line Interrupt Enable Bit
SCCR2.TE              3   Transmitter Enable Bit
SCCR2.RE              2   Receiver Enable Bit
SCCR2.RWU             1   Receiver Wakeup Control Bit
SCCR2.SBK             0   Send Break
SCSR                 0x102E     Serial Communications Status Register
SCSR.TDRE             7   Transmit Data Register Empty Flag
SCSR.TC               6   Transmit Complete Flag
SCSR.RDRF             5   Receive Data Register Full Flag
SCSR.IDLE             4   Idle Line Detected Flag
SCSR.OR               3   Overrun Error Flag
SCSR.NF               2   Noise Error Flag
SCSR.FE               1   Framing Error Flag
SCDR                 0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7             7
SCDR.R6T6             6
SCDR.R5T5             5
SCDR.R4T4             4
SCDR.R3T3             3
SCDR.R2T2             2
SCDR.R1T1             1
SCDR.R0T0             0
ADCTL                0x1030     A_D Control Register
ADCTL.CCF             7   Conversion Complete Flag
ADCTL.SCAN            5   Continuous Scan Control Bit
ADCTL.MULT            4   Multiple Channel/Single Channel Control Bit
ADCTL.CD              3   Channel Selects D Bits
ADCTL.CC              2   Channel Selects C Bits
ADCTL.CB              1   Channel Selects B Bits
ADCTL.CA              0   Channel Selects A Bits
ADR1                 0x1031     A_D Result Register 1
ADR2                 0x1032     A_D Result Register 2
ADR3                 0x1033     A_D Result Register 3
ADR4                 0x1034     A_D Result Register 4
BPROT                0x1035     Block Protect Register
BPROT.PTCON           4   Protect CONFIG Register Bit
BPROT.BPRT3           3   Block Protect Bits for EEPROM 3
BPROT.BPRT2           2   Block Protect Bits for EEPROM 2
BPROT.BPRT1           1   Block Protect Bits for EEPROM 1
BPROT.BPRT0           0   Block Protect Bits for EEPROM 0
RESERV1036           0x1036     RESERVED
RESERV1037           0x1037     RESERVED
RESERV1038           0x1038     RESERVED
OPTION               0x1039     System Configuration Options
OPTION.ADPU           7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL           6   Clock Select Bit
OPTION.IRQE           5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY            4   Enable Oscillator Startup Delay Bit
OPTION.CME            3   Clock Monitor Enable Bit
OPTION.CR1            1   COP Timer Rate Select Bits 1
OPTION.CR0            0   COP Timer Rate Select Bits 0
COPRST               0x103A     Arm_Reset COP Timer Circuitry
PPROG                0x103B     EEPROM Program Control Register
PPROG.ODD             7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN            6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE            4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW             3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE           2   Erase Mode Select Bit
PPROG.EELAT           1   EEPROM Latch Control Bit
PPROG.EEPGM           0   EPROM/OTPROM/EEPROM Programming
HPRIO                0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT           7   Read Bootstrap ROM Bit
HPRIO.SMOD            6   Special Mode Select
HPRIO.MDA             5   Mode Select A Bits
HPRIO.IRV             4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3           3   Priority Select Bits 3
HPRIO.PSEL2           2   Priority Select Bits 2
HPRIO.PSEL1           1   Priority Select Bits 1
HPRIO.PSEL0           0   Priority Select Bits 0
INIT                 0x103D     RAM and I_O Mapping Register
INIT.RAM3             7   RAM Map Position Bits 3
INIT.RAM2             6   RAM Map Position Bits 2
INIT.RAM1             5   RAM Map Position Bits 1
INIT.RAM0             4   RAM Map Position Bits 0
INIT.REG3             3   64-Byte Register Block Position 3
INIT.REG2             2   64-Byte Register Block Position 2
INIT.REG1             1   64-Byte Register Block Position 1
INIT.REG0             0   64-Byte Register Block Position 0
RESERV3E             0x103E     RESERVED
CONFIG               0x103F     System Configuration Register
CONFIG.NOSEC          3   Security Disable Bit
CONFIG.NOCOP          2   COP System Disable Bit
CONFIG.ROMON          1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON           0   EEPROM Enable Bit
RESERVFFC0           0xFFC0     RESERVED
RESERVFFC1           0xFFC1     RESERVED
RESERVFFC2           0xFFC2     RESERVED
RESERVFFC3           0xFFC3     RESERVED
RESERVFFC4           0xFFC4     RESERVED
RESERVFFC5           0xFFC5     RESERVED
RESERVFFC6           0xFFC6     RESERVED
RESERVFFC7           0xFFC7     RESERVED
RESERVFFC8           0xFFC8     RESERVED
RESERVFFC9           0xFFC9     RESERVED
RESERVFFCA           0xFFCA     RESERVED
RESERVFFCB           0xFFCB     RESERVED
RESERVFFCC           0xFFCC     RESERVED
RESERVFFCD           0xFFCD     RESERVED
RESERVFFCE           0xFFCE     RESERVED
RESERVFFCF           0xFFCF     RESERVED
RESERVFFD0           0xFFD0     RESERVED
RESERVFFD1           0xFFD1     RESERVED
RESERVFFD2           0xFFD2     RESERVED
RESERVFFD3           0xFFD3     RESERVED
RESERVFFD4           0xFFD4     RESERVED
RESERVFFD5           0xFFD5     RESERVED


.68HC11E8
; http://
; M68HC11E.pdf

; RAM=512
; ROM=12K
; EPROM=0
; EEPROM=0


; MEMORY MAP

; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       RESET 
interrupt CLOCK 	0xFFFC       Clock monitor fail 
interrupt COP 		0xFFFA       COP failure 
interrupt OPC	 	0xFFF8       Illegal opcode trap 
interrupt SOFT 		0xFFF6       Software interrupt 
interrupt XIRQ 		0xFFF4       XIRQ pin 
interrupt IRQ 		0xFFF2       IRQ (external pin) 
interrupt RTI 		0xFFF0       Real-time interrupt 
interrupt TIC1 		0xFFEE       Timer input capture 1 
interrupt TIC2 		0xFFEC       Timer input capture 2 
interrupt TIC3 		0xFFEA       Timer input capture 3 
interrupt TOC1 		0xFFE8       Timer output compare 1 
interrupt TOC2 		0xFFE6       Timer output compare 2 
interrupt TOC3 		0xFFE4       Timer output compare 3 
interrupt TOC4 		0xFFE2       Timer output compare 4 
interrupt TIC4_TOC5 	0xFFE0       Timer input capture 4/output compare 5 
interrupt TIMER 	0xFFDE       Timer overflow 
interrupt PAO 		0xFFDC       Pulse accumulator overflow 
interrupt PAIE 		0xFFDA       Pulse accumulator input edge 
interrupt SPI 		0xFFD8       SPI serial transfer complete 
interrupt SCI 		0xFFD6       SCI serial system


; INPUT/ OUTPUT PORTS
PORTA                0x1000     Port A data
PORTA.PA7     	      7   Port A Data Bit 7
PORTA.PA6             6   Port A Data Bit 6
PORTA.PA5             5   Port A Data Bit 5
PORTA.PA4             4   Port A Data Bit 4
PORTA.PA3             3   Port A Data Bit 3
PORTA.PA2             2   Port A Data Bit 2
PORTA.PA1             1   Port A Data Bit 1
PORTA.PA0             0   Port A Data Bit 0
RESERV01             0x1001     RESERVED
PIOC                 0x1002     Parallel I_O Control Register
PIOC.STAF             7   Strobe A Interrupt Status Flag
PIOC.STAI             6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM             5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS             4   Handshake Mode Bit
PIOC.OIN              3   Output or Input Handshake Select Bit
PIOC.PLS              2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA              1   Active Edge for Strobe A Bit
PIOC.INVB             0   Invert Strobe B Bit
PORTC                0x1003      Port C Data
PORTC.PC7             7   Port C Data Bit 7
PORTC.PC6             6   Port C Data Bit 6
PORTC.PC5             5   Port C Data Bit 5
PORTC.PC4             4   Port C Data Bit 4
PORTC.PC3             3   Port C Data Bit 3
PORTC.PC2             2   Port C Data Bit 2
PORTC.PC1             1   Port C Data Bit 1
PORTC.PC0             0   Port C Data Bit 0
PORTB                0x1004     Output Port B
PORTB.PB7             7   Port B Data Bit 7
PORTB.PB6             6   Port B Data Bit 6
PORTB.PB5             5   Port B Data Bit 5
PORTB.PB4             4   Port B Data Bit 4
PORTB.PB3             3   Port B Data Bit 3
PORTB.PB2             2   Port B Data Bit 2
PORTB.PB1             1   Port B Data Bit 1
PORTB.PB0             0   Port B Data Bit 0
PORTCL               0x1005     Alternate Latched Port C
PORTCL.PCL7           7
PORTCL.PCL6           6
PORTCL.PCL5           5
PORTCL.PCL4           4
PORTCL.PCL3           3
PORTCL.PCL2           2
PORTCL.PCL1           1
PORTCL.PCL0           0
RESERV1006           0x1006     RESERVED06
DDRC                 0x1007     Data Direction for Port C
DDRC.DDC7             7   Data Direction for Port C Bit 7
DDRC.DDC6             6   Data Direction for Port C Bit 6
DDRC.DDC5             5   Data Direction for Port C Bit 5
DDRC.DDC4             4   Data Direction for Port C Bit 4
DDRC.DDC3             3   Data Direction for Port C Bit 3
DDRC.DDC2             2   Data Direction for Port C Bit 2
DDRC.DDC1             1   Data Direction for Port C Bit 1
DDRC.DDC0             0   Data Direction for Port C Bit 0
PORTD                0x1008     Port D Data
PORTD.PD5             5   Port D Data Bit 5
PORTD.PD4             4   Port D Data Bit 4
PORTD.PD3             3   Port D Data Bit 3
PORTD.PD2             2   Port D Data Bit 2
PORTD.PD1             1   Port D Data Bit 1
PORTD.PD0             0   Port D Data Bit 0
DDRD                 0x1009     Data Direction for Port D
DDRD.DDD5             5   Data Direction for Port D Bit 5
DDRD.DDD4             4   Data Direction for Port D Bit 4
DDRD.DDD3             3   Data Direction for Port D Bit 3
DDRD.DDD2             2   Data Direction for Port D Bit 2
DDRD.DDD1             1   Data Direction for Port D Bit 1
DDRD.DDD0             0   Data Direction for Port D Bit 0
PORTE                0x100A     Port E Data
PORTE.PE7             7   Port E Data Bit 7
PORTE.PE6             6   Port E Data Bit 6
PORTE.PE5             5   Port E Data Bit 5
PORTE.PE4             4   Port E Data Bit 4
PORTE.PE3             3   Port E Data Bit 3
PORTE.PE2             2   Port E Data Bit 2
PORTE.PE1             1   Port E Data Bit 1
PORTE.PE0             0   Port E Data Bit 0
CFORC                0x100B     Timer Compare Force Register
CFORC.FOC1            7   Force Output Comparison Bit 1
CFORC.FOC2            6   Force Output Comparison Bit 2
CFORC.FOC3            5   Force Output Comparison Bit 3
CFORC.FOC4            4   Force Output Comparison Bit 4
CFORC.FOC5            3   Force Output Comparison Bit 5
OC1M                 0x100C     Output Compare 1 Mask Register
OC1M.OC1M7            7   Output Compare Masks 7
OC1M.OC1M6            6   Output Compare Masks 6
OC1M.OC1M5            5   Output Compare Masks 5
OC1M.OC1M4            4   Output Compare Masks 4
OC1M.OC1M3            3   Output Compare Masks 3
OC1D                 0x100D     Output Compare 1 Data Register
OC1D.OC1D7            7
OC1D.OC1D6            6
OC1D.OC1D5            5
OC1D.OC1D4            4
OC1D.OC1D3            3
TCNTH                0x100E     Timer Counter Register
TCNTL                0x100F     Timer Counter Register
TIC1H                0x1010     Input Capture 1 Register
TIC1L                0x1011     Input Capture 1 Register
TIC2H                0x1012     Input Capture 2 Register
TIC2L                0x1013     Input Capture 2 Register
TIC3H                0x1014     Input Capture 3 Register
TIC3L                0x1015     Input Capture 3 Register
TOC1H                0x1016     Output Compare 1 Register
TOC1L                0x1017     Output Compare 1 Register
TOC2H                0x1018     Output Compare 2 Register
TOC2L                0x1019     Output Compare 2 Register
TOC3H                0x101A     Output Compare 3 Register
TOC3L                0x101B     Output Compare 3 Register
TOC4H                0x101C     Output Compare 4 Register
TOC4L                0x101D     Output Compare 4 Register
TCO5H                0x101E     Output Compare 5 Register
TCO5L                0x101F     Output Compare 5 Register
TCTL1                0x1020     Timer Control Register 1
TCTL1.OM2             7   Output Mode Bits 2
TCTL1.OL2             6   Output Level Bits 2
TCTL1.OM3             5   Output Mode Bits 3
TCTL1.OL3             4   Output Level Bits 3
TCTL1.OM4             3   Output Mode Bits 4
TCTL1.OL4             2   Output Level Bits 4
TCTL1.OM5             1   Output Mode Bits 5
TCTL1.OL5             0   Output Level Bits 5
TCTL2                0x1021     Timer Control Register 2
TCTL2.EDG4B           7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A           6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B           5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A           4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B           3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A           2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B           1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A           0   EDG3A  Input Capture Edge Control Bits
TMSK1                0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I            7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I            6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I            5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I            4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I          3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I            2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I            1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I            0   Input Capture 3 Interrupt Enable Bits
TFLG1                0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F            7   Output Compare 1 Flag
TFLG1.OC2F            6   Output Compare 2 Flag
TFLG1.OC3F            5   Output Compare 3 Flag
TFLG1.OC4F            4   Output Compare 4 Flag
TFLG1.I4_O5F          3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F            2   Input Capture 1 Flag
TFLG1.IC2F            1   Input Capture 2 Flag
TFLG1.IC3F            0   Input Capture 3 Flag
TMSK2                0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI             7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII            6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI           5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII            4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1             1   Timer Prescaler Select Bits 1
TMSK2.PR0             0   Timer Prescaler Select Bits 0
TFLG2                0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF             7   Timer Overflow Interrupt Flag
TFLG2.RTIF            6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF           5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF            4   Pulse Accumulator Input Edge Interrupt Flag
PACTL                0x1026     Pulse Accumulator Control Register
PACTL.DDRA7           7   Data Direction for Port A Bit 7
PACTL.PAEN            6   Pulse Accumulator System Enable Bit
PACTL.PAMOD           5   Pulse Accumulator Mode Bit
PACTL.PEDGE           4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3           3   Data Direction for Port A Bit 3
PACTL.I4_O5           2   Input Capture 4/Output Compare Bit
PACTL.RTR1            1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0            0   RTI Interrupt Rate Select Bits 0
PACNT                0x1027     Pulse Accumulator Count Register
SPCR                 0x1028     SPI Control Register
SPCR.SPIE             7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE              6   Serial Peripheral System Enable Bit
SPCR.DWOM             5   Port D Wired-OR Mode Bit
SPCR.MSTR             4   Master Mode Select Bit
SPCR.CPOL             3   Clock Polarity Bit
SPCR.CPHA             2   Clock Phase Bit
SPCR.SPR1             1   SPI Clock Rate Select Bits 1
SPCR.SPR0             0   SPI Clock Rate Select Bits 0
SPSR                 0x1029     SPI Status Register
SPSR.SPIF             7   SPI Interrupt Complete Flag
SPSR.WCOL             6   Write Collision Bit
SPSR.MODF             4   Mode Fault Bit
SPDR                 0x102A     SPI Data Register
BAUD                 0x102B     SCI Baud Rate Control 3
BAUD.TCLR             7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP1             5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0             4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB             3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2             2   SCI Baud Rate Select Bits 2
BAUD.SCR1             1   SCI Baud Rate Select Bits 1
BAUD.SCR0             0   SCI Baud Rate Select Bits 0
SCCR1                0x102C     SCI Control Register 1
SCCR1.R8              7   Receive Data Bit 8
SCCR1.T8              6   Transmit Data Bit 8
SCCR1.M               4   Mode Bit (select character format)
SCCR1.WAKE            3   Wakeup by Address Mark/Idle Bit
SCCR2                0x102D     Serial Communications Control Register 2
SCCR2.TIE             7   Transmit Interrupt Enable Bit
SCCR2.TCIE            6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE             5   Receiver Interrupt Enable Bit
SCCR2.ILIE            4   Idle-Line Interrupt Enable Bit
SCCR2.TE              3   Transmitter Enable Bit
SCCR2.RE              2   Receiver Enable Bit
SCCR2.RWU             1   Receiver Wakeup Control Bit
SCCR2.SBK             0   Send Break
SCSR                 0x102E     Serial Communications Status Register
SCSR.TDRE             7   Transmit Data Register Empty Flag
SCSR.TC               6   Transmit Complete Flag
SCSR.RDRF             5   Receive Data Register Full Flag
SCSR.IDLE             4   Idle Line Detected Flag
SCSR.OR               3   Overrun Error Flag
SCSR.NF               2   Noise Error Flag
SCSR.FE               1   Framing Error Flag
SCDR                 0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7             7
SCDR.R6T6             6
SCDR.R5T5             5
SCDR.R4T4             4
SCDR.R3T3             3
SCDR.R2T2             2
SCDR.R1T1             1
SCDR.R0T0             0
ADCTL                0x1030     A_D Control Register
ADCTL.CCF             7   Conversion Complete Flag
ADCTL.SCAN            5   Continuous Scan Control Bit
ADCTL.MULT            4   Multiple Channel/Single Channel Control Bit
ADCTL.CD              3   Channel Selects D Bits
ADCTL.CC              2   Channel Selects C Bits
ADCTL.CB              1   Channel Selects B Bits
ADCTL.CA              0   Channel Selects A Bits
ADR1                 0x1031     A_D Result Register 1
ADR2                 0x1032     A_D Result Register 2
ADR3                 0x1033     A_D Result Register 3
ADR4                 0x1034     A_D Result Register 4
BPROT                0x1035     Block Protect Register
BPROT.PTCON           4   Protect CONFIG Register Bit
BPROT.BPRT3           3   Block Protect Bits for EEPROM 3
BPROT.BPRT2           2   Block Protect Bits for EEPROM 2
BPROT.BPRT1           1   Block Protect Bits for EEPROM 1
BPROT.BPRT0           0   Block Protect Bits for EEPROM 0
RESERV1036           0x1036     RESERVED
RESERV1037           0x1037     RESERVED
RESERV1038           0x1038     RESERVED
OPTION               0x1039     System Configuration Options
OPTION.ADPU           7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL           6   Clock Select Bit
OPTION.IRQE           5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY            4   Enable Oscillator Startup Delay Bit
OPTION.CME            3   Clock Monitor Enable Bit
OPTION.CR1            1   COP Timer Rate Select Bits 1
OPTION.CR0            0   COP Timer Rate Select Bits 0
COPRST               0x103A     Arm_Reset COP Timer Circuitry
PPROG                0x103B     EEPROM Program Control Register
PPROG.ODD             7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN            6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE            4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW             3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE           2   Erase Mode Select Bit
PPROG.EELAT           1   EEPROM Latch Control Bit
PPROG.EEPGM           0   EPROM/OTPROM/EEPROM Programming
HPRIO                0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT           7   Read Bootstrap ROM Bit
HPRIO.SMOD            6   Special Mode Select
HPRIO.MDA             5   Mode Select A Bits
HPRIO.IRV             4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3           3   Priority Select Bits 3
HPRIO.PSEL2           2   Priority Select Bits 2
HPRIO.PSEL1           1   Priority Select Bits 1
HPRIO.PSEL0           0   Priority Select Bits 0
INIT                 0x103D     RAM and I_O Mapping Register
INIT.RAM3             7   RAM Map Position Bits 3
INIT.RAM2             6   RAM Map Position Bits 2
INIT.RAM1             5   RAM Map Position Bits 1
INIT.RAM0             4   RAM Map Position Bits 0
INIT.REG3             3   64-Byte Register Block Position 3
INIT.REG2             2   64-Byte Register Block Position 2
INIT.REG1             1   64-Byte Register Block Position 1
INIT.REG0             0   64-Byte Register Block Position 0
RESERV3E             0x103E     RESERVED
CONFIG               0x103F     System Configuration Register
CONFIG.NOSEC          3   Security Disable Bit
CONFIG.NOCOP          2   COP System Disable Bit
CONFIG.ROMON          1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON           0   EEPROM Enable Bit
RESERVFFC0           0xFFC0     RESERVED
RESERVFFC1           0xFFC1     RESERVED
RESERVFFC2           0xFFC2     RESERVED
RESERVFFC3           0xFFC3     RESERVED
RESERVFFC4           0xFFC4     RESERVED
RESERVFFC5           0xFFC5     RESERVED
RESERVFFC6           0xFFC6     RESERVED
RESERVFFC7           0xFFC7     RESERVED
RESERVFFC8           0xFFC8     RESERVED
RESERVFFC9           0xFFC9     RESERVED
RESERVFFCA           0xFFCA     RESERVED
RESERVFFCB           0xFFCB     RESERVED
RESERVFFCC           0xFFCC     RESERVED
RESERVFFCD           0xFFCD     RESERVED
RESERVFFCE           0xFFCE     RESERVED
RESERVFFCF           0xFFCF     RESERVED
RESERVFFD0           0xFFD0     RESERVED
RESERVFFD1           0xFFD1     RESERVED
RESERVFFD2           0xFFD2     RESERVED
RESERVFFD3           0xFFD3     RESERVED
RESERVFFD4           0xFFD4     RESERVED
RESERVFFD5           0xFFD5     RESERVED


.68HC11E9
;  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11E9&nodeId=01M98635
; M68HC11E.pdf

; RAM=512
; ROM=12K
; EPROM=0
; EEPROM=512


; MEMORY MAP
area DATA RAM          0x0000:0x0200
area BSS  RESERVED     0x0200:0x1000
area DATA FSR          0x1000:0x1040
area BSS  RESERVED     0x1040:0xB600
area DATA EEPROM       0xB600:0xB800
area BSS  RESERVED     0xB800:0xD000
area DATA ROM_EPROM    0xD000:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA                0x1000     Port A data
PORTA.PA7     	      7   Port A Data Bit 7
PORTA.PA6             6   Port A Data Bit 6
PORTA.PA5             5   Port A Data Bit 5
PORTA.PA4             4   Port A Data Bit 4
PORTA.PA3             3   Port A Data Bit 3
PORTA.PA2             2   Port A Data Bit 2
PORTA.PA1             1   Port A Data Bit 1
PORTA.PA0             0   Port A Data Bit 0
RESERV01             0x1001     RESERVED
PIOC                 0x1002     Parallel I_O Control Register
PIOC.STAF             7   Strobe A Interrupt Status Flag
PIOC.STAI             6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM             5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS             4   Handshake Mode Bit
PIOC.OIN              3   Output or Input Handshake Select Bit
PIOC.PLS              2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA              1   Active Edge for Strobe A Bit
PIOC.INVB             0   Invert Strobe B Bit
PORTC                0x1003      Port C Data
PORTC.PC7             7   Port C Data Bit 7
PORTC.PC6             6   Port C Data Bit 6
PORTC.PC5             5   Port C Data Bit 5
PORTC.PC4             4   Port C Data Bit 4
PORTC.PC3             3   Port C Data Bit 3
PORTC.PC2             2   Port C Data Bit 2
PORTC.PC1             1   Port C Data Bit 1
PORTC.PC0             0   Port C Data Bit 0
PORTB                0x1004     Output Port B
PORTB.PB7             7   Port B Data Bit 7
PORTB.PB6             6   Port B Data Bit 6
PORTB.PB5             5   Port B Data Bit 5
PORTB.PB4             4   Port B Data Bit 4
PORTB.PB3             3   Port B Data Bit 3
PORTB.PB2             2   Port B Data Bit 2
PORTB.PB1             1   Port B Data Bit 1
PORTB.PB0             0   Port B Data Bit 0
PORTCL               0x1005     Alternate Latched Port C
PORTCL.PCL7           7
PORTCL.PCL6           6
PORTCL.PCL5           5
PORTCL.PCL4           4
PORTCL.PCL3           3
PORTCL.PCL2           2
PORTCL.PCL1           1
PORTCL.PCL0           0
RESERV1006           0x1006     RESERVED06
DDRC                 0x1007     Data Direction for Port C
DDRC.DDC7             7   Data Direction for Port C Bit 7
DDRC.DDC6             6   Data Direction for Port C Bit 6
DDRC.DDC5             5   Data Direction for Port C Bit 5
DDRC.DDC4             4   Data Direction for Port C Bit 4
DDRC.DDC3             3   Data Direction for Port C Bit 3
DDRC.DDC2             2   Data Direction for Port C Bit 2
DDRC.DDC1             1   Data Direction for Port C Bit 1
DDRC.DDC0             0   Data Direction for Port C Bit 0
PORTD                0x1008     Port D Data
PORTD.PD5             5   Port D Data Bit 5
PORTD.PD4             4   Port D Data Bit 4
PORTD.PD3             3   Port D Data Bit 3
PORTD.PD2             2   Port D Data Bit 2
PORTD.PD1             1   Port D Data Bit 1
PORTD.PD0             0   Port D Data Bit 0
DDRD                 0x1009     Data Direction for Port D
DDRD.DDD5             5   Data Direction for Port D Bit 5
DDRD.DDD4             4   Data Direction for Port D Bit 4
DDRD.DDD3             3   Data Direction for Port D Bit 3
DDRD.DDD2             2   Data Direction for Port D Bit 2
DDRD.DDD1             1   Data Direction for Port D Bit 1
DDRD.DDD0             0   Data Direction for Port D Bit 0
PORTE                0x100A     Port E Data
PORTE.PE7             7   Port E Data Bit 7
PORTE.PE6             6   Port E Data Bit 6
PORTE.PE5             5   Port E Data Bit 5
PORTE.PE4             4   Port E Data Bit 4
PORTE.PE3             3   Port E Data Bit 3
PORTE.PE2             2   Port E Data Bit 2
PORTE.PE1             1   Port E Data Bit 1
PORTE.PE0             0   Port E Data Bit 0
CFORC                0x100B     Timer Compare Force Register
CFORC.FOC1            7   Force Output Comparison Bit 1
CFORC.FOC2            6   Force Output Comparison Bit 2
CFORC.FOC3            5   Force Output Comparison Bit 3
CFORC.FOC4            4   Force Output Comparison Bit 4
CFORC.FOC5            3   Force Output Comparison Bit 5
OC1M                 0x100C     Output Compare 1 Mask Register
OC1M.OC1M7            7   Output Compare Masks 7
OC1M.OC1M6            6   Output Compare Masks 6
OC1M.OC1M5            5   Output Compare Masks 5
OC1M.OC1M4            4   Output Compare Masks 4
OC1M.OC1M3            3   Output Compare Masks 3
OC1D                 0x100D     Output Compare 1 Data Register
OC1D.OC1D7            7
OC1D.OC1D6            6
OC1D.OC1D5            5
OC1D.OC1D4            4
OC1D.OC1D3            3
TCNTH                0x100E     Timer Counter Register
TCNTL                0x100F     Timer Counter Register
TIC1H                0x1010     Input Capture 1 Register
TIC1L                0x1011     Input Capture 1 Register
TIC2H                0x1012     Input Capture 2 Register
TIC2L                0x1013     Input Capture 2 Register
TIC3H                0x1014     Input Capture 3 Register
TIC3L                0x1015     Input Capture 3 Register
TOC1H                0x1016     Output Compare 1 Register
TOC1L                0x1017     Output Compare 1 Register
TOC2H                0x1018     Output Compare 2 Register
TOC2L                0x1019     Output Compare 2 Register
TOC3H                0x101A     Output Compare 3 Register
TOC3L                0x101B     Output Compare 3 Register
TOC4H                0x101C     Output Compare 4 Register
TOC4L                0x101D     Output Compare 4 Register
TCO5H                0x101E     Output Compare 5 Register
TCO5L                0x101F     Output Compare 5 Register
TCTL1                0x1020     Timer Control Register 1
TCTL1.OM2             7   Output Mode Bits 2
TCTL1.OL2             6   Output Level Bits 2
TCTL1.OM3             5   Output Mode Bits 3
TCTL1.OL3             4   Output Level Bits 3
TCTL1.OM4             3   Output Mode Bits 4
TCTL1.OL4             2   Output Level Bits 4
TCTL1.OM5             1   Output Mode Bits 5
TCTL1.OL5             0   Output Level Bits 5
TCTL2                0x1021     Timer Control Register 2
TCTL2.EDG4B           7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A           6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B           5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A           4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B           3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A           2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B           1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A           0   EDG3A  Input Capture Edge Control Bits
TMSK1                0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I            7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I            6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I            5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I            4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I          3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I            2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I            1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I            0   Input Capture 3 Interrupt Enable Bits
TFLG1                0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F            7   Output Compare 1 Flag
TFLG1.OC2F            6   Output Compare 2 Flag
TFLG1.OC3F            5   Output Compare 3 Flag
TFLG1.OC4F            4   Output Compare 4 Flag
TFLG1.I4_O5F          3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F            2   Input Capture 1 Flag
TFLG1.IC2F            1   Input Capture 2 Flag
TFLG1.IC3F            0   Input Capture 3 Flag
TMSK2                0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI             7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII            6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI           5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII            4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1             1   Timer Prescaler Select Bits 1
TMSK2.PR0             0   Timer Prescaler Select Bits 0
TFLG2                0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF             7   Timer Overflow Interrupt Flag
TFLG2.RTIF            6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF           5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF            4   Pulse Accumulator Input Edge Interrupt Flag
PACTL                0x1026     Pulse Accumulator Control Register
PACTL.DDRA7           7   Data Direction for Port A Bit 7
PACTL.PAEN            6   Pulse Accumulator System Enable Bit
PACTL.PAMOD           5   Pulse Accumulator Mode Bit
PACTL.PEDGE           4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3           3   Data Direction for Port A Bit 3
PACTL.I4_O5           2   Input Capture 4/Output Compare Bit
PACTL.RTR1            1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0            0   RTI Interrupt Rate Select Bits 0
PACNT                0x1027     Pulse Accumulator Count Register
SPCR                 0x1028     SPI Control Register
SPCR.SPIE             7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE              6   Serial Peripheral System Enable Bit
SPCR.DWOM             5   Port D Wired-OR Mode Bit
SPCR.MSTR             4   Master Mode Select Bit
SPCR.CPOL             3   Clock Polarity Bit
SPCR.CPHA             2   Clock Phase Bit
SPCR.SPR1             1   SPI Clock Rate Select Bits 1
SPCR.SPR0             0   SPI Clock Rate Select Bits 0
SPSR                 0x1029     SPI Status Register
SPSR.SPIF             7   SPI Interrupt Complete Flag
SPSR.WCOL             6   Write Collision Bit
SPSR.MODF             4   Mode Fault Bit
SPDR                 0x102A     SPI Data Register
BAUD                 0x102B     SCI Baud Rate Control 3
BAUD.TCLR             7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP1             5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0             4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB             3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2             2   SCI Baud Rate Select Bits 2
BAUD.SCR1             1   SCI Baud Rate Select Bits 1
BAUD.SCR0             0   SCI Baud Rate Select Bits 0
SCCR1                0x102C     SCI Control Register 1
SCCR1.R8              7   Receive Data Bit 8
SCCR1.T8              6   Transmit Data Bit 8
SCCR1.M               4   Mode Bit (select character format)
SCCR1.WAKE            3   Wakeup by Address Mark/Idle Bit
SCCR2                0x102D     Serial Communications Control Register 2
SCCR2.TIE             7   Transmit Interrupt Enable Bit
SCCR2.TCIE            6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE             5   Receiver Interrupt Enable Bit
SCCR2.ILIE            4   Idle-Line Interrupt Enable Bit
SCCR2.TE              3   Transmitter Enable Bit
SCCR2.RE              2   Receiver Enable Bit
SCCR2.RWU             1   Receiver Wakeup Control Bit
SCCR2.SBK             0   Send Break
SCSR                 0x102E     Serial Communications Status Register
SCSR.TDRE             7   Transmit Data Register Empty Flag
SCSR.TC               6   Transmit Complete Flag
SCSR.RDRF             5   Receive Data Register Full Flag
SCSR.IDLE             4   Idle Line Detected Flag
SCSR.OR               3   Overrun Error Flag
SCSR.NF               2   Noise Error Flag
SCSR.FE               1   Framing Error Flag
SCDR                 0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7             7
SCDR.R6T6             6
SCDR.R5T5             5
SCDR.R4T4             4
SCDR.R3T3             3
SCDR.R2T2             2
SCDR.R1T1             1
SCDR.R0T0             0
ADCTL                0x1030     A_D Control Register
ADCTL.CCF             7   Conversion Complete Flag
ADCTL.SCAN            5   Continuous Scan Control Bit
ADCTL.MULT            4   Multiple Channel/Single Channel Control Bit
ADCTL.CD              3   Channel Selects D Bits
ADCTL.CC              2   Channel Selects C Bits
ADCTL.CB              1   Channel Selects B Bits
ADCTL.CA              0   Channel Selects A Bits
ADR1                 0x1031     A_D Result Register 1
ADR2                 0x1032     A_D Result Register 2
ADR3                 0x1033     A_D Result Register 3
ADR4                 0x1034     A_D Result Register 4
BPROT                0x1035     Block Protect Register
BPROT.PTCON           4   Protect CONFIG Register Bit
BPROT.BPRT3           3   Block Protect Bits for EEPROM 3
BPROT.BPRT2           2   Block Protect Bits for EEPROM 2
BPROT.BPRT1           1   Block Protect Bits for EEPROM 1
BPROT.BPRT0           0   Block Protect Bits for EEPROM 0
RESERV1036           0x1036     RESERVED
RESERV1037           0x1037     RESERVED
RESERV1038           0x1038     RESERVED
OPTION               0x1039     System Configuration Options
OPTION.ADPU           7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL           6   Clock Select Bit
OPTION.IRQE           5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY            4   Enable Oscillator Startup Delay Bit
OPTION.CME            3   Clock Monitor Enable Bit
OPTION.CR1            1   COP Timer Rate Select Bits 1
OPTION.CR0            0   COP Timer Rate Select Bits 0
COPRST               0x103A     Arm_Reset COP Timer Circuitry
PPROG                0x103B     EEPROM Program Control Register
PPROG.ODD             7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN            6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE            4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW             3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE           2   Erase Mode Select Bit
PPROG.EELAT           1   EEPROM Latch Control Bit
PPROG.EEPGM           0   EPROM/OTPROM/EEPROM Programming
HPRIO                0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT           7   Read Bootstrap ROM Bit
HPRIO.SMOD            6   Special Mode Select
HPRIO.MDA             5   Mode Select A Bits
HPRIO.IRV             4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3           3   Priority Select Bits 3
HPRIO.PSEL2           2   Priority Select Bits 2
HPRIO.PSEL1           1   Priority Select Bits 1
HPRIO.PSEL0           0   Priority Select Bits 0
INIT                 0x103D     RAM and I_O Mapping Register
INIT.RAM3             7   RAM Map Position Bits 3
INIT.RAM2             6   RAM Map Position Bits 2
INIT.RAM1             5   RAM Map Position Bits 1
INIT.RAM0             4   RAM Map Position Bits 0
INIT.REG3             3   64-Byte Register Block Position 3
INIT.REG2             2   64-Byte Register Block Position 2
INIT.REG1             1   64-Byte Register Block Position 1
INIT.REG0             0   64-Byte Register Block Position 0
RESERV3E             0x103E     RESERVED
CONFIG               0x103F     System Configuration Register
CONFIG.NOSEC          3   Security Disable Bit
CONFIG.NOCOP          2   COP System Disable Bit
CONFIG.ROMON          1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON           0   EEPROM Enable Bit
RESERVFFC0           0xFFC0     RESERVED
RESERVFFC1           0xFFC1     RESERVED
RESERVFFC2           0xFFC2     RESERVED
RESERVFFC3           0xFFC3     RESERVED
RESERVFFC4           0xFFC4     RESERVED
RESERVFFC5           0xFFC5     RESERVED
RESERVFFC6           0xFFC6     RESERVED
RESERVFFC7           0xFFC7     RESERVED
RESERVFFC8           0xFFC8     RESERVED
RESERVFFC9           0xFFC9     RESERVED
RESERVFFCA           0xFFCA     RESERVED
RESERVFFCB           0xFFCB     RESERVED
RESERVFFCC           0xFFCC     RESERVED
RESERVFFCD           0xFFCD     RESERVED
RESERVFFCE           0xFFCE     RESERVED
RESERVFFCF           0xFFCF     RESERVED
RESERVFFD0           0xFFD0     RESERVED
RESERVFFD1           0xFFD1     RESERVED
RESERVFFD2           0xFFD2     RESERVED
RESERVFFD3           0xFFD3     RESERVED
RESERVFFD4           0xFFD4     RESERVED
RESERVFFD5           0xFFD5     RESERVED


.68HC11EA9
; MC68HC11EA9TS/D http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11EA9TS.pdf
; ea9.pdf

; RAM=512
; ROM=12K
; EPROM=0
; EEPROM=512


; MEMORY MAP
area DATA RAM          0x0000:0x0200
area BSS  RESERVED     0x0200:0x1000
area DATA FSR          0x1000:0x1040
area BSS  RESERVED     0x1040:0xB600
area DATA EEPROM       0xB600:0xB800
area BSS  RESERVED     0xB800:0xD000
area DATA ROM_EPROM    0xD000:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET   0xFFFE    Processor reset
interrupt CME       0xFFFC    Clock Monitor Fail
interrupt NOCOP     0xFFFA    COP Failure
interrupt OPC       0xFFF8    Illegal Opcode Trap
interrupt SOFT      0xFFF6    Software Interrupt
interrupt XIRQ      0xFFF4    XIRQ Pin
interrupt IRQ       0xFFF2    IRQ
interrupt RTII      0xFFF0    Real Time Interrupt
interrupt IC1I      0xFFEE    Timer Input Capture 1
interrupt IC2I      0xFFEC    Timer Input Capture 2
interrupt IC3I      0xFFEA    Timer Input Capture 3
interrupt OC1I      0xFFE8    Timer Output Compare 1
interrupt OC2I      0xFFE6    Timer Output Compare 2
interrupt OC3I      0xFFE4    Timer Output Compare 3
interrupt OC4I      0xFFE2    Timer Output Compare 4
interrupt I4_I5     0xFFE0    Timer Input Capture 4 / Output Compare 5
interrupt TOI       0xFFDE    Timer Overflow
interrupt PAOVI     0xFFDC    Pulse Accumulator Overflow
interrupt PAII      0xFFDA    Pulse Accumulator Input Edge
interrupt SCISS     0xFFD6    SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA            0x1000     Port A data
PORTA.PA7     	  7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
DDRA             0x1001     Data Direction Port A
DDRA.DDA7         7   Data Direction for Port A Bit 7
DDRA.DDA6         6   Data Direction for Port A Bit 6
DDRA.DDA5         5   Data Direction for Port A Bit 5
DDRA.DDA4         4   Data Direction for Port A Bit 4
DDRA.DDA3         3   Data Direction for Port A Bit 3
DDRA.DDA2         2   Data Direction for Port A Bit 2
DDRA.DDA1         1   Data Direction for Port A Bit 1
DDRA.DDA0         0   Data Direction for Port A Bit 0
PIOC             0x1002     Parallel I_O Control Register
PIOC.STAF         7   Strobe A Interrupt Status Flag
PIOC.STAI         6   Strobe A Interrupt Enable
PIOC.CWOM         5   Strobe A Interrupt Enable
PIOC.HNDS         4   Handshake Mode
PIOC.OIN          3   Output or Input Handshaking
PIOC.PLS          2   Pulse/Interlocked Handshake Operation
PIOC.EGA          1   Active Edge for Strobe A
PIOC.INVB         0   Invert Strobe B
PORTC            0x1003      Port C Data
PORTC.PC7         7   Port C Data Bit 7
PORTC.PC6         6   Port C Data Bit 6
PORTC.PC5         5   Port C Data Bit 5
PORTC.PC4         4   Port C Data Bit 4
PORTC.PC3         3   Port C Data Bit 3
PORTC.PC2         2   Port C Data Bit 2
PORTC.PC1         1   Port C Data Bit 1
PORTC.PC0         0   Port C Data Bit 0
PORTB            0x1004     Port B Data
PORTB.PB7         7   Port B Data Bit 7
PORTB.PB6         6   Port B Data Bit 6
PORTB.PB5         5   Port B Data Bit 5
PORTB.PB4         4   Port B Data Bit 4
PORTB.PB3         3   Port B Data Bit 3
PORTB.PB2         2   Port B Data Bit 2
PORTB.PB1         1   Port B Data Bit 1
PORTB.PB0         0   Port B Data Bit 0
PORTCL           0x1005     Alternate Latched Port C
PORTCL.PCL7       7
PORTCL.PCL6       6
PORTCL.PCL5       5
PORTCL.PCL4       4
PORTCL.PCL3       3
PORTCL.PCL2       2
PORTCL.PCL1       1
PORTCL.PCL0       0
DDRB             0x1006     Data Direction Port B
DDRB.DDB7         7   Data Direction for Port B Bit 7
DDRB.DDB6         6   Data Direction for Port B Bit 6
DDRB.DDB5         5   Data Direction for Port B Bit 5
DDRB.DDB4         4   Data Direction for Port B Bit 4
DDRB.DDB3         3   Data Direction for Port B Bit 3
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRB.DDB1         1   Data Direction for Port B Bit 1
DDRB.DDB0         0   Data Direction for Port B Bit 0
DDRC             0x1007     Data Direction for Port C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x1008     Port D Data
PORTD.XPIN        7   XIRQ Interrupt Pin Status Flag
PORTD.IPIN        6   IRQ Interrupt Pin Status Flag
PORTD.PD1         1   Port D Data Bit 1
PORTD.PD0         0   Port D Data Bit 0
DDRD             0x1009     Data Direction for Port D
DDRD.DISX         7   Disable XIRQ Pin Interrupts
DDRD.DISI         6   Disable IRQ Pin Interrupts
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
PORTE            0x100A     Port E Data
PORTE.PE7         7   Port E Data Bit 7
PORTE.PE6         6   Port E Data Bit 6
PORTE.PE5         5   Port E Data Bit 5
PORTE.PE4         4   Port E Data Bit 4
PORTE.PE3         3   Port E Data Bit 3
PORTE.PE2         2   Port E Data Bit 2
PORTE.PE1         1   Port E Data Bit 1
PORTE.PE0         0   Port E Data Bit 0
CFORC            0x100B     Compare Force Register
CFORC.FOC1        7   Force Output Compare 1
CFORC.FOC2        6   Force Output Compare 2
CFORC.FOC3        5   Force Output Compare 3
CFORC.FOC4        4   Force Output Compare 4
CFORC.FOC5        3   Force Output Compare 5
OC1M             0x100C     OC1 Action Mask Register
OC1M.OC1M7        7
OC1M.OC1M6        6
OC1M.OC1M5        5
OC1M.OC1M4        4
OC1M.OC1M3        3
OC1D             0x100D      OC1 Action Data Register
OC1D.OC1D7        7
OC1D.OC1D6        6
OC1D.OC1D5        5
OC1D.OC1D4        4
OC1D.OC1D3        3
TCNTH            0x100E     Timer Counter Register (HI)
TCNTL            0x100F     Timer Counter Register (LO)
TIC1H            0x1010     Input Capture 1 Register (HI)
TIC1L            0x1011     Input Capture 1 Register (LO)
TIC2H            0x1012     Input Capture 2 Register (HI)
TIC2L            0x1013     Input Capture 2 Register (LO)
TIC3H            0x1014     Input Capture 3 Register (HI)
TIC3L            0x1015     Input Capture 3 Register (LO)
TOC1H            0x1016     Output Compare 1 Register (HI)
TOC1L            0x1017     Output Compare 1 Register (LO)
TOC2H            0x1018     Output Compare 2 Register (HI)
TOC2L            0x1019     Output Compare 2 Register (LO)
TOC3H            0x101A     Output Compare 3 Register (HI)
TOC3L            0x101B     Output Compare 3 Register (LO)
TOC4H            0x101C     Output Compare 4 Register (HI)
TOC4L            0x101D     Output Compare 4 Register (LO)
TCO5H            0x101E     Output Compare 5 Register (HI)
TCO5L            0x101F     Output Compare 5 Register (LO)
TCTL1            0x1020     Timer Control Register 1
TCTL1.OM2         7
TCTL1.OL2         6
TCTL1.OM3         5
TCTL1.OL3         4
TCTL1.OM4         3
TCTL1.OL4         2
TCTL1.OM5         1
TCTL1.OL5         0
TCTL2            0x1021     Timer Control Register 2
TCTL2.EDG4B       7
TCTL2.EDG4A       6
TCTL2.EDG1B       5
TCTL2.EDG1A       4
TCTL2.EDG2B       3
TCTL2.EDG2A       2
TCTL2.EDG3B       1
TCTL2.EDG3A       0
TMSK1            0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I        7   Output Compare (OC1) Interrupt Enable
TMSK1.OC2I        6   Output Compare (OC2) Interrupt Enable
TMSK1.OC3I        5   Output Compare (OC3) Interrupt Enable
TMSK1.OC4I        4   Output Compare (OC4) Interrupt Enable
TMSK1.I4_O5I      3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I        2   Input Capture (IC1) Interrupt Enable
TMSK1.IC2I        1   Input Capture (IC2) Interrupt Enable
TMSK1.IC3I        0   Input Capture (IC3) Interrupt Enable
TFLG1            0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F        7   Output Compare (OC1) Interrupt Flag
TFLG1.OC2F        6   Output Compare (OC2) Interrupt Flag
TFLG1.OC3F        5   Output Compare (OC3) Interrupt Flag
TFLG1.OC4F        4   Output Compare (OC4) Interrupt Flag
TFLG1.I4_O5F      3   Input Capture 4/Output Compare 5 Interrupt Enable
TFLG1.IC1F        2   Input Capture (IC1) Interrupt Enable
TFLG1.IC2F        1   Input Capture (IC2) Interrupt Enable
TFLG1.IC3F        0   Input Capture (IC3) Interrupt Enable
TMSK2            0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable
TMSK2.RTII        6   Real-Time Interrupt Enable
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII        4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1         1   Timer Prescaler Select 1
TMSK2.PR0         0   Timer Prescaler Select 0
TFLG2            0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF         7   Timer Overflow Interrupt Flag
TFLG2.RTIF        6   Real-Time Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Interrupt Flag
PACTL            0x1026     Pulse Accumulator Control Register
PACTL.PAEN        6   Pulse Accumulator Enable
PACTL.PAMOD       5   Pulse Accumulator Mode Select
PACTL.PEDGE       4   Pulse Accumulator Input Edge Select
PACTL.I4_O5       2   Input Capture 4/Output Compare 5 Select
PACTL.RTR1        1   Real-Time Interrupt Rate Select 1
PACTL.RTR0        0   Real-Time Interrupt Rate Select 0
PACNT            0x1027     Pulse Accumulator Count Register
SCBDH            0x1028     SCI Baud Rate Select High
SCBDH.BTST        7   Baud Register Test (TEST)
SCBDH.BSPL        6   Baud Rate Counter Split (TEST)
SCBDH.SBR12       4   SCI Baud Rate Select Bits 12
SCBDH.SBR11       3   SCI Baud Rate Select Bits 11
SCBDH.SBR10       2   SCI Baud Rate Select Bits 10
SCBDH.SBR9        1   SCI Baud Rate Select Bits 9
SCBDH.SBR8        0   SCI Baud Rate Select Bits 8
SCBDL            0x1029     SCI Baud Rate Select Low
SCBDL.SBR7        7   SCI Baud Rate Select Bits 7
SCBDL.SBR6        6   SCI Baud Rate Select Bits 6
SCBDL.SBR5        5   SCI Baud Rate Select Bits 5
SCBDL.SBR4        4   SCI Baud Rate Select Bits 4
SCBDL.SBR3        3   SCI Baud Rate Select Bits 3
SCBDL.SBR2        2   SCI Baud Rate Select Bits 2
SCBDL.SBR1        1   SCI Baud Rate Select Bits 1
SCBDL.SBR0        0   SCI Baud Rate Select Bits 0
SCCR1            0x102A     SCI Control Register 1
SCCR1.LOOPS       7   SCI LOOP Mode Enable
SCCR1.WOMS        6   Wired-Or Mode Option for PD[1:0] (See also DWOM bit in SPCR.)
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake-Up by Address Mark/Idle
SCCR1.ILT         2   Idle Line Type
SCCR1.PE          1   Parity Enable
SCCR1.PT          0   Parity Type
SCCR2            0x102B     SCI Control Register 2
SCCR2.TIE         7   Transmit Interrupt Enable
SCCR2.TCIE        6   Transmit Complete Interrupt Enable
SCCR2.RIE         5   Receiver Interrupt Enable
SCCR2.ILIE        4   Idle Line Interrupt Enable
SCCR2.TE          3   Transmitter Enable
SCCR2.RE          2   Receiver Enable
SCCR2.RWU         1   Receiver Wake-Up Control
SCCR2.SBK         0   Send Break
SCSR1            0x102C     SCI Status Register
SCSR1.TDRE        7   Transmit Data Register Empty Flag
SCSR1.TC          6   Transmit Complete Flag
SCSR1.RDRF        5   Receive Data Register Full Flag
SCSR1.IDLE        4   Idle Line Detected Flag
SCSR1.OR          3   Overrun Error Flag
SCSR1.NF          2   Noise Error Flag
SCSR1.FE          1   Framing Error
SCSR1.PF          0   Parity Error Flag
SCSR2            0x102D     SCI Status Register 2
SCSR2.RAF         0   Receiver Active Flag (Read only)
SCDRH            0x102E     SCI Data High
SCDRH.R8          7   Receiver Bit 8
SCDRH.T8          6   Transmitter Bit 8
SCDRL            0x102F     SCI Data Low
SCDRL.R7T7        7   Receiver/Transmitter Data Bits 7
SCDRL.R6T6        6   Receiver/Transmitter Data Bits 6
SCDRL.R5T5        5   Receiver/Transmitter Data Bits 5
SCDRL.R4T4        4   Receiver/Transmitter Data Bits 4
SCDRL.R3T3        3   Receiver/Transmitter Data Bits 3
SCDRL.R2T2        2   Receiver/Transmitter Data Bits 2
SCDRL.R1T1        1   Receiver/Transmitter Data Bits 1
SCDRL.R0T0        0   Receiver/Transmitter Data Bits 0
ADCTL            0x1030     A_D Control Register
ADCTL.CCF         7   Conversions Complete Flag
ADCTL.SCAN        5   Continuous Scan Control
ADCTL.MULT        4   Multiple Channel/Single Channel Control
ADCTL.CD          3   Channel Select D
ADCTL.CC          2   Channel Select C
ADCTL.CB          1   Channel Select B
ADCTL.CA          0   Channel Select A
ADR1             0x1031     A_D Result Register 1
ADR2             0x1032     A_D Result Register 2
ADR3             0x1033     A_D Result Register 3
ADR4             0x1034     A_D Result Register 4
BPROT            0x1035     Block Protect Register
BPROT.PTCON       4   Protect CONFIG Register
BPROT.BPRT3       3   Block Protect Bits for EEPROM 3
BPROT.BPRT2       2   Block Protect Bits for EEPROM 2
BPROT.BPRT1       1   Block Protect Bits for EEPROM 1
BPROT.BPRT0       0   Block Protect Bits for EEPROM 0
PLLCR            0x1036     PLL Control
PLLCR.PLLON       7   PLL System Enable
PLLCR.BCS         6   Bus Clock Select
PLLCR.AUTO        5   Automatic/Manual Loop Filter Bandwidth Control
PLLCR.BWC         4   Loop Filter Bandwidth Control/Status
PLLCR.VCOT        3   Voltage Controlled Oscillator (VCO) Test
PLLCR.MCS         2   Module Clock Select
PLLCR.LCK         1   Synthesizer Lock Detect Flag
PLLCR.WEN         0   WAIT Enable
SYNR             0x1037     Frequency Synthesizer Control
SYNR.SYNX1        7   Binary Tap Select Bits 1
SYNR.SYNX0        6   Binary Tap Select Bits 0
SYNR.SYNY5        5   Modulo Counter Rate Select Bits 5
SYNR.SYNY4        4   Modulo Counter Rate Select Bits 4
SYNR.SYNY3        3   Modulo Counter Rate Select Bits 3
SYNR.SYNY2        2   Modulo Counter Rate Select Bits 2
SYNR.SYNY1        1   Modulo Counter Rate Select Bits 1
SYNR.SYNY0        0   Modulo Counter Rate Select Bits 0
RESERV38         0x1038     RESERVED
OPTION           0x1039     System Configuration Options
OPTION.ADPU       7   A/D Converter Power up
OPTION.CSEL       6   Clock Select
OPTION.IRQE       5   IRQ Select Edge-Sensitive Only
OPTION.DLY        4   Enable Oscillator Start-up Delay
OPTION.CME        3   Clock Monitor Enable
OPTION.CR1        1   COP Timer Rate Select 1
OPTION.CR0        0   COP Timer Rate Select 0
COPRST           0x103A     Arm_Reset COP Timer Circuitry
PPROG            0x103B     EEPROM Program Control Register
PPROG.ODD         7   Program Odd Rows in Half of EEPROM (TEST)
PPROG.EVEN        6   Program Even Rows in Half of EEPROM (TEST)
PPROG.BYTE        4   Byte/Other EEPROM Erase Mode
PPROG.ROW         3   Row/All EEPROM Erase Mode
PPROG.ERASE       2   Erase/Normal Control for EEPROM
PPROG.EELAT       1   EEPROM Latch Control
PPROG.PGM         0   EPROM/OTPROM/EEPROM Programming Voltage Enable
HPRIO            0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT       7   Read Bootstrap ROM/EPROM
HPRIO.SMOD        6   Special Mode Select
HPRIO.MDA         5   Mode Select A
HPRIO.IRVNE       4   Internal Read Visibility(Not E)
HPRIO.PSEL3       3   Priority Select Bits 3
HPRIO.PSEL2       2   Priority Select Bits 2
HPRIO.PSEL1       1   Priority Select Bits 1
HPRIO.PSEL0       0   Priority Select Bits 0
INIT             0x103D     RAM and I_O Mapping Register
INIT.RAM3         7   RAM Map Position 3
INIT.RAM2         6   RAM Map Position 2
INIT.RAM1         5   RAM Map Position 1
INIT.RAM0         4   RAM Map Position 0
INIT.REG3         3   64-Byte Register Block Position 3
INIT.REG2         2   64-Byte Register Block Position 2
INIT.REG1         1   64-Byte Register Block Position 1
INIT.REG0         0   64-Byte Register Block Position 0
RESERV103E       0x103E     RESERVED
CONFIG           0x103F     COP, ROM, and EEPROM Enables
CONFIG.NOSEC      3   Security Disable
CONFIG.NOCOP      2   COP System Disable
CONFIG.ROMON      1   ROM/EPROM/OTPROM Enable
CONFIG.EEON       0   EEPROM Enable
RESERVFFC0       0xFFC0     RESERVED
RESERVFFC1       0xFFC1     RESERVED
RESERVFFC2       0xFFC2     RESERVED
RESERVFFC3       0xFFC3     RESERVED
RESERVFFC4       0xFFC4     RESERVED
RESERVFFC5       0xFFC5     RESERVED
RESERVFFC6       0xFFC6     RESERVED
RESERVFFC7       0xFFC7     RESERVED
RESERVFFC8       0xFFC8     RESERVED
RESERVFFC9       0xFFC9     RESERVED
RESERVFFCA       0xFFCA     RESERVED
RESERVFFCB       0xFFCB     RESERVED
RESERVFFCC       0xFFCC     RESERVED
RESERVFFCD       0xFFCD     RESERVED
RESERVFFCE       0xFFCE     RESERVED
RESERVFFCF       0xFFCF     RESERVED
RESERVFFD0       0xFFD0     RESERVED
RESERVFFD1       0xFFD1     RESERVED
RESERVFFD2       0xFFD2     RESERVED
RESERVFFD3       0xFFD3     RESERVED
RESERVFFD4       0xFFD4     RESERVED
RESERVFFD5       0xFFD5     RESERVED
RESERVFFD8       0xFFD8     RESERVED
RESERVFFD9       0xFFD9     RESERVED


.68HC11ED0
; MC68HC11ED0TS/D http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11ED0TS.pdf
; MC68HC11ED0TS.pdf

; RAM=512
; ROM=
; EPROM=
; EEPROM=


;MEMORY MAP
area DATA FSR        0x0000:0x0040
area DATA RAM        0x0040:0x1040
area DATA EXT        0x1040:0xFFC0
area DATA USER_VEC   0xFFC0:0x10000

; area DATA RAM        0x0000:0x0100
; area BSS  RESERVED   0x0100:0x1000
; area DATA FSR        0x1000:0x1040
; area BSS  RESERVED   0x1040:0xB600
; area DATA EEPROM     0xB600:0xB800
; area BSS  RESERVED   0xB800:0xE000
; area DATA ROM        0xE000:0xFFC0
; area DATA USER_VEC   0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


;INPUT/ OUTPUT PORTS
PORTA            0x0000   Data Port A
PORTA.PA7         7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
Reserv01         0x0001   RESERVED
Reserv02         0x0002   RESERVED
Reserv03         0x0003   RESERVED
Reserv04         0x0004   RESERVED
Reserv05         0x0005   RESERVED
Reserv06         0x0006   RESERVED
Reserv07         0x0007   RESERVED
PORTD            0x0008   Data Port D
PORTD.PD5         5   Port D Data Bit 5
PORTD.PD4         4   Port D Data Bit 4
PORTD.PD3         3   Port D Data Bit 3
PORTD.PD2         2   Port D Data Bit 2
PORTD.PD1         1   Port D Data Bit 1
PORTD.PD0         0   Port D Data Bit 0
DDRD             0x0009   Data Direction Port D
DDRD.DDD5         5   Data Direction for Port D Bit 5
DDRD.DDD4         4   Data Direction for Port D Bit 4
DDRD.DDD3         3   Data Direction for Port D Bit 3
DDRD.DDD2         2   Data Direction for Port D Bit 2
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
Reserv0A         0x000A   RESERVED
CFORC            0x000B   Timer Compare Force
CFORC.FOC1        7   Force Output Compare Bits 1
CFORC.FOC2        6   Force Output Compare Bits 2
CFORC.FOC3        5   Force Output Compare Bits 3
CFORC.FOC4        4   Force Output Compare Bits 4
CFORC.FOC5        3   Force Output Compare Bits 5
OC1M             0x000C   Output Compare 1 Mask
OC1M.OC1M7        7   Output Compare 1 Mask Bits 7
OC1M.OC1M6        6   Output Compare 1 Mask Bits 6
OC1M.OC1M5        5   Output Compare 1 Mask Bits 5
OC1M.OC1M4        4   Output Compare 1 Mask Bits 4
OC1M.OC1M3        3   Output Compare 1 Mask Bits 3
OC1D             0x000D   Output Compare 1 Data
OC1D.OC1D7        7   Output Compare 1 Data Bits 7
OC1D.OC1D6        6   Output Compare 1 Data Bits 6
OC1D.OC1D5        5   Output Compare 1 Data Bits 5
OC1D.OC1D4        4   Output Compare 1 Data Bits 4
OC1D.OC1D3        3   Output Compare 1 Data Bits 3
TCNTH            0x000E   Timer Count High
TCNTL            0x000F   Timer Count Low
TIC1H            0x0010   Timer Input Capture 1 HigH
TIC1L            0x0011   Timer Input Capture 1 Low
TIC2H            0x0012   Timer Input Capture 2 HigH
TIC2L            0x0013   Timer Input Capture 2 Low
TIC3H            0x0014   Timer Input Capture 3 HigH
TIC3L            0x0015   Timer Input Capture 3 Low
TOC1H            0x0016   Timer Output Compare 1 High
TOC1L            0x0017   Timer Output Compare 1 Low
TOC2H            0x0018   Timer Output Compare 2 High
TOC2L            0x0019   Timer Output Compare 2 Low
TOC3H            0x001A   Timer Output Compare 3 High
TOC3L            0x001B   Timer Output Compare 3 Low
TOC4H            0x001C   Timer Output Compare 4 High
TOC4L            0x001D   Timer Output Compare 4 Low
TI4O5H           0x001E   Timer Input Capture 4/Output Compare 5 High
TI4O5L           0x001F   Timer Input Capture 4/Output Compare 5 Low
TCTL1            0x0020   Timer Control 1
TCTL1.OM2         7   Output Mode 2
TCTL1.OL2         6   Output Level 2
TCTL1.OM3         5   Output Mode 3
TCTL1.OL3         4   Output Level 3
TCTL1.OM4         3   Output Mode 4
TCTL1.OL4         2   Output Level 4
TCTL1.OM5         1   Output Mode 5
TCTL1.OL5         0   Output Level 5
TCTL2            0x0021   Timer Control 2
TCTL2.EDG4B       7
TCTL2.EDG4A       6
TCTL2.EDG1B       5
TCTL2.EDG1A       4
TCTL2.EDG2B       3
TCTL2.EDG2A       2
TCTL2.EDG3B       1
TCTL2.EDG3A       0
TMSK1            0x0022   Timer Interrupt Mask 1
TMSK1.OC1I        7   Output Compare Interrupt Enable Bits 1
TMSK1.OC2I        6   Output Compare Interrupt Enable Bits 2
TMSK1.OC3I        5   Output Compare Interrupt Enable Bits 3
TMSK1.OC4I        4   Output Compare Interrupt Enable Bits 4
TMSK1.I4O5I       3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I        2   Input Capture Interrupt Enable Bits 1
TMSK1.IC2I        1   Input Capture Interrupt Enable Bits 2
TMSK1.IC3I        0   Input Capture Interrupt Enable Bits 3
TFLG1            0x0023   Timer Interrupt Flag 1
TFLG1.OC1F        7   Output Compare 1 Flags
TFLG1.OC2F        6   Output Compare 2 Flags
TFLG1.OC3F        5   Output Compare 3 Flags
TFLG1.OC4F        4   Output Compare 4 Flags
TFLG1.I4O5F       3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F        2   Input Capture 1 Flag
TFLG1.IC2F        1   Input Capture 2 Flag
TFLG1.IC3F        0   Input Capture 3 Flag
TMSK2            0x0024   Timer Interrupt Mask 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII        6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII        4   Pulse Accumulator Interrupt Enable Bit
TMSK2.PR1         1   Timer Prescaler Select Bits 1
TMSK2.PR0         0   Timer Prescaler Select Bits 0
TFLG2            0x0025   Timer Interrupt Flag 2
TFLG2.TOF         7   Timer Overflow Interrupt Flag
TFLG2.RTIF        6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Flag
PACTL            0x0026   Pulse Accumulator Control
PACTL.DDRA7       7   Data Direction for Port A Bit 7
PACTL.PAEN        6   Pulse Accumulator System Enable Bit
PACTL.PAMOD       5   Pulse Accumulator Mode Bit
PACTL.PEDGE       4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3       3   Data Direction for Port A Bit 3
PACTL.I4O5        2   Input Capture 4/Output Compare Bit
PACTL.RTR1        1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0        0   RTI Interrupt Rate Select Bits 0
PACNT            0x0027   Pulse Accumulator Counter
SPCR             0x0028   Serial Peripheral Control Register
SPCR.SPIE         7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE          6   Serial Peripheral System Enable Bit
SPCR.DWOM         5   Port D Wired-OR Mode Option Bit for Port D Pins PD[5:2]
SPCR.MSTR         4   Master Mode Select Bit
SPCR.CPOL         3   Clock Polarity Bit 
SPCR.CPHA         2   Clock Phase Bit
SPCR.SPR1         1   SPI Clock Rate Select Bits 1
SPCR.SPR0         0   SPI Clock Rate Select Bits 0
SPSR             0x0029   Serial Peripheral Status Register
SPSR.SPIF         7   SPI Transfer Complete Flag
SPSR.WCOL         6   Write Collision Error Flag
SPSR.MODF         4   Mode Fault Bit (mode fault terminates SPI operation)
SPDR             0x002A   SPI Data
BAUD             0x002B   Baud Rate
BAUD.TCLR         7   Clear Baud Rate Counter Bit
BAUD.SCP1         5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0         4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB         3   SCI Baud Rate Clock Check Bit
BAUD.SCR2         2   SCI Baud Rate Select Bits 2
BAUD.SCR1         1   SCI Baud Rate Select Bits 1
BAUD.SCR0         0   SCI Baud Rate Select Bits 0
SCCR1            0x002C   SCI Control 1
SCCR1.R8          7   Receive Data Bit 8
SCCR1.T8          6   Transmit Data Bit 8
SCCR1.M           4   Mode Bit (select character format)
SCCR1.WAKE        3   Wakeup by Address Mark/Idle Bit
SCCR2            0x002D   SCI Control 2
SCCR2.TIE         7   Transmit Interrupt Enable Bit
SCCR2.TCIE        6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE         5   Receiver Interrupt Enable Bit
SCCR2.ILIE        4   Idle-Line Interrupt Enable Bit
SCCR2.TE          3   Transmitter Enable Bit
SCCR2.RE          2   Receiver Enable Bit
SCCR2.RWU         1   Receiver Wakeup Control Bit
SCCR2.SBK         0   Send Break Bit
SCSR             0x002E   SCI Status Register
SCSR.TDRE         7   Transmit Data Register Empty Flag
SCSR.TC           6   Transmit Complete Flag
SCSR.RDRF         5   Receive Data Register Full Flag
SCSR.IDLE         4   Idle Line Detected Flag
SCSR.OR           3   Overrun Error Flag
SCSR.NF           2   Noise Error Flag
SCSR.FE           1   Framing Error Flag
SCDR             0x002F   SCI Data Register
SCDR.R7T7         7
SCDR.R6T6         6
SCDR.R5T5         5
SCDR.R4T4         4
SCDR.R3T3         3
SCDR.R2T2         2
SCDR.R1T1         1
SCDR.R0T0         0
Reserv30         0x0030   RESERVED
Reserv31         0x0031   RESERVED
Reserv32         0x0032   RESERVED
Reserv33         0x0033   RESERVED
Reserv34         0x0034   RESERVED
Reserv35         0x0035   RESERVED
Reserv36         0x0036   RESERVED
Reserv37         0x0037   RESERVED
Reserv38         0x0038   RESERVED
OPTION           0x0039   System Configuration OptionS
OPTION.IRQE       5   IRQ Select Edge Sensitive Only Bit
OPTION.DLY        4   Enable Oscillator Startup Delay on Exit from Stop Mode Bit
OPTION.CME        3   Clock Monitor Enable Bit
OPTION.CR1        1   COP Timer Rate Select Bit 1
OPTION.CR0        0   COP Timer Rate Select Bit 0
COPRST           0x003A   Arm/Reset COP Timer Circuitry
Reserv3B         0x003B   RESERVED
HPRIO            0x003C   Highest Priority I-Bit Interrupt and Miscellaneous
HPRIO.RBOOT       7   Read Bootstrap ROM Bit
HPRIO.SMOD        6   Special Mode Select Bit
HPRIO.MDA         5   Mode Select A Bit
HPRIO.IRVNE       4   Internal Read Visibility/Not E Bit
HPRIO.PSEL3       3   Priority Select Bits 3
HPRIO.PSEL2       2   Priority Select Bits 2
HPRIO.PSEL1       1   Priority Select Bits 1
HPRIO.PSEL0       0   Priority Select Bits 0
INIT             0x003D   RAM and Register Mapping
INIT.RAM3         7   Internal RAM Map Position Bits 3
INIT.RAM2         6   Internal RAM Map Position Bits 2
INIT.RAM1         5   Internal RAM Map Position Bits 1
INIT.RAM0         4   Internal RAM Map Position Bits 0
INIT.REG3         3   128-Byte Register Block Map Position Bits 3
INIT.REG2         2   128-Byte Register Block Map Position Bits 2
INIT.REG1         1   128-Byte Register Block Map Position Bits 1
INIT.REG0         0   128-Byte Register Block Map Position Bits 0
RESERV3E         0x003E   RESERVED
CONFIG           0x003F   System Configuration Register
CONFIG.NOCOP      2   COP System Disable Bit
RESERVFFC0       0xFFC0   RESERVED
RESERVFFC1       0xFFC1   RESERVED
RESERVFFC2       0xFFC2   RESERVED
RESERVFFC3       0xFFC3   RESERVED
RESERVFFC4       0xFFC4   RESERVED
RESERVFFC5       0xFFC5   RESERVED
RESERVFFC6       0xFFC6   RESERVED
RESERVFFC7       0xFFC7   RESERVED
RESERVFFC8       0xFFC8   RESERVED
RESERVFFC9       0xFFC9   RESERVED
RESERVFFCA       0xFFCA   RESERVED
RESERVFFCB       0xFFCB   RESERVED
RESERVFFCC       0xFFCC   RESERVED
RESERVFFCD       0xFFCD   RESERVED
RESERVFFCE       0xFFCE   RESERVED
RESERVFFCF       0xFFCF   RESERVED
RESERVFFD0       0xFFD0   RESERVED
RESERVFFD1       0xFFD1   RESERVED
RESERVFFD2       0xFFD2   RESERVED
RESERVFFD3       0xFFD3   RESERVED
RESERVFFD4       0xFFD4   RESERVED
RESERVFFD5       0xFFD5   RESERVED

                                
.68HC11F1
; MC68HC11FTS/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11F1&nodeId=01M98635
; MC68HC11F1.pdf

; RAM=1K 
; ROM=0   
; EPROM=0   
; EEPROM=512


; MEMORY MAP
area DATA RAM        0x0000:0x0400
area BSS  RESERVED   0x0400:0x1000
area DATA FSR        0x1000:0x1060
area BSS  RESERVED   0x1060:0xFE00
area DATA EEPROM     0xFE00:0xFFC0
area DATA USER_VEC   0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA           0x1000  Port A data
PORTA.PA7        7   Port A Data Bit 7
PORTA.PA6        6   Port A Data Bit 6
PORTA.PA5        5   Port A Data Bit 5
PORTA.PA4        4   Port A Data Bit 4
PORTA.PA3        3   Port A Data Bit 3
PORTA.PA2        2   Port A Data Bit 2
PORTA.PA1        1   Port A Data Bit 1
PORTA.PA0        0   Port A Data Bit 0
DDRA            0x1001  Data Direction Port A
DDRA.DDA7        7   Data Direction for Port A Bit 7
DDRA.DDA6        6   Data Direction for Port A Bit 6
DDRA.DDA5        5   Data Direction for Port A Bit 5
DDRA.DDA4        4   Data Direction for Port A Bit 4
DDRA.DDA3        3   Data Direction for Port A Bit 3
DDRA.DDA2        2   Data Direction for Port A Bit 2
DDRA.DDA1        1   Data Direction for Port A Bit 1
DDRA.DDA0        0   Data Direction for Port A Bit 0
PORTG           0x1002  Port G Data
PORTG.PG7        7   Port G Data Bit 7
PORTG.PG6        6   Port G Data Bit 6
PORTG.PG5        5   Port G Data Bit 5
PORTG.PG4        4   Port G Data Bit 4
PORTG.PG3        3   Port G Data Bit 3
PORTG.PG2        2   Port G Data Bit 2
PORTG.PG1        1   Port G Data Bit 1
PORTG.PG0        0   Port G Data Bit 0
DDRG            0x1003  Data Direction PortG
DDRG.DDG7        7   Data Direction for Port G Bit 7
DDRG.DDG6        6   Data Direction for Port G Bit 6
DDRG.DDG5        5   Data Direction for Port G Bit 5
DDRG.DDG4        4   Data Direction for Port G Bit 4
DDRG.DDG3        3   Data Direction for Port G Bit 3
DDRG.DDG2        2   Data Direction for Port G Bit 2
DDRG.DDG1        1   Data Direction for Port G Bit 1
DDRG.DDG0        0   Data Direction for Port G Bit 0
PORTB           0x1004  Port B Data
PORTB.PB7        7   Port B Data Bit 7
PORTB.PB6        6   Port B Data Bit 6
PORTB.PB5        5   Port B Data Bit 5
PORTB.PB4        4   Port B Data Bit 4
PORTB.PB3        3   Port B Data Bit 3
PORTB.PB2        2   Port B Data Bit 2
PORTB.PB1        1   Port B Data Bit 1
PORTB.PB0        0   Port B Data Bit 0
PORTF           0x1005  Data Port F
PORTF.PF7        7   Port F Data Bit 7
PORTF.PF6        6   Port F Data Bit 6
PORTF.PF5        5   Port F Data Bit 5
PORTF.PF4        4   Port F Data Bit 4
PORTF.PF3        3   Port F Data Bit 3
PORTF.PF2        2   Port F Data Bit 2
PORTF.PF1        1   Port F Data Bit 1
PORTF.PF0        0   Port F Data Bit 0
PORTC           0x1006  Data Port C
PORTC.PC7        7   Port C Data Bit 7
PORTC.PC6        6   Port C Data Bit 6
PORTC.PC5        5   Port C Data Bit 5
PORTC.PC4        4   Port C Data Bit 4
PORTC.PC3        3   Port C Data Bit 3
PORTC.PC2        2   Port C Data Bit 2
PORTC.PC1        1   Port C Data Bit 1
PORTC.PC0        0   Port C Data Bit 0
DDRC            0x1007  Data Direction for Port C
DDRC.DDC7        7   Data Direction for Port C Bit 7
DDRC.DDC6        6   Data Direction for Port C Bit 6
DDRC.DDC5        5   Data Direction for Port C Bit 5
DDRC.DDC4        4   Data Direction for Port C Bit 4
DDRC.DDC3        3   Data Direction for Port C Bit 3
DDRC.DDC2        2   Data Direction for Port C Bit 2
DDRC.DDC1        1   Data Direction for Port C Bit 1
DDRC.DDC0        0   Data Direction for Port C Bit 0
PORTD           0x1008  Port D Data
PORTD.PD5        5   Port D Data Bit 5
PORTD.PD4        4   Port D Data Bit 4
PORTD.PD3        3   Port D Data Bit 3
PORTD.PD2        2   Port D Data Bit 2
PORTD.PD1        1   Port D Data Bit 1
PORTD.PD0        0   Port D Data Bit 0
DDRD            0x1009  Data Direction for Port D
DDRD.DDD5        5   Data Direction for Port D Bit 5
DDRD.DDD4        4   Data Direction for Port D Bit 4
DDRD.DDD3        3   Data Direction for Port D Bit 3
DDRD.DDD2        2   Data Direction for Port D Bit 2
DDRD.DDD1        1   Data Direction for Port D Bit 1
DDRD.DDD0        0   Data Direction for Port D Bit 0
PORTE           0x100A  Port E Data
PORTE.PE7        7   Port E Data Bit 7
PORTE.PE6        6   Port E Data Bit 6
PORTE.PE5        5   Port E Data Bit 5
PORTE.PE4        4   Port E Data Bit 4
PORTE.PE3        3   Port E Data Bit 3
PORTE.PE2        2   Port E Data Bit 2
PORTE.PE1        1   Port E Data Bit 1
PORTE.PE0        0   Port E Data Bit 0
CFORC           0x100B  Compare Force Register
CFORC.FOC1       7   Force Output Comparison 1
CFORC.FOC2       6   Force Output Comparison 2
CFORC.FOC3       5   Force Output Comparison 3
CFORC.FOC4       4   Force Output Comparison 4
CFORC.FOC5       3   Force Output Comparison 5
OC1M            0x100C  OC1 Action Mask Register
OC1M.OC1M7       7   Output Compare Masks 7
OC1M.OC1M6       6   Output Compare Masks 6
OC1M.OC1M5       5   Output Compare Masks 5
OC1M.OC1M4       4   Output Compare Masks 4
OC1M.OC1M3       3   Output Compare Masks 3
OC1D            0x100D   OC1 Action Data Register
OC1D.OC1D7       7   Output Compare Data 7
OC1D.OC1D6       6   Output Compare Data 6
OC1D.OC1D5       5   Output Compare Data 5
OC1D.OC1D4       4   Output Compare Data 4
OC1D.OC1D3       3   Output Compare Data 3
TCNTH           0x100E  Timer Counter Register (High)
TCNTL           0x100F  Timer Counter Register (Low)
TIC1H           0x1010  Input Capture 1 Register (High)
TIC1L           0x1011  Input Capture 1 Register (Low)
TIC2H           0x1012  Input Capture 2 Register (High)
TIC2L           0x1013  Input Capture 2 Register (Low)
TIC3H           0x1014  Input Capture 3 Register (High)
TIC3L           0x1015  Input Capture 3 Register (Low)
TOC1H           0x1016  Output Compare 1 Register (High)
TOC1L           0x1017  Output Compare 1 Register (Low)
TOC2H           0x1018  Output Compare 2 Register (High)
TOC2L           0x1019  Output Compare 2 Register (Low)
TOC3H           0x101A  Output Compare 3 Register (High)
TOC3L           0x101B  Output Compare 3 Register (Low)
TOC4H           0x101C  Output Compare 4 Register (High)
TOC4L           0x101D  Output Compare 4 Register (Low)
TCO5H           0x101E  Output Compare 5 Register (High)
TCO5L           0x101F  Output Compare 5 Register (Low)
TCTL1           0x1020  Timer Control Register 1
TCTL1.OM2        7   Output Mode 2
TCTL1.OL2        6   Output Level 2
TCTL1.OM3        5   Output Mode 3
TCTL1.OL3        4   Output Level 3
TCTL1.OM4        3   Output Mode 4
TCTL1.OL4        2   Output Level 4
TCTL1.OM5        1   Output Mode 5
TCTL1.OL5        0   Output Level 5
TCTL2           0x1021  Timer Control Register 2
TCTL2.EDG4B      7   EDG4B Input Capture Edge Control
TCTL2.EDG4A      6   EDG4A Input Capture Edge Control
TCTL2.EDG1B      5   EDG1B Input Capture Edge Control
TCTL2.EDG1A      4   EDG1A Input Capture Edge Control
TCTL2.EDG2B      3   EDG2B Input Capture Edge Control
TCTL2.EDG2A      2   EDG2A Input Capture Edge Control
TCTL2.EDG3B      1   EDG3B Input Capture Edge Control
TCTL2.EDG3A      0   EDG3A Input Capture Edge Control
TMSK1           0x1022  Timer Interrupt Mask Register 1
TMSK1.OC1I       7   Output Compare 1 Interrupt Enable
TMSK1.OC2I       6   Output Compare 2 Interrupt Enable
TMSK1.OC3I       5   Output Compare 3 Interrupt Enable
TMSK1.OC4I       4   Output Compare 4 Interrupt Enable
TMSK1.I4_O5I     3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I       2   Input Capture 1 Interrupt Enable
TMSK1.IC2I       1   Input Capture 2 Interrupt Enable
TMSK1.IC3I       0   Input Capture 3 Interrupt Enable
TFLG1           0x1023  Timer Interrupt Flag Register 1
TFLG1.OC1F       7   Output Compare 1 Flag
TFLG1.OC2F       6   Output Compare 2 Flag
TFLG1.OC3F       5   Output Compare 3 Flag
TFLG1.OC4F       4   Output Compare 4 Flag
TFLG1.I4_O5F     3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F       2   Input Capture 1 Flag
TFLG1.IC2F       1   Input Capture 2 Flag
TFLG1.IC3F       0   Input Capture 3 Flag
TMSK2           0x1024  Timer Interrupt Mask Register 2
TMSK2.TOI        7   Timer Overflow Interrupt Enable
TMSK2.RTII       6   Real-Time Interrupt Enable
TMSK2.PAOVI      5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII       4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1        1   Timer Prescaler Select 1
TMSK2.PR0        0   Timer Prescaler Select 0
TFLG2           0x1025  Timer Interrupt Flag Register 2
TFLG2.TOF        7   Timer Overflow Interrupt Flag
TFLG2.RTIF       6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF      5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF       4   Pulse Accumulator Input Edge Interrupt Flag
PACTL           0x1026  Pulse Accumulator Control Register
PACTL.PAEN       6   Pulse Accumulator System Enable
PACTL.PAMOD      5   Pulse Accumulator Mode
PACTL.PEDGE      4   Pulse Accumulator Edge Control
PACTL.I4_O5      2   Input Capture 4/Output Compare
PACTL.RTR1       1   RTI Interrupt Rate Select 1
PACTL.RTR0       0   RTI Interrupt Rate Select 0
PACNT           0x1027  Pulse Accumulator Count Register
SPCR            0x1028  Serial Peripheral Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable
SPCR.DWOM        5   Port D Wired-OR Mode
SPCR.MSTR        4   Master Mode Select
SPCR.CPOL        3   Clock Polarity
SPCR.CPHA        2   Clock Phase
SPCR.SPR1        1   SPI Clock Rate Selects 1
SPCR.SPR0        0   SPI Clock Rate Selects 0
SPSR            0x1029  Serial Peripheral Status Register
SPSR.SPIF        7   SPI Interrupt Complete Flag
SPSR.WCOL        6   Write Collision
SPSR.MODF        4   Mode Fault
SPDR            0x102A  SPI Data Register
BAUD            0x102B  Baud Rate
BAUD.TCLR        7   Clear Baud Rate Counters (Test)
BAUD.SCP1        5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0        4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB        3   SCI Baud Rate Clock Check (Test)
BAUD.SCR2        2   SCI Baud Rate Selects 2
BAUD.SCR1        1   SCI Baud Rate Selects 1
BAUD.SCR0        0   SCI Baud Rate Selects 0
SCCR1           0x102C  SCI Control Register
SCCR1.R8         7   Receive Data Bit 8
SCCR1.T8         6   Transmit Data Bit 8
SCCR1.M          4   Mode (Select Character Format)
SCCR1.WAKE       3   Wakeup by Address Mark/Idle
SCCR2           0x102D  SCI Control Register
SCCR2.TIE        7   Transmit Interrupt Enable
SCCR2.TCIE       6   Transmit Complete Interrupt Enable
SCCR2.RIE        5   Receiver Interrupt Enable
SCCR2.ILIE       4   Idle-Line Interrupt Enable
SCCR2.TE         3   Transmitter Enable
SCCR2.RE         2   Receiver Enable
SCCR2.RWU        1   Receiver Wakeup Control
SCCR2.SBK        0   Send Break
SCSR            0x102E  SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty Flag
SCSR.TC          6   Transmit Complete Flag
SCSR.RDRF        5   Receive Data Register Full Flag
SCSR.IDLE        4   Idle Line Detected Flag
SCSR.OR          3   Overrun Error Flag
SCSR.NF          2   Noise Error Flag
SCSR.FE          1   Framing Error
SCDR            0x102F  SCI Data (Read RDR, Write TDR)
ADCTL           0x1030  A_D Control Register
ADCTL.CCF        7   Conversions Complete Flag
ADCTL.SCAN       5   Continuous Scan Control
ADCTL.MULT       4   Multiple Channel/Single Channel Control
ADCTL.CD         3   Channel Selects D
ADCTL.CC         2   Channel Selects C
ADCTL.CB         1   Channel Selects B
ADCTL.CA         0   Channel Selects A
ADR1            0x1031  A_D Result Register 1
ADR2            0x1032  A_D Result Register 2
ADR3            0x1033  A_D Result Register 3
ADR4            0x1034  A_D Result Register 4
BPROT           0x1035  Block Protect Register
BPROT.PTCON      4   Protect for CONFIG
BPROT.BPRT3      3   Block Protect Bits for EEPROM 3
BPROT.BPRT2      2   Block Protect Bits for EEPROM 2
BPROT.BPRT1      1   Block Protect Bits for EEPROM 1
BPROT.BPRT0      0   Block Protect Bits for EEPROM 0
RESERV36        0x1036  RESERVED
RESERV37        0x1037  RESERVED
OPT2            0x1038  System Configuration Options 2
OPT2.GWOM        7   Port G Wired-OR Mode
OPT2.CWOM        6   Port C Wired-OR Mode
OPT2.CLK4X       5   4XOUT Clock Enable
OPTION          0x1039  System Configuration Options
OPTION.ADPU      7   A/D Power-Up
OPTION.CSEL      6   Clock Select
OPTION.IRQE      5   Configure IRQ for Falling Edge-Sensitive Operation
OPTION.DLY       4   Enable Oscillator Start-up Delay
OPTION.CME       3   Clock Monitor Enable
OPTION.CR1       1   COP Timer Rate Select Bits 1
OPTION.CR0       0   COP Timer Rate Select Bits 0
COPRST          0x103A  Arm_Reset COP Timer Circuitry
PPROG           0x103B  EEPROM Program Control Register
PPROG.ODD        7   Program Odd Rows in Half of EEPROM (TEST)
PPROG.EVEN       6   Program Even Rows in Half of EEPROM (TEST)
PPROG.BYTE       4   Byte/Other EEPROM Erase Mode
PPROG.ROW        3   Row/All EEPROM Erase Mode (only valid when BYTE = 0)
PPROG.ERASE      2   Erase/Normal Control for EEPROM
PPROG.EELAT      1   EEPROM Latch Control
PPROG.EEPGM      0   EEPROM Program Command
HPRIO           0x103C  Highest Priority I-Bit Int and Misc
HPRIO.RBOOT      7   Read Bootstrap ROM
HPRIO.SMOD       6   Special Mode Select 
HPRIO.MDA        5   Mode Select A
HPRIO.IRV        4   Internal Read Visibility
HPRIO.PSEL3      3   Priority Select Bits 3
HPRIO.PSEL2      2   Priority Select Bits 2
HPRIO.PSEL1      1   Priority Select Bits 1
HPRIO.PSEL0      0   Priority Select Bits 0
INIT            0x103D  RAM and I_O Mapping Register
INIT.RAM3        7   RAM Map Position 3
INIT.RAM2        6   RAM Map Position 2
INIT.RAM1        5   RAM Map Position 1
INIT.RAM0        4   RAM Map Position 0
INIT.REG3        3   128-Byte Register Block Position 3
INIT.REG2        2   128-Byte Register Block Position 2
INIT.REG1        1   128-Byte Register Block Position 1
INIT.REG0        0   128-Byte Register Block Position 0
TEST1           0x103E  Factory Test
TEST.TILOP       7   Test Illegal Opcode                         
TEST.OCCR        5   Output Condition Code Register to Timer Port
TEST.CBYP        4   Timer Divider Chain Bypass                  
TEST.DISR        3   Disable Resets from COP and Clock Monitor   
TEST.FCM         2   Force Clock Monitor Failure                 
TEST.FCOP        1   Force COP Watchdog Failure                  
CONFIG          0x103F  System Configuration Register
CONFIG.EE3       7   EEPROM Mapping Control 3
CONFIG.EE2       6   EEPROM Mapping Control 2
CONFIG.EE1       5   EEPROM Mapping Control 1
CONFIG.EE0       4   EEPROM Mapping Control 0
CONFIG.NOCOP     2   COP System Disable
CONFIG.EEON      0   EEPROM Enable
RESERV40        0x1040  RESERVED
RESERV41        0x1041  RESERVED
RESERV42        0x1042  RESERVED
RESERV43        0x1043  RESERVED
RESERV44        0x1044  RESERVED
RESERV45        0x1045  RESERVED
RESERV46        0x1046  RESERVED
RESERV47        0x1047  RESERVED
RESERV48        0x1048  RESERVED
RESERV49        0x1049  RESERVED
RESERV4A        0x104A  RESERVED
RESERV4B        0x104B  RESERVED
RESERV4C        0x104C  RESERVED
RESERV4D        0x104D  RESERVED
RESERV4E        0x104E  RESERVED
RESERV4F        0x104F  RESERVED
RESERV50        0x1050  RESERVED
RESERV51        0x1051  RESERVED
RESERV52        0x1052  RESERVED
RESERV53        0x1053  RESERVED
RESERV54        0x1054  RESERVED
RESERV55        0x1055  RESERVED
RESERV56        0x1056  RESERVED
RESERV57        0x1057  RESERVED
RESERV58        0x1058  RESERVED
RESERV59        0x1059  RESERVED
RESERV5A        0x105A  RESERVED
RESERV5B        0x105B  RESERVED
CSSTRH          0x105C  Chip Select Clock Stretch Select
CSSTRH.IO1SA     7   I/O Chip Select 1 Clock Stretch Select A
CSSTRH.IO1SB     6   I/O Chip Select 1 Clock Stretch Select B
CSSTRH.IO2SA     5   I/O Chip Select 2 Clock Stretch Select A
CSSTRH.IO2SB     4   I/O Chip Select 2 Clock Stretch Select B
CSSTRH.GSTHA     3   General-Purpose Chip Select Clock Stretch Select A
CSSTRH.GSTHB     2   General-Purpose Chip Select Clock Stretch Select B
CSSTRH.PSTHA     1   Program Chip Select Clock Stretch Select A
CSSTRH.PSTHB     0   Program Chip Select Clock Stretch Select B
CSCTL           0x105D  Chip Select Control
CSCTL.IO1EN      7   I/O Chip Select 1 Enable
CSCTL.IO1PL      6   I/O Chip Select 1 Polarity Select
CSCTL.IO2EN      5   I/O Chip Select 2 Enable
CSCTL.IO2PL      4   I/O Chip Select 2 Polarity Select
CSCTL.GCSPR      3   General-Purpose Chip Select Priority
CSCTL.PCSEN      2   Program Chip Select Enable
CSCTL.PSIZA      1   Program Chip Select Size A
CSCTL.PSIZB      0   Program Chip Select Size B
CSGADR          0x105E  General-Purpose Chip Select Address Register
CSGADR.GA15      7   General-Purpose Chip Select Base Address 15
CSGADR.GA14      6   General-Purpose Chip Select Base Address 14
CSGADR.GA13      5   General-Purpose Chip Select Base Address 13
CSGADR.GA12      4   General-Purpose Chip Select Base Address 12
CSGADR.GA11      3   General-Purpose Chip Select Base Address 11
CSGADR.GA10      2   General-Purpose Chip Select Base Address 10
CSGSIZ          0x105F  General-Purpose Chip Select Size Control
CSGSIZ.IO1AV     7   I/O Chip Select 1 Address Valid
CSGSIZ.IO2AV     6   I/O Chip Select 2 Address Valid
CSGSIZ.GNPOL     4   General-Purpose Chip Select Polarity Select
CSGSIZ.GAVLD     3   General-Purpose Chip Select Address Valid Select
CSGSIZ.GSIZA     2   General-Purpose Chip Select Size A
CSGSIZ.GSIZB     1   General-Purpose Chip Select Size B
CSGSIZ.GSIZC     0   General-Purpose Chip Select Size C
RESERVFFC0      0xFFC0  RESERVED
RESERVFFC1      0xFFC1  RESERVED
RESERVFFC2      0xFFC2  RESERVED
RESERVFFC3      0xFFC3  RESERVED
RESERVFFC4      0xFFC4  RESERVED
RESERVFFC5      0xFFC5  RESERVED
RESERVFFC6      0xFFC6  RESERVED
RESERVFFC7      0xFFC7  RESERVED
RESERVFFC8      0xFFC8  RESERVED
RESERVFFC9      0xFFC9  RESERVED
RESERVFFCA      0xFFCA  RESERVED
RESERVFFCB      0xFFCB  RESERVED
RESERVFFCC      0xFFCC  RESERVED
RESERVFFCD      0xFFCD  RESERVED
RESERVFFCE      0xFFCE  RESERVED
RESERVFFCF      0xFFCF  RESERVED
RESERVFFD0      0xFFD0  RESERVED
RESERVFFD1      0xFFD1  RESERVED
RESERVFFD2      0xFFD2  RESERVED
RESERVFFD3      0xFFD3  RESERVED
RESERVFFD4      0xFFD4  RESERVED
RESERVFFD5      0xFFD5  RESERVED


.68HC11FC0
; MC68HC11FTS/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11FC0&nodeId=01M98635
; MC68HC11FTS.pdf

; RAM=1K
; ROM=0
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA RAM         0x0000:0x0400
area BSS  RESERVED    0x0400:0x1000
area DATA FSR         0x1000:0x1060
area BSS  RESERVED    0x1060:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA           0x1000   Port A data
PORTA.PA7        7   Port A Data Bit 7
PORTA.PA6        6   Port A Data Bit 6
PORTA.PA5        5   Port A Data Bit 5
PORTA.PA4        4   Port A Data Bit 4
PORTA.PA3        3   Port A Data Bit 3
PORTA.PA2        2   Port A Data Bit 2
PORTA.PA1        1   Port A Data Bit 1
PORTA.PA0        0   Port A Data Bit 0
DDRA            0x1001   Data Direction Port A
DDRA.DDA7        7   Data Direction for Port A Bit 7
DDRA.DDA6        6   Data Direction for Port A Bit 6
DDRA.DDA5        5   Data Direction for Port A Bit 5
DDRA.DDA4        4   Data Direction for Port A Bit 4
DDRA.DDA3        3   Data Direction for Port A Bit 3
DDRA.DDA2        2   Data Direction for Port A Bit 2
DDRA.DDA1        1   Data Direction for Port A Bit 1
DDRA.DDA0        0   Data Direction for Port A Bit 0
PORTG           0x1002   Port G Data
PORTG.PG7        7   Port G Data Bit 7
PORTG.PG6        6   Port G Data Bit 6
PORTG.PG5        5   Port G Data Bit 5
PORTG.PG4        4   Port G Data Bit 4
PORTG.PG3        3   Port G Data Bit 3
PORTG.PG2        2   Port G Data Bit 2
PORTG.PG1        1   Port G Data Bit 1
PORTG.PG0        0   Port G Data Bit 0
DDRG            0x1003   Data Direction PortG
DDRG.DDG7        7   Data Direction for Port G Bit 7
DDRG.DDG6        6   Data Direction for Port G Bit 6
DDRG.DDG5        5   Data Direction for Port G Bit 5
DDRG.DDG4        4   Data Direction for Port G Bit 4
DDRG.DDG3        3   Data Direction for Port G Bit 3
DDRG.DDG2        2   Data Direction for Port G Bit 2
DDRG.DDG1        1   Data Direction for Port G Bit 1
DDRG.DDG0        0   Data Direction for Port G Bit 0
PORTB           0x1004   Port B Data
PORTB.PB7        7   Port B Data Bit 7
PORTB.PB6        6   Port B Data Bit 6
PORTB.PB5        5   Port B Data Bit 5
PORTB.PB4        4   Port B Data Bit 4
PORTB.PB3        3   Port B Data Bit 3
PORTB.PB2        2   Port B Data Bit 2
PORTB.PB1        1   Port B Data Bit 1
PORTB.PB0        0   Port B Data Bit 0
PORTF           0x1005   Data Port F
PORTF.PF7        7   Port F Data Bit 7
PORTF.PF6        6   Port F Data Bit 6
PORTF.PF5        5   Port F Data Bit 5
PORTF.PF4        4   Port F Data Bit 4
PORTF.PF3        3   Port F Data Bit 3
PORTF.PF2        2   Port F Data Bit 2
PORTF.PF1        1   Port F Data Bit 1
PORTF.PF0        0   Port F Data Bit 0
PORTC           0x1006   Data Port C
PORTC.PC7        7   Port C Data Bit 7
PORTC.PC6        6   Port C Data Bit 6
PORTC.PC5        5   Port C Data Bit 5
PORTC.PC4        4   Port C Data Bit 4
PORTC.PC3        3   Port C Data Bit 3
PORTC.PC2        2   Port C Data Bit 2
PORTC.PC1        1   Port C Data Bit 1
PORTC.PC0        0   Port C Data Bit 0
DDRC            0x1007   Data Direction for Port C
DDRC.DDC7        7   Data Direction for Port C Bit 7
DDRC.DDC6        6   Data Direction for Port C Bit 6
DDRC.DDC5        5   Data Direction for Port C Bit 5
DDRC.DDC4        4   Data Direction for Port C Bit 4
DDRC.DDC3        3   Data Direction for Port C Bit 3
DDRC.DDC2        2   Data Direction for Port C Bit 2
DDRC.DDC1        1   Data Direction for Port C Bit 1
DDRC.DDC0        0   Data Direction for Port C Bit 0
PORTD           0x1008   Port D Data
PORTD.PD5        5   Port D Data Bit 5
PORTD.PD4        4   Port D Data Bit 4
PORTD.PD3        3   Port D Data Bit 3
PORTD.PD2        2   Port D Data Bit 2
PORTD.PD1        1   Port D Data Bit 1
PORTD.PD0        0   Port D Data Bit 0
DDRD            0x1009   Data Direction for Port D
DDRD.DDD5        5   Data Direction for Port D Bit 5
DDRD.DDD4        4   Data Direction for Port D Bit 4
DDRD.DDD3        3   Data Direction for Port D Bit 3
DDRD.DDD2        2   Data Direction for Port D Bit 2
DDRD.DDD1        1   Data Direction for Port D Bit 1
DDRD.DDD0        0   Data Direction for Port D Bit 0
PORTE           0x100A   Port E Data
PORTE.PE7        7   Port E Data Bit 7
PORTE.PE6        6   Port E Data Bit 6
PORTE.PE5        5   Port E Data Bit 5
PORTE.PE4        4   Port E Data Bit 4
PORTE.PE3        3   Port E Data Bit 3
PORTE.PE2        2   Port E Data Bit 2
PORTE.PE1        1   Port E Data Bit 1
PORTE.PE0        0   Port E Data Bit 0
CFORC           0x100B   Compare Force Register
CFORC.FOC1       7   Force Output Comparison 1
CFORC.FOC2       6   Force Output Comparison 2
CFORC.FOC3       5   Force Output Comparison 3
CFORC.FOC4       4   Force Output Comparison 4
CFORC.FOC5       3   Force Output Comparison 5
OC1M            0x100C   OC1 Action Mask Register
OC1M.OC1M7       7   Output Compare Masks 7
OC1M.OC1M6       6   Output Compare Masks 6
OC1M.OC1M5       5   Output Compare Masks 5
OC1M.OC1M4       4   Output Compare Masks 4
OC1M.OC1M3       3   Output Compare Masks 3
OC1D            0x100D   OC1 Action Data Register
OC1D.OC1D7       7   Output Compare Data 7
OC1D.OC1D6       6   Output Compare Data 6
OC1D.OC1D5       5   Output Compare Data 5
OC1D.OC1D4       4   Output Compare Data 4
OC1D.OC1D3       3   Output Compare Data 3
TCNTH           0x100E   Timer Counter Register (High)   
TCNTL           0x100F   Timer Counter Register (Low)    
TIC1H           0x1010   Input Capture 1 Register (High) 
TIC1L           0x1011   Input Capture 1 Register (Low)  
TIC2H           0x1012   Input Capture 2 Register (High) 
TIC2L           0x1013   Input Capture 2 Register (Low)  
TIC3H           0x1014   Input Capture 3 Register (High) 
TIC3L           0x1015   Input Capture 3 Register (Low)  
TOC1H           0x1016   Output Compare 1 Register (High)
TOC1L           0x1017   Output Compare 1 Register (Low) 
TOC2H           0x1018   Output Compare 2 Register (High)
TOC2L           0x1019   Output Compare 2 Register (Low) 
TOC3H           0x101A   Output Compare 3 Register (High)
TOC3L           0x101B   Output Compare 3 Register (Low) 
TOC4H           0x101C   Output Compare 4 Register (High)
TOC4L           0x101D   Output Compare 4 Register (Low) 
TI4_O5H         0x101E   Output Compare 5 Register (High)
TI4_O5L         0x101F   Output Compare 5 Register (Low) 
TCTL1           0x1020   Timer Control Register 1        
TCTL1.OM2        7   Output Mode 2 
TCTL1.OL2        6   Output Level 2
TCTL1.OM3        5   Output Mode 3 
TCTL1.OL3        4   Output Level 3
TCTL1.OM4        3   Output Mode 4 
TCTL1.OL4        2   Output Level 4
TCTL1.OM5        1   Output Mode 5 
TCTL1.OL5        0   Output Level 5
TCTL2           0x1021   Timer Control Register 2
TCTL2.EDG4B      7   EDG4B Input Capture Edge Control
TCTL2.EDG4A      6   EDG4A Input Capture Edge Control
TCTL2.EDG1B      5   EDG1B Input Capture Edge Control
TCTL2.EDG1A      4   EDG1A Input Capture Edge Control
TCTL2.EDG2B      3   EDG2B Input Capture Edge Control
TCTL2.EDG2A      2   EDG2A Input Capture Edge Control
TCTL2.EDG3B      1   EDG3B Input Capture Edge Control
TCTL2.EDG3A      0   EDG3A Input Capture Edge Control
TMSK1           0x1022   Timer Interrupt Mask Register 1
TMSK1.OC1I       7   Output Compare 1 Interrupt Enable
TMSK1.OC2I       6   Output Compare 2 Interrupt Enable
TMSK1.OC3I       5   Output Compare 3 Interrupt Enable
TMSK1.OC4I       4   Output Compare 4 Interrupt Enable
TMSK1.I4_O5I     3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I       2   Input Capture 1 Interrupt Enable
TMSK1.IC2I       1   Input Capture 2 Interrupt Enable
TMSK1.IC3I       0   Input Capture 3 Interrupt Enable
TFLG1           0x1023   Timer Interrupt Flag Register 1
TFLG1.OC1F       7   Output Compare 1 Flag                
TFLG1.OC2F       6   Output Compare 2 Flag                
TFLG1.OC3F       5   Output Compare 3 Flag                
TFLG1.OC4F       4   Output Compare 4 Flag                
TFLG1.I4_O5F     3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F       2   Input Capture 1 Flag                 
TFLG1.IC2F       1   Input Capture 2 Flag                 
TFLG1.IC3F       0   Input Capture 3 Flag                 
TMSK2           0x1024   Timer Interrupt Mask Register 2
TMSK2.TOI        7   Timer Overflow Interrupt Enable              
TMSK2.RTII       6   Real-Time Interrupt Enable                   
TMSK2.PAOVI      5   Pulse Accumulator Overflow Interrupt Enable  
TMSK2.PAII       4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1        1   Timer Prescaler Select 1                     
TMSK2.PR0        0   Timer Prescaler Select 0                     
TFLG2           0x1025   Timer Interrupt Flag Register 2
TFLG2.TOF        7   Timer Overflow Interrupt Flag              
TFLG2.RTIF       6   Real-Time (Periodic) Interrupt Flag        
TFLG2.PAOVF      5   Pulse Accumulator Overflow Interrupt Flag  
TFLG2.PAIF       4   Pulse Accumulator Input Edge Interrupt Flag
PACTL           0x1026   Pulse Accumulator Control Register
PACTL.PAEN       6   Pulse Accumulator System Enable
PACTL.PAMOD      5   Pulse Accumulator Mode         
PACTL.PEDGE      4   Pulse Accumulator Edge Control 
PACTL.I4_05      2   Input Capture 4/Output Compare 
PACTL.RTR1       1   RTI Interrupt Rate Select 1    
PACTL.RTR0       0   RTI Interrupt Rate Select 0    
PACNT           0x1027   Pulse Accumulator Count Register  
SPCR            0x1028   Serial Peripheral Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable   
SPCR.DWOM        5   Port D Wired-OR Mode              
SPCR.MSTR        4   Master Mode Select                
SPCR.CPOL        3   Clock Polarity                    
SPCR.CPHA        2   Clock Phase                       
SPCR.SPR1        1   SPI Clock Rate Selects 1          
SPCR.SPR0        0   SPI Clock Rate Selects 0          
SPSR            0x1029   Serial Peripheral Status Register
SPSR.SPIF        7   SPI Interrupt Complete Flag
SPSR.WCOL        6   Write Collision            
SPSR.MODF        4   Mode Fault                 
SPDR            0x102A   SPI Data Register
BAUD            0x102B   Baud Rate        
BAUD.TCLR        7   Clear Baud Rate Counters (Test)  
BAUD.SCP1        5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0        4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB        3   SCI Baud Rate Clock Check (Test) 
BAUD.SCR2        2   SCI Baud Rate Selects 2          
BAUD.SCR1        1   SCI Baud Rate Selects 1          
BAUD.SCR0        0   SCI Baud Rate Selects 0          
SCCR1           0x102C   SCI Control Register
SCCR1.R8         7   Receive Data Bit 8            
SCCR1.T8         6   Transmit Data Bit 8           
SCCR1.M          4   Mode (Select Character Format)
SCCR1.WAKE       3   Wakeup by Address Mark/Idle   
SCCR2           0x102D   SCI Control Register
SCCR2.TIE        7   Transmit Interrupt Enable         
SCCR2.TCIE       6   Transmit Complete Interrupt Enable
SCCR2.RIE        5   Receiver Interrupt Enable         
SCCR2.ILIE       4   Idle-Line Interrupt Enable        
SCCR2.TE         3   Transmitter Enable                
SCCR2.RE         2   Receiver Enable                   
SCCR2.RWU        1   Receiver Wakeup Control           
SCCR2.SBK        0   Send Break                        
SCSR            0x102E   SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty Flag
SCSR.TC          6   Transmit Complete Flag           
SCSR.RDRF        5   Receive Data Register Full Flag  
SCSR.IDLE        4   Idle Line Detected Flag          
SCSR.OR          3   Overrun Error Flag               
SCSR.NF          2   Noise Error Flag                 
SCSR.FE          1   Framing Error                    
SCDR            0x102F   SCI Data (Read RDR, Write TDR)
RESERVED30      0x1030   RESERVED
RESERVED31      0x1031   RESERVED
RESERVED32      0x1032   RESERVED
RESERVED33      0x1033   RESERVED
RESERVED34      0x1034   RESERVED
RESERVED35      0x1035   RESERVED
RESERVED36      0x1036   RESERVED
RESERVED37      0x1037   RESERVED
OPT2            0x1038   System Configuration Options 2
OPT2.GWOM        7   Port G Wired-OR Mode
OPT2.CWOM        6   Port C Wired-OR Mode
OPT2.CLK4X       5   4XCLK Output Enable
OPT2.LIRDV       4   Load Instruction Register Driven
OPT2.SPRBYP      2   Refer to SPI Registers
OPTION          0x1039   System Configuration Options
OPTION.IRQE      5   IRQ Select Edge Sensitive Only
OPTION.DLY       4   Enable Oscillator Start-Up Delay on Exit from STOP
OPTION.CME       3   Clock Monitor Enable
OPTION.FCME      2   Force Clock Monitor Enable
OPTION.CR1       1   COP Timer Rate Select Bits 1                      
OPTION.CR0       0   COP Timer Rate Select Bits 0
COPRST          0x103A   Arm_Reset COP Timer Circuitry
RESERVED3B      0x103B   RESERVED
HPRIO           0x103C   Highest Priority I-Bit Int and Misc
HPRIO.RBOOT      7   Read Bootstrap ROM      
HPRIO.SMOD       6   Special Mode Select     
HPRIO.MDA        5   Mode Select A           
HPRIO.IRV        4   Internal Read Visibility
HPRIO.PSEL3      3   Priority Select Bits 3  
HPRIO.PSEL2      2   Priority Select Bits 2  
HPRIO.PSEL1      1   Priority Select Bits 1  
HPRIO.PSEL0      0   Priority Select Bits 0  
INIT            0x103D   RAM and I_O Mapping Register
INIT.RAM5        7   RAM Map Position 5
INIT.RAM4        6   RAM Map Position 4
INIT.RAM3        5   RAM Map Position 3
INIT.RAM2        4   RAM Map Position 2
INIT.RAM1        3   RAM Map Position 1
INIT.RAM0        2   RAM Map Position 0
INIT.REG1        1   Register Block Map Position 1
INIT.REG0        0   Register Block Map Position 0
TEST1           0x103E   Factory Test
TEST1.TILOP      7   Test Illegal Opcode
TEST1.OCCR       5   Output Condition Code Register to Timer Port
TEST1.CBYP       4   Timer Divider Chain Bypass
TEST1.DISR       3   Disable Resets from COP and Clock Monitor
TEST1.FCM        2   Force Clock Monitor Failure
TEST1.FCOP       1   Force COP Watchdog Failure
CONFIG          0x103F   System Configuration Register
CONFIG.NOCOP     2   COP System Disable
RESERVED40      0x1040   RESERVED
RESERVED41      0x1041   RESERVED
RESERVED42      0x1042   RESERVED
RESERVED43      0x1043   RESERVED
RESERVED44      0x1044   RESERVED
RESERVED45      0x1045   RESERVED
RESERVED46      0x1046   RESERVED
RESERVED47      0x1047   RESERVED
RESERVED48      0x1048   RESERVED
RESERVED49      0x1049   RESERVED
RESERVED4A      0x104A   RESERVED
RESERVED4B      0x104B   RESERVED
RESERVED4C      0x104C   RESERVED
RESERVED4D      0x104D   RESERVED
RESERVED4E      0x104E   RESERVED
RESERVED4F      0x104F   RESERVED
RESERVED50      0x1050   RESERVED
RESERVED51      0x1051   RESERVED
RESERVED52      0x1052   RESERVED
RESERVED53      0x1053   RESERVED
RESERVED54      0x1054   RESERVED
RESERVED55      0x1055   RESERVED
RESERVED56      0x1056   RESERVED
RESERVED57      0x1057   RESERVED
RESERVED58      0x1058   RESERVED
RESERVED59      0x1059   RESERVED
RESERVED5A      0x105A   RESERVED
RESERVED5B      0x105B   RESERVED
CSSTRH          0x105C   Chip Select Clock Stretch Select
CSSTRH.I01SA     7   I/O Chip Select 1 Clock Stretch Select A          
CSSTRH.I01SB     6   I/O Chip Select 1 Clock Stretch Select B          
CSSTRH.I02SA     5   I/O Chip Select 2 Clock Stretch Select A          
CSSTRH.I02SB     4   I/O Chip Select 2 Clock Stretch Select B          
CSSTRH.GSTHA     3   General-Purpose Chip Select Clock Stretch Select A
CSSTRH.GSTGB     2   General-Purpose Chip Select Clock Stretch Select B
CSSTRH.PSTHA     1   Program Chip Select Clock Stretch Select A        
CSSTRH.PSTHB     0   Program Chip Select Clock Stretch Select B        
CSCTL           0x105D   Chip Select Control
CSCTL.I01EN      7   I/O Chip Select 1 Enable            
CSCTL.I01PL      6   I/O Chip Select 1 Polarity Select   
CSCTL.I02EN      5   I/O Chip Select 2 Enable            
CSCTL.I02PL      4   I/O Chip Select 2 Polarity Select   
CSCTL.GCSPR      3   General-Purpose Chip Select Priority
CSCTL.PCSEN      2   Program Chip Select Enable          
CSCTL.PSIZA      1   Program Chip Select Size A          
CSCTL.PSIZB      0   Program Chip Select Size B          
CSGADR          0x105E   General-Purpose Chip Select Address Register
CSGADR.GA15      7   General-Purpose Chip Select Base Address 15
CSGADR.GA14      6   General-Purpose Chip Select Base Address 14
CSGADR.GA13      5   General-Purpose Chip Select Base Address 13
CSGADR.GA12      4   General-Purpose Chip Select Base Address 12
CSGADR.GA11      3   General-Purpose Chip Select Base Address 11
CSGADR.GA10      2   General-Purpose Chip Select Base Address 10
CSGSIZ          0x105F   General-Purpose Chip Select Size Control
CSGSIZ.I01AV     7   I/O Chip Select 1 Address Valid                 
CSGSIZ.I02AV     6   I/O Chip Select 2 Address Valid                 
CSGSIZ.GNPOL     4   General-Purpose Chip Select Polarity Select     
CSGSIZ.GAVLD     3   General-Purpose Chip Select Address Valid Select
CSGSIZ.GSIZA     2   General-Purpose Chip Select Size A              
CSGSIZ.GSIZB     1   General-Purpose Chip Select Size B              
CSGSIZ.GSIZC     0   General-Purpose Chip Select Size C              
RESERVFFC0      0xFFC0   RESERVED
RESERVFFC1      0xFFC1   RESERVED
RESERVFFC2      0xFFC2   RESERVED
RESERVFFC3      0xFFC3   RESERVED
RESERVFFC4      0xFFC4   RESERVED
RESERVFFC5      0xFFC5   RESERVED
RESERVFFC6      0xFFC6   RESERVED
RESERVFFC7      0xFFC7   RESERVED
RESERVFFC8      0xFFC8   RESERVED
RESERVFFC9      0xFFC9   RESERVED
RESERVFFCA      0xFFCA   RESERVED
RESERVFFCB      0xFFCB   RESERVED
RESERVFFCC      0xFFCC   RESERVED
RESERVFFCD      0xFFCD   RESERVED
RESERVFFCE      0xFFCE   RESERVED
RESERVFFCF      0xFFCF   RESERVED
RESERVFFD0      0xFFD0   RESERVED
RESERVFFD1      0xFFD1   RESERVED
RESERVFFD2      0xFFD2   RESERVED
RESERVFFD3      0xFFD3   RESERVED
RESERVFFD4      0xFFD4   RESERVED
RESERVFFD5      0xFFD5   RESERVED


.68HC11G0
; http://

; RAM=512
; ROM=0
; EPROM=0
; EEPROM=0

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS


.68HC11G5
; MC68HC11G5/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11G5.pdf
; MC68HC11G5.pdf

; RAM=512
; ROM=16K
; EPROM=0
; EEPROM=0


; MEMORY MAP
area DATA RAM        0x0000:0x0200
area BSS  RESERVED   0x0200:0x1000
area DATA FSR        0x1000:0x1080
area BSS  RESERVED   0x1080:0xC000
area DATA ROM        0xC000:0xFFC0
area DATA USER_VEC   0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SWI               0xFFF6      SWI
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt OC5_IC4           0xFFE0      Timer Output Compare 5/Input Capture 4
interrupt TO1               0xFFDE      Timer Overflow 1
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System
interrupt OC6_IC5           0xFFD4      Timer Output Compare 6/Input Capture 5
interrupt OC7_IC6           0xFFD2      Timer Output Compare 7/Input Capture 6
interrupt TO2               0xFFD0      Timer Overflow 2
interrupt Event_1           0xFFCE      Event 1
interrupt Event_2           0xFFCC      Event 2


; INPUT/ OUTPUT PORTS
PORTA             0x1000   PORTA I_O Port A
PORTA.PA7          7   Port A Data Bit 7
PORTA.PA6          6   Port A Data Bit 6
PORTA.PA5          5   Port A Data Bit 5
PORTA.PA4          4   Port A Data Bit 4
PORTA.PA3          3   Port A Data Bit 3
PORTA.PA2          2   Port A Data Bit 2
PORTA.PA1          1   Port A Data Bit 1
PORTA.PA0          0   Port A Data Bit 0
DDRA              0x1001   DDRA Data Direction for Port A
DDRA.DDA7          7   Data Direction for Port A Bit 7
DDRA.DDA6          6   Data Direction for Port A Bit 6
DDRA.DDA5          5   Data Direction for Port A Bit 5
DDRA.DDA4          4   Data Direction for Port A Bit 4
DDRA.DDA3          3   Data Direction for Port A Bit 3
DDRA.DDA2          2   Data Direction for Port A Bit 2
DDRA.DDA1          1   Data Direction for Port A Bit 1
DDRA.DDA0          0   Data Direction for Port A Bit 0
PORTG             0x1002   PORTG I_O Port G
PORTG.PG7          7   Port G Data Bit 7
PORTG.PG6          6   Port G Data Bit 6
PORTG.PG5          5   Port G Data Bit 5
PORTG.PG4          4   Port G Data Bit 4
PORTG.PG3          3   Port G Data Bit 3
PORTG.PG2          2   Port G Data Bit 2
PORTG.PG1          1   Port G Data Bit 1
PORTG.PG0          0   Port G Data Bit 0
DDRG              0x1003   DDRG Data Direction for Port G
DDRG.DDG7          7   Data Direction for Port G Bit 7
DDRG.DDG6          6   Data Direction for Port G Bit 6
DDRG.DDG5          5   Data Direction for Port G Bit 5
DDRG.DDG4          4   Data Direction for Port G Bit 4
DDRG.DDG3          3   Data Direction for Port G Bit 3
DDRG.DDG2          2   Data Direction for Port G Bit 2
DDRG.DDG1          1   Data Direction for Port G Bit 1
DDRG.DDG0          0   Data Direction for Port G Bit 0
PORTB             0x1004   PORTB I_O Port B
PORTB.PB7          7   Port B Data Bit 7
PORTB.PB6          6   Port B Data Bit 6
PORTB.PB5          5   Port B Data Bit 5
PORTB.PB4          4   Port B Data Bit 4
PORTB.PB3          3   Port B Data Bit 3
PORTB.PB2          2   Port B Data Bit 2
PORTB.PB1          1   Port B Data Bit 1
PORTB.PB0          0   Port B Data Bit 0
PORTF             0x1005   PORTF I_O Port F
PORTF.PF7          7   Port F Data Bit 7
PORTF.PF6          6   Port F Data Bit 6
PORTF.PF5          5   Port F Data Bit 5
PORTF.PF4          4   Port F Data Bit 4
PORTF.PF3          3   Port F Data Bit 3
PORTF.PF2          2   Port F Data Bit 2
PORTF.PF1          1   Port F Data Bit 1
PORTF.PF0          0   Port F Data Bit 0
PORTC             0x1006   PORTC I_O Port C
PORTC.PC7          7   Port C Data Bit 7
PORTC.PC6          6   Port C Data Bit 6
PORTC.PC5          5   Port C Data Bit 5
PORTC.PC4          4   Port C Data Bit 4
PORTC.PC3          3   Port C Data Bit 3
PORTC.PC2          2   Port C Data Bit 2
PORTC.PC1          1   Port C Data Bit 1
PORTC.PC0          0   Port C Data Bit 0
DDRC              0x1007   DDRC Data Direction for Port C
DDRC.DDC7          7   Data Direction for Port C Bit 7
DDRC.DDC6          6   Data Direction for Port C Bit 6
DDRC.DDC5          5   Data Direction for Port C Bit 5
DDRC.DDC4          4   Data Direction for Port C Bit 4
DDRC.DDC3          3   Data Direction for Port C Bit 3
DDRC.DDC2          2   Data Direction for Port C Bit 2
DDRC.DDC1          1   Data Direction for Port C Bit 1
DDRC.DDC0          0   Data Direction for Port C Bit 0
PORTD             0x1008   PORTD I_O Port D
PORTD.PD5          5   Port D Data Bit 5
PORTD.PD4          4   Port D Data Bit 4
PORTD.PD3          3   Port D Data Bit 3
PORTD.PD2          2   Port D Data Bit 2
PORTD.PD1          1   Port D Data Bit 1
PORTD.PD0          0   Port D Data Bit 0
DDRD              0x1009   DDRD Data Direction for Port D
DDRD.DDD5          5   Data Direction for Port D Bit 5
DDRD.DDD4          4   Data Direction for Port D Bit 4
DDRD.DDD3          3   Data Direction for Port D Bit 3
DDRD.DDD2          2   Data Direction for Port D Bit 2
DDRD.DDD1          1   Data Direction for Port D Bit 1
DDRD.DDD0          0   Data Direction for Port D Bit 0
PORTE             0x100A   PORTE I_O Port E
PORTE.PE7          7   Port E Data Bit 7
PORTE.PE6          6   Port E Data Bit 6
PORTE.PE5          5   Port E Data Bit 5
PORTE.PE4          4   Port E Data Bit 4
PORTE.PE3          3   Port E Data Bit 3
PORTE.PE2          2   Port E Data Bit 2
PORTE.PE1          1   Port E Data Bit 1
PORTE.PE0          0   Port E Data Bit 0
CFORC             0x100B   CFORC Compare Force Register
CFORC.FOC1         7   Force Output Comparison 1
CFORC.FOC2         6   Force Output Comparison 2
CFORC.FOC3         5   Force Output Comparison 3
CFORC.FOC4         4   Force Output Comparison 4
CFORC.FOC5         3   Force Output Comparison 5
CFORC.FOC6         2   Force Output Comparison 6
CFORC.FOC7         1   Force Output Comparison 7
OC1M              0x100C   OC1M OC1 Action Mask Register
OC1M.OC1M7         7   Output Compare Masks 7
OC1M.OC1M6         6   Output Compare Masks 6
OC1M.OC1M5         5   Output Compare Masks 5
OC1M.OC1M4         4   Output Compare Masks 4
OC1M.OC1M3         3   Output Compare Masks 3
OC1D              0x100D   OC1D OC1 Action Data Register
OC1D.OC1D7         7   Output Compare Data 7
OC1D.OC1D6         6   Output Compare Data 6
OC1D.OC1D5         5   Output Compare Data 5
OC1D.OC1D4         4   Output Compare Data 4
OC1D.OC1D3         3   Output Compare Data 3
TCNT1H            0x100E   TCNT1H Timer Counter Register 1 H
TCNT1L            0x100F   TCNT1L Timer Counter Register 1 L
TIC1H             0x1010   TIC1H Input Capture 1 Register H
TIC1L             0x1011   TIC1L Input Capture 1 Register L
TIC2H             0x1012   TIC2H Input Capture 2 Register H
TIC2L             0x1013   TIC2L Input Capture 2 Register L
TIC3H             0x1014   TIC3H Input Capture 3 Register H
TIC3L             0x1015   TIC3L Input Capture 3 Register L
TOC1H             0x1016   TOC1H Output Compare 1 Register H
TOC1L             0x1017   TOC1L Output Compare 1 Register L
TOC2H             0x1018   TOC2H Output Compare 2 Register H
TOC2L             0x1019   TOC2L Output Compare 2 Register L
TOC3H             0x101A   TOC3H Output Compare 3 Register H
TOC3L             0x101B   TOC3L Output Compare 3 Register L
TOC4H             0x101C   TOC4H Output Compare 4 Register H
TOC4L             0x101D   TOC4L Output Compare 4 Register L
TO5I4H            0x101E   TO5I4H Output Compare 5_Input Capture 4 Register H
TO5I4L            0x101F   TO5I4L Output Compare 5_Input Capture 4 Register L
TCTL1             0x1020   TCTL1 Timer Control Register 1
TCTL1.OM2          7   Output Mode 2 
TCTL1.OL2          6   Output Level 2
TCTL1.OM3          5   Output Mode 3 
TCTL1.OL3          4   Output Level 3
TCTL1.OM4          3   Output Mode 4 
TCTL1.OL4          2   Output Level 4
TCTL1.OM5          1   Output Mode 5 
TCTL1.OL5          0   Output Level 5
TCTL2             0x1021   TCTL2 Timer Control Register 2
TCTL2.EDG4B        7   EDG4B Input Capture Edge Control
TCTL2.EDG4A        6   EDG4A Input Capture Edge Control
TCTL2.EDG1B        5   EDG1B Input Capture Edge Control
TCTL2.EDG1A        4   EDG1A Input Capture Edge Control
TCTL2.EDG2B        3   EDG2B Input Capture Edge Control
TCTL2.EDG2A        2   EDG2A Input Capture Edge Control
TCTL2.EDG3B        1   EDG3B Input Capture Edge Control
TCTL2.EDG3A        0   EDG3A Input Capture Edge Control
TMSK1             0x1022   TMSK1 Main Timer Interrupt Mask Register 1
TMSK1.OC1I         7   Output Compare 1 Interrupt Enable
TMSK1.OC2I         6   Output Compare 2 Interrupt Enable
TMSK1.OC3I         5   Output Compare 3 Interrupt Enable
TMSK1.OC4I         4   Output Compare 4 Interrupt Enable
TMSK1.4_5I         3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I         2   Input Capture 1 Interrupt Enable
TMSK1.IC2I         1   Input Capture 2 Interrupt Enable
TMSK1.IC3I         0   Input Capture 3 Interrupt Enable
TFLG1             0x1023   TFLG1 Main Timer Interrupt Flag Register 1
TFLG1.OC1F         7   Output Compare 1 Flag                
TFLG1.OC2F         6   Output Compare 2 Flag                
TFLG1.OC3F         5   Output Compare 3 Flag                
TFLG1.OC4F         4   Output Compare 4 Flag                
TFLG1.4_5F         3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F         2   Input Capture 1 Flag                 
TFLG1.IC2F         1   Input Capture 2 Flag                 
TFLG1.IC3F         0   Input Capture 3 Flag                 
TMSK2             0x1024   TMSK2 Misc. Timer Interrupt Mask Register 2
TMSK2.TO1I         7   Timer Overflow 1 Interrupt Enable
TMSK2.RTII         6   RTI Interrupt Enable
TMSK2.PAOVI        5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII         4   Pulse Accumulator Input Interrupt Enable
TMSK2.TO2I         3   Timer Overflow 2 Interrupt Enable
TMSK2.5_6I         2   Input Capture 5/Output Compare 6 Interrupt Enable
TMSK2.6_7I         1   Input Capture 6/Output Compare 7 Interrupt Enable
TFLG2             0x1025   TFLG2 Misc. Timer Interrupt Flag Register 2
TFLG2.TO1F         7   Timer Overflow 1 Flag
TFLG2.RTIF         6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF        5   Pulse Accumulator Overflow Flag
TFLG2.PAIF         4   Pulse Accumulator Input Edge Flag
TFLG2.TO2F         3   Timer Overflow 2 Flag
TFLG2.5_6F         2   Input Capture 5/Output Compare 6 Flag
TFLG2.6_7F         1   Input Capture 6/Output Compare 7 Flag
PACTL             0x1026   PACTL Pulse Accumulator Control Register
PACTL.PAEN         6   Pulse Accumulator System Enable
PACTL.PAMOD        5   Pulse Accumulator Mode         
PACTL.PEDGE        4   Pulse Accumulator Edge Control 
PACTL.I4_O5        3   Input Capture 4/Output Compare 
PACTL.RTR2         2   RTI Interrupt Rate Select 2
PACTL.RTR1         1   RTI Interrupt Rate Select 1
PACTL.RTR0         0   RTI Interrupt Rate Select 0
PACNT             0x1027   PACNT Pulse Accumulator Count Register
SPCR              0x1028   SPCR SPI Control Register
SPCR.SPIE          7   Serial Peripheral Interrupt Enable
SPCR.SPE           6   Serial Peripheral System Enable   
SPCR.DWOM          5   Port D Wired-OR Mode              
SPCR.MSTR          4   Master Mode Select                
SPCR.CPOL          3   Clock Polarity                    
SPCR.CPHA          2   Clock Phase                       
SPCR.SPR1          1   SPI Clock Rate Selects 1          
SPCR.SPR0          0   SPI Clock Rate Selects 0          
SPSR              0x1029   SPSR SPI Status Register
SPSR.SPIF          7   SPI Interrupt Complete Flag
SPSR.WCOL          6   Write Collision            
SPSR.MODF          4   Mode Fault                 
SPDAT             0x102A   SPDAT SPI Data Register
BAUD              0x102B   BAUD SCI Baud Rate Control
BAUD.TCLR          7   Clear Baud Rate Counters (Test)  
BAUD.SCP1          5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0          4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB          3   SCI Receive Baud Rate Clock Test
BAUD.SCR2          2   SCI Baud Rate Selects 2          
BAUD.SCR1          1   SCI Baud Rate Selects 1          
BAUD.SCR0          0   SCI Baud Rate Selects 0          
SCCR1             0x102C   SCCR1 SCI Control Register 1
SCCR1.R8           7   Receive Data Bit 8            
SCCR1.T8           6   Transmit Data Bit 8           
SCCR1.M            4   Mode (Select Character Format)
SCCR1.WAKE         3   Wakeup by Address Mark/Idle   
SCCR2             0x102D   SCCR2 SCI Control Register 2
SCCR2.TIE          7   Transmit Interrupt Enable         
SCCR2.TCIE         6   Transmit Complete Interrupt Enable
SCCR2.RIE          5   Receiver Interrupt Enable         
SCCR2.ILIE         4   Idle-Line Interrupt Enable        
SCCR2.TE           3   Transmitter Enable                
SCCR2.RE           2   Receiver Enable                   
SCCR2.RWU          1   Receiver Wakeup Control           
SCCR2.SBK          0   Send Break                        
SCSR              0x102E   SCSR SCI Status Register
SCSR.TDRE          7   Transmit Data Register Empty Flag
SCSR.TC            6   Transmit Complete Flag           
SCSR.RDRF          5   Receive Data Register Full Flag  
SCSR.IDLE          4   Idle Line Detected Flag          
SCSR.OR            3   Overrun Error Flag               
SCSR.NF            2   Noise Error Flag                 
SCSR.FE            1   Framing Error                    
SCDAT             0x102F   SCDAT SCI Data (Read RDR, Write TDR)
ADCTL             0x1030   ADCTL A_D Control Register
ADCTL.CCF          7   Conversions Complete Flag
ADCTL.CONV8        6   Convert 8/Convert 4 Select Bit
ADCTL.SCAN         5   Continuous Scan Control
ADCTL.MULT         4   Multiple Channel/Single Channel Control
ADCTL.CD           3   Channel Select Bits D
ADCTL.CC           2   Channel Select Bits C
ADCTL.CB           1   Channel Select Bits B
ADCTL.CA           0   Channel Select Bits A
PORTJ             0x1031   PORTJ I_O Port J
PORTJ.PJ3          3   Port J Data Bit 3
PORTJ.PJ2          2   Port J Data Bit 2
PORTJ.PJ1          1   Port J Data Bit 1
PORTJ.PJ0          0   Port J Data Bit 0
DDRJ              0x1032   DDRJ Data Direction for Port J
DDRJ.DDJ3          3   Data Direction for Port J Bit 3
DDRJ.DDJ2          2   Data Direction for Port J Bit 2
DDRJ.DDJ1          1   Data Direction for Port J Bit 1
DDRJ.DDJ0          0   Data Direction for Port J Bit 0
PORTH             0x1033   PORTH I_O Port H
PORTH.PH7          7   Port H Data Bit 7
PORTH.PH6          6   Port H Data Bit 6
PORTH.PH5          5   Port H Data Bit 5
PORTH.PH4          4   Port H Data Bit 4
PORTH.PH3          3   Port H Data Bit 3
PORTH.PH2          2   Port H Data Bit 2
PORTH.PH1          1   Port H Data Bit 1
PORTH.PH0          0   Port H Data Bit 0
DDRH              0x1034   DDRH Data Direction for Port H
DDRH.DDH7          7   Data Direction for Port H Bit 7
DDRH.DDH6          6   Data Direction for Port H Bit 6
DDRH.DDH5          5   Data Direction for Port H Bit 5
DDRH.DDH4          4   Data Direction for Port H Bit 4
DDRH.DDH3          3   Data Direction for Port H Bit 3
DDRH.DDH2          2   Data Direction for Port H Bit 2
DDRH.DDH1          1   Data Direction for Port H Bit 1
DDRH.DDH0          0   Data Direction for Port H Bit 0
RESERV1035        0x1035   RESERVED
RESERV1036        0x1036   RESERVED
RESERV1037        0x1037   RESERVED
OPT2              0x1038   OPT2 System Configuration Options 2 Reg.
OPT2.GWOM          7   Port G Wired-OR Mode
OPT2.CWOM          6   Port C Wired-OR Mode
OPT2.IRV           4   Internal Read Visibility
OPT2.MRDY          1   Memory Ready Enable
OPT2.NHALT         0   Enable Halt Function
OPTION            0x1039   OPTION System Configuration Options
OPTION.ADPU        7   A/D Power Up
OPTION.CSEL        6   Clock Select
OPTION.IRQE        5   IRQ Select Edge Sensitive Only
OPTION.DLY         4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME         3   Clock Monitor Enable
OPTION.CR1         1   COP Timer Rate select bits 1
OPTION.CR0         0   COP Timer Rate select bits 0
COPRST            0x103A   COPRST Arm_Reset COP Timer Circuitry
RESERV103B        0x103B   RESERVED
HPRIO             0x103C   HPRIO Highest Priority I-terrupt and Misc.
HPRIO.RBOOT        7   Read Bootstrap ROM
HPRIO.SMOD         6   Special Mode Select
HPRIO.MDA          5   Mode Select A
HPRIO.PSEL4        4   Priority Select Bits 4
HPRIO.PSEL3        3   Priority Select Bits 3
HPRIO.PSEL2        2   Priority Select Bits 2
HPRIO.PSEL1        1   Priority Select Bits 1
HPRIO.PSEL0        0   Priority Select Bits 0
INIT              0x103D   INIT RAM and I_O Mapping Register
INIT.RAM3          7   RAM Map Position 3
INIT.RAM2          6   RAM Map Position 2
INIT.RAM1          5   RAM Map Position 1
INIT.RAM0          4   RAM Map Position 0
INIT.REG3          3   Register Block Map Position 3
INIT.REG2          2   Register Block Map Position 2
INIT.REG1          1   Register Block Map Position 1
INIT.REG0          0   Register Block Map Position 0
TEST1             0x103E   TEST1 Factory Test Control Register
TEST1.TILOP        7   Test Illegal Opcode
TEST1.TPWSL        6   Pulse Width Modulation Scaled Clock
TEST1.OCCR         5   Output Condition Code Register Status to Timer Port
TEST1.CBYP1        4   Timer Counter 1 Divider Chain By-pass
TEST1.DISR         3   Disable Resets from COP and Clock Monitor
TEST1.FCM          2   Force Clock Monitor Failure
TEST1.FCOP         1   Force COP Watchdog Failure
TEST1.CBYP2        0   Timer Counter 2 Chain By-pass
CONFIG            0x103F   CONFIG COP and ROM Enables
CONFIG.NOCOP       2   COP System Disable
CONFIG.ROMON       1   ROM Enable
ADR1H             0x1040   ADR1H A_D Result Register 1 H
ADR1L             0x1041   ADR1L A_D Result Register 1 L
ADR2H             0x1042   ADR2H A_D Result Register 2 H
ADR2L             0x1043   ADR2L A_D Result Register 2 L
ADR3H             0x1044   ADR3H A_D Result Register 3 H
ADR3L             0x1045   ADR3L A_D Result Register 3 L
ADR4H             0x1046   ADR4H A_D Result Register 4 H
ADR4L             0x1047   ADR4L A_D Result Register 4 L
ADR5H             0x1048   ADR5H A_D Result Register 5 H
ADR5L             0x1049   ADR5L A_D Result Register 5 L
ADR6H             0x104A   ADR6 A_D Result Register 6 H
ADR6L             0x104B   ADR6 A_D Result Register 6 L
ADR7H             0x104C   ADR7H A_D Result Register 7 H
ADR7L             0x104D   ADR7L A_D Result Register 7 L
ADR8H             0x104E   ADR8H A_D Result Register 8 H
ADR8L             0x104F   ADR8L A_D Result Register 8 L
TCTL3             0x1050   TCTL3 Timer Control Register 3
TCTL3.EDG5B        7   Input Capture Edge Control 5B
TCTL3.EDG5A        6   Input Capture Edge Control 5A
TCTL3.EDG6B        5   Input Capture Edge Control 6B
TCTL3.EDG6A        4   Input Capture Edge Control 6A
TCTL3.OM6          3   Output Mode 6
TCTL3.OL6          2   Output Level 6
TCTL3.OM7          1   Output Mode 7
TCTL3.OL7          0   Output Level 7
TCTL4             0x1051   TCTL4 Timer Control Register 4
TCTL4.CT2SP        7   Timer Counter 2 Stop (used to facilitate testing)
TCTL4.CT1SP        6   Timer Counter 1 Stop (used to facilitate testing)
TCTL4.I5_O6        1   Configure TO6I5 Register for Input Capture or Output Compare
TCTL4.I6_O7        0   Configure TO7I6 Register for Input Capture or Output Compare
TCNT2H            0x1052   TCNT2H Timer Counter Register 2 H
TCNT2L            0x1053   TCNT2L Timer Counter Register 2 L
TO6I5H            0x1054   TO6I5H Output Compare 6_Input Capture 5 Register H
TO6I5L            0x1055   TO6I5L Output Compare 6_Input Capture 5 Register L
TO7I6H            0x1056   TO7I6H Output Compare 7_Input Capture 6 Register H
TO7I6L            0x1057   TO7I6L Output Compare 7_Input Capture 6 Register L
TPRE              0x1058   TPRE Timer Prescaler Register
TPRE.TEDGB         7   Timer External Clock Edge Select B
TPRE.TEDGA         6   Timer External Clock Edge Select A
TPRE.PR2B          5   Timer Prescaler Select 2B
TPRE.PR2A          4   Timer Prescaler Select 2A
TPRE.PR1B          1   Timer Prescaler Select 1B
TPRE.PR1A          0   Timer Prescaler Select 1A
RESERV1059        0x1059   RESERVED
RESERV105A        0x105A   RESERVED
RESERV105B        0x105B   RESERVED
RESERV105C        0x105C   RESERVED
RESERV105D        0x105D   RESERVED
RESERV105E        0x105E   RESERVED
RESERV105F        0x105F   RESERVED
PWCLK             0x1060   PWCLK PWM Timer Clock Select
PWCLK.CON34        7   Concatenate channels 3 and 4
PWCLK.CON12        6   Concatenate channels 1 and 2
PWCLK.PCKA2        5   Prescaler for clock A BIT 2
PWCLK.PCKA1        4   Prescaler for clock A BIT 1
PWCLK.PCKB3        2   Prescaler for clock B BIT 3
PWCLK.PCKB2        1   Prescaler for clock B BIT 2
PWCLK.PCKB1        0   Prescaler for clock B BIT 1
PWPOL             0x1061   PWPOL PWM Timer Polarity
PWPOL.PCLK4        7   Pulse Width Channel 4 Clock Select
PWPOL.PCLK3        6   Pulse Width Channel 3 Clock Select
PWPOL.PCLK2        5   Pulse Width Channel 2 Clock Select
PWPOL.PCLK1        4   Pulse Width Channel 1 Clock Select
PWPOL.PPOL4        3   Pulse Width Channel 4 Polarity
PWPOL.PPOL3        2   Pulse Width Channel 3 Polarity
PWPOL.PPOL2        1   Pulse Width Channel 2 Polarity
PWPOL.PPOL1        0   Pulse Width Channel 1 Polarity
PWSCAL            0x1062   PWSCAL PWM Timer Prescaler
PWEN              0x1063   PWEN PWM Timer Enable
PWEN.PWEN4         3   Pulse Width Channel 4 Enable
PWEN.PWEN3         2   Pulse Width Channel 3 Enable
PWEN.PWEN2         1   Pulse Width Channel 2 Enable
PWEN.PWEN1         0   Pulse Width Channel 1 Enable
PWCNT1            0x1064   PWCNT1 PWM Timer Counter 1
PWCNT2            0x1065   PWCNT2 PWM Timer Counter 2
PWCNT3            0x1066   PWCNT3 PWM Timer Counter 3
PWCNT4            0x1067   PWCNT4 PWM Timer Counter 4
PWPER1            0x1068   PWPER1 PWM Timer Period 1
PWPER2            0x1069   PWPER2 PWM Timer Period 2
PWPER3            0x106A   PWPER3 PWM Timer Period 3
PWPER4            0x106B   PWPER4 PWM Timer Period 4
PWDTY1            0x106C   PWDTY1 PWM Timer Duty 1
PWDTY2            0x106D   PWDTY2 PWM Timer Duty 2
PWDTY3            0x106E   PWDTY3 PWM Timer Duty 3
PWDTY4            0x106F   PWDTY4 PWM Timer Duty 4
EVCLK             0x1070   EVCLK Event Counter Clock Select
EVCLK.EVMDB        5   Event Counter Mode bits B
EVCLK.EVMDA        4   Event Counter Mode bits A
EVCLK.EVCKC        2   Event Counter Prescaler bits C
EVCLK.EVCKB        1   Event Counter Prescaler bits B
EVCLK.EVCKA        0   Event Counter Prescaler bits A
EVCTL            0x1071    EVCTL Event Counter Control Register                 
EVCTL.EVOEN       7   Event Output Enable (Port H, bit 6)
EVCTL.EVPOL       6   Event Output Polarity
EVCTL.EVI2C       5   Event Input Select 2 C (EVI2)
EVCTL.EVI2B       4   Event Input Select 2 B (EVI2)
EVCTL.EVI2A       3   Event Input Select 2 A (EVI2)
EVCTL.EVI1C       2   Event Input Select 1 C (EVI1)
EVCTL.EVI1B       1   Event Input Select 1 B (EVI1)
EVCTL.EVI1A       0   Event Input Select 1 A (EVI1)
EVMSK            0x1072    EVMSK Event Counter Interrupt Mask Register                
EVMSK.EVCEN       7   Event Counters Enable
EVMSK.EV2I        1   Event 2 Interrupt Enable
EVMSK.EV1I        0   Event 1 Interrupt Enable
EVFLG            0x1073    EVFLG Event Counter Interrupt Flag Register                
EVFLG.EV2F        1   Event Interrupt 2 Flag
EVFLG.EV1F        0   Event Interrupt 1 Flag
EVCNT1           0x1074    EVCNT1 Event Counter Count Register 1
EVCNT2           0x1075    EVCNT2 Event Counter Count Register 2
ECMP1A           0x1076    ECMP1A Event Counter Compare Register 1A
ECMP2A           0x1077    ECMP2A Event Counter Compare Register 2A
ECMP1B           0x1078    ECMP1B Event Counter Compare Register 1B
ECMP2B           0x1079    ECMP2B Event Counter Compare Register 2B
RESERV107A       0x107A    RESERVED
RESERV107B       0x107B    RESERVED
RESERV107C       0x107C    RESERVED
RESERV107D       0x107D    RESERVED
RESERV107E       0x107E    RESERVED
RESERV107F       0x107F    RESERVED
RESERVFFC0       0xFFC0    RESERVED
RESERVFFC1       0xFFC1    RESERVED
RESERVFFC2       0xFFC2    RESERVED
RESERVFFC3       0xFFC3    RESERVED
RESERVFFC4       0xFFC4    RESERVED
RESERVFFC5       0xFFC5    RESERVED
RESERVFFC6       0xFFC6    RESERVED
RESERVFFC7       0xFFC7    RESERVED
RESERVFFC8       0xFFC8    RESERVED
RESERVFFC9       0xFFC9    RESERVED
RESERVFFCA       0xFFCA    RESERVED
RESERVFFCB       0xFFCB    RESERVED
                     

.68HC11G7
; MC68HC11G5/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11G5.pdf
; MC68HC11G5.pdf (Appendix A not present)

; RAM=512
; ROM=24K
; EPROM=0
; EEPROM=0

; MEMORY MAP

; area DATA RAM         0x0000:0x0200
; area BSS  RESERVED    0x0200:0x1000
; area DATA FSR         0x1000:0x1080
; area BSS  RESERVED    0x1080:0xC000
; area DATA ROM	        0xC000:0xFFC0
; area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments

interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SWI               0xFFF6      SWI
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt OC5_IC4           0xFFE0      Timer OC5/IC4
interrupt TOI_1             0xFFDE      Timer Overflow 1
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System
interrupt OC6_IC5           0xFFD4      Timer OC6/IC5
interrupt OC7_IC6           0xFFD2      Timer OC7/IC6
interrupt TOI_2             0xFFD0      Timer Overflow 2
interrupt Event_1           0xFFCE      Event_1
interrupt Event_2           0xFFCC      Event_2


; INPUT/ OUTPUT PORTS
PORTA             0x1000   PORTA I_O Port A
PORTA.PA7          7   Port A Data Bit 7
PORTA.PA6          6   Port A Data Bit 6
PORTA.PA5          5   Port A Data Bit 5
PORTA.PA4          4   Port A Data Bit 4
PORTA.PA3          3   Port A Data Bit 3
PORTA.PA2          2   Port A Data Bit 2
PORTA.PA1          1   Port A Data Bit 1
PORTA.PA0          0   Port A Data Bit 0
DDRA              0x1001   DDRA Data Direction for Port A
DDRA.DDA7          7   Data Direction for Port A Bit 7
DDRA.DDA6          6   Data Direction for Port A Bit 6
DDRA.DDA5          5   Data Direction for Port A Bit 5
DDRA.DDA4          4   Data Direction for Port A Bit 4
DDRA.DDA3          3   Data Direction for Port A Bit 3
DDRA.DDA2          2   Data Direction for Port A Bit 2
DDRA.DDA1          1   Data Direction for Port A Bit 1
DDRA.DDA0          0   Data Direction for Port A Bit 0
PORTG             0x1002   PORTG I_O Port G
PORTG.PG7          7   Port G Data Bit 7
PORTG.PG6          6   Port G Data Bit 6
PORTG.PG5          5   Port G Data Bit 5
PORTG.PG4          4   Port G Data Bit 4
PORTG.PG3          3   Port G Data Bit 3
PORTG.PG2          2   Port G Data Bit 2
PORTG.PG1          1   Port G Data Bit 1
PORTG.PG0          0   Port G Data Bit 0
DDRG              0x1003   DDRG Data Direction for Port G
DDRG.DDG7          7   Data Direction for Port G Bit 7
DDRG.DDG6          6   Data Direction for Port G Bit 6
DDRG.DDG5          5   Data Direction for Port G Bit 5
DDRG.DDG4          4   Data Direction for Port G Bit 4
DDRG.DDG3          3   Data Direction for Port G Bit 3
DDRG.DDG2          2   Data Direction for Port G Bit 2
DDRG.DDG1          1   Data Direction for Port G Bit 1
DDRG.DDG0          0   Data Direction for Port G Bit 0
PORTB             0x1004   PORTB I_O Port B
PORTB.PB7          7   Port B Data Bit 7
PORTB.PB6          6   Port B Data Bit 6
PORTB.PB5          5   Port B Data Bit 5
PORTB.PB4          4   Port B Data Bit 4
PORTB.PB3          3   Port B Data Bit 3
PORTB.PB2          2   Port B Data Bit 2
PORTB.PB1          1   Port B Data Bit 1
PORTB.PB0          0   Port B Data Bit 0
PORTF             0x1005   PORTF I_O Port F
PORTF.PF7          7   Port F Data Bit 7
PORTF.PF6          6   Port F Data Bit 6
PORTF.PF5          5   Port F Data Bit 5
PORTF.PF4          4   Port F Data Bit 4
PORTF.PF3          3   Port F Data Bit 3
PORTF.PF2          2   Port F Data Bit 2
PORTF.PF1          1   Port F Data Bit 1
PORTF.PF0          0   Port F Data Bit 0
PORTC             0x1006   PORTC I_O Port C
PORTC.PC7          7   Port C Data Bit 7
PORTC.PC6          6   Port C Data Bit 6
PORTC.PC5          5   Port C Data Bit 5
PORTC.PC4          4   Port C Data Bit 4
PORTC.PC3          3   Port C Data Bit 3
PORTC.PC2          2   Port C Data Bit 2
PORTC.PC1          1   Port C Data Bit 1
PORTC.PC0          0   Port C Data Bit 0
DDRC              0x1007   DDRC Data Direction for Port C
DDRC.DDC7          7   Data Direction for Port C Bit 7
DDRC.DDC6          6   Data Direction for Port C Bit 6
DDRC.DDC5          5   Data Direction for Port C Bit 5
DDRC.DDC4          4   Data Direction for Port C Bit 4
DDRC.DDC3          3   Data Direction for Port C Bit 3
DDRC.DDC2          2   Data Direction for Port C Bit 2
DDRC.DDC1          1   Data Direction for Port C Bit 1
DDRC.DDC0          0   Data Direction for Port C Bit 0
PORTD             0x1008   PORTD I_O Port D
PORTD.PD5          5   Port D Data Bit 5
PORTD.PD4          4   Port D Data Bit 4
PORTD.PD3          3   Port D Data Bit 3
PORTD.PD2          2   Port D Data Bit 2
PORTD.PD1          1   Port D Data Bit 1
PORTD.PD0          0   Port D Data Bit 0
DDRD              0x1009   DDRD Data Direction for Port D
DDRD.DDD5          5   Data Direction for Port D Bit 5
DDRD.DDD4          4   Data Direction for Port D Bit 4
DDRD.DDD3          3   Data Direction for Port D Bit 3
DDRD.DDD2          2   Data Direction for Port D Bit 2
DDRD.DDD1          1   Data Direction for Port D Bit 1
DDRD.DDD0          0   Data Direction for Port D Bit 0
PORTE             0x100A   PORTE I_O Port E
PORTE.PE7          7   Port E Data Bit 7
PORTE.PE6          6   Port E Data Bit 6
PORTE.PE5          5   Port E Data Bit 5
PORTE.PE4          4   Port E Data Bit 4
PORTE.PE3          3   Port E Data Bit 3
PORTE.PE2          2   Port E Data Bit 2
PORTE.PE1          1   Port E Data Bit 1
PORTE.PE0          0   Port E Data Bit 0
CFORC             0x100B   CFORC Compare Force Register
CFORC.FOC1         7   Force Output Comparison 1
CFORC.FOC2         6   Force Output Comparison 2
CFORC.FOC3         5   Force Output Comparison 3
CFORC.FOC4         4   Force Output Comparison 4
CFORC.FOC5         3   Force Output Comparison 5
CFORC.FOC6         2   Force Output Comparison 6
CFORC.FOC7         1   Force Output Comparison 7
OC1M              0x100C   OC1M OC1 Action Mask Register
OC1M.OC1M7         7   Output Compare Masks 7
OC1M.OC1M6         6   Output Compare Masks 6
OC1M.OC1M5         5   Output Compare Masks 5
OC1M.OC1M4         4   Output Compare Masks 4
OC1M.OC1M3         3   Output Compare Masks 3
OC1D              0x100D   OC1D OC1 Action Data Register
OC1D.OC1D7         7   Output Compare Data 7
OC1D.OC1D6         6   Output Compare Data 6
OC1D.OC1D5         5   Output Compare Data 5
OC1D.OC1D4         4   Output Compare Data 4
OC1D.OC1D3         3   Output Compare Data 3
TCNT1H            0x100E   TCNT1H Timer Counter Register 1 H
TCNT1L            0x100F   TCNT1L Timer Counter Register 1 L
TIC1H             0x1010   TIC1H Input Capture 1 Register H
TIC1L             0x1011   TIC1L Input Capture 1 Register L
TIC2H             0x1012   TIC2H Input Capture 2 Register H
TIC2L             0x1013   TIC2L Input Capture 2 Register L
TIC3H             0x1014   TIC3H Input Capture 3 Register H
TIC3L             0x1015   TIC3L Input Capture 3 Register L
TOC1H             0x1016   TOC1H Output Compare 1 Register H
TOC1L             0x1017   TOC1L Output Compare 1 Register L
TOC2H             0x1018   TOC2H Output Compare 2 Register H
TOC2L             0x1019   TOC2L Output Compare 2 Register L
TOC3H             0x101A   TOC3H Output Compare 3 Register H
TOC3L             0x101B   TOC3L Output Compare 3 Register L
TOC4H             0x101C   TOC4H Output Compare 4 Register H
TOC4L             0x101D   TOC4L Output Compare 4 Register L
TO5I4H            0x101E   TO5I4H Output Compare 5_Input Capture 4 Register H
TO5I4L            0x101F   TO5I4L Output Compare 5_Input Capture 4 Register L
TCTL1             0x1020   TCTL1 Timer Control Register 1
TCTL1.OM2          7   Output Mode 2 
TCTL1.OL2          6   Output Level 2
TCTL1.OM3          5   Output Mode 3 
TCTL1.OL3          4   Output Level 3
TCTL1.OM4          3   Output Mode 4 
TCTL1.OL4          2   Output Level 4
TCTL1.OM5          1   Output Mode 5 
TCTL1.OL5          0   Output Level 5
TCTL2             0x1021   TCTL2 Timer Control Register 2
TCTL2.EDG4B        7   EDG4B Input Capture Edge Control
TCTL2.EDG4A        6   EDG4A Input Capture Edge Control
TCTL2.EDG1B        5   EDG1B Input Capture Edge Control
TCTL2.EDG1A        4   EDG1A Input Capture Edge Control
TCTL2.EDG2B        3   EDG2B Input Capture Edge Control
TCTL2.EDG2A        2   EDG2A Input Capture Edge Control
TCTL2.EDG3B        1   EDG3B Input Capture Edge Control
TCTL2.EDG3A        0   EDG3A Input Capture Edge Control
TMSK1             0x1022   TMSK1 Main Timer Interrupt Mask Register 1
TMSK1.OC1I         7   Output Compare 1 Interrupt Enable
TMSK1.OC2I         6   Output Compare 2 Interrupt Enable
TMSK1.OC3I         5   Output Compare 3 Interrupt Enable
TMSK1.OC4I         4   Output Compare 4 Interrupt Enable
TMSK1.4_5I         3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I         2   Input Capture 1 Interrupt Enable
TMSK1.IC2I         1   Input Capture 2 Interrupt Enable
TMSK1.IC3I         0   Input Capture 3 Interrupt Enable
TFLG1             0x1023   TFLG1 Main Timer Interrupt Flag Register 1
TFLG1.OC1F         7   Output Compare 1 Flag                
TFLG1.OC2F         6   Output Compare 2 Flag                
TFLG1.OC3F         5   Output Compare 3 Flag                
TFLG1.OC4F         4   Output Compare 4 Flag                
TFLG1.4_5F         3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F         2   Input Capture 1 Flag                 
TFLG1.IC2F         1   Input Capture 2 Flag                 
TFLG1.IC3F         0   Input Capture 3 Flag                 
TMSK2             0x1024   TMSK2 Misc. Timer Interrupt Mask Register 2
TMSK2.TO1I         7   Timer Overflow 1 Interrupt Enable
TMSK2.RTII         6   RTI Interrupt Enable
TMSK2.PAOVI        5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII         4   Pulse Accumulator Input Interrupt Enable
TMSK2.TO2I         3   Timer Overflow 2 Interrupt Enable
TMSK2.5_6I         2   Input Capture 5/Output Compare 6 Interrupt Enable
TMSK2.6_7I         1   Input Capture 6/Output Compare 7 Interrupt Enable
TFLG2             0x1025   TFLG2 Misc. Timer Interrupt Flag Register 2
TFLG2.TO1F         7   Timer Overflow 1 Flag
TFLG2.RTIF         6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF        5   Pulse Accumulator Overflow Flag
TFLG2.PAIF         4   Pulse Accumulator Input Edge Flag
TFLG2.TO2F         3   Timer Overflow 2 Flag
TFLG2.5_6F         2   Input Capture 5/Output Compare 6 Flag
TFLG2.6_7F         1   Input Capture 6/Output Compare 7 Flag
PACTL             0x1026   PACTL Pulse Accumulator Control Register
PACTL.PAEN         6   Pulse Accumulator System Enable
PACTL.PAMOD        5   Pulse Accumulator Mode         
PACTL.PEDGE        4   Pulse Accumulator Edge Control 
PACTL.I4_O5        3   Input Capture 4/Output Compare 
PACTL.RTR2         2   RTI Interrupt Rate Select 2
PACTL.RTR1         1   RTI Interrupt Rate Select 1
PACTL.RTR0         0   RTI Interrupt Rate Select 0
PACNT             0x1027   PACNT Pulse Accumulator Count Register
SPCR              0x1028   SPCR SPI Control Register
SPCR.SPIE          7   Serial Peripheral Interrupt Enable
SPCR.SPE           6   Serial Peripheral System Enable   
SPCR.DWOM          5   Port D Wired-OR Mode              
SPCR.MSTR          4   Master Mode Select                
SPCR.CPOL          3   Clock Polarity                    
SPCR.CPHA          2   Clock Phase                       
SPCR.SPR1          1   SPI Clock Rate Selects 1          
SPCR.SPR0          0   SPI Clock Rate Selects 0          
SPSR              0x1029   SPSR SPI Status Register
SPSR.SPIF          7   SPI Interrupt Complete Flag
SPSR.WCOL          6   Write Collision            
SPSR.MODF          4   Mode Fault                 
SPDAT             0x102A   SPDAT SPI Data Register
BAUD              0x102B   BAUD SCI Baud Rate Control
BAUD.TCLR          7   Clear Baud Rate Counters (Test)  
BAUD.SCP1          5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0          4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB          3   SCI Receive Baud Rate Clock Test
BAUD.SCR2          2   SCI Baud Rate Selects 2          
BAUD.SCR1          1   SCI Baud Rate Selects 1          
BAUD.SCR0          0   SCI Baud Rate Selects 0          
SCCR1             0x102C   SCCR1 SCI Control Register 1
SCCR1.R8           7   Receive Data Bit 8            
SCCR1.T8           6   Transmit Data Bit 8           
SCCR1.M            4   Mode (Select Character Format)
SCCR1.WAKE         3   Wakeup by Address Mark/Idle   
SCCR2             0x102D   SCCR2 SCI Control Register 2
SCCR2.TIE          7   Transmit Interrupt Enable         
SCCR2.TCIE         6   Transmit Complete Interrupt Enable
SCCR2.RIE          5   Receiver Interrupt Enable         
SCCR2.ILIE         4   Idle-Line Interrupt Enable        
SCCR2.TE           3   Transmitter Enable                
SCCR2.RE           2   Receiver Enable                   
SCCR2.RWU          1   Receiver Wakeup Control           
SCCR2.SBK          0   Send Break                        
SCSR              0x102E   SCSR SCI Status Register
SCSR.TDRE          7   Transmit Data Register Empty Flag
SCSR.TC            6   Transmit Complete Flag           
SCSR.RDRF          5   Receive Data Register Full Flag  
SCSR.IDLE          4   Idle Line Detected Flag          
SCSR.OR            3   Overrun Error Flag               
SCSR.NF            2   Noise Error Flag                 
SCSR.FE            1   Framing Error                    
SCDAT             0x102F   SCDAT SCI Data (Read RDR, Write TDR)
ADCTL             0x1030   ADCTL A_D Control Register
ADCTL.CCF          7   Conversions Complete Flag
ADCTL.CONV8        6   Convert 8/Convert 4 Select Bit
ADCTL.SCAN         5   Continuous Scan Control
ADCTL.MULT         4   Multiple Channel/Single Channel Control
ADCTL.CD           3   Channel Select Bits D
ADCTL.CC           2   Channel Select Bits C
ADCTL.CB           1   Channel Select Bits B
ADCTL.CA           0   Channel Select Bits A
PORTJ             0x1031   PORTJ I_O Port J
PORTJ.PJ3          3   Port J Data Bit 3
PORTJ.PJ2          2   Port J Data Bit 2
PORTJ.PJ1          1   Port J Data Bit 1
PORTJ.PJ0          0   Port J Data Bit 0
DDRJ              0x1032   DDRJ Data Direction for Port J
DDRJ.DDJ3          3   Data Direction for Port J Bit 3
DDRJ.DDJ2          2   Data Direction for Port J Bit 2
DDRJ.DDJ1          1   Data Direction for Port J Bit 1
DDRJ.DDJ0          0   Data Direction for Port J Bit 0
PORTH             0x1033   PORTH I_O Port H
PORTH.PH7          7   Port H Data Bit 7
PORTH.PH6          6   Port H Data Bit 6
PORTH.PH5          5   Port H Data Bit 5
PORTH.PH4          4   Port H Data Bit 4
PORTH.PH3          3   Port H Data Bit 3
PORTH.PH2          2   Port H Data Bit 2
PORTH.PH1          1   Port H Data Bit 1
PORTH.PH0          0   Port H Data Bit 0
DDRH              0x1034   DDRH Data Direction for Port H
DDRH.DDH7          7   Data Direction for Port C Bit 7
DDRH.DDH6          6   Data Direction for Port C Bit 6
DDRH.DDH5          5   Data Direction for Port C Bit 5
DDRH.DDH4          4   Data Direction for Port C Bit 4
DDRH.DDH3          3   Data Direction for Port C Bit 3
DDRH.DDH2          2   Data Direction for Port C Bit 2
DDRH.DDH1          1   Data Direction for Port C Bit 1
DDRH.DDH0          0   Data Direction for Port C Bit 0
RESERV1035        0x1035   RESERVED
RESERV1036        0x1036   RESERVED
RESERV1037        0x1037   RESERVED
OPT2              0x1038   OPT2 System Configuration Options 2 Reg.
OPT2.GWOM          7   Port G Wired-OR Mode
OPT2.CWOM          6   Port C Wired-OR Mode
OPT2.IRV           4   Internal Read Visibility
OPT2.MRDY          1   Memory Ready Enable
OPT2.NHALT         0   Enable Halt Function
OPTION            0x1039   OPTION System Configuration Options
OPTION.ADPU        7   A/D Power Up
OPTION.CSEL        6   Clock Select
OPTION.IRQE        5   IRQ Select Edge Sensitive Only
OPTION.DLY         4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME         3   Clock Monitor Enable
OPTION.CR1         1   COP Timer Rate select bits 1
OPTION.CR0         0   COP Timer Rate select bits 0
COPRST            0x103A   COPRST Arm_Reset COP Timer Circuitry
RESERV103B        0x103B   RESERVED
HPRIO             0x103C   HPRIO Highest Priority I-terrupt and Misc.
HPRIO.RBOOT        7   Read Bootstrap ROM
HPRIO.SMOD         6   Special Mode Select
HPRIO.MDA          5   Mode Select A
HPRIO.PSEL4        4   Priority Select Bits 4
HPRIO.PSEL3        3   Priority Select Bits 3
HPRIO.PSEL2        2   Priority Select Bits 2
HPRIO.PSEL1        1   Priority Select Bits 1
HPRIO.PSEL0        0   Priority Select Bits 0
INIT              0x103D   INIT RAM and I_O Mapping Register
INIT.RAM3          7   RAM Map Position 3
INIT.RAM2          6   RAM Map Position 2
INIT.RAM1          5   RAM Map Position 1
INIT.RAM0          4   RAM Map Position 0
INIT.REG3          3   Register Block Map Position 3
INIT.REG2          2   Register Block Map Position 2
INIT.REG1          1   Register Block Map Position 1
INIT.REG0          0   Register Block Map Position 0
TEST1             0x103E   TEST1 Factory Test Control Register
TEST1.TILOP        7   Test Illegal Opcode
TEST1.TPWSL        6   Pulse Width Modulation Scaled Clock
TEST1.OCCR         5   Output Condition Code Register Status to Timer Port
TEST1.CBYP1        4   Timer Counter 1 Divider Chain By-pass
TEST1.DISR         3   Disable Resets from COP and Clock Monitor
TEST1.FCM          2   Force Clock Monitor Failure
TEST1.FCOP         1   Force COP Watchdog Failure
TEST1.CBYP2        0   Timer Counter 2 Chain By-pass
CONFIG            0x103F   CONFIG COP and ROM Enables
CONFIG.NOCOP       2   COP System Disable
CONFIG.ROMON       1   ROM Enable
ADR1H             0x1040   ADR1H A_D Result Register 1 H
ADR1L             0x1041   ADR1L A_D Result Register 1 L
ADR2H             0x1042   ADR2H A_D Result Register 2 H
ADR2L             0x1043   ADR2L A_D Result Register 2 L
ADR3H             0x1044   ADR3H A_D Result Register 3 H
ADR3L             0x1045   ADR3L A_D Result Register 3 L
ADR4H             0x1046   ADR4H A_D Result Register 4 H
ADR4L             0x1047   ADR4L A_D Result Register 4 L
ADR5H             0x1048   ADR5H A_D Result Register 5 H
ADR5L             0x1049   ADR5L A_D Result Register 5 L
ADR6H             0x104A   ADR6 A_D Result Register 6 H
ADR6L             0x104B   ADR6 A_D Result Register 6 L
ADR7H             0x104C   ADR7H A_D Result Register 7 H
ADR7L             0x104D   ADR7L A_D Result Register 7 L
ADR8H             0x104E   ADR8H A_D Result Register 8 H
ADR8L             0x104F   ADR8L A_D Result Register 8 L
TCTL3             0x1050   TCTL3 Timer Control Register 3
TCTL3.EDG5B        7   Input Capture Edge Control 5B
TCTL3.EDG5A        6   Input Capture Edge Control 5A
TCTL3.EDG6B        5   Input Capture Edge Control 6B
TCTL3.EDG6A        4   Input Capture Edge Control 6A
TCTL3.OM6          3   Output Mode 6
TCTL3.OL6          2   Output Level 6
TCTL3.OM7          1   Output Mode 7
TCTL3.OL7          0   Output Level 7
TCTL4             0x1051   TCTL4 Timer Control Register 4
TCTL4.CT2SP        7   Timer Counter 2 Stop (used to facilitate testing)
TCTL4.CT1SP        6   Timer Counter 1 Stop (used to facilitate testing)
TCTL4.I5_O6        1   Configure TO6I5 Register for Input Capture or Output Compare
TCTL4.I6_O7        0   Configure TO7I6 Register for Input Capture or Output Compare
TCNT2H            0x1052   TCNT2H Timer Counter Register 2 H
TCNT2L            0x1053   TCNT2L Timer Counter Register 2 L
TO6I5H            0x1054   TO6I5H Output Compare 6_Input Capture 5 Register H
TO6I5L            0x1055   TO6I5L Output Compare 6_Input Capture 5 Register L
TO7I6H            0x1056   TO7I6H Output Compare 7_Input Capture 6 Register H
TO7I6L            0x1057   TO7I6L Output Compare 7_Input Capture 6 Register L
TPRE              0x1058   TPRE Timer Prescaler Register
TPRE.TEDGB         7   Timer External Clock Edge Select B
TPRE.TEDGA         6   Timer External Clock Edge Select A
TPRE.PR2B          5   Timer Prescaler Select 2B
TPRE.PR2A          4   Timer Prescaler Select 2A
TPRE.PR1B          1   Timer Prescaler Select 1B
TPRE.PR1A          0   Timer Prescaler Select 1A
RESERV1059        0x1059   RESERVED
RESERV105A        0x105A   RESERVED
RESERV105B        0x105B   RESERVED
RESERV105C        0x105C   RESERVED
RESERV105D        0x105D   RESERVED
RESERV105E        0x105E   RESERVED
RESERV105F        0x105F   RESERVED
PWCLK             0x1060   PWCLK PWM Timer Clock Select
PWCLK.CON34        7   Concatenate channels 3 and 4
PWCLK.CON12        6   Concatenate channels 1 and 2
PWCLK.PCKA2        5   Prescaler for clock A BIT 2
PWCLK.PCKA1        4   Prescaler for clock A BIT 1
PWCLK.PCKB3        2   Prescaler for clock B BIT 3
PWCLK.PCKB2        1   Prescaler for clock B BIT 2
PWCLK.PCKB1        0   Prescaler for clock B BIT 1
PWPOL             0x1061   PWPOL PWM Timer Polarity
PWPOL.PCLK4        7   Pulse Width Channel 4 Clock Select
PWPOL.PCLK3        6   Pulse Width Channel 3 Clock Select
PWPOL.PCLK2        5   Pulse Width Channel 2 Clock Select
PWPOL.PCLK1        4   Pulse Width Channel 1 Clock Select
PWPOL.PPOL4        3   Pulse Width Channel 4 Polarity
PWPOL.PPOL3        2   Pulse Width Channel 3 Polarity
PWPOL.PPOL2        1   Pulse Width Channel 2 Polarity
PWPOL.PPOL1        0   Pulse Width Channel 1 Polarity
PWSCAL            0x1062   PWSCAL PWM Timer Prescaler
PWEN              0x1063   PWEN PWM Timer Enable
PWEN.PWEN4         3   Pulse Width Channel 4 Enable
PWEN.PWEN3         2   Pulse Width Channel 3 Enable
PWEN.PWEN2         1   Pulse Width Channel 2 Enable
PWEN.PWEN1         0   Pulse Width Channel 1 Enable
PWCNT1            0x1064   PWCNT1 PWM Timer Counter 1
PWCNT2            0x1065   PWCNT2 PWM Timer Counter 2
PWCNT3            0x1066   PWCNT3 PWM Timer Counter 3
PWCNT4            0x1067   PWCNT4 PWM Timer Counter 4
PWPER1            0x1068   PWPER1 PWM Timer Period 1
PWPER2            0x1069   PWPER2 PWM Timer Period 2
PWPER3            0x106A   PWPER3 PWM Timer Period 3
PWPER4            0x106B   PWPER4 PWM Timer Period 4
PWDTY1            0x106C   PWDTY1 PWM Timer Duty 1
PWDTY2            0x106D   PWDTY2 PWM Timer Duty 2
PWDTY3            0x106E   PWDTY3 PWM Timer Duty 3
PWDTY4            0x106F   PWDTY4 PWM Timer Duty 4
EVCLK             0x1070   EVCLK Event Counter Clock Select
EVCLK.EVMDB        5   Event Counter Mode bits B
EVCLK.EVMDA        4   Event Counter Mode bits A
EVCLK.EVCKC        2   Event Counter Prescaler bits C
EVCLK.EVCKB        1   Event Counter Prescaler bits B
EVCLK.EVCKA        0   Event Counter Prescaler bits A
EVCTL            0x1071    EVCTL Event Counter Control Register                 
EVCTL.EVOEN       7   Event Output Enable (Port H, bit 6)
EVCTL.EVPOL       6   Event Output Polarity
EVCTL.EVI2C       5   Event Input Select 2 C (EVI2)
EVCTL.EVI2B       4   Event Input Select 2 B (EVI2)
EVCTL.EVI2A       3   Event Input Select 2 A (EVI2)
EVCTL.EVI1C       2   Event Input Select 1 C (EVI1)
EVCTL.EVI1B       1   Event Input Select 1 B (EVI1)
EVCTL.EVI1A       0   Event Input Select 1 A (EVI1)
EVMSK            0x1072    EVMSK Event Counter Interrupt Mask Register                
EVMSK.EVCEN       7   Event Counters Enable
EVMSK.EV2I        1   Event 2 Interrupt Enable
EVMSK.EV1I        0   Event 1 Interrupt Enable
EVFLG            0x1073    EVFLG Event Counter Interrupt Flag Register                
EVFLG.EV2F        1   Event Interrupt 2 Flag
EVFLG.EV1F        0   Event Interrupt 1 Flag
EVCNT1           0x1074    EVCNT1 Event Counter Count Register 1
EVCNT2           0x1075    EVCNT2 Event Counter Count Register 2
ECMP1A           0x1076    ECMP1A Event Counter Compare Register 1A
ECMP2A           0x1077    ECMP2A Event Counter Compare Register 2A
ECMP1B           0x1078    ECMP1B Event Counter Compare Register 1B
ECMP2B           0x1079    ECMP2B Event Counter Compare Register 2B
RESERV107A       0x107A    RESERVED
RESERV107B       0x107B    RESERVED
RESERV107C       0x107C    RESERVED
RESERV107D       0x107D    RESERVED
RESERV107E       0x107E    RESERVED
RESERV107F       0x107F    RESERVED
RESERVFFC0       0xFFC0    RESERVED
RESERVFFC1       0xFFC1    RESERVED
RESERVFFC2       0xFFC2    RESERVED
RESERVFFC3       0xFFC3    RESERVED
RESERVFFC4       0xFFC4    RESERVED
RESERVFFC5       0xFFC5    RESERVED
RESERVFFC6       0xFFC6    RESERVED
RESERVFFC7       0xFFC7    RESERVED
RESERVFFC8       0xFFC8    RESERVED
RESERVFFC9       0xFFC9    RESERVED
RESERVFFCA       0xFFCA    RESERVED
RESERVFFCB       0xFFCB    RESERVED


.68HC11K0
;M68HC11K/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11K0&nodeId=01M98635

; RAM=768
; ROM=0
; EPROM=0
; EEPROM=0

; MEMORY MAP


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select Bit 1
TMSK2.PR0       0   Timer Prescaler Select Bit 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
; EPROG          0x002B    EPROM Programming Control Register (Present only in EPROM (711) devices)
; EPROG.ELAT      5   EPROM Latch Control Bit
; EPROG.EXCOL     4   Select Extra Columns Bit
; EPROG.EXROW     3   Select Extra Rows Bit
; EPROG.EPGM      0   EPROM Programming Enable Bit
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
PGAR           0x002D    Port G Assignment Register
PGAR.PGAR5      5   Port G Pin Assignment Bit 5
PGAR.PGAR4      4   Port G Pin Assignment Bit 4
PGAR.PGAR3      3   Port G Pin Assignment Bit 3
PGAR.PGAR2      2   Port G Pin Assignment Bit 2
PGAR.PGAR1      1   Port G Pin Assignment Bit 1
PGAR.PGAR0      0   Port G Pin Assignment Bit 0
OPT3           0x002E    System Configuration Options 3 Register (Not available on M68HC11K4 devices)
OPT3.SM         6   Slow-Mode Enable Bit
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG Bit
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.STRCH      5   Stretch External Accesses Bit (Not available on M68HC11KS devices)
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode                                
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM Address Mapping Control Bit
CONFIG.CLKX     5   XOUT Clock Enable Bit
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   RAM and EPROM Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/PROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
MMSIZ          0x0056    Memory Mapping Size Register (Not for M68HC11KS)
MMSIZ.MXGS2     7   Memory Expansion Select for GPCS 2 Bit
MMSIZ.MXGS1     6   Memory Expansion Select for GPCS 1 Bit
MMSIZ.W2SZ1     5   Window 2 Size Bit 1
MMSIZ.W2SZ0     4   Window 2 Size Bit 0
MMSIZ.W1SZ1     1   Window 1 Size Bit 1
MMSIZ.W1SZ0     0   Window 1 Size Bit 0
MMWBR          0x0057    Memory Mapping Window Base Register (Not for M68HC11KS)
MMWBR.W2A15     7   Window 2 Base Address Bit 5
MMWBR.W2A14     6   Window 2 Base Address Bit 4
MMWBR.W2A13     5   Window 2 Base Address Bit 3
MMWBR.W1A15     3   Window Base 1 Address Bit 5
MMWBR.W1A14     2   Window Base 1 Address Bit 4
MMWBR.W1A13     1   Window Base 1 Address Bit 3
MM1CR          0x0058    Memory Mapping Window 1 Control Register (Not for M68HC11KS)
MM1CR.X1A18     6   Memory Mapping Window 1 Expansion Address Line Select Bit 18
MM1CR.X1A17     5   Memory Mapping Window 1 Expansion Address Line Select Bit 17
MM1CR.X1A16     4   Memory Mapping Window 1 Expansion Address Line Select Bit 16
MM1CR.X1A15     3   Memory Mapping Window 1 Expansion Address Line Select Bit 15
MM1CR.X1A14     2   Memory Mapping Window 1 Expansion Address Line Select Bit 14
MM1CR.X1A13     1   Memory Mapping Window 1 Expansion Address Line Select Bit 13
MM2CR          0x0059    Memory Mapping Window 2 Control Register (Not for M68HC11KS)
MM2CR.X2A18     6   Memory Mapping Window 2 Expansion Address Line Select Bit 18
MM2CR.X2A17     5   Memory Mapping Window 2 Expansion Address Line Select Bit 17
MM2CR.X2A16     4   Memory Mapping Window 2 Expansion Address Line Select Bit 16
MM2CR.X2A15     3   Memory Mapping Window 2 Expansion Address Line Select Bit 15
MM2CR.X2A14     2   Memory Mapping Window 2 Expansion Address Line Select Bit 14
MM2CR.X2A13     1   Memory Mapping Window 2 Expansion Address Line Select Bit 13
CSCSTR         0x005A    Chip Select Clock Stretch Register (Not for M68HC11KS)
CSCSTR.IOSA     7   CSIO Stretch Select Bit A
CSCSTR.IOSB     6   CSIO Stretch Select Bit B
CSCSTR.GP1SA    5   CSGP1 Stretch Select Bit A
CSCSTR.GP1SB    4   CSGP1 Stretch Select Bit B
CSCSTR.GP2SA    3   CSGP2 Stretch Select Bit A
CSCSTR.GP2SB    2   CSGP2 Stretch Select Bit B
CSCSTR.PCSA     1   CSPROG Stretch Select Bit A
CSCSTR.PCSB     0   CSPROG Stretch Select Bit B
CSCTL          0x005B    Chip Select Control Register (Not for M68HC11KS)
CSCTL.IOEN      7   I/O Chip-Select Enable Bit
CSCTL.IOPL      6   I/O Chip-Select Polarity Select Bit
CSCTL.IOCSA     5   I/O Chip-Select Address Valid Bit
CSCTL.IOSZ      4   I/O Chip-Select Size Select Bit
CSCTL.GCSPR     3   General-Purpose Chip Select Priority Bit
CSCTL.PCSEN     2   Program Chip Select Enable Bit
CSCTL.PCSZA     1   Program Chip Select Size A Bit
CSCTL.PCSZB     0   Program Chip Select Size B Bit
GPCS1A         0x005C    General-Purpose Chip Select 1 Address Register (Not for M68HC11KS)
GPCS1A.G1A18    7   General-Purpose Chip Select 1 Address Bit 18
GPCS1A.G1A17    6   General-Purpose Chip Select 1 Address Bit 17
GPCS1A.G1A16    5   General-Purpose Chip Select 1 Address Bit 16
GPCS1A.G1A15    4   General-Purpose Chip Select 1 Address Bit 15
GPCS1A.G1A14    3   General-Purpose Chip Select 1 Address Bit 14
GPCS1A.G1A13    2   General-Purpose Chip Select 1 Address Bit 13
GPCS1A.G1A12    1   General-Purpose Chip Select 1 Address Bit 12
GPCS1A.G1A11    0   General-Purpose Chip Select 1 Address Bit 11
GPCS1C         0x005D    General-Purpose Chip Select 1 Control Register (Not for M68HC11KS)
GPCS1C.G1DG2    7   GPCS 1 Drives GPCS 2 Bit
GPCS1C.G1DPC    6   General-Purpose Chip Select 1 Drives Program Chip Select Bit
GPCS1C.G1POL    5   General-Purpose Chip Select 1 Polarity Select Bit
GPCS1C.G1AV     4   General-Purpose Chip Select 1 Address Valid Select Bit
GPCS1C.G1SZA    3   General-Purpose Chip Select 1 Size Bit A
GPCS1C.G1SZB    2   General-Purpose Chip Select 1 Size Bit B
GPCS1C.G1SZC    1   General-Purpose Chip Select 1 Size Bit C
GPCS1C.G1SZD    0   General-Purpose Chip Select 1 Size Bit D
GPCS2A         0x005E    General-Purpose Chip Select 2 Address Register (Not for M68HC11KS)
GPCS2A.G2A18    7   General-Purpose Chip Select 2 Address Bit 18
GPCS2A.G2A17    6   General-Purpose Chip Select 2 Address Bit 17
GPCS2A.G2A16    5   General-Purpose Chip Select 2 Address Bit 16
GPCS2A.G2A15    4   General-Purpose Chip Select 2 Address Bit 15
GPCS2A.G2A14    3   General-Purpose Chip Select 2 Address Bit 14
GPCS2A.G2A13    2   General-Purpose Chip Select 2 Address Bit 13
GPCS2A.G2A12    1   General-Purpose Chip Select 2 Address Bit 12
GPCS2A.G2A11    0   General-Purpose Chip Select 2 Address Bit 11
GPCS2C         0x005F    General-Purpose Chip Select 2 Control Register (Not for M68HC11KS)
GPCS2C.G2DPC    6   General-Purpose Chip Select 2 Drives Program Chip Select Bit
GPCS2C.G2POL    5   General-Purpose Chip Select 2 Polarity Select Bit
GPCS2C.G2AV     4   General-Purpose Chip Select 2 Address Valid Select Bit
GPCS2C.G2SZA    3   General-Purpose Chip Select 2 Size Bit A
GPCS2C.G2SZB    2   General-Purpose Chip Select 2 Size Bit B
GPCS2C.G2SZC    1   General-Purpose Chip Select 2 Size Bit C
GPCS2C.G2SZD    0   General-Purpose Chip Select 2 Size Bit D
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH7       7   Port H Data Bit 7 (Not for M68HC11KS)
PORTH.PH6       6   Port H Data Bit 6 (Not for M68HC11KS)
PORTH.PH5       5   Port H Data Bit 5 (Not for M68HC11KS)
PORTH.PH4       4   Port H Data Bit 4 (Not for M68HC11KS)
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH7       7   Data Direction for Port H Bit 7 (Not for M68HC11KS)
DDRH.DDH6       6   Data Direction for Port H Bit 6 (Not for M68HC11KS)
DDRH.DDH5       5   Data Direction for Port H Bit 5 (Not for M68HC11KS)
DDRH.DDH4       4   Data Direction for Port H Bit 4 (Not for M68HC11KS)
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6 (Not for M68HC11KS)
PORTG.PG5       5   Port G Data Bit 5 (Not for M68HC11KS)
PORTG.PG4       4   Port G Data Bit 4 (Not for M68HC11KS)
PORTG.PG3       3   Port G Data Bit 3 (Not for M68HC11KS)
PORTG.PG2       2   Port G Data Bit 2 (Not for M68HC11KS)
PORTG.PG1       1   Port G Data Bit 1 (Not for M68HC11KS)
PORTG.PG0       0   Port G Data Bit 0 (Not for M68HC11KS)
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6 (Not for M68HC11KS)
DDRG.DDG5       5   Data Direction for Port G Bit 5 (Not for M68HC11KS)
DDRG.DDG4       4   Data Direction for Port G Bit 4 (Not for M68HC11KS)
DDRG.DDG3       3   Data Direction for Port G Bit 3 (Not for M68HC11KS)
DDRG.DDG2       2   Data Direction for Port G Bit 2 (Not for M68HC11KS)
DDRG.DDG1       1   Data Direction for Port G Bit 1 (Not for M68HC11KS)
DDRG.DDG0       0   Data Direction for Port G Bit 0 (Not for M68HC11KS)
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC11K1
; M68HC11K/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11K1&nodeId=01M98635
; M68HC11K.pdf

; RAM=768
; ROM=0
; EPROM=0
; EEPROM=640


; MEMORY MAP


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select Bit 1
TMSK2.PR0       0   Timer Prescaler Select Bit 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
PGAR           0x002D    Port G Assignment Register
PGAR.PGAR5      5   Port G Pin Assignment Bit 5
PGAR.PGAR4      4   Port G Pin Assignment Bit 4
PGAR.PGAR3      3   Port G Pin Assignment Bit 3
PGAR.PGAR2      2   Port G Pin Assignment Bit 2
PGAR.PGAR1      1   Port G Pin Assignment Bit 1
PGAR.PGAR0      0   Port G Pin Assignment Bit 0
OPT3           0x002E    System Configuration Options 3 Register
OPT3.SM         6   Slow-Mode Enable Bit
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG Bit
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.STRCH      5   Stretch External Accesses Bit (Not available on M68HC11KS devices)
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode                                
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM Address Mapping Control Bit
CONFIG.CLKX     5   XOUT Clock Enable Bit
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   RAM and EPROM Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/PROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
MMSIZ          0x0056    Memory Mapping Size Register
MMSIZ.MXGS2     7   Memory Expansion Select for GPCS 2 Bit
MMSIZ.MXGS1     6   Memory Expansion Select for GPCS 1 Bit
MMSIZ.W2SZ1     5   Window 2 Size Bit 1
MMSIZ.W2SZ0     4   Window 2 Size Bit 0
MMSIZ.W1SZ1     1   Window 1 Size Bit 1
MMSIZ.W1SZ0     0   Window 1 Size Bit 0
MMWBR          0x0057    Memory Mapping Window Base Register
MMWBR.W2A15     7   Window 2 Base Address Bit 5
MMWBR.W2A14     6   Window 2 Base Address Bit 4
MMWBR.W2A13     5   Window 2 Base Address Bit 3
MMWBR.W1A15     3   Window Base 1 Address Bit 5
MMWBR.W1A14     2   Window Base 1 Address Bit 4
MMWBR.W1A13     1   Window Base 1 Address Bit 3
MM1CR          0x0058    Memory Mapping Window 1 Control Register
MM1CR.X1A18     6   Memory Mapping Window 1 Expansion Address Line Select Bit 18
MM1CR.X1A17     5   Memory Mapping Window 1 Expansion Address Line Select Bit 17
MM1CR.X1A16     4   Memory Mapping Window 1 Expansion Address Line Select Bit 16
MM1CR.X1A15     3   Memory Mapping Window 1 Expansion Address Line Select Bit 15
MM1CR.X1A14     2   Memory Mapping Window 1 Expansion Address Line Select Bit 14
MM1CR.X1A13     1   Memory Mapping Window 1 Expansion Address Line Select Bit 13
MM2CR          0x0059    Memory Mapping Window 2 Control Register
MM2CR.X2A18     6   Memory Mapping Window 2 Expansion Address Line Select Bit 18
MM2CR.X2A17     5   Memory Mapping Window 2 Expansion Address Line Select Bit 17
MM2CR.X2A16     4   Memory Mapping Window 2 Expansion Address Line Select Bit 16
MM2CR.X2A15     3   Memory Mapping Window 2 Expansion Address Line Select Bit 15
MM2CR.X2A14     2   Memory Mapping Window 2 Expansion Address Line Select Bit 14
MM2CR.X2A13     1   Memory Mapping Window 2 Expansion Address Line Select Bit 13
CSCSTR         0x005A    Chip Select Clock Stretch Register
CSCSTR.IOSA     7   CSIO Stretch Select Bit A
CSCSTR.IOSB     6   CSIO Stretch Select Bit B
CSCSTR.GP1SA    5   CSGP1 Stretch Select Bit A
CSCSTR.GP1SB    4   CSGP1 Stretch Select Bit B
CSCSTR.GP2SA    3   CSGP2 Stretch Select Bit A
CSCSTR.GP2SB    2   CSGP2 Stretch Select Bit B
CSCSTR.PCSA     1   CSPROG Stretch Select Bit A
CSCSTR.PCSB     0   CSPROG Stretch Select Bit B
CSCTL          0x005B    Chip Select Control Register
CSCTL.IOEN      7   I/O Chip-Select Enable Bit
CSCTL.IOPL      6   I/O Chip-Select Polarity Select Bit
CSCTL.IOCSA     5   I/O Chip-Select Address Valid Bit
CSCTL.IOSZ      4   I/O Chip-Select Size Select Bit
CSCTL.GCSPR     3   General-Purpose Chip Select Priority Bit
CSCTL.PCSEN     2   Program Chip Select Enable Bit
CSCTL.PCSZA     1   Program Chip Select Size A Bit
CSCTL.PCSZB     0   Program Chip Select Size B Bit
GPCS1A         0x005C    General-Purpose Chip Select 1 Address Register
GPCS1A.G1A18    7   General-Purpose Chip Select 1 Address Bit 18
GPCS1A.G1A17    6   General-Purpose Chip Select 1 Address Bit 17
GPCS1A.G1A16    5   General-Purpose Chip Select 1 Address Bit 16
GPCS1A.G1A15    4   General-Purpose Chip Select 1 Address Bit 15
GPCS1A.G1A14    3   General-Purpose Chip Select 1 Address Bit 14
GPCS1A.G1A13    2   General-Purpose Chip Select 1 Address Bit 13
GPCS1A.G1A12    1   General-Purpose Chip Select 1 Address Bit 12
GPCS1A.G1A11    0   General-Purpose Chip Select 1 Address Bit 11
GPCS1C         0x005D    General-Purpose Chip Select 1 Control Register
GPCS1C.G1DG2    7   GPCS 1 Drives GPCS 2 Bit
GPCS1C.G1DPC    6   General-Purpose Chip Select 1 Drives Program Chip Select Bit
GPCS1C.G1POL    5   General-Purpose Chip Select 1 Polarity Select Bit
GPCS1C.G1AV     4   General-Purpose Chip Select 1 Address Valid Select Bit
GPCS1C.G1SZA    3   General-Purpose Chip Select 1 Size Bit A
GPCS1C.G1SZB    2   General-Purpose Chip Select 1 Size Bit B
GPCS1C.G1SZC    1   General-Purpose Chip Select 1 Size Bit C
GPCS1C.G1SZD    0   General-Purpose Chip Select 1 Size Bit D
GPCS2A         0x005E    General-Purpose Chip Select 2 Address Register
GPCS2A.G2A18    7   General-Purpose Chip Select 2 Address Bit 18
GPCS2A.G2A17    6   General-Purpose Chip Select 2 Address Bit 17
GPCS2A.G2A16    5   General-Purpose Chip Select 2 Address Bit 16
GPCS2A.G2A15    4   General-Purpose Chip Select 2 Address Bit 15
GPCS2A.G2A14    3   General-Purpose Chip Select 2 Address Bit 14
GPCS2A.G2A13    2   General-Purpose Chip Select 2 Address Bit 13
GPCS2A.G2A12    1   General-Purpose Chip Select 2 Address Bit 12
GPCS2A.G2A11    0   General-Purpose Chip Select 2 Address Bit 11
GPCS2C         0x005F    General-Purpose Chip Select 2 Control Register
GPCS2C.G2DPC    6   General-Purpose Chip Select 2 Drives Program Chip Select Bit
GPCS2C.G2POL    5   General-Purpose Chip Select 2 Polarity Select Bit
GPCS2C.G2AV     4   General-Purpose Chip Select 2 Address Valid Select Bit
GPCS2C.G2SZA    3   General-Purpose Chip Select 2 Size Bit A
GPCS2C.G2SZB    2   General-Purpose Chip Select 2 Size Bit B
GPCS2C.G2SZC    1   General-Purpose Chip Select 2 Size Bit C
GPCS2C.G2SZD    0   General-Purpose Chip Select 2 Size Bit D
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH7       7   Port H Data Bit 7
PORTH.PH6       6   Port H Data Bit 6
PORTH.PH5       5   Port H Data Bit 5
PORTH.PH4       4   Port H Data Bit 4
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH7       7   Data Direction for Port H Bit 7
DDRH.DDH6       6   Data Direction for Port H Bit 6
DDRH.DDH5       5   Data Direction for Port H Bit 5
DDRH.DDH4       4   Data Direction for Port H Bit 4
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6
PORTG.PG5       5   Port G Data Bit 5
PORTG.PG4       4   Port G Data Bit 4
PORTG.PG3       3   Port G Data Bit 3
PORTG.PG2       2   Port G Data Bit 2
PORTG.PG1       1   Port G Data Bit 1
PORTG.PG0       0   Port G Data Bit 0
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6
DDRG.DDG5       5   Data Direction for Port G Bit 5
DDRG.DDG4       4   Data Direction for Port G Bit 4
DDRG.DDG3       3   Data Direction for Port G Bit 3
DDRG.DDG2       2   Data Direction for Port G Bit 2
DDRG.DDG1       1   Data Direction for Port G Bit 1
DDRG.DDG0       0   Data Direction for Port G Bit 0
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC11K3
; M68HC11K/D  http://
; M68HC11K.pdf

; RAM=768
; ROM=24K
; EPROM=0
; EEPROM=0


; MEMORY MAP


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select Bit 1
TMSK2.PR0       0   Timer Prescaler Select Bit 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
PGAR           0x002D    Port G Assignment Register
PGAR.PGAR5      5   Port G Pin Assignment Bit 5
PGAR.PGAR4      4   Port G Pin Assignment Bit 4
PGAR.PGAR3      3   Port G Pin Assignment Bit 3
PGAR.PGAR2      2   Port G Pin Assignment Bit 2
PGAR.PGAR1      1   Port G Pin Assignment Bit 1
PGAR.PGAR0      0   Port G Pin Assignment Bit 0
OPT3           0x002E    System Configuration Options 3 Register
OPT3.SM         6   Slow-Mode Enable Bit
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG Bit
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.STRCH      5   Stretch External Accesses Bit (Not available on M68HC11KS devices)
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode                                
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM Address Mapping Control Bit
CONFIG.CLKX     5   XOUT Clock Enable Bit
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   RAM and EPROM Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/PROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
MMSIZ          0x0056    Memory Mapping Size Register
MMSIZ.MXGS2     7   Memory Expansion Select for GPCS 2 Bit
MMSIZ.MXGS1     6   Memory Expansion Select for GPCS 1 Bit
MMSIZ.W2SZ1     5   Window 2 Size Bit 1
MMSIZ.W2SZ0     4   Window 2 Size Bit 0
MMSIZ.W1SZ1     1   Window 1 Size Bit 1
MMSIZ.W1SZ0     0   Window 1 Size Bit 0
MMWBR          0x0057    Memory Mapping Window Base Register
MMWBR.W2A15     7   Window 2 Base Address Bit 5
MMWBR.W2A14     6   Window 2 Base Address Bit 4
MMWBR.W2A13     5   Window 2 Base Address Bit 3
MMWBR.W1A15     3   Window Base 1 Address Bit 5
MMWBR.W1A14     2   Window Base 1 Address Bit 4
MMWBR.W1A13     1   Window Base 1 Address Bit 3
MM1CR          0x0058    Memory Mapping Window 1 Control Register
MM1CR.X1A18     6   Memory Mapping Window 1 Expansion Address Line Select Bit 18
MM1CR.X1A17     5   Memory Mapping Window 1 Expansion Address Line Select Bit 17
MM1CR.X1A16     4   Memory Mapping Window 1 Expansion Address Line Select Bit 16
MM1CR.X1A15     3   Memory Mapping Window 1 Expansion Address Line Select Bit 15
MM1CR.X1A14     2   Memory Mapping Window 1 Expansion Address Line Select Bit 14
MM1CR.X1A13     1   Memory Mapping Window 1 Expansion Address Line Select Bit 13
MM2CR          0x0059    Memory Mapping Window 2 Control Register
MM2CR.X2A18     6   Memory Mapping Window 2 Expansion Address Line Select Bit 18
MM2CR.X2A17     5   Memory Mapping Window 2 Expansion Address Line Select Bit 17
MM2CR.X2A16     4   Memory Mapping Window 2 Expansion Address Line Select Bit 16
MM2CR.X2A15     3   Memory Mapping Window 2 Expansion Address Line Select Bit 15
MM2CR.X2A14     2   Memory Mapping Window 2 Expansion Address Line Select Bit 14
MM2CR.X2A13     1   Memory Mapping Window 2 Expansion Address Line Select Bit 13
CSCSTR         0x005A    Chip Select Clock Stretch Register
CSCSTR.IOSA     7   CSIO Stretch Select Bit A
CSCSTR.IOSB     6   CSIO Stretch Select Bit B
CSCSTR.GP1SA    5   CSGP1 Stretch Select Bit A
CSCSTR.GP1SB    4   CSGP1 Stretch Select Bit B
CSCSTR.GP2SA    3   CSGP2 Stretch Select Bit A
CSCSTR.GP2SB    2   CSGP2 Stretch Select Bit B
CSCSTR.PCSA     1   CSPROG Stretch Select Bit A
CSCSTR.PCSB     0   CSPROG Stretch Select Bit B
CSCTL          0x005B    Chip Select Control Register
CSCTL.IOEN      7   I/O Chip-Select Enable Bit
CSCTL.IOPL      6   I/O Chip-Select Polarity Select Bit
CSCTL.IOCSA     5   I/O Chip-Select Address Valid Bit
CSCTL.IOSZ      4   I/O Chip-Select Size Select Bit
CSCTL.GCSPR     3   General-Purpose Chip Select Priority Bit
CSCTL.PCSEN     2   Program Chip Select Enable Bit
CSCTL.PCSZA     1   Program Chip Select Size A Bit
CSCTL.PCSZB     0   Program Chip Select Size B Bit
GPCS1A         0x005C    General-Purpose Chip Select 1 Address Register
GPCS1A.G1A18    7   General-Purpose Chip Select 1 Address Bit 18
GPCS1A.G1A17    6   General-Purpose Chip Select 1 Address Bit 17
GPCS1A.G1A16    5   General-Purpose Chip Select 1 Address Bit 16
GPCS1A.G1A15    4   General-Purpose Chip Select 1 Address Bit 15
GPCS1A.G1A14    3   General-Purpose Chip Select 1 Address Bit 14
GPCS1A.G1A13    2   General-Purpose Chip Select 1 Address Bit 13
GPCS1A.G1A12    1   General-Purpose Chip Select 1 Address Bit 12
GPCS1A.G1A11    0   General-Purpose Chip Select 1 Address Bit 11
GPCS1C         0x005D    General-Purpose Chip Select 1 Control Register
GPCS1C.G1DG2    7   GPCS 1 Drives GPCS 2 Bit
GPCS1C.G1DPC    6   General-Purpose Chip Select 1 Drives Program Chip Select Bit
GPCS1C.G1POL    5   General-Purpose Chip Select 1 Polarity Select Bit
GPCS1C.G1AV     4   General-Purpose Chip Select 1 Address Valid Select Bit
GPCS1C.G1SZA    3   General-Purpose Chip Select 1 Size Bit A
GPCS1C.G1SZB    2   General-Purpose Chip Select 1 Size Bit B
GPCS1C.G1SZC    1   General-Purpose Chip Select 1 Size Bit C
GPCS1C.G1SZD    0   General-Purpose Chip Select 1 Size Bit D
GPCS2A         0x005E    General-Purpose Chip Select 2 Address Register
GPCS2A.G2A18    7   General-Purpose Chip Select 2 Address Bit 18
GPCS2A.G2A17    6   General-Purpose Chip Select 2 Address Bit 17
GPCS2A.G2A16    5   General-Purpose Chip Select 2 Address Bit 16
GPCS2A.G2A15    4   General-Purpose Chip Select 2 Address Bit 15
GPCS2A.G2A14    3   General-Purpose Chip Select 2 Address Bit 14
GPCS2A.G2A13    2   General-Purpose Chip Select 2 Address Bit 13
GPCS2A.G2A12    1   General-Purpose Chip Select 2 Address Bit 12
GPCS2A.G2A11    0   General-Purpose Chip Select 2 Address Bit 11
GPCS2C         0x005F    General-Purpose Chip Select 2 Control Register
GPCS2C.G2DPC    6   General-Purpose Chip Select 2 Drives Program Chip Select Bit
GPCS2C.G2POL    5   General-Purpose Chip Select 2 Polarity Select Bit
GPCS2C.G2AV     4   General-Purpose Chip Select 2 Address Valid Select Bit
GPCS2C.G2SZA    3   General-Purpose Chip Select 2 Size Bit A
GPCS2C.G2SZB    2   General-Purpose Chip Select 2 Size Bit B
GPCS2C.G2SZC    1   General-Purpose Chip Select 2 Size Bit C
GPCS2C.G2SZD    0   General-Purpose Chip Select 2 Size Bit D
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH7       7   Port H Data Bit 7
PORTH.PH6       6   Port H Data Bit 6
PORTH.PH5       5   Port H Data Bit 5
PORTH.PH4       4   Port H Data Bit 4
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH7       7   Data Direction for Port H Bit 7
DDRH.DDH6       6   Data Direction for Port H Bit 6
DDRH.DDH5       5   Data Direction for Port H Bit 5
DDRH.DDH4       4   Data Direction for Port H Bit 4
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6
PORTG.PG5       5   Port G Data Bit 5
PORTG.PG4       4   Port G Data Bit 4
PORTG.PG3       3   Port G Data Bit 3
PORTG.PG2       2   Port G Data Bit 2
PORTG.PG1       1   Port G Data Bit 1
PORTG.PG0       0   Port G Data Bit 0
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6
DDRG.DDG5       5   Data Direction for Port G Bit 5
DDRG.DDG4       4   Data Direction for Port G Bit 4
DDRG.DDG3       3   Data Direction for Port G Bit 3
DDRG.DDG2       2   Data Direction for Port G Bit 2
DDRG.DDG1       1   Data Direction for Port G Bit 1
DDRG.DDG0       0   Data Direction for Port G Bit 0
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC11K4
; M68HC11K/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11K4&nodeId=01M98635
; M68HC11K.pdf

; RAM=768
; ROM=24K
; EPROM=0
; EEPROM=640


; MEMORY MAP
area DATA FSR          0x0000:0x0080
area DATA RAM          0x0080:0x0380
area BSS  RESERVED     0x0380:0x0D80
area DATA EEPROM       0x0D80:0x1000
area BSS  RESERVED     0x1000:0xA000
area DATA ROM          0xA000:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select Bit 1
TMSK2.PR0       0   Timer Prescaler Select Bit 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
PGAR           0x002D    Port G Assignment Register
PGAR.PGAR5      5   Port G Pin Assignment Bit 5
PGAR.PGAR4      4   Port G Pin Assignment Bit 4
PGAR.PGAR3      3   Port G Pin Assignment Bit 3
PGAR.PGAR2      2   Port G Pin Assignment Bit 2
PGAR.PGAR1      1   Port G Pin Assignment Bit 1
PGAR.PGAR0      0   Port G Pin Assignment Bit 0
RESERV002E     0x002E    RESERVED
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG Bit
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.STRCH      5   Stretch External Accesses Bit
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode                                
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM Address Mapping Control Bit
CONFIG.CLKX     5   XOUT Clock Enable Bit
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   RAM and EPROM Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/PROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
MMSIZ          0x0056    Memory Mapping Size Register
MMSIZ.MXGS2     7   Memory Expansion Select for GPCS 2 Bit
MMSIZ.MXGS1     6   Memory Expansion Select for GPCS 1 Bit
MMSIZ.W2SZ1     5   Window 2 Size Bit 1
MMSIZ.W2SZ0     4   Window 2 Size Bit 0
MMSIZ.W1SZ1     1   Window 1 Size Bit 1
MMSIZ.W1SZ0     0   Window 1 Size Bit 0
MMWBR          0x0057    Memory Mapping Window Base Register
MMWBR.W2A15     7   Window 2 Base Address Bit 5
MMWBR.W2A14     6   Window 2 Base Address Bit 4
MMWBR.W2A13     5   Window 2 Base Address Bit 3
MMWBR.W1A15     3   Window Base 1 Address Bit 5
MMWBR.W1A14     2   Window Base 1 Address Bit 4
MMWBR.W1A13     1   Window Base 1 Address Bit 3
MM1CR          0x0058    Memory Mapping Window 1 Control Register
MM1CR.X1A18     6   Memory Mapping Window 1 Expansion Address Line Select Bit 18
MM1CR.X1A17     5   Memory Mapping Window 1 Expansion Address Line Select Bit 17
MM1CR.X1A16     4   Memory Mapping Window 1 Expansion Address Line Select Bit 16
MM1CR.X1A15     3   Memory Mapping Window 1 Expansion Address Line Select Bit 15
MM1CR.X1A14     2   Memory Mapping Window 1 Expansion Address Line Select Bit 14
MM1CR.X1A13     1   Memory Mapping Window 1 Expansion Address Line Select Bit 13
MM2CR          0x0059    Memory Mapping Window 2 Control Register
MM2CR.X2A18     6   Memory Mapping Window 2 Expansion Address Line Select Bit 18
MM2CR.X2A17     5   Memory Mapping Window 2 Expansion Address Line Select Bit 17
MM2CR.X2A16     4   Memory Mapping Window 2 Expansion Address Line Select Bit 16
MM2CR.X2A15     3   Memory Mapping Window 2 Expansion Address Line Select Bit 15
MM2CR.X2A14     2   Memory Mapping Window 2 Expansion Address Line Select Bit 14
MM2CR.X2A13     1   Memory Mapping Window 2 Expansion Address Line Select Bit 13
CSCSTR         0x005A    Chip Select Clock Stretch Register
CSCSTR.IOSA     7   CSIO Stretch Select Bit A
CSCSTR.IOSB     6   CSIO Stretch Select Bit B
CSCSTR.GP1SA    5   CSGP1 Stretch Select Bit A
CSCSTR.GP1SB    4   CSGP1 Stretch Select Bit B
CSCSTR.GP2SA    3   CSGP2 Stretch Select Bit A
CSCSTR.GP2SB    2   CSGP2 Stretch Select Bit B
CSCSTR.PCSA     1   CSPROG Stretch Select Bit A
CSCSTR.PCSB     0   CSPROG Stretch Select Bit B
CSCTL          0x005B    Chip Select Control Register
CSCTL.IOEN      7   I/O Chip-Select Enable Bit
CSCTL.IOPL      6   I/O Chip-Select Polarity Select Bit
CSCTL.IOCSA     5   I/O Chip-Select Address Valid Bit
CSCTL.IOSZ      4   I/O Chip-Select Size Select Bit
CSCTL.GCSPR     3   General-Purpose Chip Select Priority Bit
CSCTL.PCSEN     2   Program Chip Select Enable Bit
CSCTL.PCSZA     1   Program Chip Select Size A Bit
CSCTL.PCSZB     0   Program Chip Select Size B Bit
GPCS1A         0x005C    General-Purpose Chip Select 1 Address Register
GPCS1A.G1A18    7   General-Purpose Chip Select 1 Address Bit 18
GPCS1A.G1A17    6   General-Purpose Chip Select 1 Address Bit 17
GPCS1A.G1A16    5   General-Purpose Chip Select 1 Address Bit 16
GPCS1A.G1A15    4   General-Purpose Chip Select 1 Address Bit 15
GPCS1A.G1A14    3   General-Purpose Chip Select 1 Address Bit 14
GPCS1A.G1A13    2   General-Purpose Chip Select 1 Address Bit 13
GPCS1A.G1A12    1   General-Purpose Chip Select 1 Address Bit 12
GPCS1A.G1A11    0   General-Purpose Chip Select 1 Address Bit 11
GPCS1C         0x005D    General-Purpose Chip Select 1 Control Register
GPCS1C.G1DG2    7   GPCS 1 Drives GPCS 2 Bit
GPCS1C.G1DPC    6   General-Purpose Chip Select 1 Drives Program Chip Select Bit
GPCS1C.G1POL    5   General-Purpose Chip Select 1 Polarity Select Bit
GPCS1C.G1AV     4   General-Purpose Chip Select 1 Address Valid Select Bit
GPCS1C.G1SZA    3   General-Purpose Chip Select 1 Size Bit A
GPCS1C.G1SZB    2   General-Purpose Chip Select 1 Size Bit B
GPCS1C.G1SZC    1   General-Purpose Chip Select 1 Size Bit C
GPCS1C.G1SZD    0   General-Purpose Chip Select 1 Size Bit D
GPCS2A         0x005E    General-Purpose Chip Select 2 Address Register
GPCS2A.G2A18    7   General-Purpose Chip Select 2 Address Bit 18
GPCS2A.G2A17    6   General-Purpose Chip Select 2 Address Bit 17
GPCS2A.G2A16    5   General-Purpose Chip Select 2 Address Bit 16
GPCS2A.G2A15    4   General-Purpose Chip Select 2 Address Bit 15
GPCS2A.G2A14    3   General-Purpose Chip Select 2 Address Bit 14
GPCS2A.G2A13    2   General-Purpose Chip Select 2 Address Bit 13
GPCS2A.G2A12    1   General-Purpose Chip Select 2 Address Bit 12
GPCS2A.G2A11    0   General-Purpose Chip Select 2 Address Bit 11
GPCS2C         0x005F    General-Purpose Chip Select 2 Control Register
GPCS2C.G2DPC    6   General-Purpose Chip Select 2 Drives Program Chip Select Bit
GPCS2C.G2POL    5   General-Purpose Chip Select 2 Polarity Select Bit
GPCS2C.G2AV     4   General-Purpose Chip Select 2 Address Valid Select Bit
GPCS2C.G2SZA    3   General-Purpose Chip Select 2 Size Bit A
GPCS2C.G2SZB    2   General-Purpose Chip Select 2 Size Bit B
GPCS2C.G2SZC    1   General-Purpose Chip Select 2 Size Bit C
GPCS2C.G2SZD    0   General-Purpose Chip Select 2 Size Bit D
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH7       7   Port H Data Bit 7
PORTH.PH6       6   Port H Data Bit 6
PORTH.PH5       5   Port H Data Bit 5
PORTH.PH4       4   Port H Data Bit 4
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH7       7   Data Direction for Port H Bit 7
DDRH.DDH6       6   Data Direction for Port H Bit 6
DDRH.DDH5       5   Data Direction for Port H Bit 5
DDRH.DDH4       4   Data Direction for Port H Bit 4
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6
PORTG.PG5       5   Port G Data Bit 5
PORTG.PG4       4   Port G Data Bit 4
PORTG.PG3       3   Port G Data Bit 3
PORTG.PG2       2   Port G Data Bit 2
PORTG.PG1       1   Port G Data Bit 1
PORTG.PG0       0   Port G Data Bit 0
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6
DDRG.DDG5       5   Data Direction for Port G Bit 5
DDRG.DDG4       4   Data Direction for Port G Bit 4
DDRG.DDG3       3   Data Direction for Port G Bit 3
DDRG.DDG2       2   Data Direction for Port G Bit 2
DDRG.DDG1       1   Data Direction for Port G Bit 1
DDRG.DDG0       0   Data Direction for Port G Bit 0
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC11KA2
; M68HC11K/D  http://
; ka4.pdf

; RAM=1024
; ROM=32K
; EPROM=0
; EEPROM=640


; MEMORY MAP
area DATA FSR		0x0000:0x0080
area DATA RAM		0x0080:0x0480
area BSS  RESERVED      0x0480:0x0D80
area DATA EEPROM	0x0D80:0x1000
area BSS  RESERVED      0x1000:0x8000
area DATA ROM           0x8000:0xFFC0
area DATA USER_VEC	0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select 1
TMSK2.PR0       0   Timer Prescaler Select 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
RESERV002D     0x002D    RESERVED
RESERV002E     0x002E    RESERVED
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM/EPROM Mapping Control
CONFIG.CLKX     5   XOUT Clock Enable
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/EPROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
RESERV0055     0x0056    RESERVED
RESERV0055     0x0057    RESERVED
RESERV0055     0x0058    RESERVED
RESERV0055     0x0059    RESERVED
RESERV0055     0x005A    RESERVED
RESERV0055     0x005B    RESERVED
RESERV0055     0x005C    RESERVED
RESERV0055     0x005D    RESERVED
RESERV0055     0x005E    RESERVED
RESERV0055     0x005F    RESERVED
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register 
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register 
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register 
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register 
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1                             
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low 
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC11KA4
; MC68HC11KA4TS/D  http://
; ka4.pdf

; RAM=768
; ROM=24K
; EPROM=0
; EEPROM=640


; MEMORY MAP
area DATA FSR		0x0000:0x0080
area DATA RAM		0x0080:0x0380
area BSS  RESERVED      0x0380:0x0D80
area DATA EEPROM	0x0D80:0x1000
area BSS  RESERVED      0x1000:0xA000
area DATA ROM           0xA000:0xFFC0
area DATA USER_VEC	0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select 1
TMSK2.PR0       0   Timer Prescaler Select 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
RESERV002D     0x002D    RESERVED
RESERV002E     0x002E    RESERVED
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM/EPROM Mapping Control
CONFIG.CLKX     5   XOUT Clock Enable
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/EPROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
RESERV0055     0x0056    RESERVED
RESERV0055     0x0057    RESERVED
RESERV0055     0x0058    RESERVED
RESERV0055     0x0059    RESERVED
RESERV0055     0x005A    RESERVED
RESERV0055     0x005B    RESERVED
RESERV0055     0x005C    RESERVED
RESERV0055     0x005D    RESERVED
RESERV0055     0x005E    RESERVED
RESERV0055     0x005F    RESERVED
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register 
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register 
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register 
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register 
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1                             
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low 
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC11KG4
; MC68HC11KG4/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11KG4.pdf
; kg4.pdf

; RAM=768
; ROM=24K
; EPROM=0
; EEPROM=640


; MEMORY MAP
area DATA FSR		0x0000:0x0080
area DATA RAM		0x0080:0x0380
area BSS  RESERVED      0x0380:0x0D80
area DATA EEPROM	0x0D80:0x1000
area BSS  RESERVED      0x1000:0xA000
area DATA ROM		0xA000:0xFFC0
area DATA USER_VEC	0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE    RESET
interrupt CME 		0xFFFC    Clock monitor fail
interrupt NOCOP_NWCOP 	0xFFFA    COP failure / WCOP failure
interrupt OPCODE 	0xFFF8    Illegal opcode trap
interrupt SOFT 		0xFFF6    Software interrupt
interrupt XIRQ 		0xFFF4    XIRQ pin (SRTI interrupt wired to XIRQ)
interrupt IRQ 		0xFFF2    IRQ pin
interrupt RTII 		0xFFF0    Real-time interrupt
interrupt IC1I 		0xFFEE    Timer input capture 1
interrupt IC2I 		0xFFEC    Timer input capture 2
interrupt IC3I 		0xFFEA    Timer input capture 3
interrupt OC1I 		0xFFE8    Timer output compare 1
interrupt OC2I 		0xFFE6    Timer output compare 2
interrupt OC3I 		0xFFE4    Timer output compare 3
interrupt OC4I 		0xFFE2    Timer output compare 4
interrupt I4_O5I 	0xFFE0    Timer input capture 4/output compare 5
interrupt TOI 		0xFFDE    Timer overflow
interrupt PAOVI 	0xFFDC    Pulse accumulator overflow
interrupt PAII 		0xFFDA    Pulse accumulator input edge
interrupt SPIE 		0xFFD8    SPI serial transfer complete
interrupt SCI2 		0xFFD6    SCI2
interrupt PWMI 		0xFFD0    PWMI
interrupt SCI1 		0xFFCE    SCI1
interrupt KMSK	 	0xFFCC    Port J keyboard interrupt


; INPUT/ OUTPUT PORTS
PORTA          0x0000   Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001   Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002   Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003   Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004   Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005   Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006   Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007   Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008   Port D Data Register
PORTD.PD7       7   Port D Data Bit 7
PORTD.PD6       6   Port D Data Bit 6
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009   Port D Data Direction Register
DDRD.DDD7       7   Data Direction for Port D Bit 7
DDRD.DDD6       6   Data Direction for Port D Bit 6
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A   Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PD1       1   Port E Data Bit 1
PORTE.PD0       0   Port E Data Bit 0
CFORC          0x000B   Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C   Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D   Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E   Timer Counter Register High
TCNTL          0x000F   Timer Counter Register Low
TIC1H          0x0010   Timer Input Capture 1 Register High
TIC1L          0x0011   Timer Input Capture 1 Register Low
TIC2H          0x0012   Timer Input Capture 2 Register High
TIC2L          0x0013   Timer Input Capture 2 Register Low
TIC3H          0x0014   Timer Input Capture 3 Register High
TIC3L          0x0015   Timer Input Capture 3 Register Low
TOC1H          0x0016   Timer Output Compare 1 High Register
TOC1L          0x0017   Timer Output Compare 1 Low Register
TOC2H          0x0018   Timer Output Compare 2 High Register
TOC2L          0x0019   Timer Output Compare 2 Low Register
TOC3H          0x001A   Timer Output Compare 3 High Register
TOC3L          0x001B   Timer Output Compare 3 Low Register
TOC4H          0x001C   Timer Output Compare 4 High Register
TOC4L          0x001D   Timer Output Compare 4 Low Register
TI4H_O5H       0x001E   Timer Input Capture 4_ Output Compare 5 Reg. High
TI4L_O5L       0x001F   Timer Input Capture 4_ Output Compare 5 Low Reg.
TCTL1          0x0020   Timer Control 1 Register
TCTL1.OM2       7   Output mode 2
TCTL1.OL2       6   Output level 2
TCTL1.OM3       5   Output mode 3
TCTL1.OL3       4   Output level 3
TCTL1.OM4       3   Output mode 4
TCTL1.OL4       2   Output level 4
TCTL1.OM5       1   Output mode 5
TCTL1.OL5       0   Output level 5
TCTL2          0x0021   Timer Control 2 Register
TCTL2.EDG4B     7   Input capture edge control 4B
TCTL2.EDG4A     6   Input capture edge control 4A
TCTL2.EDG1B     5   Input capture edge control 1B
TCTL2.EDG1A     4   Input capture edge control 1A
TCTL2.EDG2B     3   Input capture edge control 2B
TCTL2.EDG2A     2   Input capture edge control 2A
TCTL2.EDG3B     1   Input capture edge control 3B
TCTL2.EDG3A     0   Input capture edge control 3A
TMSK1          0x0022   Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output compare 1 interrupt enable
TMSK1.OC2I      6   Output compare 2 interrupt enable
TMSK1.OC3I      5   Output compare 3 interrupt enable
TMSK1.OC4I      4   Output compare 4 interrupt enable
TMSK1.I4_O5I    3   Input capture 4/output compare 5 interrupt enable
TMSK1.IC1I      2   Input capture 1 interrupt enable
TMSK1.IC2I      1   Input capture 2 interrupt enable
TMSK1.IC3I      0   Input capture 3 interrupt enable
TFLG1          0x0023   Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output compare 1 flag
TFLG1.OC2F      6   Output compare 2 flag
TFLG1.OC3F      5   Output compare 3 flag
TFLG1.OC4F      4   Output compare 4 flag
TFLG1.I4_O5F    3   Input capture 4/output compare 5 flag
TFLG1.IC1F      2   Input capture 1 flag
TFLG1.IC2F      1   Input capture 2 flag
TFLG1.IC3F      0   Input capture 3 flag
TMSK2          0x0024   Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer overflow interrupt enable
TMSK2.RTII      6   Real-time interrupt enable
TMSK2.PAOVI     5   Pulse accumulator overflow interrupt enable
TMSK2.PAII      4   Pulse accumulator interrupt enable
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025   Timer Interrupt Flag 2
TFLG2.TOF       7   Timer overflow interrupt flag
TFLG2.RTIF      6   Real time (periodic) interrupt flag
TFLG2.PAOVF     5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF      4   Pulse accumulator input edge interrupt flag
PACTL          0x0026   Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse accumulator system enable
PACTL.PAMOD     5   Pulse accumulator mode
PACTL.PEDGE     4   Pulse accumulator edge control
PACTL.I4_O5     2   Input capture 4/output compare 5
PACTL.RTR1      1   RTI interrupt rate select 1
PACTL.RTR0      0   RTI interrupt rate select 0
PACNT          0x0027   Pulse Accumulator Count Register
SPCR           0x0028   Serial Peripheral Control Register
SPCR.SPIE       7   Serial peripheral interrupt enable
SPCR.SPE        6   Serial peripheral system enable
SPCR.DWOM       5   Port D wired-OR mode
SPCR.MSTR       4   Master mode select
SPCR.CPOL       3   Clock polarity
SPCR.CPHA       2   Clock phase
SPCR.SPR1       1   SPI clock rate selects 1
SPCR.SPR0       0   SPI clock rate selects 0
SPSR           0x0029   Serial Peripheral Status Register
SPSR.SPIF       7   SPI interrupt complete flag
SPSR.WCOL       6   Write collision
SPSR.MODF       4   Mode fault
SPDR           0x002A   Serial Peripheral Data Register
Reserved2B     0x002B   RESERVED
PPAR           0x002C   Port Pullup Assignment Register
PPAR.JPPUE      3   Port J pin pull-up enable
PPAR.FPPUE      1   Port F pin pull-up enable
PPAR.BPPUE      0   Port B pin pull-up enable
Reserved2D     0x002D   RESERVED
PLLCR          0x002E   PLL control
PLLCR.PLLON     7   PLL on
PLLCR.BCS       6   Bus clock select
PLLCR.AUTO      5   Automatic bandwidth control (Test mode only)
PLLCR.BWC       4   Bandwidth control
PLLCR.VCOT      3   VCO test (Test mode only)
PLLCR.MCS       2   Module clock select
PLLCR.WSLOW     1   Slow frequency in WAIT
PLLCR.WEN       0   WAIT enable
SYNR           0x002F   Synthesizer program
SYNR.SYNX1      7
SYNR.SYNX0      6
SYNR.SYNY5      5
SYNR.SYNY4      4
SYNR.SYNY3      3
SYNR.SYNY2      2
SYNR.SYNY1      1
SYNR.SYNY0      0
ADCTL          0x0030   Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions complete flag
ADCTL.CONV8     6   Convert 8/convert 4 select bit
ADCTL.SCAN      5   Continuous scan control
ADCTL.MULT      4   Multiple channel/single channel control
ADCTL.CD        3   Channel select bit D
ADCTL.CC        2   Channel select bit C
ADCTL.CB        1   Channel select bit B
ADCTL.CA        0   Channel select bit A
Reserved31     0x0031   RESERVED
ADFRQ          0x0032   A_D frequency select
ADFRQ.ADER      0   A/D frequency select
RTREG          0x0033   SRTI programming
RTREG.SRTI3     7
RTREG.SRTI2     6
RTREG.SRTI1     5
RTREG.SRTI0     4
RTCTL          0x0034   SRTI control
RTCTL.RTF       7   Slow real time interrupt flag
RTCTL.RTI       6   Slow real time interrupt enable
RTCTL.RTCK2     3   Prescaler for SRTI clock 2
RTCTL.RTCK1     2   Prescaler for SRTI clock 1
RTCTL.RTHF      1   SRTI high part counter overflow flag
RTCTL.RTLF      0   SRTI low part counter overflow flag
BPROT          0x0035   Block Protect Register
BPROT.BULKP     7   Bulk erase of EEPROM protect
BPROT.LVPEN     6   EEPROM programming enable
BPROT.BPRT4     5   Block protect bits for EEPROM bit 4
BPROT.PTCON     4   Protect for CONFIG register
BPROT.BPRT3     3   Block protect bits for EEPROM bit 3
BPROT.BPRT2     2   Block protect bits for EEPROM bit 2
BPROT.BPRT1     1   Block protect bits for EEPROM bit 1
BPROT.BPRT0     0   Block protect bits for EEPROM bit 0
Reserved36     0x0036   RESERVED
INIT2          0x0037   EEPROM Mapping Register
INIT2.EE3       7   EEPROM map position 3
INIT2.EE2       6   EEPROM map position 2
INIT2.EE1       5   EEPROM map position 1
INIT2.EE0       4   EEPROM map position 0
OPT2           0x0038   System Configuration Options 2 Register
OPT2.LIRDV      7   LIR driven
OPT2.CWOM       6   Port C wired-OR mode
OPT2.STRCH      5   Stretch external accesses
OPT2.IRVNE      4   Internal read visibility/not E
OPT2.LSBF       3   LSB-first enable
OPT2.SPR2       2   SPI clock rate select
OPT2.XDV1       1   XOUT clock divide select 1
OPT2.XDV0       0   XOUT clock divide select 0
OPTION         0x0039   System Configuration Options Register
OPTION.ADPU     7   A/D power-up
OPTION.CSEL     6   Clock select
OPTION.IRQE     5   Configure IRQ for falling-edge-sensitive operation
OPTION.DLY      4   Enable oscillator start-up delay
OPTION.CME      3   Clock monitor enable
OPTION.FCME     2   Force clock monitor enable
OPTION.CR1      1   COP timer rate select bit 1
OPTION.CR0      0   COP timer rate select bit 0
COPRST         0x003A   Arm_Reset COP Timer Circuitry Register
PPROG          0x003B   EEPROM Programming Control Register
PPROG.ODD       7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN      6   Program even rows in half of EEPROM (Test)
PPROG.LVPI      5   EEPROM programming status
PPROG.BYTE      4   EEPROM byte erase mode
PPROG.ROW       3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE     2   Erase/normal control for EEPROM
PPROG.EELAT     1   EEPROM latch control
PPROG.EEPGM     0   EEPROM program command
HPRIO          0x003C   Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read bootstrap ROM
HPRIO.SMOD      6   Special mode select
HPRIO.MDA       5   Mode select A
HPRIO.PSEL4     4   Priority select bit 4
HPRIO.PSEL3     3   Priority select bit 3
HPRIO.PSEL2     2   Priority select bit 2
HPRIO.PSEL1     1   Priority select bit 1
HPRIO.PSEL0     0   Priority select bit 0
INIT           0x003D   RAM and I_O Mapping Register
INIT.RAM3       7   RAM map position 3
INIT.RAM2       6   RAM map position 2
INIT.RAM1       5   RAM map position 1
INIT.RAM0       4   RAM map position 0
INIT.REG3       3   128-byte register block position 3
INIT.REG2       2   128-byte register block position 2
INIT.REG1       1   128-byte register block position 1
INIT.REG0       0   128-byte register block position 0
TEST1          0x003E   Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode
TEST1.PLST      6   
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
TEST1.DLVR      0
CONFIG         0x003F   Configuration control
CONFIG.ROMAD    7   ROM mapping control
CONFIG.NWCOP    6   WCOP system disable
CONFIG.CLKX     5   WCOP system disable
CONFIG.PAREN    4   Pull-up assignment register enable
CONFIG.NOSEC    3   EEPROM security disabled
CONFIG.NOCOP    2   COP system disable
CONFIG.ROMON    1   ROM enable
CONFIG.EEON     0   EEPROM enable
ADR1H          0x0040   A_D result 1 high
ADR1L          0x0041   A_D result 1 low
ADR2H          0x0042   A_D result 2 high
ADR2L          0x0043   A_D result 2 low
ADR3H          0x0044   A_D result 3 high
ADR3L          0x0045   A_D result 3 low
ADR4H          0x0046   A_D result 4 high
ADR4L          0x0047   A_D result 4 low
ADR5H          0x0048   A_D result 5 high
ADR5L          0x0049   A_D result 5 low
ADR6H          0x004A   A_D result 6 high
ADR6L          0x004B   A_D result 6 low
ADR7H          0x004C   A_D result 7 high
ADR7L          0x004D   A_D result 7 low
ADR8H          0x004E   A_D result 8 high
ADR8L          0x004F   A_D result 8 low
SC1BDH         0x0050   SCI1 Baud Rate Control Register High
SC1BDH.BTST     7   Baud register test (Test mode only)
SC1BDH.BSPL     6   Baud rate counter split (Test mode only)
SC1BDH.SYNC     5   Baud rate counter synchronization (Test mode only)
SC1BDH.SBR12    4   SCI1 baud rate selects 12
SC1BDH.SBR11    3   SCI1 baud rate selects 11
SC1BDH.SBR10    2   SCI1 baud rate selects 10
SC1BDH.SBR9     1   SCI1 baud rate selects 9 
SC1BDH.SBR8     0   SCI1 baud rate selects 8 
SC1BDL         0x0051   SCI1 Baud Rate Control Register Low
SC1BDL.SBR7     7   SCI1 baud rate selects 7
SC1BDL.SBR6     6   SCI1 baud rate selects 6
SC1BDL.SBR5     5   SCI1 baud rate selects 5
SC1BDL.SBR4     4   SCI1 baud rate selects 4
SC1BDL.SBR3     3   SCI1 baud rate selects 3
SC1BDL.SBR2     2   SCI1 baud rate selects 2
SC1BDL.SBR1     1   SCI1 baud rate selects 1
SC1BDL.SBR0     0   SCI1 baud rate selects 0
SC1CR1         0x0052   SCI1 Control Register 1
SC1CR1.LOOPS    7   SCI1 loop mode enable
SC1CR1.WOMS     6   Wired-OR mode for SCI1 pins (PD7, PD6)
SC1CR1.M        4   Mode (select character format)
SC1CR1.WAKE     3   Wake-up by address mark/idle
SC1CR1.ILT      2   Idle line type
SC1CR1.PE       1   Parity enable
SC1CR1.PT       0   Parity type
SC1CR2         0x0053   SCI1 Control Register 2
SC1CR2.TIE      7   Transmit interrupt enable
SC1CR2.TCIE     6   Transmit complete interrupt enable
SC1CR2.RIE      5   Receiver interrupt enable
SC1CR2.ILIE     4   Idle line interrupt enable
SC1CR2.TE       3   Transmitter enable
SC1CR2.RE       2   Receiver enable
SC1CR2.RWU      1   Receiver wake-up control
SC1CR2.SBK      0   Send break
SC1SR1         0x0054   SCI1 Status Register 1
SC1SR1.TDRE     7   Transmit data register empty flag
SC1SR1.TC       6   Transmit complete flag
SC1SR1.RDRF     5   Receive data register full flag
SC1SR1.IDLE     4   Idle line detected flag
SC1SR1.OR       3   Overrun error flag
SC1SR1.NF       2   Noise error flag
SC1SR1.FE       1   Framing error
SC1SR1.PF       0   Parity error flag
SC1SR2         0x0055   SCI1 Status Register 2
SC1SR2.RAF      0   Receiver active flag (read only)
SC1DRH         0x0056   SCI1 Data Register high
SC1DRH.R8       7   Receiver bit 8
SC1DRH.T8       6   Transmitter bit 8
SC1DRL         0x0057   SCI1 Data Register low
SC1DRL.R7_T7    7   Receiver/transmitter data bit 7
SC1DRL.R6_T6    6   Receiver/transmitter data bit 6
SC1DRL.R5_T5    5   Receiver/transmitter data bit 5
SC1DRL.R4_T4    4   Receiver/transmitter data bit 4
SC1DRL.R3_T3    3   Receiver/transmitter data bit 3
SC1DRL.R2_T2    2   Receiver/transmitter data bit 2
SC1DRL.R1_T1    1   Receiver/transmitter data bit 1
SC1DRL.R0_T0    0   Receiver/transmitter data bit 0
JKFLAG         0x0058   Port J keyboard interrupt flag
JKFLAG.KFLG3    3
JKFLAG.KFLG2    2
JKFLAG.KFLG1    1
JKFLAG.KFLG0    0
JKMASK         0x0059   Port J keyboard interrupt mask
JKMASK.KEDG3	7   Keyboard interrupt active edge 3
JKMASK.KEDG2    6   Keyboard interrupt active edge 2
JKMASK.KEDG1    5   Keyboard interrupt active edge 1
JKMASK.KEDG0    4   Keyboard interrupt active edge 0
JKMASK.KMSK3    3   Keyboard interrupt mask 3
JKMASK.KMSK2    2   Keyboard interrupt mask 2
JKMASK.KMSK1    1   Keyboard interrupt mask 1
JKMASK.KMSK0    0   Keyboard interrupt mask 0
PORTJ          0x005A   Port J data
PORTJ.PJ3       3   Port J Data Bit 3
PORTJ.PJ2       2   Port J Data Bit 2
PORTJ.PJ1       1   Port J Data Bit 1
PORTJ.PJ0       0   Port J Data Bit 0
DDRJ           0x005B   Data direction J
DDRJ.DDJ        3   Data Direction for Port J Bit 3
DDRJ.DDJ        2   Data Direction for Port J Bit 2
DDRJ.DDJ        1   Data Direction for Port J Bit 1
DDRJ.DDJ        0   Data Direction for Port J Bit 0
PORTH          0x005C   Port H data
PORTH.PH7       7   Port H Data Bit 7
PORTH.PH6       6   Port H Data Bit 6
PORTH.PH5       5   Port H Data Bit 5
PORTH.PH4       4   Port H Data Bit 4
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
PTHMS          0x005D   Port H mismatch
PORTK          0x005E   Port K data
PORTK.PK7       7   Port K Data Bit 7
PORTK.PK6       6   Port K Data Bit 6
PORTK.PK5       5   Port K Data Bit 5
PORTK.PK4       4   Port K Data Bit 4
PORTK.PK3       3   Port K Data Bit 3
PORTK.PK2       2   Port K Data Bit 2
PORTK.PK1       1   Port K Data Bit 1
PORTK.PK0       0   Port K Data Bit 0
PTKMS          0x005F   Port K mismatch
PWDTY0H        0x0060   PWM channel duty 0 high
PWDTY0H.MSB	1
PWDTY0L        0x0061   PWM channel duty 0 low
PWDTY1H        0x0062   PWM channel duty 1 high
PWDTY1H.MSB	1
PWDTY1L        0x0063   PWM channel duty 1 low
PWDTY2H        0x0064   PWM channel duty 2 high
PWDTY2H.MSB	1
PWDTY2L        0x0065   PWM channel duty 2 low
PWDTY3H        0x0066   PWM channel duty 3 high
PWDTY3H.MSB	1
PWDTY3L        0x0067   PWM channel duty 3 low
PWDTY4H        0x0068   PWM channel duty 4 high
PWDTY4H.MSB	1
PWDTY4L        0x0069   PWM channel duty 4 low
PWDTY5H        0x006A   PWM channel duty 5 high
PWDTY5H.MSB	1
PWDTY5L        0x006B   PWM channel duty 5 low
PWDTY6H        0x006C   PWM channel duty 6 high
PWDTY6H.MSB	1
PWDTY6L        0x006D   PWM channel duty 6 low
PWDTY7H        0x006E   PWM channel duty 7 high
PWDTY7H.MSB	1
PWDTY7L        0x006F   PWM channel duty 7 low
SC2BDH         0x0070   SCI2 baud rate high
SC2BDH.BTST     7   Baud register test (Test mode only)               
SC2BDH.BSPL     6   Baud rate counter split (Test mode only)          
SC2BDH.SYNC     5   Baud rate counter synchronization (Test mode only)
SC2BDH.SBR12    4   SCI1 baud rate selects 12                         
SC2BDH.SBR11    3   SCI1 baud rate selects 11                         
SC2BDH.SBR10    2   SCI1 baud rate selects 10                         
SC2BDH.SBR9     1   SCI1 baud rate selects 9                          
SC2BDH.SBR8     0   SCI1 baud rate selects 8                          
SC2BDL         0x0071   SCI2 baud rate low
SC2BDL.SBR7     7   SCI1 baud rate selects 7
SC2BDL.SBR6     6   SCI1 baud rate selects 6
SC2BDL.SBR5     5   SCI1 baud rate selects 5
SC2BDL.SBR4     4   SCI1 baud rate selects 4
SC2BDL.SBR3     3   SCI1 baud rate selects 3
SC2BDL.SBR2     2   SCI1 baud rate selects 2
SC2BDL.SBR1     1   SCI1 baud rate selects 1
SC2BDL.SBR0     0   SCI1 baud rate selects 0
SC2CR1         0x0072   SCI2 Control Register 1
SC2CR1.LOOPS    7   SCI1 loop mode enable                 
SC2CR1.WOMS     6   Wired-OR mode for SCI1 pins (PD7, PD6)
SC2CR1.M        4   Mode (select character format)        
SC2CR1.WAKE     3   Wake-up by address mark/idle          
SC2CR1.ILT      2   Idle line type                        
SC2CR1.PE       1   Parity enable                         
SC2CR1.PT       0   Parity type                           
SC2CR2         0x0073   SCI2 Control Register 2
SC2CR2.TIE      7   Transmit interrupt enable         
SC2CR2.TCIE     6   Transmit complete interrupt enable
SC2CR2.RIE      5   Receiver interrupt enable         
SC2CR2.ILIE     4   Idle line interrupt enable        
SC2CR2.TE       3   Transmitter enable                
SC2CR2.RE       2   Receiver enable                   
SC2CR2.RWU      1   Receiver wake-up control          
SC2CR2.SBK      0   Send break                        
SC2SR1         0x0074   SCI2 Status Register 1
SC2SR1.TDRE     7   Transmit data register empty flag
SC2SR1.TC       6   Transmit complete flag           
SC2SR1.RDRF     5   Receive data register full flag  
SC2SR1.IDLE     4   Idle line detected flag          
SC2SR1.OR       3   Overrun error flag               
SC2SR1.NF       2   Noise error flag                 
SC2SR1.FE       1   Framing error                    
SC2SR1.PF       0   Parity error flag                
SC2SR2         0x0075   SCI2 Status Register 2
SC2SR2.RAF      0   Receiver active flag (read only)
SC2DRH         0x0076   SCI2 Data Register high
SC2DRH.R8       7   Receiver bit 8   
SC2DRH.T8       6   Transmitter bit 8
SC2DRL         0x0077   SCI2 Data Register low
SC2DRL.R7_T7    7   Receiver/transmitter data bit 7
SC2DRL.R6_T6    6   Receiver/transmitter data bit 6
SC2DRL.R5_T5    5   Receiver/transmitter data bit 5
SC2DRL.R4_T4    4   Receiver/transmitter data bit 4
SC2DRL.R3_T3    3   Receiver/transmitter data bit 3
SC2DRL.R2_T2    2   Receiver/transmitter data bit 2
SC2DRL.R1_T1    1   Receiver/transmitter data bit 1
SC2DRL.R0_T0    0   Receiver/transmitter data bit 0
PWCLK          0x0078   PWM control
PWCLK.PCKC2     5   Prescaler for clock C 2
PWCLK.PCKC1     4   Prescaler for clock C 1
PWCLK.PWMF      1   PWM interrupt flag
PWCLK.PWMI      0   PWM interrupt mask
PWEN           0x0079   PWM channel enable
PWEN.PWEN7      7   Pulse width channel 7 enable
PWEN.PWEN6      6   Pulse width channel 6 enable
PWEN.PWEN5      5   Pulse width channel 5 enable
PWEN.PWEN4      4   Pulse width channel 4 enable
PWEN.PWEN3      3   Pulse width channel 3 enable
PWEN.PWEN2      2   Pulse width channel 2 enable
PWEN.PWEN1      1   Pulse width channel 1 enable
PWEN.PWEN0      0   Pulse width channel 0 enable
PWPOL          0x007A   PWM channel polarity
PWPOL.PPOL7     7   Pulse width channel 7 polarity
PWPOL.PPOL6     6   Pulse width channel 6 polarity
PWPOL.PPOL5     5   Pulse width channel 5 polarity
PWPOL.PPOL4     4   Pulse width channel 4 polarity
PWPOL.PPOL3     3   Pulse width channel 3 polarity
PWPOL.PPOL2     2   Pulse width channel 2 polarity
PWPOL.PPOL1     1   Pulse width channel 1 polarity
PWPOL.PPOL0     0   Pulse width channel 0 polarity
PWCNTH         0x007B   PWM channel counter high
PWCNTL         0x007C   PWM channel counter low
DACON          0x007D   D/A control
DACON.DAEI      0   Digital to analog enable
DAI            0x007E   D/A data
Reserved7F     0x007F   RESERVED
RESERVFFC0     0xFFC0   RESERVED
RESERVFFC1     0xFFC1   RESERVED
RESERVFFC2     0xFFC2   RESERVED
RESERVFFC3     0xFFC3   RESERVED
RESERVFFC4     0xFFC4   RESERVED
RESERVFFC5     0xFFC5   RESERVED
RESERVFFC6     0xFFC6   RESERVED
RESERVFFC7     0xFFC7   RESERVED
RESERVFFC8     0xFFC8   RESERVED
RESERVFFC9     0xFFC9   RESERVED
RESERVFFCA     0xFFCA   RESERVED
RESERVFFCB     0xFFCB   RESERVED

.68HC11KS2
; M68HC11K/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11KS2&nodeId=01M98635
; M68HC11K.pdf

; RAM=1K  
; ROM=32K
; EPROM=0
; EEPROM=640


; MEMORY MAP
area DATA FSR         0x0000:0x0080
area DATA RAM         0x0080:0x0480
area BSS  RESERVED    0x0480:0x0D80
area DATA EEPROM      0x0D80:0x1000
area BSS  RESERVED    0x1000:0x8000
area DATA ROM_EPR     0x8000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
PGAR           0x002D    Port G Assignment Register
PGAR.PGAR5      5   Port G Pin Assignment Bit 5
PGAR.PGAR4      4   Port G Pin Assignment Bit 4
PGAR.PGAR3      3   Port G Pin Assignment Bit 3
PGAR.PGAR2      2   Port G Pin Assignment Bit 2
PGAR.PGAR1      1   Port G Pin Assignment Bit 1
PGAR.PGAR0      0   Port G Pin Assignment Bit 0
OPT3           0x002E    System Configuration Options 3 Register (Not available on M68HC11K4 devices)
OPT3.SM         6   Slow-Mode Enable Bit
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG Bit
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode                                
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM Address Mapping Control Bit
CONFIG.CLKX     5   WCOP system disable
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   RAM and EPROM Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/PROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
RESERV0056     0x0056    RESERVED
RESERV0057     0x0057    RESERVED
RESERV0058     0x0058    RESERVED
RESERV0059     0x0059    RESERVED
RESERV005A     0x005A    RESERVED
RESERV005B     0x005B    RESERVED
RESERV005C     0x005C    RESERVED
RESERV005D     0x005D    RESERVED
RESERV005E     0x005E    RESERVED
RESERV005F     0x005F    RESERVED
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC11KW1
; MC68HC11KW1/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11KW1&nodeId=01M98635
; MC68HC11KW1.pdf

; RAM=768
; ROM=448
; EPROM=0
; EEPROM=640


;MEMORY MAP
area DATA FSR        0x0000:0x00A0
area DATA RAM        0x00A0:0x03A0
area BSS  RESERVED   0x03A0:0x0D80
area DATA EEPROM     0x0D80:0x1000      EEPROM 640 bytes
area BSS  RESERVED   0x1000:0xFFC0
area DATA USER_VEC   0xFFC0:0x10000     


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      COP Clock Monitor Fail (Reset)
interrupt NOCOP             0xFFFA      COP Failure (Reset)
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SWI               0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer 1 Input Capture 1
interrupt IC2I              0xFFEC      Timer 1 Input Capture 2
interrupt IC3I              0xFFEA      Timer 1 Input Capture 3
interrupt OC1I              0xFFE8      Timer 1 Output Compare 1
interrupt OC2I              0xFFE6      Timer 1 Output Compare 2
interrupt OC3I              0xFFE4      Timer 1 Output Compare 3
interrupt OC4I              0xFFE2      Timer 1 Output Compare 4
interrupt I4_I5             0xFFE0      Timer 1 Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer 1 Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System
interrupt OC_1I_2I_3I       0xFFD4      Timer 2 out compare 1_2_3
interrupt C4I               0xFFD2      Timer 2 input capture 1 / output compare 4
interrupt TO2I              0xFFD0      Timer 2 overflow
interrupt TIC_OC            0xFFCE      Timer 3 input capture 1 / output compare 4
interrupt TO3I              0xFFCC      Timer 3 overflow


;INPUT/ OUTPUT PORTS
PORTA            0x0000   Port A data (ALT - Timer 1)
PORTA.PA7         7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
DDRA             0x0001   Data direction A
DDRA.DDA7         7   Data Direction for Port A Bit 7
DDRA.DDA6         6   Data Direction for Port A Bit 6
DDRA.DDA5         5   Data Direction for Port A Bit 5
DDRA.DDA4         4   Data Direction for Port A Bit 4
DDRA.DDA3         3   Data Direction for Port A Bit 3
DDRA.DDA2         2   Data Direction for Port A Bit 2
DDRA.DDA1         1   Data Direction for Port A Bit 1
DDRA.DDA0         0   Data Direction for Port A Bit 0
DDRB             0x0002   Data direction B
DDRB.DDB7         7   Data Direction for Port B Bit 7
DDRB.DDB6         6   Data Direction for Port B Bit 6
DDRB.DDB5         5   Data Direction for Port B Bit 5
DDRB.DDB4         4   Data Direction for Port B Bit 4
DDRB.DDB3         3   Data Direction for Port B Bit 3
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRB.DDB1         1   Data Direction for Port B Bit 1
DDRB.DDB0         0   Data Direction for Port B Bit 0
DDRF             0x0003   Data direction F
DDRF.DDF7         7   Data Direction for Port F Bit 7
DDRF.DDF6         6   Data Direction for Port F Bit 6
DDRF.DDF5         5   Data Direction for Port F Bit 5
DDRF.DDF4         4   Data Direction for Port F Bit 4
DDRF.DDF3         3   Data Direction for Port F Bit 3
DDRF.DDF2         2   Data Direction for Port F Bit 2
DDRF.DDF1         1   Data Direction for Port F Bit 1
DDRF.DDF0         0   Data Direction for Port F Bit 0
PORTB            0x0004   Port B data (ALT - High order address)
PORTB.PB7         7   Port B Data Bit 7
PORTB.PB6         6   Port B Data Bit 6
PORTB.PB5         5   Port B Data Bit 5
PORTB.PB4         4   Port B Data Bit 4
PORTB.PB3         3   Port B Data Bit 3
PORTB.PB2         2   Port B Data Bit 2
PORTB.PB1         1   Port B Data Bit 1
PORTB.PB0         0   Port B Data Bit 0
PORTF            0x0005   Port F data (ALT - Low order address)
PORTF.PF7         7   Port F Data Bit 7
PORTF.PF6         6   Port F Data Bit 6
PORTF.PF5         5   Port F Data Bit 5
PORTF.PF4         4   Port F Data Bit 4
PORTF.PF3         3   Port F Data Bit 3
PORTF.PF2         2   Port F Data Bit 2
PORTF.PF1         1   Port F Data Bit 1
PORTF.PF0         0   Port F Data Bit 0
PORTC            0x0006   Port C data (ALT - Data bus)
PORTC.PC7         7   Port C Data Bit 7
PORTC.PC6         6   Port C Data Bit 6
PORTC.PC5         5   Port C Data Bit 5
PORTC.PC4         4   Port C Data Bit 4
PORTC.PC3         3   Port C Data Bit 3
PORTC.PC2         2   Port C Data Bit 2
PORTC.PC1         1   Port C Data Bit 1
PORTC.PC0         0   Port C Data Bit 0
DDRC             0x0007   Data direction C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x0008   Port D data (ALT - SCI and SPI)
PORTD.PD7         7   Port D Data Bit 7
PORTD.PD6         6   Port D Data Bit 6
PORTD.PD5_SS      5   Port D Data Bit 5
PORTD.PD4_SCK     4   Port D Data Bit 4
PORTD.PD3_MOSI    3   Port D Data Bit 3
PORTD.PD2_MISO    2   Port D Data Bit 2
PORTD.PD1_TXD     1   Port D Data Bit 1
PORTD.PD0_RXD     0   Port D Data Bit 0
DDRD             0x0009   Data direction D
DDRD.DDD7         7   Data Direction for Port D Bit 7
DDRD.DDD6         6   Data Direction for Port D Bit 6
DDRD.DDD5         5   Data Direction for Port D Bit 5
DDRD.DDD4         4   Data Direction for Port D Bit 4
DDRD.DDD3         3   Data Direction for Port D Bit 3
DDRD.DDD2         2   Data Direction for Port D Bit 2
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
PORTE            0x000A   Port E data (ALT - A/D converter)
PORTE.PE7_AN9     7   Port E Data Bit 7
PORTE.PE6_AN8     6   Port E Data Bit 6
PORTE.PE5_AN7     5   Port E Data Bit 5
PORTE.PE4_AN6     4   Port E Data Bit 4
PORTE.PE3_AN5     3   Port E Data Bit 3
PORTE.PE2_AN4     2   Port E Data Bit 2
PORTE.PE1_AN3     1   Port E Data Bit 1
PORTE.PE0_AN2     0   Port E Data Bit 0
CFORC            0x000B   Timer compare force
CFORC.FOC1        7   Force output compares 1
CFORC.FOC2        6   Force output compares 2
CFORC.FOC3        5   Force output compares 3
CFORC.FOC4        4   Force output compares 4
CFORC.FOC5        3   Force output compares 5
OC1M             0x000C   Output compare 1 mask
OC1M.OC1M7        7   Output compare masks 7 for OC1
OC1M.OC1M6        6   Output compare masks 6 for OC1
OC1M.OC1M5        5   Output compare masks 5 for OC1
OC1M.OC1M4        4   Output compare masks 4 for OC1
OC1M.OC1M3        3   Output compare masks 3 for OC1
OC1D             0x000D   Output compare 1 data
OC1D.OC1D7        7   Output compare data 7 for OC1
OC1D.OC1D6        6   Output compare data 6 for OC1
OC1D.OC1D5        5   Output compare data 5 for OC1
OC1D.OC1D4        4   Output compare data 4 for OC1
OC1D.OC1D3        3   Output compare data 3 for OC1
TCNTH            0x000E   Timer count high
TCNTL            0x000F   Timer count low
TIC1H            0x0010   Timer input capture 1 high
TIC1L            0x0011   Timer input capture 1 low
TIC2H            0x0012   Timer input capture 2 high
TIC2L            0x0013   Timer input capture 2 low
TIC3H            0x0014   Timer input capture 3 high
TIC3L            0x0015   Timer input capture 3 low
TOC1H            0x0016   Timer output compare 1 high
TOC1L            0x0017   Timer output compare 1 low
TOC2H            0x0018   Timer output compare 2 high
TOC2L            0x0019   Timer output compare 2 low
TOC3H            0x001A   Timer output compare 3 high
TOC3L            0x001B   Timer output compare 3 low
TOC4H            0x001C   Timer output compare 4 high
TOC4L            0x001D   Timer output compare 4 low
TI4O5H           0x001E   Capture 4/compare 5 high
TI4O5L           0x001F   Capture 4/compare 5 low
TCTL1            0x0020   Timer control 1 
TCTL1.OM2         7   Output mode 2
TCTL1.OL2         6   Output level 2
TCTL1.OM3         5   Output mode 3
TCTL1.OL3         4   Output level 3
TCTL1.OM4         3   Output mode 4
TCTL1.OL4         2   Output level 4
TCTL1.OM5         1   Output mode 5
TCTL1.OL5         0   Output level 5
TCTL2            0x0021   Timer control 2
TCTL2.EDG4B       7   EDG4B  Input capture edge control
TCTL2.EDG4A       6   EDG4A  Input capture edge control
TCTL2.EDG1B       5   EDG1B  Input capture edge control
TCTL2.EDG1A       4   EDG1A  Input capture edge control
TCTL2.EDG2B       3   EDG2B  Input capture edge control
TCTL2.EDG2A       2   EDG2A  Input capture edge control
TCTL2.EDG3B       1   EDG3B  Input capture edge control
TCTL2.EDG3A       0   EDG3A  Input capture edge control
TMSK1            0x0022   Timer interrupt mask 1
TMSK1.OC1I        7   Output compare 1 interrupt enable
TMSK1.OC2I        6   Output compare 2 interrupt enable
TMSK1.OC3I        5   Output compare 3 interrupt enable
TMSK1.OC4I        4   Output compare 4 interrupt enable
TMSK1.I4O5I       3   Input capture 4/output compare 5 interrupt enable
TMSK1.IC1I        2   Input capture 1 interrupt enable
TMSK1.IC2I        1   Input capture 2 interrupt enable
TMSK1.IC3I        0   Input capture 3 interrupt enable
TFLG1            0x0023   Timer interrupt flag 1
TFLG1.OC1F        7   Output compare 1 flag
TFLG1.OC2F        6   Output compare 2 flag
TFLG1.OC3F        5   Output compare 3 flag
TFLG1.OC4F        4   Output compare 4 flag
TFLG1.I4O5F       3   Input capture 4/output compare 5 flag
TFLG1.IC1F        2   Input capture 1 flag
TFLG1.IC2F        1   Input capture 2 flag
TFLG1.IC3F        0   Input capture 3 flag
TMSK2            0x0024   Timer interrupt mask register 2
TMSK2.TOI         7   Timer overflow interrupt enable
TMSK2.RTII        6   Real-time interrupt enable
TMSK2.PAOVI       5   Pulse accumulator overflow interrupt enable
TMSK2.PAII        4   Pulse accumulator input edge interrupt enable
TMSK2.PR1         1   Timer prescaler select bit 1
TMSK2.PR0         0   Timer prescaler select bit 0
TFLG2            0x0025   Timer interrupt flag 2
TFLG2.TOF         7   Timer overflow interrupt flag
TFLG2.RTIF        6   Real time (periodic) interrupt flag
TFLG2.PAOVF       5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF        4   Pulse accumulator input edge interrupt flag
PACTL            0x0026   4 Pulse accumulator control
PACTL.PAEN        6   Pulse accumulator system enable
PACTL.PAMOD       5   Pulse accumulator mode
PACTL.PEDGE       4   Pulse accumulator edge control
PACTL.I4O5        2   Input capture 4/output compare
PACTL.RTR1        1   RTI interrupt rate select 1
PACTL.RTR0        0   RTI interrupt rate select 0
PACNT            0x0027   Pulse accumulator count
SPCR             0x0028   SPI control
SPCR.SPIE         7   Serial peripheral interrupt enable
SPCR.SPE          6   Serial peripheral system enable
SPCR.DWOM         5   Port D wired-OR mode
SPCR.MSTR         4   Master mode select
SPCR.CPOL         3   Clock polarity
SPCR.CPHA         2   Clock phase
SPCR.SPR1         1   SPI clock rate selects
SPCR.SPR0         0   SPI clock rate selects
SPSR             0x0029   SPI status
SPSR.SPIF         7   SPI interrupt complete flag
SPSR.WCOL         6   Write collision
SPSR.MODF         4   Mode fault
SPDR             0x002A   SPI data
Reserv002B       0x002B   Reserved2B
PPAR             0x002C   Port pull-up assignment
PPAR.HPPUE        3   Port H pin pull-up enable
PPAR.GPPUE        2   Port G pin pull-up enable
PPAR.FPPUE        1   Port F pin pull-up enable
PPAR.BPPUE        0   Port B pin pull-up enable
PGAR             0x002D   Port G assignment (PGAR)
PGAR.PGAR5        5   Port G pin assignment 5
PGAR.PGAR4        4   Port G pin assignment 4
PGAR.PGAR3        3   Port G pin assignment 3
PGAR.PGAR2        2   Port G pin assignment 2
PGAR.PGAR1        1   Port G pin assignment 1
PGAR.PGAR0        0   Port G pin assignment 0
Reserv002E       0x002E   Reserved2E
Reserv002F       0x002F   Reserved2E
ADCTL            0x0030   A_D control & status
ADCTL.CCF         7   Conversions complete flag
ADCTL.CONV8       6   Convert 8/convert 4 select bit
ADCTL.SCAN        5   Continuous scan control
ADCTL.MULT        4   Multiple channel/single channel control
ADCTL.CD          3   CD - Channel select bits
ADCTL.CC          2   CC - Channel select bits
ADCTL.CB          1   CB - Channel select bits
ADCTL.CA          0   CA - Channel select bits
F23FCR           0x0031   Compare force for timers 2 and 3
F23FCR.FT3C1      7   Force output 3 compares 1
F23FCR.FT3C2      6   Force output 3 compares 2
F23FCR.FT3C3      5   Force output 3 compares 3
F23FCR.FT3C4      4   Force output 3 compares 4
F23FCR.FT2C1      3   Force output 2 compares 1
F23FCR.FT2C2      2   Force output 2 compares 2
F23FCR.FT2C3      1   Force output 2 compares 3
F23FCR.FT2C4      0   Force output 2 compares 4
ADFRQ            0x0032   A_D frequency select
ADFRQ.ADER        0   A/D frequency select
Reserv0033       0x0033   Reserved33
Reserv0034       0x0034   Reserved34
BPROT            0x0035   Block protect register
BPROT.BULKP       7   Bulk erase of EEPROM protect
BPROT.BIT6        6   BIT6 can be programmed to 0 in the first 64 cycles
BPROT.BPRT4       5   BPRT4 Block protect bits for EEPROM 0x0F80-0x0FFF 128 bytes
BPROT.PTCON       4   Protect for CONFIG register
BPROT.BPRT3       3   BPRT3 Block protect bits for EEPROM 0x0E60-0x0F7F 288 bytes
BPROT.BTRT2       2   BPRT2 Block protect bits for EEPROM 0x0DE0-0x0E5F 128 bytes
BPROT.BTRT1       1   BPRT1 Block protect bits for EEPROM 0x0DA0-0x0DDF 64 bytes
BPROT.BPRT0       0   BPRT0 Block protect bits for EEPROM 0x0D80-0x0D9F 32 bytes
Reserv0036       0x0036   Reserved36
INIT2            0x0037   EEPROM mapping register
INIT2.EE3         7   EEPROM map position 3
INIT2.EE2         6   EEPROM map position 2
INIT2.EE1         5   EEPROM map position 1
INIT2.EE0         4   EEPROM map position 0
OPT2             0x0038   System configuration options register 2
OPT2.LIRDV        7   LIR driven
OPT2.CWOM         6   Port C wired-OR mode
OPT2.IRVNE        4   Internal read visibility/not E
OPT2.LSBF         3   LSB first enable
OPT2.SPR2         2   SPI clock rate select
OPT2.XDV1         1   XOUT clock divide select bit 1
OPT2.XDV0         0   XOUT clock divide select bit 0
OPTION           0x0039   System configuration options register
OPTION.ADPU       7   A/D power-up
OPTION.CSEL       6   Clock select
OPTION.IRQE       5   Configure IRQ for falling-edge-sensitive operation
OPTION.DLY        4   Enable oscillator start-up delay
OPTION.CME        3   Clock monitor enable
OPTION.FCME       2   Force clock monitor enable
OPTION.CR1        1   COP timer rate select bits 1
OPTION.CR0        0   COP timer rate select bits 0
COPRST           0x003A   COP timer arm/reset
PPROG            0x003B   EEPROM programming
PPROG.ODD         7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN        6   Program even rows in half of EEPROM (Test)
PPROG.BYTE        4   EEPROM byte erase mode
PPROG.ROW         3   EEPROM row/bulk erase mode
PPROG.ERASE       2   Erase/normal control for EEPROM
PPROG.EELAT       1   EEPROM latch control
PPROG.EEPGM       0   EEPROM program command
HPRIO            0x003C   Highest priority interrupt
HPRIO.RBOOT       7   Read bootstrap ROM
HPRIO.SMOD        6   Special mode select
HPRIO.MDA         5   Mode select A
HPRIO.PSEL4       4   Priority select bits 4
HPRIO.PSEL3       3   Priority select bits 3
HPRIO.PSEL2       2   Priority select bits 2
HPRIO.PSEL1       1   Priority select bits 1
HPRIO.PSEL0       0   Priority select bits 0
INIT             0x003D   RAM and I/O map register
INIT.RAM3         7   RAM map position bit 3
INIT.RAM2         6   RAM map position bit 2
INIT.RAM1         5   RAM map position bit 1
INIT.RAM0         4   RAM map position bit 0
INIT.REG3         3   160-byte register block position bit 3
INIT.REG2         2   160-byte register block position bit 2
INIT.REG1         1   160-byte register block position bit 1
INIT.REG0         0   160-byte register block position bit 0
TEST1            0x003E   Factory test
TEST1.TILOP       7   Test Illegal Opcode                                
TEST1.OCCR        5   Output Condition Code Register Status to Timer Port
TEST1.CBYP        4   Timer Counter Divider Chain By-pass                
TEST1.DISR        3   Disable Resets from COP and Clock Monitor          
TEST1.FCM         2   Force Clock Monitor Failure                        
TEST1.FCOP        1   Force COP Watchdog Failure                         
CONFIG           0x003F   Configuration control
CONFIG.CLKX       5   XOUT enable
CONFIG.PAREN      4   Pull-up assignment register enable
CONFIG.NOSEC      3   EEPROM security disabled
CONFIG.NOCOP      2   COP system disable
CONFIG.EEON       0   EEPROM enable
ADR1H            0x0040   A/D result 1 high
ADR1L            0x0041   A/D result 1 low
ADR2H            0x0042   A/D result 2 high
ADR2L            0x0043   A/D result 2 low
ADR3H            0x0044   A/D result 3 high
ADR3L            0x0045   A/D result 3 low
ADR4H            0x0046   A/D result 4 high
ADR4L            0x0047   A/D result 4 low
ADR5H            0x0048   A/D result 5 high
ADR5L            0x0049   A/D result 5 low
ADR6H            0x004A   A/D result 6 high
ADR6L            0x004B   A/D result 6 low
ADR7H            0x004C   A/D result 7 high
ADR7L            0x004D   A/D result 7 low
ADR8H            0x004E   A/D result 8 high
ADR8L            0x004F   A/D result 8 low
Reserv0050       0x0050   Reserved50
Reserv0051       0x0051   Reserved51
Reserv0052       0x0052   Reserved52
Reserv0053       0x0053   Reserved53
Reserv0054       0x0054   Reserved54
Reserv0055       0x0055   Reserved55
MMSIZ            0x0056   Memory mapping window size
MMSIZ.MXGS2       7   Memory expansion select for general-purpose chip select 1
MMSIZ.MXGS1       6   Memory expansion select for general-purpose chip select 2
MMSIZ.W2SZ1       5   Window 2 size 1
MMSIZ.W2SZ0       4   Window 2 size 0
MMSIZ.W1SZ1       1   Window 1 size 1
MMSIZ.W1SZ0       0   Window 1 size 0
MMWBR            0x0057   Memory mapping window base
MMWBR.W2A15       7   Window 2 base address 5
MMWBR.W2A14       6   Window 2 base address 4
MMWBR.W2A13       5   Window 2 base address 3
MMWBR.W1A15       3   Window base 1 address 5
MMWBR.W1A14       2   Window base 1 address 4
MMWBR.W1A13       1   Window base 1 address 3
MM1CR            0x0058   Memory mapping window 1 control
MM1CR.X1A18       6
MM1CR.X1A17       5
MM1CR.X1A16       4
MM1CR.X1A15       3
MM1CR.X1A14       2
MM1CR.X1A13       1
MM2CR            0x0059   Memory mapping window 2 control
MM2CR.X2A18       6
MM2CR.X2A17       5
MM2CR.X2A16       4
MM2CR.X2A15       3
MM2CR.X2A14       2
MM2CR.X2A13       1
CSCSTR           0x005A   Chip select clock stretch
CSCSTR.IOSA       7   CSIO stretch select A
CSCSTR.IOSB       6   CSIO stretch select B
CSCSTR.GP1SA      5   CSGP1 stretch select A
CSCSTR.GP1SB      4   CSGP1 stretch select B
CSCSTR.GP2SA      3   CSGP2 stretch select A
CSCSTR.GP2SB      2   CSGP2 stretch select B
CSCSTR.PCSA       1   CSPROG stretch select A
CSCSTR.PCSB       0   CSPROG stretch select B
CSCTL            0x005B   Chip select control
CSCTL.IOEN        7   I/O chip select enable
CSCTL.IOPL        6   I/O chip select polarity select
CSCTL.IOCSA       5   I/O chip select address valid
CSCTL.IOSZ        4   I/O chip select size select
CSCTL.GCSPR       3   General-purpose chip select priority
CSCTL.PCSEN       2   Program chip select enable
CSCTL.PCSZA       1   Program chip select size A
CSCTL.PCSZB       0   Program chip select size B
GPCS1A           0x005C   Gen. purpose chip select 1 addr.
GPCS1A.G1A18      7   General-purpose chip select 1 address 18
GPCS1A.G1A17      6   General-purpose chip select 1 address 17
GPCS1A.G1A16      5   General-purpose chip select 1 address 16
GPCS1A.G1A15      4   General-purpose chip select 1 address 15
GPCS1A.G1A14      3   General-purpose chip select 1 address 14
GPCS1A.G1A13      2   General-purpose chip select 1 address 13
GPCS1A.G1A12      1   General-purpose chip select 1 address 12
GPCS1A.G1A11      0   General-purpose chip select 1 address 11
GPCS1C           0x005D   Gen. purpose chip select 1 con.
GPCS1C.G1DG2      7   General-purpose chip select 1 drives general-purpose chip select 2
GPCS1C.G1DPC      6   General-purpose chip select 1 drives program chip select
GPCS1C.G1POL      5   General-purpose chip select 1 polarity select
GPCS1C.G1AV       4   General-purpose chip select 1 address valid select
GPCS1C.G1SZA      3   GP chip select 1 size A
GPCS1C.G1SZB      2   GP chip select 1 size B
GPCS1C.G1SZC      1   GP chip select 1 size C
GPCS1C.G1SZD      0   GP chip select 1 size D
GPCS2A           0x005E   Gen. purpose chip select 2 addr.
GPCS2A.G2A18      7   General-purpose chip select 2 address 18
GPCS2A.G2A17      6   General-purpose chip select 2 address 17
GPCS2A.G2A16      5   General-purpose chip select 2 address 16
GPCS2A.G2A15      4   General-purpose chip select 2 address 15
GPCS2A.G2A14      3   General-purpose chip select 2 address 14
GPCS2A.G2A13      2   General-purpose chip select 2 address 13
GPCS2A.G2A12      1   General-purpose chip select 2 address 12
GPCS2A.G2A11      0   General-purpose chip select 2 address 11
GPCS2C           0x005F   Gen. purpose chip select 2 con.
GPCS2C.G2DPC      6   General-purpose chip select 2 drives program chip select
GPCS2C.G2POL      5   General-purpose chip select 2 polarity select
GPCS2C.G2AV       4   General-purpose chip select 2 address valid select
GPCS2C.G2SZA      3   General-purpose chip select 2 size A
GPCS2C.G2SZB      2   General-purpose chip select 2 size B
GPCS2C.G2SZC      1   General-purpose chip select 2 size C
GPCS2C.G2SZD      0   General-purpose chip select 2 size D
PWCLK            0x0060   Pulse width clock select
PWCLK.CON34       7   Concatenate channels 3 and 4
PWCLK.CON12       6   Concatenate Channels 1 and 2
PWCLK.PCKA2       5   Prescaler for clock A 2
PWCLK.PCKA1       4   Prescaler for clock A 1
PWCLK.PCKB3       2   Prescaler for clock B 3
PWCLK.PCKB2       1   Prescaler for clock B 2
PWCLK.PCKB1       0   Prescaler for clock B 1
PWPOL            0x0061   Pulse width polarity select
PWPOL.PCLK4       7   Pulse width channel 4 clock select
PWPOL.PCLK3       6   Pulse width channel 3 clock select
PWPOL.PCLK2       5   Pulse width channel 2 clock select
PWPOL.PCLK1       4   Pulse width channel 1 clock select
PWPOL.PPOL4       3   Pulse width channel 4 polarity
PWPOL.PPOL3       2   Pulse width channel 3 polarity
PWPOL.PPOL2       1   Pulse width channel 2 polarity
PWPOL.PPOL1       0   Pulse width channel 1 polarity
PWSCAL           0x0062   Pulse width scale
PWEN             0x0063   Pulse width enable
PWEN.TPWSL        7   PWM scaled clock test bit (Test mode only)
PWEN.DISCP        6   Disable compare scaled E clock (Test mode only)
PWEN.PWEN4        3   Pulse width channels 4
PWEN.PWEN3        2   Pulse width channels 3
PWEN.PWEN2        1   Pulse width channels 2
PWEN.PWEN1        0   Pulse width channels 1
PWCNT1           0x0064   Pulse width count 1 
PWCNT2           0x0065   Pulse width count 2 
PWCNT3           0x0066   Pulse width count 3 
PWCNT4           0x0067   Pulse width count 4 
PWPER1           0x0068   4 Pulse width period 1
PWPER2           0x0069   Pulse width period 2
PWPER3           0x006A   Pulse width period 3
PWPER4           0x006B   Pulse width period 4
PWDTY1           0x006C   Pulse width duty 1
PWDTY2           0x006D   Pulse width duty 2
PWDTY3           0x006E   Pulse width duty 3
PWDTY4           0x006F   Pulse width duty 4
SCBDH            0x0070   SCI baud rate high
SCBDH.BTST        7   Baud register test (Test mode only)
SCBDH.BSPL        6   Baud rate counter split (Test mode only)
SCBDH.SYNC        5   Baud rate counter reset and sync (Test mode only)
SCBDH.SBR12       4   SCI baud rate selects 12
SCBDH.SBR11       3   SCI baud rate selects 11
SCBDH.SBR10       2   SCI baud rate selects 10
SCBDH.SBR9        1   SCI baud rate selects 9
SCBDH.SBR8        0   SCI baud rate selects 8
SCBDL            0x0071   SCI baud rate low
SCBDL.SBR7        7   SCI baud rate selects 7
SCBDL.SBR6        6   SCI baud rate selects 6
SCBDL.SBR5        5   SCI baud rate selects 5
SCBDL.SBR4        4   SCI baud rate selects 4
SCBDL.SBR3        3   SCI baud rate selects 3
SCBDL.SBR2        2   SCI baud rate selects 2
SCBDL.SBR1        1   SCI baud rate selects 1
SCBDL.SBR0        0   SCI baud rate selects 0
SCCR1            0x0072   SCI control 1
SCCR1.LOOPS       7   SCI loop mode enable
SCCR1.WOMS        6   Wired-OR mode for SCI pins (PD1, PD0)
SCCR1.M           4   Mode (select character format)
SCCR1.WAKE        3   Wake-up by address mark/idle
SCCR1.ILT         2   Idle line type
SCCR1.PE          1   Parity enable
SCCR1.PT          0   Parity type
SCCR2            0x0073   SCI control 2
SCCR2.TIE         7   Transmit interrupt enable
SCCR2.TCIE        6   Transmit complete interrupt enable
SCCR2.RIE         5   Receiver interrupt enable
SCCR2.ILIE        4   Idle line interrupt enable
SCCR2.TE          3   Transmitter enable
SCCR2.RE          2   Receiver enable
SCCR2.RWU         1   Receiver wake-up control
SCCR2.SBK         0   Send break
SCSR1            0x0074   SCI status 1
SCSR1.TDRE        7   Transmit data register empty flag
SCSR1.TC          6   Transmit complete flag
SCSR1.RDRF        5   Receive data register full flag
SCSR1.IDEL        4   Idle line detected flag
SCSR1.OR          3   Overrun error flag
SCSR1.NF          2   Noise error flag
SCSR1.FE          1   Framing error
SCSR1.PF          0   Parity error flag
SCSR2            0x0075   SCI status 2
SCSR2.RAF         0   Receiver active flag (read only)
SCDRH            0x0076   SCI data high
SCDRH.R8          7   Receiver bit 8
SCDRH.T8          6   Transmitter bit 8
SCDRL            0x0077   SCI data low
SCDRL.R7T7        7   Receiver/transmitter data bits 7
SCDRL.R6T6        6   Receiver/transmitter data bits 6
SCDRL.R5T5        5   Receiver/transmitter data bits 5
SCDRL.R4T4        4   Receiver/transmitter data bits 4
SCDRL.R3T3        3   Receiver/transmitter data bits 3
SCDRL.R2T2        2   Receiver/transmitter data bits 2
SCDRL.R1T1        1   Receiver/transmitter data bits 1
SCDRL.R0T0        0   Receiver/transmitter data bits 0
Reserv0078       0x0078   Reserved78
Reserv0079       0x0079   Reserved79
Reserv007A       0x007A   Reserved7A
Reserv007B       0x007B   Reserved7B
PORTH            0x007C   Port H data (ALT - Chip selects and PWM)
PORTH.PH7_CSPROG  7   Port H Data Bit 7
PORTH.PH6_CSGP2   6   Port H Data Bit 6
PORTH.PH5_CSGP1   5   Port H Data Bit 5
PORTH.PH4_CSIO    4   Port H Data Bit 4
PORTH.PH3_PWM4    3   Port H Data Bit 3
PORTH.PH2_PWM3    2   Port H Data Bit 2
PORTH.PH1_PWM2    1   Port H Data Bit 1
PORTH.PH0_PWM1    0   Port H Data Bit 0
DDRH             0x007D   Data direction H
DDRH.DDH7         7   Data Direction for Port H Bit 7
DDRH.DDH6         6   Data Direction for Port H Bit 6
DDRH.DDH5         5   Data Direction for Port H Bit 5
DDRH.DDH4         4   Data Direction for Port H Bit 4
DDRH.DDH3         3   Data Direction for Port H Bit 3
DDRH.DDH2         2   Data Direction for Port H Bit 2
DDRH.DDH1         1   Data Direction for Port H Bit 1
DDRH.DDH0         0   Data Direction for Port H Bit 0
PORTG            0x007E   Port G data (ALT - Memory expansion and A/D converter)
PORTG.PG7_AN1     7   Port G Data Bit 7
PORTG.PG6_AN0     6   Port G Data Bit 6
PORTG.PG5_XA18    5   Port G Data Bit 5
PORTG.PG4_XA17    4   Port G Data Bit 4
PORTG.PG3_XA16    3   Port G Data Bit 3
PORTG.PG2_XA15    2   Port G Data Bit 2
PORTG.PG1_XA14    1   Port G Data Bit 1
PORTG.PG0_XA13    0   Port G Data Bit 0
DDRG             0x007F   Data direction G
DDRG.DDG5         5   Data Direction for Port G Bit 5
DDRG.DDG4         4   Data Direction for Port G Bit 4
DDRG.DDG3         3   Data Direction for Port G Bit 3
DDRG.DDG2         2   Data Direction for Port G Bit 2
DDRG.DDG1         1   Data Direction for Port G Bit 1
DDRG.DDG0         0   Data Direction for Port G Bit 0
TCTL3            0x0080   Timer control register 3
TCTL3.OM1         7   Output mode 1
TCTL3.OL1         6   Output level 1
TCTL3.OM2         5   Output mode 2
TCTL3.OL2         4   Output level 2
TCTL3.OM3         3   Output mode 3
TCTL3.OL3         2   Output level 3
TCTL3.OM4         1   Output mode 4
TCTL3.OL4         0   Output level 4
TCTL4            0x0081   Timer control register 4 TCTL4
TCTL4.EDGB        7   Input capture edge control bit B
TCTL4.EDGA        6   Input capture edge control bit A
TCTL4.PR2B        5   Timer 2 prescaler select bit B
TCTL4.PR2A        4   Timer 2 prescaler select bit A
TCTL4.ECEB        3   Event counter edge control bit B
TCTL4.ECEA        2   Event counter edge control bit A
TCTL4.T2STP       1   Stop Timer 2 counter
TCTL4.I1_O4       0   Input capture 1/output compare 4
TCNT2H           0x0082   Timer 2 counter register high
TCNT2L           0x0083   Timer 2 counter register low
T2OC1H           0x0084   Timer 2 output compare 1 high
T2OC1L           0x0085   Timer 2 output compare 1 low
T2OC2H           0x0086   Timer 2 output comp. 2 high
T2OC2L           0x0087   Timer 2 output comp. 2 low
T2OC3H           0x0088   Timer 2 output comp. 3 high
T2OC3L           0x0089   Timer 2 output comp. 3 low
T2C4H            0x008A   Timer 2 channel 4 high
T2C4L            0x008B   Timer 2 channel 4 low
T2MSK            0x008C   Timer 2 mask
T2MSK.OC1I        7   Output compare 1 interrupt enable
T2MSK.OC2I        6   Output compare 2 interrupt enable
T2MSK.OC3I        5   Output compare 3 interrupt enable
T2MSK.C4I         4   Input capture 1/output compare 4 interrupt enable
T2MSK.TO2I        3   Timer 2 overflow interrupt enable
T2FLG            0x008D   Timer 2 flag
T2FLG.OC1F        7   Output compare 1 flag
T2FLG.OC2F        6   Output compare 2 flag
T2FLG.OC3F        5   Output compare 3 flag
T2FLG.C4F         4   Input capture 1/output compare 4 flag
T2FLG.TO2F        3   Timer 2 overflow flag
PORTJ            0x008E   Port J data (ALT - Timer 2)
PORTJ.PJ7_C4      7   Port J Data Bit 7
PORTJ.PJ6_OC3     6   Port J Data Bit 6
PORTJ.PJ5_OC2     5   Port J Data Bit 5
PORTJ.PJ4_OC1     4   Port J Data Bit 4
PORTJ.PJ3_ECIN    3   Port J Data Bit 3
PORTJ.PJ2         2   Port J Data Bit 2
PORTJ.PJ1         1   Port J Data Bit 1
PORTJ.PJ0         0   Port J Data Bit 0
DDRJ             0x008F   Data direction J
DDRJ.DDJ7         7   Data Direction for Port J Bit 7
DDRJ.DDJ6         6   Data Direction for Port J Bit 6
DDRJ.DDJ5         5   Data Direction for Port J Bit 5
DDRJ.DDJ4         4   Data Direction for Port J Bit 4
DDRJ.DDJ3         3   Data Direction for Port J Bit 3
DDRJ.DDJ2         2   Data Direction for Port J Bit 2
DDRJ.DDJ1         1   Data Direction for Port J Bit 1
DDRJ.DDJ0         0   Data Direction for Port J Bit 0
TCTL5            0x0090   Timer control register 5
TCTL5.OM1         7   Output mode 1
TCTL5.OL1         6   Output level 1
TCTL5.OM2         5   Output mode 2
TCTL5.OL2         4   Output level 2
TCTL5.OM3         3   Output mode 3
TCTL5.OL3         2   Output level 3
TCTL5.OM4         1   Output mode 4
TCTL5.OL4         0   Output level 4
TCTL6            0x0091   Timer control register 6 TCTL6
TCTL6.EDGB        7   Input capture edge control bit B
TCTL6.EDGA        6   Input capture edge control bit A
TCTL6.PR3B        5   Timer 3 prescaler select bit B
TCTL6.PR3A        4   Timer 3 prescaler select bit A
TCTL6.ECEB        3   Event counter edge control bit B
TCTL6.ECEA        2   Event counter edge control bit A
TCTL6.T3STP       1   Stop Timer 3 counter
TCTL6.I4_O4       0   Input capture 4/output compare 4
TCNT3H           0x0092   Timer 3 counter high
TCNT3L           0x0093   Timer 3 counter low
T3OC1H           0x0094   Timer 3 output compare 1 high
T3OC1L           0x0095   Timer 3 output compare 1 low
T3OC2H           0x0096   Timer 3 output compare 2 high
T3OC2L           0x0097   Timer 3 output compare 2 low
T3OC3H           0x0098   Timer 3 output comp. 3 high
T3OC3L           0x0099   Timer 3 output comp. 3 low
T3C4H            0x009A   Timer 3 channel 4 high
T3C4L            0x009B   Timer 3 channel 4 low
T3MSK            0x009C   Timer 3 mask
T3MSK.OC1I        7   Output compare 1 interrupt enable
T3MSK.OC2I        6   Output compare 2 interrupt enable
T3MSK.OC3I        5   Output compare 3 interrupt enable
T3MSK.C4I         4   Input capture 1/output compare 4 interrupt enable
T3MSK.TO3I        3   Timer 3 overflow interrupt enable
T3FLG            0x009D   Timer 3 flag
T3FLG.OC1F        7   Output compare 1 flag
T3FLG.OC2F        6   Output compare 2 flag
T3FLG.OC3F        5   Output compare 3 flag
T3FLG.C4F         4   Input capture 1/output compare 4flag
T3FLG.TO3F        3   Timer 3 overflow flag
PORTK            0x009E   Port K data (ALT - Timer 3)
PORTK.PK7_C4      7   Port K Data Bit 7
PORTK.PK6_OC3     6   Port K Data Bit 6
PORTK.PK5_OC2     5   Port K Data Bit 5
PORTK.PK4_OC1     4   Port K Data Bit 4
PORTK.PK3_ECIN    3   Port K Data Bit 3
PORTK.PK2         2   Port K Data Bit 2
PORTK.PK1         1   Port K Data Bit 1
PORTK.PK0         0   Port K Data Bit 0
DDRK             0x009F   Data direction K
DDRK.DDK7         7   Data Direction for Port K Bit 7
DDRK.DDK6         6   Data Direction for Port K Bit 6
DDRK.DDK5         5   Data Direction for Port K Bit 5
DDRK.DDK4         4   Data Direction for Port K Bit 4
DDRK.DDK3         3   Data Direction for Port K Bit 3
DDRK.DDK2         2   Data Direction for Port K Bit 2
DDRK.DDK1         1   Data Direction for Port K Bit 1
DDRK.DDK0         0   Data Direction for Port K Bit 0
RESERVFFC0       0xFFC0   RESERVED
RESERVFFC1       0xFFC1   RESERVED
RESERVFFC2       0xFFC2   RESERVED
RESERVFFC3       0xFFC3   RESERVED
RESERVFFC4       0xFFC4   RESERVED
RESERVFFC5       0xFFC5   RESERVED
RESERVFFC6       0xFFC6   RESERVED
RESERVFFC7       0xFFC7   RESERVED
RESERVFFC8       0xFFC8   RESERVED
RESERVFFC9       0xFFC9   RESERVED
RESERVFFCA       0xFFCA   RESERVED
RESERVFFCB       0xFFCB   RESERVED


.68HC11L0
; http://

; RAM=512
; ROM=0
; EPROM=0
; EEPROM=0

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS


.68HC11L1
; http://

; RAM=512
; ROM=0
; EPROM=0
; EEPROM=512

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS



.68HC11L5
; http://

; RAM=512
; ROM=16K
; EPROM=0
; EEPROM=0

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS


.68HC11L6
; MC68HC11L6/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11L6.pdf
; HC11L6.pdf

; RAM=512
; ROM=16K
; EPROM=0  
; EEPROM=512


; MEMORY MAP
area DATA RAM         0x0000:0x0200
area BSS  RESERVED    0x0200:0x1000
area DATA FSR         0x1000:0x1040
area BSS  RESERVED    0x1040:0xB600
area DATA EEPROM      0xB600:0xB800
area BSS  RESERVED    0xB800:0xC000
area DATA ROM         0xC000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET   0xFFFE   Processor reset
interrupt CME       0xFFFC   Clock Monitor Fail
interrupt NOCOP     0xFFFA   COP Failure
interrupt OPC       0xFFF8   Illegal Opcode Trap
interrupt SOFT      0xFFF6   Software Interrupt
interrupt XIRQ      0xFFF4   XIRQ Pin
interrupt IRQ       0xFFF2   IRQ
interrupt RTII      0xFFF0   Real Time Interrupt
interrupt IC1I      0xFFEE   Timer Input Capture 1
interrupt IC2I      0xFFEC   Timer Input Capture 2
interrupt IC3I      0xFFEA   Timer Input Capture 3
interrupt OC1I      0xFFE8   Timer Output Compare 1
interrupt OC2I      0xFFE6   Timer Output Compare 2
interrupt OC3I      0xFFE4   Timer Output Compare 3
interrupt OC4I      0xFFE2   Timer Output Compare 4
interrupt I4_I5     0xFFE0   Timer Input Capture 4 / Output Compare 5
interrupt TOI       0xFFDE   Timer Overflow
interrupt PAOVI     0xFFDC   Pulse Accumulator Overflow
interrupt PAII      0xFFDA   Pulse Accumulator Input Edge
interrupt SPIE      0xFFD8   SPI Serial Transfer Complete
interrupt SCISS     0xFFD6   SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x1000   Port A data
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
RESERVED01     0x1001   RESERVED01
PIOC           0x1002   Parallel I_O Control Register
PIOC.STAF       7   Strobe A Interrupt Status Flag
PIOC.STAI       6   Strobe A Interrupt Enable Mask
PIOC.CWOM       5   Port C Wired-OR Mode (affects all eight port C pins)
PIOC.HNDS       4   Handshake Mode
PIOC.OIN        3   Output or Input Handshake Select
PIOC.PLS        2   Pulsed/Interlocked Handshake Operation
PIOC.EGA        1   Active Edge for Strobe A
PIOC.INVB       0   Invert Strobe B
PORTC          0x1003   I_O Port C
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
PORTB          0x1004   Output Port B
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTCL         0x1005   Alternate Latched Port C
PORTCL.PCL7     7
PORTCL.PCL6     6
PORTCL.PCL5     5
PORTCL.PCL4     4
PORTCL.PCL3     3
PORTCL.PCL2     2
PORTCL.PCL1     1
PORTCL.PCL0     0
RESERVED06     0x1006   RESERVED06
DDRC           0x1007   Data Direction for Port C
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x1008   I_O Port D
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x1009   Data Direction for Port D
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x100A   Input Port E
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x100B   Compare Force Register
CFORC.FOC1      7   Write Ones to Force Compare 1
CFORC.FOC2      6   Write Ones to Force Compare 2
CFORC.FOC3      5   Write Ones to Force Compare 3
CFORC.FOC4      4   Write Ones to Force Compare 4
CFORC.FOC5      3   Write Ones to Force Compare 5
OC1M           0x100C   OC1 Action Mask Register
OC1M.OC1M7      7   Output Compare Masks 7
OC1M.OC1M6      6   Output Compare Masks 6
OC1M.OC1M5      5   Output Compare Masks 5
OC1M.OC1M4      4   Output Compare Masks 4
OC1M.OC1M3      3   Output Compare Masks 3
OC1D           0x100D    OC1 Action Data Register
OC1D.OC1D7      7   Output compare data 7
OC1D.OC1D6      6   Output compare data 6
OC1D.OC1D5      5   Output compare data 5
OC1D.OC1D4      4   Output compare data 4
OC1D.OC1D3      3   Output compare data 3
TCNTH          0x100E   Timer Counter Register (High)
TCNTL          0x100F   Timer Counter Register (Low)
TIC1H          0x1010   Input Capture 1 Register (High)
TIC1L          0x1011   Input Capture 1 Register (Low) 
TIC2H          0x1012   Input Capture 2 Register (High)
TIC2L          0x1013   Input Capture 2 Register (Low) 
TIC3H          0x1014   Input Capture 3 Register (High)
TIC3L          0x1015   Input Capture 3 Register (Low) 
TOC1H          0x1016   Output Compare 1 Register (High)
TOC1L          0x1017   Output Compare 1 Register (Low) 
TOC2H          0x1018   Output Compare 2 Register (High)
TOC2L          0x1019   Output Compare 2 Register (Low) 
TOC3H          0x101A   Output Compare 3 Register (High)
TOC3L          0x101B   Output Compare 3 Register (Low) 
TOC4H          0x101C   Output Compare 4 Register (High)
TOC4L          0x101D   Output Compare 4 Register (Low) 
TI4_O5H        0x101E   Timer Input Capture 4/Output Compare 5 (High)
TI4_O5L        0x101F   Timer Input Capture 4/Output Compare 5 (Low) 
TCTL1          0x1020   Timer Control Register 1
TCTL1.OM2       7   Output Mode 2
TCTL1.OL2       6   Output Level 2
TCTL1.OM3       5   Output Mode 3
TCTL1.OL3       4   Output Level 3
TCTL1.OM4       3   Output Mode 4
TCTL1.OL4       2   Output Level 4
TCTL1.OM5       1   Output Mode 5
TCTL1.OL5       0   Output Level 5
TCTL2          0x1021   Timer Control Register 2
TCTL2.EDG4B     7   Input Capture Edge Control 4B
TCTL2.EDG4A     6   Input Capture Edge Control 4A
TCTL2.EDG1B     5   Input Capture Edge Control 1B
TCTL2.EDG1A     4   Input Capture Edge Control 1A
TCTL2.EDG2B     3   Input Capture Edge Control 2B
TCTL2.EDG2A     2   Input Capture Edge Control 2A
TCTL2.EDG3B     1   Input Capture Edge Control 3B
TCTL2.EDG3A     0   Input Capture Edge Control 3A
TMSK1          0x1022   Timer Interrupt Mask Register 1
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable
TMSK1.I4_O5I    3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x1023   Timer Interrupt Flag Register 1
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x1024   Timer Interrupt Mask Register 2
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1       1   Timer Prescaler Select 1
TMSK2.PR0       0   Timer Prescaler Select 0
TFLG2          0x1025   Timer Interrupt Flag Register 2
TFLG2.TOF       7   Timer Overflow Interrupt Flag
TFLG2.RTIF      6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF      4   Pulse Accumulator Input Edge Interrupt Flag
PACTL          0x1026   Pulse Accumulator Control Register
PACTL.DDRA7     7   Data Direction for Port A Bit 7
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.DDRA3     3   Data Direction for Port A Bit 3
PACTL.I4_O5     2   Input Capture 4/Output Compare 5
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x1027   Pulse Accumulator Count Register
SPCR           0x1028   SPI Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable
SPCR.DWOM       5   Port D Wired-OR Mode
SPCR.MSTR       4   Master Mode Select
SPCR.CPOL       3   Clock Polarity
SPCR.CPHA       2   Clock Phase
SPCR.SPR1       1   SPI Clock Rate Selects 1
SPCR.SPR0       0   SPI Clock Rate Selects 0
SPSR           0x1029   SPI Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision
SPSR.MODF       4   Mode Fault
SPDR           0x102A   SPI Data Register
BAUD           0x102B   SCI Baud Rate Control 3
BAUD.TCLR       7   Clear Baud Rate Counters (Test)
BAUD.SCP1       5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0       4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB       3   SCI Baud Rate Clock Check (Test)
BAUD.SCR2       2   SCI Baud Rate Selects 2
BAUD.SCR1       1   SCI Baud Rate Selects 1
BAUD.SCR0       0   SCI Baud Rate Selects 0
SCCR1          0x102C   SCI Control Register 1
SCCR1.R8        7   Receive Data Bit 8
SCCR1.T8        6   Transmit Data Bit 8
SCCR1.M         4   Mode (Select Character Format)
SCCR1.WAKE      3   Wakeup by Address Mark/Idle
SCCR2          0x102D   SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable
SCCR2.TCIE      6   Transmit Complete Interrupt Enable
SCCR2.RIE       5   Receiver Interrupt Enable
SCCR2.ILIE      4   Idle Line Interrupt Enable
SCCR2.TE        3   Transmitter Enable
SCCR2.RE        2   Receiver Enable
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break
SCSR           0x102E   SCI Status Register
SCSR.TDRE       7   Transmit Data Register Empty Flag
SCSR.TC         6   Transmit Complete Flag
SCSR.RDRF       5   Receive Data Register Full Flag
SCSR.IDLE       4   Idle Line Detected Flag
SCSR.OR         3   Overrun Error Flag
SCSR.NF         2   Noise Error Flag
SCSR.FE         1   Framing Error
SCDR           0x102F   SCI Data (Read RDR, Write TDR)
SCDR.R7T7       7   Receiver/transmitter data bits 7
SCDR.R6T6       6   Receiver/transmitter data bits 6
SCDR.R5T5       5   Receiver/transmitter data bits 5
SCDR.R4T4       4   Receiver/transmitter data bits 4
SCDR.R3T3       3   Receiver/transmitter data bits 3
SCDR.R2T2       2   Receiver/transmitter data bits 2
SCDR.R1T1       1   Receiver/transmitter data bits 1
SCDR.R0T0       0   Receiver/transmitter data bits 0
ADCTL          0x1030   A_D Control Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control
ADCTL.MULT      4   Multiple-Channel/Single-Channel Control
ADCTL.CD        3   Channel Selects D
ADCTL.CC        2   Channel Selects C
ADCTL.CB        1   Channel Selects B
ADCTL.CA        0   Channel Selects A
ADR1           0x1031   A_D Result Register 1
ADR2           0x1032   A_D Result Register 2
ADR3           0x1033   A_D Result Register 3
ADR4           0x1034   A_D Result Register 4
BPROT          0x1035   Block Protect Register
BPROT.PTCON     4   Protect CONFIG Register
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
PORTG          0x1036   Port G data
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6
PORTG.PG5       5   Port G Data Bit 5
PORTG.PG4       4   Port G Data Bit 4
PORTG.PG3       3   Port G Data Bit 3
PORTG.PG2       2   Port G Data Bit 2
PORTG.PG1       1   Port G Data Bit 1
PORTG.PG0       0   Port G Data Bit 0
DDRG           0x1037   Data direction G
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6
DDRG.DDG5       5   Data Direction for Port G Bit 5
DDRG.DDG4       4   Data Direction for Port G Bit 4
DDRG.DDG3       3   Data Direction for Port G Bit 3
DDRG.DDG2       2   Data Direction for Port G Bit 2
DDRG.DDG1       1   Data Direction for Port G Bit 1
DDRG.DDG0       0   Data Direction for Port G Bit 0
RESERVED38     0x1038   RESERVED38
OPTION         0x1039   System Configuration Options
OPTION.ADPU     7   Analog-to-Digital Converter Power-Up
OPTION.CSEL     6   Clock Select
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Only Operation
OPTION.DLY      4   Enable Oscillator Startup Delay
OPTION.CME      3   Clock Monitor Enable
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x103A   Arm_Reset COP Timer Circuitry
PPROG          0x103B   EEPROM Program Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM (Test)
PPROG.EVEN      6   Program Even Rows in Half of EEPROM (Test)
PPROG.BYTE      4   Byte/Erase Select
PPROG.ROW       3   Row/All Erase Select
PPROG.ERASE     2   Erase Mode Select
PPROG.EELAT     1   EEPROM Latch Control
PPROG.EEPGM     0   EEPROM Program Command
HPRIO          0x103C   Highest Priority I-Bit Int and Misc
HPRIO.RBOOT     7   Read Bootstrap ROM
HPRIO.SMOD      6   Special Mode Select
HPRIO.MDA       5   Mode Select A
HPRIO.IRV       4   Internal Read Visibility/Not E
HPRIO.PSEL3     3   Priority Select Bit 3
HPRIO.PSEL2     2   Priority Select Bit 2
HPRIO.PSEL1     1   Priority Select Bit 1
HPRIO.PSEL0     0   Priority Select Bit 0
INIT           0x103D   RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position 3
INIT.RAM2       6   RAM Map Position 2
INIT.RAM1       5   RAM Map Position 1
INIT.RAM0       4   RAM Map Position 0
INIT.REG3       3   64-Byte Register Block Position 3
INIT.REG2       2   64-Byte Register Block Position 2
INIT.REG1       1   64-Byte Register Block Position 1
INIT.REG0       0   64-Byte Register Block Position 0
TEST1          0x103E   Factory TEST Control Register
TEST1.TILOP     7   Test Illegal Opcode                                
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass                
TEST1.DISR      3   Disable Resets from COP and Clock Monitor          
TEST1.FCM       2   
TEST1.FCOP      1   
TEST1.TCON      0
CONFIG         0x103F   COP, ROM, and EEPROM Enables
CONFIG.NOSEC    3   Security Disable
CONFIG.NOCOP    2   COP System Disable
CONFIG.ROMON    1   ROM Enable
CONFIG.EEON     0   EEPROM Enable
RESERVFFC0     0xFFC0   RESERVED
RESERVFFC1     0xFFC1   RESERVED
RESERVFFC2     0xFFC2   RESERVED
RESERVFFC3     0xFFC3   RESERVED
RESERVFFC4     0xFFC4   RESERVED
RESERVFFC5     0xFFC5   RESERVED
RESERVFFC6     0xFFC6   RESERVED
RESERVFFC7     0xFFC7   RESERVED
RESERVFFC8     0xFFC8   RESERVED
RESERVFFC9     0xFFC9   RESERVED
RESERVFFCA     0xFFCA   RESERVED
RESERVFFCB     0xFFCB   RESERVED
RESERVFFCC     0xFFCC   RESERVED
RESERVFFCD     0xFFCD   RESERVED
RESERVFFCE     0xFFCE   RESERVED
RESERVFFCF     0xFFCF   RESERVED
RESERVFFD0     0xFFD0   RESERVED
RESERVFFD1     0xFFD1   RESERVED
RESERVFFD2     0xFFD2   RESERVED
RESERVFFD3     0xFFD3   RESERVED
RESERVFFD4     0xFFD4   RESERVED
RESERVFFD5     0xFFD5   RESERVED


.68HC11M
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC11M2
; http://

; RAM=1280
; ROM=32K
; EPROM=0
; EEPROM=640

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC11N
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC11N4
; http://

; RAM=768
; ROM=24K
; EPROM=0
; EEPROM=640

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC11P1
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11P1&nodeId=01M98635

; RAM=1024
; ROM=0
; EPROM=0
; EEPROM=640

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC11P2
; MC68HC11P2/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC11P2&nodeId=01M98635
; MC68HC11P2.pdf

; RAM=1K
; ROM=32K
; EPROM=0
; EEPROM=640


; MEMORY MAP
area DATA FSR         0x0000:0x0080
area DATA RAM         0x0080:0x0480
area BSS  RESERVED    0x0480:0x0D80
area DATA EEPROM      0x0D80:0x1000
area BSS  RESERVED    0x1000:0x8000
area CODE ROM         0x8000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       RESET
interrupt CME 		0xFFFC       Clock monitor fail 
interrupt NOCOP 	0xFFFA       COP failure 
interrupt OPCODE 	0xFFF8       Illegal opcode trap 
interrupt SOFT 		0xFFF6       Software interrupt 
interrupt XIRQ 		0xFFF4       XIRQ pin 
interrupt IRQ 		0xFFF2       IRQ pin I None
interrupt RTII 		0xFFF0       Real-time interrupt 
interrupt IC1I 		0xFFEE       Timer input capture 1 
interrupt IC2I 		0xFFEC       Timer input capture 2 
interrupt IC3I 		0xFFEA       Timer input capture 3 
interrupt OC1I 		0xFFE8       Timer output compare 1 
interrupt OC2I 		0xFFE6       Timer output compare 2 
interrupt OC3I 		0xFFE4       Timer output compare 3 
interrupt OC4I 		0xFFE2       Timer output compare 4 
interrupt I4_O5I 	0xFFE0       Timer input capture 4/output compare 5 
interrupt TOI 		0xFFDE       Timer overflow 
interrupt PAOVI 	0xFFDC       Pulse accumulator overflow 
interrupt PAII 		0xFFDA       Pulse accumulator input edge 
interrupt SPIE 		0xFFD8       SPI serial transfer complete 
interrupt SCI1 		0xFFD6       SCI1
interrupt SCI2 		0xFFD4       SCI2
interrupt SCI3 		0xFFD2       SCI3


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Data direction A
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0002    Data direction B
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRF           0x0003    Data direction F
DDRF.DDRF7      7   Data Direction for Port F Bit 7
DDRF.DDRF6      6   Data Direction for Port F Bit 6
DDRF.DDRF5      5   Data Direction for Port F Bit 5
DDRF.DDRF4      4   Data Direction for Port F Bit 4
DDRF.DDRF3      3   Data Direction for Port F Bit 3
DDRF.DDRF2      2   Data Direction for Port F Bit 2
DDRF.DDRF1      1   Data Direction for Port F Bit 1
DDRF.DDRF0      0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B data
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F data
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C data
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Data direction C
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC6      6   Data Direction for Port C Bit 6
DDRC.DDRC5      5   Data Direction for Port C Bit 5
DDRC.DDRC4      4   Data Direction for Port C Bit 4
DDRC.DDRC3      3   Data Direction for Port C Bit 3
DDRC.DDRC2      2   Data Direction for Port C Bit 2
DDRC.DDRC1      1   Data Direction for Port C Bit 1
DDRC.DDRC0      0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D data
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Data direction D
DDRD.DDRD5      5   Data Direction for Port D Bit 5
DDRD.DDRD4      4   Data Direction for Port D Bit 4
DDRD.DDRD3      3   Data Direction for Port D Bit 3
DDRD.DDRD2      2   Data Direction for Port D Bit 2
DDRD.DDRD1      1   Data Direction for Port D Bit 1
DDRD.DDRD0      0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E data
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer compare force
CFORC.FOC1      7   Force output compares 1
CFORC.FOC2      6   Force output compares 2
CFORC.FOC3      5   Force output compares 3
CFORC.FOC4      4   Force output compares 4
CFORC.FOC5      3   Force output compares 5
OC1M           0x000C    Output compare 1 mask
OC1M.OC1M7      7   Output compare masks for OC1 bit 7
OC1M.OC1M6      6   Output compare masks for OC1 bit 6
OC1M.OC1M5      5   Output compare masks for OC1 bit 5
OC1M.OC1M4      4   Output compare masks for OC1 bit 4
OC1M.OC1M3      3   Output compare masks for OC1 bit 3
OC1D           0x000D    Output compare 1 data
OC1D.OC1D7      7   Output compare data for OC1 bit 7
OC1D.OC1D6      6   Output compare data for OC1 bit 6
OC1D.OC1D5      5   Output compare data for OC1 bit 5
OC1D.OC1D4      4   Output compare data for OC1 bit 4
OC1D.OC1D3      3   Output compare data for OC1 bit 3
TCNTH          0x000E    Timer count HIGH
TCNTL          0x000F    Timer count LOW
TIC1H          0x0010    Timer input capture 1 HIGH
TIC1L          0x0011    Timer input capture 1 LOW
TIC2H          0x0012    Timer input capture 2 HIGH
TIC2L          0x0013    Timer input capture 2 LOW
TIC3H          0x0014    Timer input capture 3 HIGH
TIC3L          0x0015    Timer input capture 3 LOW
TOC1H          0x0016    Timer output compare 1 HIGH
TOC1L          0x0017    Timer output compare 1 LOW
TOC2H          0x0018    Timer output compare 2 HIGH
TOC2L          0x0019    Timer output compare 2 LOW
TOC3H          0x001A    Timer output compare 3 HIGH
TOC3L          0x001B    Timer output compare 3 LOW
TOC4H          0x001C    Timer output compare 4 HIGH
TOC4L          0x001D    Timer output compare 4 LOW
TI4_O5H        0x001E    Capture 4/compare 5 HIGH
TI4_O5L        0x001F    Capture 4/compare 5 LOW
TCTL1          0x0020    Timer control 1
TCTL1.OM2       7   Output mode 2
TCTL1.OL2       6   Output level 2
TCTL1.OM3       5   Output mode 3
TCTL1.OL3       4   Output level 3
TCTL1.OM4       3   Output mode 4
TCTL1.OL4       2   Output level 4
TCTL1.OM5       1   Output mode 5
TCTL1.OL5       0   Output level 5
TCTL2          0x0021    Timer control 2
TCTL2.EDG4B     7   Input capture edge control 4B
TCTL2.EDG4A     6   Input capture edge control 4A
TCTL2.EDG1B     5   Input capture edge control 1B
TCTL2.EDG1A     4   Input capture edge control 1A
TCTL2.EDG2B     3   Input capture edge control 2B
TCTL2.EDG2A     2   Input capture edge control 2A
TCTL2.EDG3B     1   Input capture edge control 3B
TCTL2.EDG3A     0   Input capture edge control 3A
TMSK1          0x0022    Timer interrupt mask 1
TMSK1.OC1I      7   Output compare 1 interrupt enable
TMSK1.OC2I      6   Output compare 2 interrupt enable
TMSK1.OC3I      5   Output compare 3 interrupt enable
TMSK1.OC4I      4   Output compare 4 interrupt enable
TMSK1.I4_O5I    3   Input capture 4/output compare 5 interrupt enable
TMSK1.IC1I      2   Input capture 1 interrupt enable
TMSK1.IC2I      1   Input capture 2 interrupt enable
TMSK1.IC3I      0   Input capture 3 interrupt enable
TFLG1          0x0023    Timer interrupt flag 1
TFLG1.OC1F      7   Output compare 1 flag
TFLG1.OC2F      6   Output compare 2 flag
TFLG1.OC3F      5   Output compare 3 flag
TFLG1.OC4F      4   Output compare 4 flag
TFLG1.I4_O5F    3   Input capture 4/output compare 5 flag
TFLG1.IC1F      2   Input capture 1 flag
TFLG1.IC2F      1   Input capture 2 flag
TFLG1.IC3F      0   Input capture 3 flag
TMSK2          0x0024    Timer interrupt mask 2
TMSK2.TOI       7   Timer overflow interrupt enable
TMSK2.RTII      6   Real-time interrupt enable
TMSK2.PAOVI     5   Pulse accumulator overflow interrupt enable
TMSK2.PALL      4   Pulse accumulator interrupt enable
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025    Timer interrupt flag 2
TFLG2.TOF       7   Timer overflow interrupt flag
TFLG2.RTIF      6   Real time (periodic) interrupt flag
TFLG2.PAOVF     5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF      4   Pulse accumulator input edge interrupt flag
PACTL          0x0026    Pulse accumulator control
PACTL.PAEN      6   Pulse accumulator system enable
PACTL.PAMOD     5   Pulse accumulator mode
PACTL.PEDGE     4   Pulse accumulator edge control
PACTL.I4_O5     2   Input capture 4/output compare
PACTL.RTR1      1   RTI interrupt rate select 1
PACTL.RTR0      0   RTI interrupt rate select 0
PACNT          0x0027    Pulse accumulator count
SPCR           0x0028    SPI control
SPCR.SPIE       7   Serial peripheral interrupt enable
SPCR.SPE        6   Serial peripheral system enable
SPCR.DWON       5   Port D wired-OR mode
SPCR.MSTR       4   Master mode select
SPCR.CPOL       3   Clock polarity
SPCR.CPHA       2   Clock phase
SPCR.SPR1       1   SPI clock rate selects 1
SPCR.SPR0       0   SPI clock rate selects 0
SPSR           0x0029    SPI status
SPSR.SPIF       7   SPI interrupt complete flag
SPSR.WCOL       6   Write collision
SPSR.MODF       4   Mode fault
SPDR           0x002A    SPI data
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port pull-up assignment
PPAR.HPPUE      3   Port H pin pull-up enable
PPAR.GPPUE      2   Port G pin pull-up enable
PPAR.FPPUE      1   Port F pin pull-up enable
PPAR.BPPUE      0   Port B pin pull-up enable
RESERV2D       0x002D    RESERVED
PLLCR          0x002E    PLL control
PLLCR.PLLON     7   PLL on
PLLCR.BCS       6   Bus clock select
PLLCR.AUTO      5   Automatic bandwidth control
PLLCR.BWC       4   Bandwidth control
PLLCR.VCOT      3   VCO test (Test mode only)
PLLCR.MCS       2   Module clock select
PLLCR.LCK       1   Synthesizer lock detect
PLLCR.WEN       0   WAIT enable
SYNR           0x002F    Synthesizer program
SYNR.SYNX1      7
SYNR.SYNX0      6
SYNR.SYN45      5
SYNR.SYNE4      4
SYNR.SYNY3      3
SYNR.SYNY2      2
SYNR.SYNY1      1
SYNR.SYNY0      0
ADCTL          0x0030    A/D control&stattus
ADCTL.CCF       7   Conversions complete flag
ADCTL.SCAN      5   Continuous scan control
ADCTL.MULT      4   Multiple-channel/single-channel control
ADCTL.CD        3   Channel select D
ADCTL.CC        2   Channel select C
ADCTL.CB        1   Channel select B
ADCTL.CA        0   Channel select A
ADR1           0x0031    A/D result 1
ADR2           0x0032    A/D result 2
ADR3           0x0033    A/D result 3
ADR4           0x0034    A/D result 4
BPROT          0x0035    Blok protect
BPROT.BULKP     7   Bulk erase of EEPROM protect
BPROT.BPRT4     5   Block protect bit for top 128 bytes of EEPROM
BPROT.PTCON     4   Protect for CONFIG register
BPROT.BPRT3     3   Block protect bit 3 for EEPROM
BPROT.BPRT2     2   Block protect bit 2 for EEPROM
BPROT.BPRT1     1   Block protect bit 1 for EEPROM
BPROT.BPRT0     0   Block protect bit 0 for EEPROM
RESERV36       0x0036    Reserved
INIT2          0x0037    EEPROM mapping
INIT2.EE3       7   EEPROM map position 3
INIT2.EE2       6   EEPROM map position 2
INIT2.EE1       5   EEPROM map position 1
INIT2.EE0       4   EEPROM map position 0
INIT2.M3DL1     3   M3DL1 MI BUS delay select
INIT2.M3DL0     2   M3DL0 MI BUS delay select
INIT2.M2DL1     1   M2DL1 MI BUS delay select
INIT2.M2DL0     0   M2DL0 MI BUS delay select
OPT2           0x0038    System config options 2
OPT2.LIRDV      7   LIR driven
OPT2.CWOM       6   Port C wired-OR mode
OPT2.STRCH      5   Stretch external accesses
OPT2.IRVNE      4   Internal read visibility/not E
OPT2.LSBF       3   LSB-first enable
OPT2.SPR2       2   SPI clock rate select
OPTION         0x0039    System config option 1
OPTION.ADPU     7   A/D power-up
OPTION.CSEL     6   Clock select
OPTION.IRQE     5   Configure IRQ for falling edge sensitive operation
OPTION.DLY      4   Enable oscillator start-up delay
OPTION.CME      3   Clock monitor enable
OPTION.FCME     2   Force clock monitor enable
OPTION.CR1      1   COP timer rate select bits 1
OPTION.CR0      0   COP timer rate select bits 0
COPRST         0x003A    COP timer arm/reset
PPROG          0x003B    EEPROM programming
PPROG.ODD       7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN      6   Program even rows in half of EEPROM (Test)
PPROG.BYTE      4   EEPROM byte erase mode
PPROG.ROW       3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE     2   Erase/normal control for EEPROM
PPROG.EELAT     1   EEPROM latch control
PPROG.EEPGM     0   EEPROM program command
HPRIO          0x003C    Highest priority interrupt
HPRIO.RBOOT     7   Read bootstrap ROM
HPRIO.SMOD      6   Special mode select
HPRIO.MDA       5   Mode select A
HPRIO.PSEL4     4   Priority select bits 4
HPRIO.PSEL3     3   Priority select bits 3
HPRIO.PSEL2     2   Priority select bits 2
HPRIO.PSEL1     1   Priority select bits 1
HPRIO.PSEL0     0   Priority select bits 0
INIT           0x003D    RAM&I/O mapping
INIT.RAM3       7   RAM map position 3
INIT.RAM2       6   RAM map position 2
INIT.RAM1       5   RAM map position 1
INIT.RAM0       4   RAM map position 0
INIT.REG3       3   128-byte register block position 3
INIT.REG2       2   128-byte register block position 2
INIT.REG1       1   128-byte register block position 1
INIT.REG0       0   128-byte register block position 0
TEST1          0x003E    Factori test
TEST1.TILOP     7   Test Illegal Opcode
TEST1.PLTST     6   
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
TEST1.MIDLY     0                                                      
CONFIG         0x003F    Configuration
CONFIG.ROMAD    7   ROM mapping control
CONFIG.PAREN    4   Pull-up assignment register enable
CONFIG.NOSEC    3   EEPROM security disabled
CONFIG.NOCOP    2   COP system disable
CONFIG.ROMON    1   ROM enable
CONFIG.EEON     0   EEPROM enable
RESERV40       0x0040    Reserved
RESERV41       0x0041    Reserved
RESERV42       0x0042    Reserved
RESERV43       0x0043    Reserved
RESERV44       0x0044    Reserved
RESERV45       0x0045    Reserved
RESERV46       0x0046    Reserved
RESERV47       0x0047    Reserved
RESERV48       0x0048    Reserved
RESERV49       0x0049    Reserved
RESERV4A       0x004A    Reserved
RESERV4B       0x004B    Reserved
RESERV4C       0x004C    Reserved
RESERV4D       0x004D    Reserved
RESERV4E       0x004E    Reserved
RESERV4F       0x004F    Reserved
S2BDH          0x0050    SCI/MI 2/3 baud HIGH
S2BDH.B2TST     7   Baud register test (Test mode only)     
S2BDH.B2SPL     6   Baud rate counter split (Test mode only)
S2BDH.S2B12     4   SCI baud rate/ MI BUS clock rate selects
S2BDH.S2B11     3   SCI baud rate/ MI BUS clock rate selects
S2BDH.S2B10     2   SCI baud rate/ MI BUS clock rate selects
S2BDH.S2B9      1   SCI baud rate/ MI BUS clock rate selects
S2BDH.S2B8      0   SCI baud rate/ MI BUS clock rate selects
S2BDL          0x0051    SCI/MI 2/3 baud LOW
S2BDL.S2B7      7   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B6      6   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B5      5   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B4      4   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B3      3   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B2      2   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B1      1   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B0      0   SCI baud rate/ MI BUS clock rate selects
S2CR1          0x0052    SCO/MI 2 control 1
S2CR1.LOPS2     7   SCI loop mode enable
S2CR1.WOMS2     6   Wired-OR mode for MI BUS2 pins (PH6, PH7)
S2CR1.MIE2      5   Motorola interface bus enable 2
S2CR1.M2        4   Mode (select character format)
S2CR1.WAKE2     3   Wakeup by address mark/idle
S2CR1.ILT2      2   Idle line type
S2CR1.PE2       1   Parity enable
S2CR1.PT2       0   MI BUS TX polarity
S2CR2          0x0053    SCO/MI 2 control 2
S2CR2.TIE2      7   Transmit interrupt enable         
S2CR2.TCIE2     6   Transmit complete interrupt enable
S2CR2.RIE2      5   Receiver interrupt enable         
S2CR2.ILIE2     4   Idle line interrupt enable        
S2CR2.TE2       3   Transmitter enable                
S2CR2.RE2       2   Receiver enable                   
S2CR2.RWU2      1   Receiver wakeup control           
S2CR2.SBK2      0   Send break                        
S2SR1          0x0054    SCI/MI 2 status 1
S2SR1.TDRE2     7   Transmit data register empty flag
S2SR1.TC2       6   Transmit complete flag           
S2SR1.RDRF2     5   Receive data register full flag 2
S2SR1.IDLE2     4   Idle line detected flag          
S2SR1.OR2       3   Bit error 2
S2SR1.NF2       2   Noise error flag                 
S2SR1.FE2       1   Framing error                    
S2SR1.PF2       0   Parity error flag                
S2SR2          0x0055    SCI/MI 2 status 2
S2SR2.RAF2      0   Receiver active flag (read only)
S2DRH          0x0056    SCI/MI 2 data HIGH
S2DRH.R8B       7   Receiver bit 8   
S2DRH.T8B       6   Transmitter bit 8
S2DRL          0x0057    SCI/MI 2 data LOW
S2DRL.R7T7B     7   Receiver/transmitter data bit 7
S2DRL.R6T6B     6   Receiver/transmitter data bit 6
S2DRL.R5T5B     5   Receiver/transmitter data bit 5
S2DRL.R4T4B     4   Receiver/transmitter data bit 4
S2DRL.R3T3B     3   Receiver/transmitter data bit 3
S2DRL.R2T2B     2   Receiver/transmitter data bit 2
S2DRL.R1T1B     1   Receiver/transmitter data bit 1
S2DRL.R0T0B     0   Receiver/transmitter data bit 0
RESERV58       0x0058    Reserved
RESERV59       0x0059    Reserved
S3CR1          0x005A    SCO/MI 3 control 1
S3CR1.LOPS3     7   SCI loop mode enable                 
S3CR1.WOMS3     6   Wired-OR mode for SCI pins (PD1, PD0)
S3CR1.MIE3      5   Motorola Interface Bus Enable 3
S3CR1.M3        4   Mode (select character format)       
S3CR1.WAKE3     3   Wakeup by address mark/idle          
S3CR1.ILT3      2   Idle line type                       
S3CR1.PE3       1   Parity enable                        
S3CR1.PT3       0   Parity type                          
S3CR2          0x005B    SCO/MI 3 control 2
S3CR2.TIE3      7   Transmit interrupt enable         
S3CR2.TCIE3     6   Transmit complete interrupt enable
S3CR2.RIE3      5   Receiver interrupt enable         
S3CR2.ILIE3     4   Idle line interrupt enable        
S3CR2.TE3       3   Transmitter enable                
S3CR2.RE3       2   Receiver enable                   
S3CR2.RWU3      1   Receiver wakeup control           
S3CR2.SBK3      0   Send break                        
S3SR1          0x005C    SCI/MI 3 status 1
S3SR1.TDRE3     7   Transmit data register empty flag
S3SR1.TC3       6   Transmit complete flag           
S3SR1.RDRF3     5   Receive data register full flag  
S3SR1.IDLE3     4   Idle line detected flag          
S3SR1.OR3       3   Overrun error flag               
S3SR1.NF3       2   Noise error flag                 
S3SR1.FE3       1   Framing error                    
S3SR1.PF3       0   Parity error flag                
S3SR2          0x005D    SCI/MI 3 status 2
S3SR2.RAF3      0   Receiver active flag (read only)
S3DRH          0x005E    SCI/MI 3 data HIGH
S3DRH.R8C       7   Receiver bit 8
S3DRH.T8C       6   Transmitter bit 8
S3DRL          0x005F    SCI/MI 3 data LOW
S3DRL.R7T7C     7   Receiver/transmitter data bit 7
S3DRL.R6T6C     6   Receiver/transmitter data bit 6
S3DRL.R5T5C     5   Receiver/transmitter data bit 5
S3DRL.R4T4C     4   Receiver/transmitter data bit 4
S3DRL.R3T3C     3   Receiver/transmitter data bit 3
S3DRL.R2T2C     2   Receiver/transmitter data bit 2
S3DRL.R1T1C     1   Receiver/transmitter data bit 1
S3DRL.R0T0C     0   Receiver/transmitter data bit 0
PWCLK          0x0060    Pulse width clock select
PWCLK.CON34     7   Concatenate channels 3 and 4
PWCLK.CON12     6   Concatenate Channels 1 and 2
PWCLK.PCKA2     5   Prescaler for clock A 2
PWCLK.PCKA1     4   Prescaler for clock A 1
PWCLK.PCKB3     2   Prescaler for clock B 3
PWCLK.PCKB2     1   Prescaler for clock B 2
PWCLK.PCKB1     0   Prescaler for clock B 1
PWPOL          0x0061    Pulse width polarity select
PWPOL.PCLK4     7   Pulse width channel 4 clock select
PWPOL.PCLK3     6   Pulse width channel 3 clock select
PWPOL.PCLK2     5   Pulse width channel 2 clock select
PWPOL.PCLK1     4   Pulse width channel 1 clock select
PWPOL.PPOL4     3   Pulse width channel 4 polarity
PWPOL.PPOL3     2   Pulse width channel 3 polarity
PWPOL.PPOL2     1   Pulse width channel 2 polarity
PWPOL.PPOL1     0   Pulse width channel 1 polarity
PWSCAL         0x0062    Pulse width scale
PWEN           0x0063    Pulse width enable
PWEN.TPWSL      7   PWM scaled clock test bit (Test mode only)
PWEN.DISCP      6   Disable compare scaled E clock (Test mode only)
PWEN.PWEN4      3   Pulse width channel 4
PWEN.PWEN3      2   Pulse width channel 3
PWEN.PWEN2      1   Pulse width channel 2
PWEN.PWEN1      0   Pulse width channel 1
PWCNT1         0x0064    Pulse width count 1
PWCNT2         0x0065    Pulse width count 2
PWCNT3         0x0066    Pulse width count 3
PWCNT4         0x0067    Pulse width count 4
PWPER1         0x0068    Pulse width period 1
PWPER2         0x0069    Pulse width period 2
PWPER3         0x006A    Pulse width period 3
PWPER4         0x006B    Pulse width period 4
PWDTY1         0x006C    Pulse width duty 1
PWDTY2         0x006D    Pulse width duty 2
PWDTY3         0x006E    Pulse width duty 3
PWDTY4         0x006F    Pulse width duty 4
SCBDH          0x0070    SCI 1 baud rate HIGH
SCBDH.BTST      7   Baud register test (Test mode only)
SCBDH.BSPL      6   Baud rate counter split (Test mode only)
SCBDH.SBR12     4   SCI baud rate selects 12
SCBDH.SBR11     3   SCI baud rate selects 11
SCBDH.SBR10     2   SCI baud rate selects 10
SCBDH.SBR9      1   SCI baud rate selects 9 
SCBDH.SBR8      0   SCI baud rate selects 8 
SCBDL          0x0071    SCI 1 baud rate LOW
SCBDL.SBR7      7   SCI baud rate selects 7
SCBDL.SBR6      6   SCI baud rate selects 6
SCBDL.SBR5      5   SCI baud rate selects 5
SCBDL.SBR4      4   SCI baud rate selects 4
SCBDL.SBR3      3   SCI baud rate selects 3
SCBDL.SBR2      2   SCI baud rate selects 2
SCBDL.SBR1      1   SCI baud rate selects 1
SCBDL.SBR0      0   SCI baud rate selects 0
SCCR1          0x0072    SCI 1 control 1
SCCR1.LOOPS     7   SCI loop mode enable
SCCR1.WOMS      6   Wired-OR mode for SCI pins (PD1, PD0)
SCCR1.M         4   Mode (select character format)
SCCR1.WAKE      3   Wakeup by address mark/idle
SCCR1.ILT       2   Idle line type
SCCR1.PE        1   Parity enable
SCCR1.PT        0   Parity type
SCCR2          0x0073    SCI 1 control 2
SCCR2.TIE       7   Transmit interrupt enable
SCCR2.TCIE      6   Transmit complete interrupt enable
SCCR2.RIE       5   Receiver interrupt enable
SCCR2.ILIE      4   Idle line interrupt enable
SCCR2.TE        3   Transmitter enable
SCCR2.RE        2   Receiver enable
SCCR2.RWU       1   Receiver wakeup control
SCCR2.SBK       0   Send break
SCSR1          0x0074    SCI 1 status 1
SCSR1.TDRE      7   Transmit data register empty flag
SCSR1.TC        6   Transmit complete flag
SCSR1.RDRF      5   Receive data register full flag
SCSR1.IDLE      4   Idle line detected flag
SCSR1.OR        3   Overrun error flag
SCSR1.NF        2   Noise error flag
SCSR1.FE        1   Framing error
SCSR1.PF        0   Parity error flag
SCSR2          0x0075    SCI 1 status 2
SCSR2.RAF       0   Receiver active flag (read only)
SCDRH          0x0076    SCI 1 data HIGH
SCDRH.R8        7   Receiver bit 8
SCDRH.T8        6   Transmitter bit 8
SCDRL          0x0077    SCI 1 data LOW
SCDRL.R7T7      7   Receiver/transmitter data bit 7
SCDRL.R6T6      6   Receiver/transmitter data bit 6
SCDRL.R5T5      5   Receiver/transmitter data bit 5
SCDRL.R4T4      4   Receiver/transmitter data bit 4
SCDRL.R3T3      3   Receiver/transmitter data bit 3
SCDRL.R2T2      2   Receiver/transmitter data bit 2
SCDRL.R1T1      1   Receiver/transmitter data bit 1
SCDRL.R0T0      0   Receiver/transmitter data bit 0
RESERV78       0x0078    Reserved
RESERV79       0x0079    Reserved
RESERV7A       0x007A    Reserved
RESERV7B       0x007B    Reserved
PORTH          0x007C    Port H data
PORTH.PH7       7    Port H Data Bit 7
PORTH.PH6       6    Port H Data Bit 6
PORTH.PH5       5    Port H Data Bit 5
PORTH.PH4       4    Port H Data Bit 4
PORTH.PH3       3    Port H Data Bit 3
PORTH.PH2       2    Port H Data Bit 2
PORTH.PH1       1    Port H Data Bit 1
PORTH.PH0       0    Port H Data Bit 0
DDRH           0x007D    Data direction H
DDRH.DDH7       7   Data Direction for Port H Bit 7
DDRH.DDH6       6   Data Direction for Port H Bit 6
DDRH.DDH5       5   Data Direction for Port H Bit 5
DDRH.DDH4       4   Data Direction for Port H Bit 4
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G data
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6
PORTG.PG5       5   Port G Data Bit 5
PORTG.PG4       4   Port G Data Bit 4
PORTG.PG3       3   Port G Data Bit 3
PORTG.PG2       2   Port G Data Bit 2
PORTG.PG1       1   Port G Data Bit 1
PORTG.PG0       0   Port G Data Bit 0
DDRG           0x007F    Data direction G
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6
DDRG.DDG5       5   Data Direction for Port G Bit 5
DDRG.DDG4       4   Data Direction for Port G Bit 4
DDRG.DDG3       3   Data Direction for Port G Bit 3
DDRG.DDG2       2   Data Direction for Port G Bit 2
DDRG.DDG1       1   Data Direction for Port G Bit 1
DDRG.DDG0       0   Data Direction for Port G Bit 0
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED


.68HC11PH8
; MC68HC11PH8/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11PH8.pdf
; MC68HC11PH8.pdf

; RAM=2K
; ROM=48K
; EPROM=0
; EEPROM=768


; MEMORY MAP
area DATA FSR         0x0000:0x0080
area DATA RAM         0x0080:0x0880
area BSS  RESERVED    0x0880:0x0D00
area DATA EEPROM      0x0D00:0x1000
area BSS  RESERVED    0x1000:0x4000
area CODE ROM         0x4000:0xFFC0
area DATA USER_VEC    0xFFC0:0x1000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI1 Serial Transfer Complete
interrupt SCI1              0xFFD6      SCI1
interrupt SPI2E             0xFFD4      SPI2 Serial Transfer Complete
interrupt SCI12             0xFFD2      SCI2
interrupt T8A_B_C_I         0xFFD0      8-bit modulus timer A/B/C underflow
interrupt IEH               0xFFCE      Wired-OR port H


; INPUT/ OUTPUT PORTS
PORTA         0x0000  Port A data
PORTA.PA7      7   Port A Data Bit 7
PORTA.PA6      6   Port A Data Bit 6
PORTA.PA5      5   Port A Data Bit 5
PORTA.PA4      4   Port A Data Bit 4
PORTA.PA3      3   Port A Data Bit 3
PORTA.PA2      2   Port A Data Bit 2
PORTA.PA1      1   Port A Data Bit 1
PORTA.PA0      0   Port A Data Bit 0
DDRA          0x0001  Data direction A
DDRA.DDA7      7   Data Direction for Port A Bit 7
DDRA.DDA6      6   Data Direction for Port A Bit 6
DDRA.DDA5      5   Data Direction for Port A Bit 5
DDRA.DDA4      4   Data Direction for Port A Bit 4
DDRA.DDA3      3   Data Direction for Port A Bit 3
DDRA.DDA2      2   Data Direction for Port A Bit 2
DDRA.DDA1      1   Data Direction for Port A Bit 1
DDRA.DDA0      0   Data Direction for Port A Bit 0
DDRB          0x0002  Data direction B
DDRB.DDB7      7   Data Direction for Port B Bit 7
DDRB.DDB6      6   Data Direction for Port B Bit 6
DDRB.DDB5      5   Data Direction for Port B Bit 5
DDRB.DDB4      4   Data Direction for Port B Bit 4
DDRB.DDB3      3   Data Direction for Port B Bit 3
DDRB.DDB2      2   Data Direction for Port B Bit 2
DDRB.DDB1      1   Data Direction for Port B Bit 1
DDRB.DDB0      0   Data Direction for Port B Bit 0
DDRF          0x0003  Data direction F
DDRF.DDF7      7   Data Direction for Port F Bit 7
DDRF.DDF6      6   Data Direction for Port F Bit 6
DDRF.DDF5      5   Data Direction for Port F Bit 5
DDRF.DDF4      4   Data Direction for Port F Bit 4
DDRF.DDF3      3   Data Direction for Port F Bit 3
DDRF.DDF2      2   Data Direction for Port F Bit 2
DDRF.DDF1      1   Data Direction for Port F Bit 1
DDRF.DDF0      0   Data Direction for Port F Bit 0
PORTB         0x0004  Port B data
PORTB.PB7      7   Port B Data Bit 7
PORTB.PB6      6   Port B Data Bit 6
PORTB.PB5      5   Port B Data Bit 5
PORTB.PB4      4   Port B Data Bit 4
PORTB.PB3      3   Port B Data Bit 3
PORTB.PB2      2   Port B Data Bit 2
PORTB.PB1      1   Port B Data Bit 1
PORTB.PB0      0   Port B Data Bit 0
PORTF         0x0005  Port F data
PORTF.PF7      7   Port F Data Bit 7
PORTF.PF6      6   Port F Data Bit 6
PORTF.PF5      5   Port F Data Bit 5
PORTF.PF4      4   Port F Data Bit 4
PORTF.PF3      3   Port F Data Bit 3
PORTF.PF2      2   Port F Data Bit 2
PORTF.PF1      1   Port F Data Bit 1
PORTF.PF0      0   Port F Data Bit 0
PORTC         0x0006  Port C data
PORTC.PC7      7   Port C Data Bit 7
PORTC.PC6      6   Port C Data Bit 6
PORTC.PC5      5   Port C Data Bit 5
PORTC.PC4      4   Port C Data Bit 4
PORTC.PC3      3   Port C Data Bit 3
PORTC.PC2      2   Port C Data Bit 2
PORTC.PC1      1   Port C Data Bit 1
PORTC.PC0      0   Port C Data Bit 0
DDRC          0x0007  Data direction C
DDRC.DDC7      7   Data Direction for Port C Bit 7
DDRC.DDC6      6   Data Direction for Port C Bit 6
DDRC.DDC5      5   Data Direction for Port C Bit 5
DDRC.DDC4      4   Data Direction for Port C Bit 4
DDRC.DDC3      3   Data Direction for Port C Bit 3
DDRC.DDC2      2   Data Direction for Port C Bit 2
DDRC.DDC1      1   Data Direction for Port C Bit 1
DDRC.DDC0      0   Data Direction for Port C Bit 0
PORTD         0x0008  Port D data
PORTD.PD5      5   Port D Data Bit 5
PORTD.PD4      4   Port D Data Bit 4
PORTD.PD3      3   Port D Data Bit 3
PORTD.PD2      2   Port D Data Bit 2
PORTD.PD1      1   Port D Data Bit 1
PORTD.PD0      0   Port D Data Bit 0
DDRD          0x0009  Data direction D
DDRD.DDD5      5   Data Direction for Port D Bit 5
DDRD.DDD4      4   Data Direction for Port D Bit 4
DDRD.DDD3      3   Data Direction for Port D Bit 3
DDRD.DDD2      2   Data Direction for Port D Bit 2
DDRD.DDD1      1   Data Direction for Port D Bit 1
DDRD.DDD0      0   Data Direction for Port D Bit 0
PORTE         0x000A  Port E data
PORTE.PE7      7   Port E Data Bit 7
PORTE.PE6      6   Port E Data Bit 6
PORTE.PE5      5   Port E Data Bit 5
PORTE.PE4      4   Port E Data Bit 4
PORTE.PE3      3   Port E Data Bit 3
PORTE.PE2      2   Port E Data Bit 2
PORTE.PE1      1   Port E Data Bit 1
PORTE.PE0      0   Port E Data Bit 0
CFORC         0x000B  Timer compare force
CFORC.FOC1     7   Force output compares 1
CFORC.FOC2     6   Force output compares 2
CFORC.FOC3     5   Force output compares 3
CFORC.FOC4     4   Force output compares 4
CFORC.FOC5     3   Force output compares 5
OC1M          0x000C  Output compare 1 mask
OC1M.OC1M7     7   Output compare masks for OC1 bit 7
OC1M.OC1M6     6   Output compare masks for OC1 bit 6
OC1M.OC1M5     5   Output compare masks for OC1 bit 5
OC1M.OC1M4     4   Output compare masks for OC1 bit 4
OC1M.OC1M3     3   Output compare masks for OC1 bit 3
OC1D          0x000D  Output compare 1 data
OC1D.OC1D7     7   Output compare data for OC1 bit 7
OC1D.OC1D6     6   Output compare data for OC1 bit 6
OC1D.OC1D5     5   Output compare data for OC1 bit 5
OC1D.OC1D4     4   Output compare data for OC1 bit 4
OC1D.OC1D3     3   Output compare data for OC1 bit 3
TCNTH         0x000E  Timer count high
TCNTL         0x000F  Timer count low
TIC1H         0x0010  Timer input capture 1 high
TIC1L         0x0011  Timer input capture 1 low 
TIC2H         0x0012  Timer input capture 2 high
TIC2L         0x0013  Timer input capture 2 low 
TIC3H         0x0014  Timer input capture 3 high
TIC3L         0x0015  Timer input capture 3 low 
TOC1H         0x0016  Timer output compare 1 high
TOC1L         0x0017  Timer output compare 1 low 
TOC2H         0x0018  Timer output compare 2 high
TOC2L         0x0019  Timer output compare 2 low 
TOC3H         0x001A  Timer output compare 3 high
TOC3L         0x001B  Timer output compare 3 low 
TOC4H         0x001C  Timer output compare 4 high
TOC4L         0x001D  Timer output compare 4 low 
TI4_O5H       0x001E  Capture 4_compare 5  high
TI4_O5L       0x001F  Capture 4_compare 5  low 
TCTL1         0x0020  Timer control 1
TCTL1.OM2      7   Output mode 2 
TCTL1.OL2      6   Output level 2
TCTL1.OM3      5   Output mode 3 
TCTL1.OL3      4   Output level 3
TCTL1.OM4      3   Output mode 4 
TCTL1.OL4      2   Output level 4
TCTL1.OM5      1   Output mode 5 
TCTL1.OL5      0   Output level 5
TCTL2         0x0021  Timer control 2
TCTL2.EDG4B    7   Input capture edge control 4B
TCTL2.EDG4A    6   Input capture edge control 4A
TCTL2.EDG1B    5   Input capture edge control 1B
TCTL2.EDG1A    4   Input capture edge control 1A
TCTL2.EDG2B    3   Input capture edge control 2B
TCTL2.EDG2A    2   Input capture edge control 2A
TCTL2.EDG3B    1   Input capture edge control 3B
TCTL2.EDG3A    0   Input capture edge control 3A
TMSK1         0x0022  Timer interrupt mask 1
TMSK1.OC1I     7   Output compare 1 interrupt enable                
TMSK1.OC2I     6   Output compare 2 interrupt enable                
TMSK1.OC3I     5   Output compare 3 interrupt enable                
TMSK1.OC4I     4   Output compare 4 interrupt enable                
TMSK1.I4_O5I   3   Input capture 4 / output compare 5 interrupt enable
TMSK1.IC1I     2   Input capture 1 interrupt enable                 
TMSK1.IC2I     1   Input capture 2 interrupt enable                 
TMSK1.IC3I     0   Input capture 3 interrupt enable                 
TFLG1         0x0023  Timer interrupt flag 1
TFLG1.OC1F     7   Output compare 1 flag
TFLG1.OC2F     6   Output compare 2 flag
TFLG1.OC3F     5   Output compare 3 flag
TFLG1.OC4F     4   Output compare 4 flag
TFLG1.I4_O5F   3   Input capture 4/output compare 5 flag
TFLG1.IC1F     2   Input capture 1 flag
TFLG1.IC2F     1   Input capture 2 flag
TFLG1.IC3F     0   Input capture 3 flag
TMSK2         0x0024  Timer interrupt mask 2
TMSK2.TOI      7   Timer overflow interrupt enable            
TMSK2.RTII     6   Real-time interrupt enable                 
TMSK2.PAOVI    5   Pulse accumulator overflow interrupt enable
TMSK2.PAII     4   Pulse accumulator interrupt enable         
TMSK2.PR1      1   Timer prescaler select 1                   
TMSK2.PR0      0   Timer prescaler select 0                   
TFLG2         0x0025  Timer interrupt flag 2
TFLG2.TOF      7   Timer overflow interrupt flag
TFLG2.RTIF     6   Real time interrupt flag
TFLG2.PAOVF    5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF     4   Pulse accumulator input edge interrupt flag
PACTL         0x0026  Pulse accumulator control
PACTL.PAEN     6   Pulse accumulator system enable
PACTL.PAMOD    5   Pulse accumulator mode
PACTL.PEDGE    4   Pulse accumulator edge control
PACTL.I4_O5    2   Input capture 4/output compare
PACTL.RTR1     1   RTI interrupt rate select 1
PACTL.RTR0     0   RTI interrupt rate select 0
PACNT         0x0027  Pulse accumulator count
SPCR          0x0028  SPI control
SPCR.SPIE      7   Serial peripheral interrupt enable
SPCR.SPE       6   Serial peripheral system enable   
SPCR.DWOM      5   Port D wired-OR mode              
SPCR.MSTR      4   Master mode select                
SPCR.CPOL      3   Clock polarity                    
SPCR.CPHA      2   Clock phase                       
SPCR.SPR1      1   SPI clock rate selects 1          
SPCR.SPR0      0   SPI clock rate selects 0          
SPSR          0x0029  SPI status
SPSR.SPIF      7   SPI interrupt complete flag
SPSR.WCOL      6   Write collision
SPSR.MODF      4   Mode fault
SPDR          0x002A  SPI data
RESERVED2B    0x002B  RESERVED
; EPROG         0x002B  EPROM programming (711)
; EPROG.MBE      7   Multiple byte program enable
; EPROG.ELAT     5   EPROM latch control
; EPROG.EXCOL    4   Select extra columns
; EPROG.EXROW    3   Select extra rows
; EPROG.EPGM     0   EPROM program command
PPAR          0x002C  Port pull-up assignment
PPAR.HWOIF     4   Port H wired-OR interrupt flag
PPAR.HPPUE     3   Port H pin pull-up enable
PPAR.GPPUE     2   Port G pin pull-up enable
PPAR.FPPUE     1   Port F pin pull-up enable
PPAR.BPPUE     0   Port B pin pull-up enable
LCDR          0x002D  LCD control and data
LCDR.LCD7      7   LCD segment data 7
LCDR.LCD6      6   LCD segment data 6
LCDR.LCD5      5   LCD segment data 5
LCDR.LCD4      4   LCD segment data 4
LCDR.LCDCK     1   LCD frequency clock select
LCDR.LCDE      0   LCD function enable
PLLCR         0x002E  PLL control
PLLCR.PLLON    7   PLL on
PLLCR.BCS      6   Bus clock select
PLLCR.AUTO     5   Automatic bandwidth control
PLLCR.BWC      4   Bandwidth control
PLLCR.VCOT     3   VCO test
PLLCR.MCS      2   Module clock select
PLLCR.T16EN    1   16-bit timer clock enable
PLLCR.WEN      0   WAIT enable
SYNR          0x002F  Synthesizer program
SYNR.SYNX1     7
SYNR.SYNX0     6
SYNR.SYNY5     5
SYNR.SYNY4     4
SYNR.SYNY3     3
SYNR.SYNY2     2
SYNR.SYNY1     1
SYNR.SYNY0     0
ADCTL         0x0030  A/D control & status
ADCTL.CCF      7   Conversions complete flag
ADCTL.SCAN     5   Continuous scan control
ADCTL.MULT     4   Multiple-channel/single-channel control
ADCTL.CD       3   Channel selects D
ADCTL.CC       2   Channel selects C
ADCTL.CB       1   Channel selects B
ADCTL.CA       0   Channel selects A
ADR1          0x0031  A/D result 1
ADR2          0x0032  A/D result 2
ADR3          0x0033  A/D result 3
ADR4          0x0034  A/D result 4
BPROT         0x0035  Block protect
BPROT.BULKP    7   Bulk erase of EEPROM protect
BPROT.BPRT4    5   Block protect bit for top 256 bytes of EEPROM
BPROT.PTCON    4   Protect for CONFIG register
BPROT.BPRT3    3   Block protect bit 3 for EEPROM
BPROT.BPRT2    2   Block protect bit 2 for EEPROM
BPROT.BPRT1    1   Block protect bit 1 for EEPROM
BPROT.BPRT0    0   Block protect bit 0 for EEPROM
RESERVED36    0x0036  RESERVED36
INIT2         0x0037  EEPROM mapping
INIT2.EE3      7   EEPROM map position 3
INIT2.EE2      6   EEPROM map position 2
INIT2.EE1      5   EEPROM map position 1
INIT2.EE0      4   EEPROM map position 0
INIT2.STRX     3   Stretch extended
INIT2.M2DL1    1   MI BUS delay select 1
INIT2.M2DL0    0   MI BUS delay select 0
OPT2          0x0038  System config. options 2 
OPT2.LIRDV     7   LIR driven
OPT2.CWOM      6   Port C wired-OR mode
OPT2.STRCH     5   Stretch external accesses
OPT2.IRVNE     4   Internal read visibility/not E
OPT2.LSBF      3   LSB-first enable
OPT2.SPR2      2   SPI clock rate select
OPT2.EXT4X     1   4XLCK or EXTAL clock output select
OPT2.DISE      0   E clock output disable
OPTION        0x0039  System config. options 1
OPTION.ADPU    7   A/D power-up
OPTION.CSEL    6   Clock select
OPTION.IRQE    5   Configure IRQ for falling edge sensitive operation
OPTION.DLY     4   Enable oscillator start-up delay
OPTION.CME     3   Clock monitor enable
OPTION.FCME    2   Force clock monitor enable
OPTION.CR1     1   COP timer rate select bit 1
OPTION.CR0     0   COP timer rate select bit 0
COPRST        0x003A  COP timer arm_reset
PPROG         0x003B  EEPROM programming
PPROG.ODD      7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN     6   Program even rows in half of EEPROM (Test)
PPROG.BYTE     4   EEPROM byte erase mode
PPROG.ROW      3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE    2   Erase/normal control for EEPROM
PPROG.EELAT    1   EEPROM latch control
PPROG.EEPGM    0   EEPROM program command
HPRIO         0x003C  Highest priority interrupt
HPRIO.RBOOT    7   Read bootstrap ROM
HPRIO.SMOD     6   Special mode select
HPRIO.MDA      5   Mode select A
HPRIO.PSEL4    4   Priority select bit 4
HPRIO.PSEL3    3   Priority select bit 3
HPRIO.PSEL2    2   Priority select bit 2
HPRIO.PSEL1    1   Priority select bit 1
HPRIO.PSEL0    0   Priority select bit 0
INIT          0x003D  RAM & I_O mapping
INIT.RAM3      7   RAM map position 3
INIT.RAM2      6   RAM map position 2
INIT.RAM1      5   RAM map position 1
INIT.RAM0      4   RAM map position 0
INIT.REG3      3   128-byte register block position 3
INIT.REG2      2   128-byte register block position 2
INIT.REG1      1   128-byte register block position 1
INIT.REG0      0   128-byte register block position 0
TEST1         0x003E  Factory test
TEST1.TILOP    7   Test Illegal Opcode
TEST1.PLTST    6
TEST1.OCCR     5   Output Condition Code Register Status to Timer Port
TEST1.CBYP     4   Timer Counter Divider Chain By-pass
TEST1.DISR     3   Disable Resets from COP and Clock Monitor
TEST1.FCM      2   Force Clock Monitor Failure
TEST1.FCOP     1   Force COP Watchdog Failure
TEST1.MIDLY    0
CONFIG        0x003F  Configuration control
CONFIG.ROMAD   7   ROM mapping control
CONFIG.FREEZ   6   Address bus freeze in expanded user mode
CONFIG.CLK4X   5   4X clock enable
CONFIG.PAREN   4   Pull-up assignment register enable
CONFIG.NOSEC   3   EEPROM security disabled
CONFIG.NOCOP   2   COP system disable
CONFIG.ROMON   1   ROM enable
CONFIG.EEON    0   EEPROM enable
RESERVED40    0x0040  RESERVED40
RESERVED41    0x0041  RESERVED41
RESERVED42    0x0042  RESERVED42
RESERVED43    0x0043  RESERVED43
RESERVED44    0x0044  RESERVED44
RESERVED45    0x0045  RESERVED45
RESERVED46    0x0046  RESERVED46
RESERVED47    0x0047  RESERVED47
RESERVED48    0x0048  RESERVED48
RESERVED49    0x0049  RESERVED49
RESERVED4A    0x004A  RESERVED4A
RESERVED4B    0x004B  RESERVED4B
SP2CR         0x004C  SPI2 control
SP2CR.SP2IE    7   Serial peripheral interrupt enable
SP2CR.SP2E     6   Serial peripheral system enable
SP2CR.GWOM     5   Port D wired-OR mode
SP2CR.MSTR2    4   Master mode select
SP2CR.CPOL2    3   Clock polarity
SP2CR.CPHA2    2   Clock phase
SP2CR.SP2R1    1   SPI clock rate selects 1
SP2CR.SP2R0    0   SPI clock rate selects 0
SP2SR         0x004D  SPI2 status
SP2SR.SP2IF    7   SPI interrupt complete flag
SP2SR.WCOL2    6   Write collision
SP2SR.MODF2    4   Mode fault
SP2DR         0x004E  SPI2 data
SP2OPT        0x004F  SPI2 control options
SP2OPT.LSBF2   3   LSB-first enable
SP2OPT.SP2R2   2   SPI clock rate select
S2BDH         0x0050  SCI2_MI baud high
S2BDH.B2TST    7   Baud register test (Test mode only)
S2BDH.B2SPL    6   Baud rate counter split (Test mode only)
S2BDH.B2RST    5   Baud rate reset (Test mode only)
S2BDH.S2B12    4   SCI baud rate selects 12
S2BDH.S2B11    3   SCI baud rate selects 11
S2BDH.S2B10    2   SCI baud rate selects 10
S2BDH.S2B9     1   SCI baud rate selects 9 
S2BDH.S2B8     0   SCI baud rate selects 8 
S2BDL         0x0051  SCI2_MI baud low
S2BDL.S2B7     7   SCI baud rate selects 7
S2BDL.S2B6     6   SCI baud rate selects 6
S2BDL.S2B5     5   SCI baud rate selects 5
S2BDL.S2B4     4   SCI baud rate selects 4
S2BDL.S2B3     3   SCI baud rate selects 3
S2BDL.S2B2     2   SCI baud rate selects 2
S2BDL.S2B1     1   SCI baud rate selects 1
S2BDL.S2B0     0   SCI baud rate selects 0
S2CR1         0x0052  SCI2_MI control 1
S2CR1.LOPS2    7   SCI loop mode enable
S2CR1.WOMS2    6   Wired-OR mode for SCI pins (PG1, PG0)
S2CR1.MIE2     5   Motorola interface bus enable 2
S2CR1.M2       4   Mode (select character format)
S2CR1.WAKE2    3   Wake-up by address mark/idle
S2CR1.ILT2     2   Idle line type
S2CR1.PE2      1   Parity enable
S2CR1.PT2      0   Parity type
S2CR2         0x0053  SCI2_MI control 2
S2CR2.TIE2     7   Transmit interrupt enable
S2CR2.TCIE2    6   Transmit complete interrupt enable
S2CR2.RIE2     5   Receiver interrupt enable
S2CR2.ILIE2    4   Idle line interrupt enable
S2CR2.TE2      3   Transmitter enable
S2CR2.RE2      2   Receiver enable
S2CR2.RWU2     1   Receiver wake-up control
S2CR2.SBK2     0   Send break
S2SR1         0x0054  SCI2_MI status 1
S2SR1.TDRE2    7   Transmit data register empty flag
S2SR1.TC2      6   Transmit complete flag
S2SR1.RDRF2    5   Receive data register full flag
S2SR1.IDLE2    4   Idle line detected flag
S2SR1.OR2      3   Overrun error flag
S2SR1.NF2      2   Noise error flag
S2SR1.FE2      1   Framing error
S2SR1.PF2      0   Parity error flag
S2SR2         0x0055  SCI2_MI status 2
S2SR2.RAF2     0   Receiver active flag (read only)
S2DRH         0x0056  SCI2_MI data high
S2DRH.R8B      7   Receiver bit 8
S2DRH.T8B      6   Transmitter bit 8
S2DRL         0x0057  SCI2_MI data low
S2DRL.R7T7B    7   Receiver/transmitter data bit 7
S2DRL.R6T6B    6   Receiver/transmitter data bit 6
S2DRL.R5T5B    5   Receiver/transmitter data bit 5
S2DRL.R4T4B    4   Receiver/transmitter data bit 4
S2DRL.R3T3B    3   Receiver/transmitter data bit 3
S2DRL.R2T2B    2   Receiver/transmitter data bit 2
S2DRL.R1T1B    1   Receiver/transmitter data bit 1
S2DRL.R0T0B    0   Receiver/transmitter data bit 0
RESERVED58    0x0058  RESERVED58
T8ADR         0x0059  8-bit modulus timer A data
T8BDR         0x005A  8-bit modulus timer B data
T8CDR         0x005B  8-bit modulus timer C data
RESERVED5C    0x005C  RESERVED5C
T8ACR         0x005D  8-bit modulus timer A control
T8ACR.T8AI     7   8-bit timer A interrupt enable
T8ACR.T8AF     6   8-bit timer A underflow flag
T8ACR.CSA2     2   8-bit timer A clock rate 2
T8ACR.CSA1     1   8-bit timer A clock rate 1
T8ACR.CSA0     0   8-bit timer A clock rate 0
T8BCR         0x005E  8-bit modulus timer B control
T8BCR.T8BI     7   8-bit timer B interrupt enable
T8BCR.T8BF     6   8-bit timer B underflow flag
T8BCR.PRB      3   8-bit timer B preset
T8BCR.CSB2     2   8-bit timer B clock rate 2
T8BCR.CSB1     1   8-bit timer B clock rate 1
T8BCR.CSB0     0   8-bit timer B clock rate 0
T8CCR         0x005F  8-bit modulus timer C control
T8CCR.T8CI     7   bit timer C interrupt enable
T8CCR.T8CF     6   8-bit timer C underflow flag
T8CCR.PRC      3   8-bit timer C preset
T8CCR.CSC2     2   8-bit timer C clock rate 2
T8CCR.CSC1     1   8-bit timer C clock rate 1
T8CCR.CSC0     0   8-bit timer C clock rate 0
PWCLK         0x0060  Pulse width clock select
PWCLK.CON34    7   Concatenate channels 3 and 4
PWCLK.CON12    6   Concatenate channels 1 and 2
PWCLK.PCKA2    5   Prescaler for clock A 2
PWCLK.PCKA1    4   Prescaler for clock A 1
PWCLK.PCKB3    2   Prescaler for clock B 3
PWCLK.PCKB2    1   Prescaler for clock B 2
PWCLK.PCKB1    0   Prescaler for clock B 1
PWPOL         0x0061  Pulse width polarity select
PWPOL.PCLK4    7   Pulse width channel 4 clock select
PWPOL.PCLK3    6   Pulse width channel 3 clock select
PWPOL.PCLK2    5   Pulse width channel 2 clock select
PWPOL.PCLK1    4   Pulse width channel 1 clock select
PWPOL.PPOL4    3   Pulse width channel 4 polarity
PWPOL.PPOL3    2   Pulse width channel 3 polarity
PWPOL.PPOL2    1   Pulse width channel 2 polarity
PWPOL.PPOL1    0   Pulse width channel 1 polarity
PWSCAL        0x0062  Pulse width scale
PWEN          0x0063  Pulse width enable
PWEN.TPWSL     7   PWM scaled clock test bit (Test mode only)
PWEN.DISCP     6   Disable compare scaled E clock (Test mode only)
PWEN.PWEN4     3   Pulse width channel 4
PWEN.PWEN3     2   Pulse width channel 3
PWEN.PWEN2     1   Pulse width channel 2
PWEN.PWEN1     0   Pulse width channel 1
PWCNT1        0x0064  Pulse width count 1
PWCNT2        0x0065  Pulse width count 2
PWCNT3        0x0066  Pulse width count 3
PWCNT4        0x0067  Pulse width count 4
PWPER1        0x0068  Pulse width period 1
PWPER2        0x0069  Pulse width period 2
PWPER3        0x006A  Pulse width period 3
PWPER4        0x006B  Pulse width period 4
PWDTY1        0x006C  Pulse width duty 1
PWDTY2        0x006D  Pulse width duty 2
PWDTY3        0x006E  Pulse width duty 3
PWDTY4        0x006F  Pulse width duty 4
SCBDH         0x0070  SCI1 baud rate high
SCBDH.BTST     7   Baud register test (Test mode only)     
SCBDH.BSPL     6   Baud rate counter split (Test mode only)
SCBDH.BRST     5   Baud rate reset (Test mode only)        
SCBDH.SBR12    4   SCI baud rate selects 12                
SCBDH.SBR11    3   SCI baud rate selects 11                
SCBDH.SBR10    2   SCI baud rate selects 10                
SCBDH.SBR9     1   SCI baud rate selects 9                 
SCBDH.SBR8     0   SCI baud rate selects 8                 
SCBDL         0x0071  SCI1 baud rate low
SCBDL.SBR7     7   SCI baud rate selects 7
SCBDL.SBR6     6   SCI baud rate selects 6
SCBDL.SBR5     5   SCI baud rate selects 5
SCBDL.SBR4     4   SCI baud rate selects 4
SCBDL.SBR3     3   SCI baud rate selects 3
SCBDL.SBR2     2   SCI baud rate selects 2
SCBDL.SBR1     1   SCI baud rate selects 1
SCBDL.SBR0     0   SCI baud rate selects 0
SCCR1         0x0072  SCCR1 SCI1 control 1
SCCR1.LOOPS    7   SCI loop mode enable
SCCR1.WOMS     6   Wired-OR mode for SCI pins (PG1, PG0)
SCCR1.M        4   Mode (select character format)
SCCR1.WAKE     3   Wake-up by address mark/idle
SCCR1.ILT      2   Idle line type
SCCR1.PE       1   Parity enable
SCCR1.PT       0   Parity type
SCCR2         0x0073  SCI1 control 2
SCCR2.TIE      7   Transmit interrupt enable
SCCR2.TCIE     6   Transmit complete interrupt enable
SCCR2.RIE      5   Receiver interrupt enable
SCCR2.ILIE     4   Idle line interrupt enable
SCCR2.TE       3   Transmitter enable
SCCR2.RE       2   Receiver enable
SCCR2.RWU      1   Receiver wake-up control
SCCR2.SBK      0   Send break
SCSR1         0x0074  SCI1 status 1
SCSR1.TDRE     7   Transmit data register empty flag
SCSR1.TC       6   Transmit complete flag
SCSR1.RDRF     5   Receive data register full flag
SCSR1.IDLE     4   Idle line detected flag
SCSR1.OR       3   Overrun error flag
SCSR1.NF       2   Noise error flag
SCSR1.FE       1   Framing error
SCSR1.PF       0   Parity error flag
SCSR2         0x0075  SCI1 status 2
SCSR2.RAF      0   Receiver active flag (read only)
SCDRH         0x0076  SCI1 data high
SCDRH.R8       7   Receiver bit 8   
SCDRH.T8       6   Transmitter bit 8
SCDRL         0x0077  SCI1 data low
SCDRL.R7T7     7   Receiver/transmitter data bit 7
SCDRL.R6T6     6   Receiver/transmitter data bit 6
SCDRL.R5T5     5   Receiver/transmitter data bit 5
SCDRL.R4T4     4   Receiver/transmitter data bit 4
SCDRL.R3T3     3   Receiver/transmitter data bit 3
SCDRL.R2T2     2   Receiver/transmitter data bit 2
SCDRL.R1T1     1   Receiver/transmitter data bit 1
SCDRL.R0T0     0   Receiver/transmitter data bit 0
RESERVED78    0x0078  RESERVED78
RESERVED79    0x0079  RESERVED79
RESERVED7A    0x007A  RESERVED7A
WOIEH         0x007B  Wired-OR interrupt enable
WOIEH.IEH7     7   Port H pin 7 wired-OR interrupt enable
WOIEH.IEH6     6   Port H pin 6 wired-OR interrupt enable
WOIEH.IEH5     5   Port H pin 5 wired-OR interrupt enable
WOIEH.IEH4     4   Port H pin 4 wired-OR interrupt enable
WOIEH.IEH3     3   Port H pin 3 wired-OR interrupt enable
WOIEH.IEH2     2   Port H pin 2 wired-OR interrupt enable
WOIEH.IEH1     1   Port H pin 1 wired-OR interrupt enable
WOIEH.IEH0     0   Port H pin 0 wired-OR interrupt enable
PORTH         0x007C  Port H data
PORTH.PH7      7   Port H Data Bit 7
PORTH.PH6      6   Port H Data Bit 6
PORTH.PH5      5   Port H Data Bit 5
PORTH.PH4      4   Port H Data Bit 4
PORTH.PH3      3   Port H Data Bit 3
PORTH.PH2      2   Port H Data Bit 2
PORTH.PH1      1   Port H Data Bit 1
PORTH.PH0      0   Port H Data Bit 0
DDRH          0x007D  Data direction H
DDRH.DDH7      7   Data Direction for Port H Bit 7
DDRH.DDH6      6   Data Direction for Port H Bit 6
DDRH.DDH5      5   Data Direction for Port H Bit 5
DDRH.DDH4      4   Data Direction for Port H Bit 4
DDRH.DDH3      3   Data Direction for Port H Bit 3
DDRH.DDH2      2   Data Direction for Port H Bit 2
DDRH.DDH1      1   Data Direction for Port H Bit 1
DDRH.DDH0      0   Data Direction for Port H Bit 0
PORTG         0x007E  Port G data
PORTG.PG7      7   Port G Data Bit 7
PORTG.PG6      6   Port G Data Bit 6
PORTG.PG5      5   Port G Data Bit 5
PORTG.PG4      4   Port G Data Bit 4
PORTG.PG3      3   Port G Data Bit 3
PORTG.PG2      2   Port G Data Bit 2
PORTG.PG1      1   Port G Data Bit 1
PORTG.PG0      0   Port G Data Bit 0
DDRG          0x007F  Data direction G
DDRG.DDG7      7   Data Direction for Port G Bit 7
DDRG.DDG6      6   Data Direction for Port G Bit 6
DDRG.DDG5      5   Data Direction for Port G Bit 5
DDRG.DDG4      4   Data Direction for Port G Bit 4
DDRG.DDG3      3   Data Direction for Port G Bit 3
DDRG.DDG2      2   Data Direction for Port G Bit 2
DDRG.DDG1      1   Data Direction for Port G Bit 1
DDRG.DDG0      0   Data Direction for Port G Bit 0
RESERVFFC0    0xFFC0  RESERVED
RESERVFFC1    0xFFC1  RESERVED
RESERVFFC2    0xFFC2  RESERVED
RESERVFFC3    0xFFC3  RESERVED
RESERVFFC4    0xFFC4  RESERVED
RESERVFFC5    0xFFC5  RESERVED
RESERVFFC6    0xFFC6  RESERVED
RESERVFFC7    0xFFC7  RESERVED
RESERVFFC8    0xFFC8  RESERVED
RESERVFFC9    0xFFC9  RESERVED
RESERVFFCA    0xFFCA  RESERVED
RESERVFFCB    0xFFCB  RESERVED
RESERVFFCC    0xFFCC  RESERVED
RESERVFFCD    0xFFCD  RESERVED


.68HC711D3
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC711D3&nodeId=01M98635
; br778.pdf

; RAM=192
; ROM=0
; EPROM=4K
; EEPROM=0


; MEMORY MAP
area DATA FSR        0x0000:0x0040
area DATA RAM        0x0040:0x0100
area BSS  RESERVED   0x0100:0xF000
area CODE EPROM      0xF000:0xFFC0
area DATA USER_VEC   0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET   0xFFFE   RESET
interrupt CME       0xFFFC   Clock Monitor Fail
interrupt NOCOP     0xFFFA   COP Failure
interrupt OPCODE    0xFFF8   Illegal Opcode Trap
interrupt SOFT      0xFFF6   Software Interrupt
interrupt XIRQ      0xFFF4   XIRQ Pin
interrupt IRQ       0xFFF2   IRQ
interrupt RTII      0xFFF0   Real-Time Interrupt
interrupt IC1I      0xFFEE   Timer Input Capture 1
interrupt IC2I      0xFFEC   Timer Input Capture 2
interrupt IC3I      0xFFEA   Timer Input Capture 3
interrupt OC1I      0xFFE8   Timer Output Compare 1
interrupt OC2I      0xFFE6   Timer Output Compare 2
interrupt OC3I      0xFFE4   Timer Output Compare 3
interrupt OC4I      0xFFE2   Timer Output Compare 4
interrupt I4_O5I    0xFFE0   Timer Input Capture 4/Output Compare
interrupt TOI       0xFFDE   Timer Overflow
interrupt PAOVI     0xFFDC   Pulse Accumulator Overflow
interrupt PAII      0xFFDA   Pulse Accumulator Input Edge
interrupt SPIE      0xFFD8   SPI Serial Transfer Complete
interrupt SCI       0xFFD6   SCI


; INPUT/ OUTPUT PORTS
PORTA         0x0000  Port A Data Register
PORTA.PA7      7   Port A Data Bit 7
PORTA.PA6      6   Port A Data Bit 6
PORTA.PA5      5   Port A Data Bit 5
PORTA.PA4      4   Port A Data Bit 4
PORTA.PA3      3   Port A Data Bit 3
PORTA.PA2      2   Port A Data Bit 2
PORTA.PA1      1   Port A Data Bit 1
PORTA.PA0      0   Port A Data Bit 0
RESERV0001    0x0001  RESERVED
PIOC          0x0002  Parallel I_O Control Register
PIOC.CWOM      5   Port C Wire-OR Mode (affects all eight port C pins)
PORTC         0x0003  Port C Data Register
PORTC.PC7      7   Port C Data Bit 7
PORTC.PC6      6   Port C Data Bit 6
PORTC.PC5      5   Port C Data Bit 5
PORTC.PC4      4   Port C Data Bit 4
PORTC.PC3      3   Port C Data Bit 3
PORTC.PC2      2   Port C Data Bit 2
PORTC.PC1      1   Port C Data Bit 1
PORTC.PC0      0   Port C Data Bit 0
PORTB         0x0004  Port B Data Register
PORTB.PB7      7   Port B Data Bit 7
PORTB.PB6      6   Port B Data Bit 6
PORTB.PB5      5   Port B Data Bit 5
PORTB.PB4      4   Port B Data Bit 4
PORTB.PB3      3   Port B Data Bit 3
PORTB.PB2      2   Port B Data Bit 2
PORTB.PB1      1   Port B Data Bit 1
PORTB.PB0      0   Port B Data Bit 0
RESERV0005    0x0005  RESERVED
DDRB          0x0006  Port B Data Direction Register
DDRB.DDB7      7   Data Direction for Port B Bit 7
DDRB.DDB6      6   Data Direction for Port B Bit 6
DDRB.DDB5      5   Data Direction for Port B Bit 5
DDRB.DDB4      4   Data Direction for Port B Bit 4
DDRB.DDB3      3   Data Direction for Port B Bit 3
DDRB.DDB2      2   Data Direction for Port B Bit 2
DDRB.DDB1      1   Data Direction for Port B Bit 1
DDRB.DDB0      0   Data Direction for Port BC Bit 0
DDRC          0x0007  Port C Data Direction Register
DDRC.DDC7      7   Data Direction for Port C Bit 7
DDRC.DDC6      6   Data Direction for Port C Bit 6
DDRC.DDC5      5   Data Direction for Port C Bit 5
DDRC.DDC4      4   Data Direction for Port C Bit 4
DDRC.DDC3      3   Data Direction for Port C Bit 3
DDRC.DDC2      2   Data Direction for Port C Bit 2
DDRC.DDC1      1   Data Direction for Port C Bit 1
DDRC.DDC0      0   Data Direction for Port C Bit 0
PORTD         0x0008  Port D Data Register
PORTD.PD7      7   Port D Data Bit 7
PORTD.PD6      6   Port D Data Bit 6
PORTD.PD5      5   Port D Data Bit 5
PORTD.PD4      4   Port D Data Bit 4
PORTD.PD3      3   Port D Data Bit 3
PORTD.PD2      2   Port D Data Bit 2
PORTD.PD1      1   Port D Data Bit 1
PORTD.PD0      0   Port D Data Bit 0
DDRD          0x0009  Port D Data Direction Register
DDRD.DDD7      7   Data Direction for Port D Bit 7
DDRD.DDD6      6   Data Direction for Port D Bit 6
DDRD.DDD5      5   Data Direction for Port D Bit 5
DDRD.DDD4      4   Data Direction for Port D Bit 4
DDRD.DDD3      3   Data Direction for Port D Bit 3
DDRD.DDD2      2   Data Direction for Port D Bit 2
DDRD.DDD1      1   Data Direction for Port D Bit 1
DDRD.DDD0      0   Data Direction for Port D Bit 0
RESERV000A    0x000A  RESERVED
CFORC         0x000B  Timer Compare Force Register
CFORC.FOC1     7   Write Ones to Force Compare 1
CFORC.FOC2     6   Write Ones to Force Compare 2
CFORC.FOC3     5   Write Ones to Force Compare 3
CFORC.FOC4     4   Write Ones to Force Compare 4
CFORC.FOC5     3   Write Ones to Force Compare 5
OC1M          0x000C  Output Compare 1 Mask Register
OC1M.OC1M7     7   Output Compare Mask 7
OC1M.OC1M6     6   Output Compare Mask 6
OC1M.OC1M5     5   Output Compare Mask 5
OC1M.OC1M4     4   Output Compare Mask 4
OC1M.OC1M3     3   Output Compare Mask 3
OC1D          0x000D  Output Compare 1 Data Register
OC1D.OC1D7     7   Output compare data for OC1 bit 7
OC1D.OC1D6     6   Output compare data for OC1 bit 6
OC1D.OC1D5     5   Output compare data for OC1 bit 5
OC1D.OC1D4     4   Output compare data for OC1 bit 4
OC1D.OC1D3     3   Output compare data for OC1 bit 3
TCNTH         0x000E  Timer Counter Register High
TCNTL         0x000F  Timer Counter Register Low
TIC1H         0x0010  Timer Input Capture 1 Register High
TIC1L         0x0011  Timer Input Capture 1 Register Low
TIC2H         0x0012  Timer Input Capture 2 Register High
TIC2L         0x0013  Timer Input Capture 2 Register Low
TIC3H         0x0014  Timer Input Capture 3 Register High
TIC3L         0x0015  Timer Input Capture 3 Register Low
TOC1H         0x0016  Timer Output Compare 1 High Register
TOC1L         0x0017  Timer Output Compare 1 Low Register
TOC2H         0x0018  Timer Output Compare 2 High Register
TOC2L         0x0019  Timer Output Compare 2 Low Register
TOC3H         0x001A  Timer Output Compare 3 High Register
TOC3L         0x001B  Timer Output Compare 3 Low Register
TOC4H         0x001C  Timer Output Compare 4 High Register
TOC4L         0x001D  Timer Output Compare 4 Low Register
TI4O5H        0x001E  Timer Input Capture 4_ Output Compare 5 Reg. High
TI4O5L        0x001F  Timer Input Capture 4_ Output Compare 5 Low Reg.
TCTL1         0x0020  Timer Control 1 Register
TCTL1.OM2      7   Output Mode 2
TCTL1.OL2      6   Output Level 2
TCTL1.OM3      5   Output Mode 3
TCTL1.OL3      4   Output Level 3
TCTL1.OM4      3   Output Mode 4
TCTL1.OL4      2   Output Level 4
TCTL1.OM5      1   Output Mode 5
TCTL1.OL5      0   Output Level 5
TCTL2         0x0021  Timer Control 2 Register
TCTL2.EDG4B    7   Input capture edge control 4B
TCTL2.EDG4A    6   Input capture edge control 4A
TCTL2.EDG1B    5   Input capture edge control 1B
TCTL2.EDG1A    4   Input capture edge control 1A
TCTL2.EDG2B    3   Input capture edge control 2B
TCTL2.EDG2A    2   Input capture edge control 2A
TCTL2.EDG3B    1   Input capture edge control 3B
TCTL2.EDG3A    0   Input capture edge control 3A
TMSK1         0x0022  Timer Interrupt Mask 1 Register
TMSK1.OC1I     7   Output Compare 1 Interrupt Enable
TMSK1.OC2I     6   Output Compare 2 Interrupt Enable
TMSK1.OC3I     5   Output Compare 3 Interrupt Enable
TMSK1.OC4I     4   Output Compare 4 Interrupt Enable
TMSK1.I4O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable
TMSK1.IC1I     2   Input Capture 1 Interrupt Enable
TMSK1.IC2I     1   Input Capture 2 Interrupt Enable
TMSK1.IC3I     0   Input Capture 3 Interrupt Enable
TFLG1         0x0023  Timer Interrupt Flag 1 Register
TFLG1.OC1F     7   Output Compare 1 Flag
TFLG1.OC2F     6   Output Compare 2 Flag
TFLG1.OC3F     5   Output Compare 3 Flag
TFLG1.OC4F     4   Output Compare 4 Flag
TFLG1.I4O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F     2   Input Capture 1 Flag
TFLG1.IC2F     1   Input Capture 2 Flag
TFLG1.IC3F     0   Input Capture 3 Flag
TMSK2         0x0024  Timer Interrupt Mask 2 Register
TMSK2.TOI      7   Timer Overflow Interrupt Enable
TMSK2.RTII     6   Real-Time Interrupt Enable
TMSK2.PAOVI    5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII     4   Pulse Accumulator Input Interrupt Enable
TMSK2.PR1      1   Timer Prescaler Select 1
TMSK2.PR0      0   Timer Prescaler Select 0
TFLG2         0x0025  Timer Interrupt Flag 2
TMSK2.TOF      7   Timer Overflow Flag
TMSK2.RTIF     6   Real-Time (Periodic) Interrupt Flag
TMSK2.PAOVF    5   Pulse Accumulator Overflow Flag
TMSK2.PAIF     4   Pulse Accumulator Input Edge Flag
PACTL         0x0026  Pulse Accumulator Control Register
PACTL.DDRA7    7   Data Direction for Port A Bit 7
PACTL.PAEN     6   Pulse Accumulator System Enable
PACTL.PAMOD    5   Pulse Accumulator Mode
PACTL.PEDGE    4   Pulse Accumulator Edge Control
PACTL.DDRA3    3   Data Direction for Port A Bit 3
PACTL.I4O5     2   Input Capture 4 or Output Compare 5 (IC4 or OC5)
PACTL.RTR1     1   RTI Interrupt Rate Select 1
PACTL.RTR0     0   RTI Interrupt Rate Select 0
PACNT         0x0027  Pulse Accumulator Count Register
SPCR          0x0028  Serial Peripheral Control Register
SPCR.SPIE      7   Serial Peripheral Interrupt Enable
SPCR.SPE       6   Serial Peripheral System Enable
SPCR.DWOM      5   Port D Wired-OR Mode Option for Pins PD5-PD0
SPCR.MSTR      4   Master Mode Select
SPCR.CPOL      3   Clock Polarity
SPCR.CPHA      2   Clock Phase
SPCR.SPR1      1   SPI Clock Rate Selects 1
SPCR.SPR0      0   SPI Clock Rate Selects 0
SPSR          0x0029  Serial Peripheral Status Register
SPSR.SPIF      7   SPI Transfer Complete Flag
SPSR.WCOL      6   Write Collision
SPSR.MODF      4   Mode Fault (A Mode Fault Terminates SPI Operation.)
SPDR          0x002A  Serial Peripheral Data Register
BAUD          0x002B  Baud Rate
BAUD.TCLR      7   Clear Baud Rate Counters (TEST)
BAUD.SCP1      5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0      4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB      3   SCI Baud-Rate Clock Check (TEST)
BAUD.SCR2      2   SCI Baud Rate Selects 2
BAUD.SCR1      1   SCI Baud Rate Selects 1
BAUD.SCR0      0   SCI Baud Rate Selects 0
SCCR1         0x002C  SCI Control Register 1
SCCR1.R8       7   Receive Data Bit 8
SCCR1.T8       6   Transmit Data Bit 8
SCCR1.M        4   Mode (Select Character Format)
SCCR1.WAKE     3   Wake-Up by Address Mark/Idle
SCCR2         0x002D  SCI Control Register 2
SCCR2.TIE      7   Transmit Interrupt Enable
SCCR2.TCIE     6   Transmit Complete Interrupt Enable
SCCR2.RIE      5   Receiver Interrupt Enable
SCCR2.ILIE     4   Idle Line Interrupt Enable
SCCR2.TE       3   Transmitter Enable
SCCR2.RE       2   Receiver Enable
SCCR2.RWU      1   Receiver Wake-Up Control
SCCR2.SBK      0   Send Break
SCSR          0x002E  SCI Status Register
SCSR.TDRE      7   Transmit Data Register Empty Flag
SCSR.TC        6   Transmit Complete Flag
SCSR.RDRF      5   Receive Data Register Full Flag
SCSR.IDLE      4   Idle Line Detected Flag
SCSR.OR        3   Overrun Error Flag
SCSR.NF        2   Noise Error Flag
SCSR.FE        1   Framing Error
SCDR          0x002F  SCI Data Register
SCDR.R7T7      7   Receiver/transmitter data bit 7
SCDR.R6T6      6   Receiver/transmitter data bit 6
SCDR.R5T5      5   Receiver/transmitter data bit 5
SCDR.R4T4      4   Receiver/transmitter data bit 4
SCDR.R3T3      3   Receiver/transmitter data bit 3
SCDR.R2T2      2   Receiver/transmitter data bit 2
SCDR.R1T1      1   Receiver/transmitter data bit 1
SCDR.R0T0      0   Receiver/transmitter data bit 0
RESERV0030    0x0030  RESERVED
RESERV0031    0x0031  RESERVED
RESERV0032    0x0032  RESERVED
RESERV0033    0x0033  RESERVED
RESERV0034    0x0034  RESERVED
RESERV0035    0x0035  RESERVED
RESERV0036    0x0036  RESERVED
RESERV0037    0x0037  RESERVED
RESERV0038    0x0038  RESERVED
OPTION        0x0039  OPTION
OPTION.IRQE    5   IRQ Select Edge Sensitive Only
OPTION.DLY     4   Enable Oscillator Start-Up Delay on Exit from STOP
OPTION.CME     3   Clock Monitor Enable
OPTION.CR1     1   COP Timer Rate Select 1
OPTION.CR0     0   COP Timer Rate Select 0
COPRST        0x003A  Arm_Reset COP Timer Circuitry Register
PPROG         0x003B  EEPROM Programming Control Register
PPROG.MBE      7   Multiple Byte Program Enable (TEST)
PPROG.ELAT     5   EPROM (OTPROM) Latch Control
PPROG.EXCOL    4   Select Extra Columns (TEST)
PPROG.EXROW    3   Select Extra Row (TEST)
PPROG.PGM      0   EPROM (OTPROM) Program Command
HPRIO         0x003C  Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT    7   Read Bootstrap ROM
HPRIO.SMOD     6   Special Mode Select
HPRIO.MDA      5   Mode Select A
HPRIO.IRVNE    4   Internal Read Visibility/Not E
HPRIO.PSEL3    3   Refer to Resets and Interrupts 3
HPRIO.PSEL2    2   Refer to Resets and Interrupts 2
HPRIO.PSEL1    1   Refer to Resets and Interrupts 1
HPRIO.PSEL0    0   Refer to Resets and Interrupts 0
INIT          0x003D  RAM and I_O Mapping Register
INIT.RAM3      7   192-Byte Internal RAM Map Position 3
INIT.RAM2      6   192-Byte Internal RAM Map Position 2
INIT.RAM1      5   192-Byte Internal RAM Map Position 1
INIT.RAM0      4   192-Byte Internal RAM Map Position 0
INIT.REG3      3   64-Byte Register Block Map Position 3
INIT.REG2      2   64-Byte Register Block Map Position 2
INIT.REG1      1   64-Byte Register Block Map Position 1
INIT.REG0      0   64-Byte Register Block Map Position 0
TEST1         0x003E  Test 1 Register
TEST1.TILOP    7   Test Illegal Opcode
TEST1.EPTST    6   EPROM Test
TEST1.OCCR     5   Output Condition Code Register to Timer Port
TEST1.CBYP     4   Timer Divider Chain Bypass
TEST1.DISR     3   Disable Resets from COP and Clock Monitor
TEST1.FCM      2   Force Clock Monitor Failure
TEST1.FCOP     1   Force COP Watchdog Failure
CONFIG        0x003F  ROM Mapping, COP, ROM, Enables
CONFIG.NOCOP   2   COP system disable
CONFIG.EPON    1   EPROM Enable
RESERVFFC0    0xFFC0  RESERVED
RESERVFFC1    0xFFC1  RESERVED
RESERVFFC2    0xFFC2  RESERVED
RESERVFFC3    0xFFC3  RESERVED
RESERVFFC4    0xFFC4  RESERVED
RESERVFFC5    0xFFC5  RESERVED
RESERVFFC6    0xFFC6  RESERVED
RESERVFFC7    0xFFC7  RESERVED
RESERVFFC8    0xFFC8  RESERVED
RESERVFFC9    0xFFC9  RESERVED
RESERVFFCA    0xFFCA  RESERVED
RESERVFFCB    0xFFCB  RESERVED
RESERVFFCC    0xFFCC  RESERVED
RESERVFFCD    0xFFCD  RESERVED
RESERVFFCE    0xFFCE  RESERVED
RESERVFFCF    0xFFCF  RESERVED
RESERVFFD0    0xFFD0  RESERVED
RESERVFFD1    0xFFD1  RESERVED
RESERVFFD2    0xFFD2  RESERVED
RESERVFFD3    0xFFD3  RESERVED
RESERVFFD4    0xFFD4  RESERVED
RESERVFFD5    0xFFD5  RESERVED


.68HC711E20
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC711E20&nodeId=01M98635
; M68HC11E.pdf

; RAM=768
; ROM=0
; EPROM=20K
; EEPROM=512


; MEMORY MAP
area DATA RAM          0x0000:0x0300
area BSS  RESERVED     0x0300:0x1000
area DATA FSR          0x1000:0x1040
area BSS  RESERVED     0x1040:0x9000
area DATA EPROM_0      0x9000:0xB000
area BSS  RESERVED     0xB000:0xB600
area DATA EEPROM       0xB600:0xB800
area BSS  RESERVED     0xB800:0xD000
area DATA EPROM_1      0xD000:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET     0xFFFE   Processor reset
interrupt CME         0xFFFC   Clock Monitor Fail
interrupt NOCOP       0xFFFA   COP Failure
interrupt OPC         0xFFF8   Illegal Opcode Trap
interrupt SOFT        0xFFF6   Software Interrupt
interrupt XIRQ        0xFFF4   XIRQ Pin
interrupt IRQ         0xFFF2   IRQ
interrupt RTII        0xFFF0   Real Time Interrupt
interrupt IC1I        0xFFEE   Timer Input Capture 1
interrupt IC2I        0xFFEC   Timer Input Capture 2
interrupt IC3I        0xFFEA   Timer Input Capture 3
interrupt OC1I        0xFFE8   Timer Output Compare 1
interrupt OC2I        0xFFE6   Timer Output Compare 2
interrupt OC3I        0xFFE4   Timer Output Compare 3
interrupt OC4I        0xFFE2   Timer Output Compare 4
interrupt I4_I5       0xFFE0   Timer Input Capture 4 / Output Compare 5
interrupt TOI         0xFFDE   Timer Overflow
interrupt PAOVI       0xFFDC   Pulse Accumulator Overflow
interrupt PAII        0xFFDA   Pulse Accumulator Input Edge
interrupt SPIE        0xFFD8   SPI Serial Transfer Complete
interrupt SCISS       0xFFD6   SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA           0x1000     Port A data
PORTA.PA7     	 7   Port A Data Bit 7
PORTA.PA6        6   Port A Data Bit 6
PORTA.PA5        5   Port A Data Bit 5
PORTA.PA4        4   Port A Data Bit 4
PORTA.PA3        3   Port A Data Bit 3
PORTA.PA2        2   Port A Data Bit 2
PORTA.PA1        1   Port A Data Bit 1
PORTA.PA0        0   Port A Data Bit 0
RESERV01        0x1001     RESERVED
PIOC            0x1002     Parallel I_O Control Register
PIOC.STAF        7   Strobe A Interrupt Status Flag
PIOC.STAI        6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM        5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS        4   Handshake Mode Bit
PIOC.OIN         3   Output or Input Handshake Select Bit
PIOC.PLS         2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA         1   Active Edge for Strobe A Bit
PIOC.INVB        0   Invert Strobe B Bit
PORTC           0x1003      Port C Data
PORTC.PC7        7   Port C Data Bit 7
PORTC.PC6        6   Port C Data Bit 6
PORTC.PC5        5   Port C Data Bit 5
PORTC.PC4        4   Port C Data Bit 4
PORTC.PC3        3   Port C Data Bit 3
PORTC.PC2        2   Port C Data Bit 2
PORTC.PC1        1   Port C Data Bit 1
PORTC.PC0        0   Port C Data Bit 0
PORTB           0x1004     Output Port B
PORTB.PB7        7   Port B Data Bit 7
PORTB.PB6        6   Port B Data Bit 6
PORTB.PB5        5   Port B Data Bit 5
PORTB.PB4        4   Port B Data Bit 4
PORTB.PB3        3   Port B Data Bit 3
PORTB.PB2        2   Port B Data Bit 2
PORTB.PB1        1   Port B Data Bit 1
PORTB.PB0        0   Port B Data Bit 0
PORTCL          0x1005     Alternate Latched Port C
PORTCL.PCL7      7
PORTCL.PCL6      6
PORTCL.PCL5      5
PORTCL.PCL4      4
PORTCL.PCL3      3
PORTCL.PCL2      2
PORTCL.PCL1      1
PORTCL.PCL0      0
RESERV1006      0x1006     RESERVED06
DDRC            0x1007     Data Direction for Port C
DDRC.DDC7        7   Data Direction for Port C Bit 7
DDRC.DDC6        6   Data Direction for Port C Bit 6
DDRC.DDC5        5   Data Direction for Port C Bit 5
DDRC.DDC4        4   Data Direction for Port C Bit 4
DDRC.DDC3        3   Data Direction for Port C Bit 3
DDRC.DDC2        2   Data Direction for Port C Bit 2
DDRC.DDC1        1   Data Direction for Port C Bit 1
DDRC.DDC0        0   Data Direction for Port C Bit 0
PORTD           0x1008     Port D Data
PORTD.PD5        5   Port D Data Bit 5
PORTD.PD4        4   Port D Data Bit 4
PORTD.PD3        3   Port D Data Bit 3
PORTD.PD2        2   Port D Data Bit 2
PORTD.PD1        1   Port D Data Bit 1
PORTD.PD0        0   Port D Data Bit 0
DDRD            0x1009     Data Direction for Port D
DDRD.DDD5        5   Data Direction for Port D Bit 5
DDRD.DDD4        4   Data Direction for Port D Bit 4
DDRD.DDD3        3   Data Direction for Port D Bit 3
DDRD.DDD2        2   Data Direction for Port D Bit 2
DDRD.DDD1        1   Data Direction for Port D Bit 1
DDRD.DDD0        0   Data Direction for Port D Bit 0
PORTE           0x100A     Port E Data
PORTE.PE7        7   Port E Data Bit 7
PORTE.PE6        6   Port E Data Bit 6
PORTE.PE5        5   Port E Data Bit 5
PORTE.PE4        4   Port E Data Bit 4
PORTE.PE3        3   Port E Data Bit 3
PORTE.PE2        2   Port E Data Bit 2
PORTE.PE1        1   Port E Data Bit 1
PORTE.PE0        0   Port E Data Bit 0
CFORC           0x100B     Timer Compare Force Register
CFORC.FOC1       7   Force Output Comparison Bit 1
CFORC.FOC2       6   Force Output Comparison Bit 2
CFORC.FOC3       5   Force Output Comparison Bit 3
CFORC.FOC4       4   Force Output Comparison Bit 4
CFORC.FOC5       3   Force Output Comparison Bit 5
OC1M            0x100C     Output Compare 1 Mask Register
OC1M.OC1M7       7   Output Compare Masks 7
OC1M.OC1M6       6   Output Compare Masks 6
OC1M.OC1M5       5   Output Compare Masks 5
OC1M.OC1M4       4   Output Compare Masks 4
OC1M.OC1M3       3   Output Compare Masks 3
OC1D            0x100D     Output Compare 1 Data Register
OC1D.OC1D7       7   Output compare data for OC1 bit 7
OC1D.OC1D6       6   Output compare data for OC1 bit 6
OC1D.OC1D5       5   Output compare data for OC1 bit 5
OC1D.OC1D4       4   Output compare data for OC1 bit 4
OC1D.OC1D3       3   Output compare data for OC1 bit 3
TCNTH           0x100E     Timer Counter Register
TCNTL           0x100F     Timer Counter Register
TIC1H           0x1010     Input Capture 1 Register
TIC1L           0x1011     Input Capture 1 Register
TIC2H           0x1012     Input Capture 2 Register
TIC2L           0x1013     Input Capture 2 Register
TIC3H           0x1014     Input Capture 3 Register
TIC3L           0x1015     Input Capture 3 Register
TOC1H           0x1016     Output Compare 1 Register
TOC1L           0x1017     Output Compare 1 Register
TOC2H           0x1018     Output Compare 2 Register
TOC2L           0x1019     Output Compare 2 Register
TOC3H           0x101A     Output Compare 3 Register
TOC3L           0x101B     Output Compare 3 Register
TOC4H           0x101C     Output Compare 4 Register
TOC4L           0x101D     Output Compare 4 Register
TCO5H           0x101E     Output Compare 5 Register
TCO5L           0x101F     Output Compare 5 Register
TCTL1           0x1020     Timer Control Register 1
TCTL1.OM2        7   Output Mode Bits 2
TCTL1.OL2        6   Output Level Bits 2
TCTL1.OM3        5   Output Mode Bits 3
TCTL1.OL3        4   Output Level Bits 3
TCTL1.OM4        3   Output Mode Bits 4
TCTL1.OL4        2   Output Level Bits 4
TCTL1.OM5        1   Output Mode Bits 5
TCTL1.OL5        0   Output Level Bits 5
TCTL2           0x1021     Timer Control Register 2
TCTL2.EDG4B      7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A      6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B      5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A      4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B      3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A      2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B      1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A      0   EDG3A  Input Capture Edge Control Bits
TMSK1           0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I       7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I       6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I       5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I       4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I     3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I       2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I       1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I       0   Input Capture 3 Interrupt Enable Bits
TFLG1           0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F       7   Output Compare 1 Flag
TFLG1.OC2F       6   Output Compare 2 Flag
TFLG1.OC3F       5   Output Compare 3 Flag
TFLG1.OC4F       4   Output Compare 4 Flag
TFLG1.I4_O5F     3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F       2   Input Capture 1 Flag
TFLG1.IC2F       1   Input Capture 2 Flag
TFLG1.IC3F       0   Input Capture 3 Flag
TMSK2           0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI        7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII       6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI      5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII       4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1        1   Timer Prescaler Select Bits 1
TMSK2.PR0        0   Timer Prescaler Select Bits 0
TFLG2           0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF        7   Timer Overflow Interrupt Flag
TFLG2.RTIF       6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF      5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF       4   Pulse Accumulator Input Edge Interrupt Flag
PACTL           0x1026     Pulse Accumulator Control Register
PACTL.DDRA7      7   Data Direction for Port A Bit 7
PACTL.PAEN       6   Pulse Accumulator System Enable Bit
PACTL.PAMOD      5   Pulse Accumulator Mode Bit
PACTL.PEDGE      4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3      3   Data Direction for Port A Bit 3
PACTL.I4_O5      2   Input Capture 4/Output Compare Bit
PACTL.RTR1       1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0       0   RTI Interrupt Rate Select Bits 0
PACNT           0x1027     Pulse Accumulator Count Register
SPCR            0x1028     SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE         6   Serial Peripheral System Enable Bit
SPCR.DWOM        5   Port D Wired-OR Mode Bit
SPCR.MSTR        4   Master Mode Select Bit
SPCR.CPOL        3   Clock Polarity Bit
SPCR.CPHA        2   Clock Phase Bit
SPCR.SPR1        1   SPI Clock Rate Select Bits 1
SPCR.SPR0        0   SPI Clock Rate Select Bits 0
SPSR            0x1029     SPI Status Register
SPSR.SPIF        7   SPI Interrupt Complete Flag
SPSR.WCOL        6   Write Collision Bit
SPSR.MODF        4   Mode Fault Bit
SPDR            0x102A     SPI Data Register
BAUD            0x102B     SCI Baud Rate Control 3
BAUD.TCLR        7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP2        6   SCI Baud Rate Prescaler Select Bits 2
BAUD.SCP1        5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0        4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB        3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2        2   SCI Baud Rate Select Bits 2
BAUD.SCR1        1   SCI Baud Rate Select Bits 1
BAUD.SCR0        0   SCI Baud Rate Select Bits 0
SCCR1           0x102C     SCI Control Register 1
SCCR1.R8         7   Receive Data Bit 8
SCCR1.T8         6   Transmit Data Bit 8
SCCR1.M          4   Mode Bit (select character format)
SCCR1.WAKE       3   Wakeup by Address Mark/Idle Bit
SCCR2           0x102D     Serial Communications Control Register 2
SCCR2.TIE        7   Transmit Interrupt Enable Bit
SCCR2.TCIE       6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE        5   Receiver Interrupt Enable Bit
SCCR2.ILIE       4   Idle-Line Interrupt Enable Bit
SCCR2.TE         3   Transmitter Enable Bit
SCCR2.RE         2   Receiver Enable Bit
SCCR2.RWU        1   Receiver Wakeup Control Bit
SCCR2.SBK        0   Send Break
SCSR            0x102E     Serial Communications Status Register
SCSR.TDRE        7   Transmit Data Register Empty Flag
SCSR.TC          6   Transmit Complete Flag
SCSR.RDRF        5   Receive Data Register Full Flag
SCSR.IDLE        4   Idle Line Detected Flag
SCSR.OR          3   Overrun Error Flag
SCSR.NF          2   Noise Error Flag
SCSR.FE          1   Framing Error Flag
SCDR            0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7        7   Receiver/Transmitter Bits 7
SCDR.R6T6        6   Receiver/Transmitter Bits 6
SCDR.R5T5        5   Receiver/Transmitter Bits 5
SCDR.R4T4        4   Receiver/Transmitter Bits 4
SCDR.R3T3        3   Receiver/Transmitter Bits 3
SCDR.R2T2        2   Receiver/Transmitter Bits 2
SCDR.R1T1        1   Receiver/Transmitter Bits 1
SCDR.R0T0        0   Receiver/Transmitter Bits 0
ADCTL           0x1030     A_D Control Register
ADCTL.CCF        7   Conversion Complete Flag
ADCTL.SCAN       5   Continuous Scan Control Bit
ADCTL.MULT       4   Multiple Channel/Single Channel Control Bit
ADCTL.CD         3   Channel Selects D Bits
ADCTL.CC         2   Channel Selects C Bits
ADCTL.CB         1   Channel Selects B Bits
ADCTL.CA         0   Channel Selects A Bits
ADR1            0x1031     A_D Result Register 1
ADR2            0x1032     A_D Result Register 2
ADR3            0x1033     A_D Result Register 3
ADR4            0x1034     A_D Result Register 4
BPROT           0x1035     Block Protect Register
BPROT.PTCON      4   Protect CONFIG Register Bit
BPROT.BPRT3      3   Block Protect Bits for EEPROM 3
BPROT.BPRT2      2   Block Protect Bits for EEPROM 2
BPROT.BPRT1      1   Block Protect Bits for EEPROM 1
BPROT.BPRT0      0   Block Protect Bits for EEPROM 0
EPROG           0x1036     EPROM Programming Control Register
EPROG.MBE        7   Multiple-Byte Programming Enable Bit
EPROG.ELAT       5   EPROM/OTPROM Latch Control Bit
EPROG.EXCOL      4   Select Extra Columns Bit
EPROG.EXROW      3   Select Extra Rows Bit
EPROG.T1         2   EPROM Test Mode Select Bit 1
EPROG.T0         1   EPROM Test Mode Select Bit 0
EPROG.PGM        0   EPROM Programming Voltage Enable Bit
RESERV1037      0x1037     RESERVED
RESERV1038      0x1038     RESERVED
OPTION          0x1039     System Configuration Options
OPTION.ADPU      7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL      6   Clock Select Bit
OPTION.IRQE      5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY       4   Enable Oscillator Startup Delay Bit
OPTION.CME       3   Clock Monitor Enable Bit
OPTION.CR1       1   COP Timer Rate Select Bits 1
OPTION.CR0       0   COP Timer Rate Select Bits 0
COPRST          0x103A     Arm_Reset COP Timer Circuitry
PPROG           0x103B     EEPROM Program Control Register
PPROG.ODD        7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN       6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE       4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW        3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE      2   Erase Mode Select Bit
PPROG.EELAT      1   EEPROM Latch Control Bit
PPROG.EEPGM      0   EPROM/OTPROM/EEPROM Programming
HPRIO           0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT      7   Read Bootstrap ROM Bit
HPRIO.SMOD       6   Special Mode Select
HPRIO.MDA        5   Mode Select A Bits
HPRIO.IRV        4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3      3   Priority Select Bits 3
HPRIO.PSEL2      2   Priority Select Bits 2
HPRIO.PSEL1      1   Priority Select Bits 1
HPRIO.PSEL0      0   Priority Select Bits 0
INIT            0x103D     RAM and I_O Mapping Register
INIT.RAM3        7   RAM Map Position Bits 3
INIT.RAM2        6   RAM Map Position Bits 2
INIT.RAM1        5   RAM Map Position Bits 1
INIT.RAM0        4   RAM Map Position Bits 0
INIT.REG3        3   64-Byte Register Block Position 3
INIT.REG2        2   64-Byte Register Block Position 2
INIT.REG1        1   64-Byte Register Block Position 1
INIT.REG0        0   64-Byte Register Block Position 0
RESERV3E        0x103E     RESERVED
CONFIG          0x103F     System Configuration Register
CONFIG.NOSEC     3   Security Disable Bit
CONFIG.NOCOP     2   COP System Disable Bit
CONFIG.ROMON     1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON      0   EEPROM Enable Bit
RESERVFFC0      0xFFC0     RESERVED
RESERVFFC1      0xFFC1     RESERVED
RESERVFFC2      0xFFC2     RESERVED
RESERVFFC3      0xFFC3     RESERVED
RESERVFFC4      0xFFC4     RESERVED
RESERVFFC5      0xFFC5     RESERVED
RESERVFFC6      0xFFC6     RESERVED
RESERVFFC7      0xFFC7     RESERVED
RESERVFFC8      0xFFC8     RESERVED
RESERVFFC9      0xFFC9     RESERVED
RESERVFFCA      0xFFCA     RESERVED
RESERVFFCB      0xFFCB     RESERVED
RESERVFFCC      0xFFCC     RESERVED
RESERVFFCD      0xFFCD     RESERVED
RESERVFFCE      0xFFCE     RESERVED
RESERVFFCF      0xFFCF     RESERVED
RESERVFFD0      0xFFD0     RESERVED
RESERVFFD1      0xFFD1     RESERVED
RESERVFFD2      0xFFD2     RESERVED
RESERVFFD3      0xFFD3     RESERVED
RESERVFFD4      0xFFD4     RESERVED
RESERVFFD5      0xFFD5     RESERVED


.68HC711E9
; http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC711E9&nodeId=01M98635 
; M68HC11E.pdf

; RAM=512
; ROM=0
; EPROM=12K
; EEPROM=512


; MEMORY MAP
area DATA RAM        0x0000:0x0200
area BSS  RESERVED   0x0200:0x1000
area DATA FSR        0x1000:0x1040
area BSS  RESERVED   0x1040:0xB600
area DATA EEPROM     0xB600:0xB800
area BSS  RESERVED   0xB800:0xD000
area DATA EPROM      0xD000:0xFFC0
area DATA USER_VEC   0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET    0xFFFE   Processor reset
interrupt CME        0xFFFC   Clock Monitor Fail
interrupt NOCOP      0xFFFA   COP Failure
interrupt OPC        0xFFF8   Illegal Opcode Trap
interrupt SOFT       0xFFF6   Software Interrupt
interrupt XIRQ       0xFFF4   XIRQ Pin
interrupt IRQ        0xFFF2   IRQ
interrupt RTII       0xFFF0   Real Time Interrupt
interrupt IC1I       0xFFEE   Timer Input Capture 1
interrupt IC2I       0xFFEC   Timer Input Capture 2
interrupt IC3I       0xFFEA   Timer Input Capture 3
interrupt OC1I       0xFFE8   Timer Output Compare 1
interrupt OC2I       0xFFE6   Timer Output Compare 2
interrupt OC3I       0xFFE4   Timer Output Compare 3
interrupt OC4I       0xFFE2   Timer Output Compare 4
interrupt I4_I5      0xFFE0   Timer Input Capture 4 / Output Compare 5
interrupt TOI        0xFFDE   Timer Overflow
interrupt PAOVI      0xFFDC   Pulse Accumulator Overflow
interrupt PAII       0xFFDA   Pulse Accumulator Input Edge
interrupt SPIE       0xFFD8   SPI Serial Transfer Complete
interrupt SCISS      0xFFD6   SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA           0x1000     Port A data
PORTA.PA7     	 7   Port A Data Bit 7
PORTA.PA6        6   Port A Data Bit 6
PORTA.PA5        5   Port A Data Bit 5
PORTA.PA4        4   Port A Data Bit 4
PORTA.PA3        3   Port A Data Bit 3
PORTA.PA2        2   Port A Data Bit 2
PORTA.PA1        1   Port A Data Bit 1
PORTA.PA0        0   Port A Data Bit 0
RESERV01        0x1001     RESERVED
PIOC            0x1002     Parallel I_O Control Register
PIOC.STAF        7   Strobe A Interrupt Status Flag
PIOC.STAI        6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM        5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS        4   Handshake Mode Bit
PIOC.OIN         3   Output or Input Handshake Select Bit
PIOC.PLS         2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA         1   Active Edge for Strobe A Bit
PIOC.INVB        0   Invert Strobe B Bit
PORTC           0x1003      Port C Data
PORTC.PC7        7   Port C Data Bit 7
PORTC.PC6        6   Port C Data Bit 6
PORTC.PC5        5   Port C Data Bit 5
PORTC.PC4        4   Port C Data Bit 4
PORTC.PC3        3   Port C Data Bit 3
PORTC.PC2        2   Port C Data Bit 2
PORTC.PC1        1   Port C Data Bit 1
PORTC.PC0        0   Port C Data Bit 0
PORTB           0x1004     Output Port B
PORTB.PB7        7   Port B Data Bit 7
PORTB.PB6        6   Port B Data Bit 6
PORTB.PB5        5   Port B Data Bit 5
PORTB.PB4        4   Port B Data Bit 4
PORTB.PB3        3   Port B Data Bit 3
PORTB.PB2        2   Port B Data Bit 2
PORTB.PB1        1   Port B Data Bit 1
PORTB.PB0        0   Port B Data Bit 0
PORTCL          0x1005     Alternate Latched Port C
PORTCL.PCL7      7
PORTCL.PCL6      6
PORTCL.PCL5      5
PORTCL.PCL4      4
PORTCL.PCL3      3
PORTCL.PCL2      2
PORTCL.PCL1      1
PORTCL.PCL0      0
RESERV1006      0x1006     RESERVED06
DDRC            0x1007     Data Direction for Port C
DDRC.DDC7        7   Data Direction for Port C Bit 7
DDRC.DDC6        6   Data Direction for Port C Bit 6
DDRC.DDC5        5   Data Direction for Port C Bit 5
DDRC.DDC4        4   Data Direction for Port C Bit 4
DDRC.DDC3        3   Data Direction for Port C Bit 3
DDRC.DDC2        2   Data Direction for Port C Bit 2
DDRC.DDC1        1   Data Direction for Port C Bit 1
DDRC.DDC0        0   Data Direction for Port C Bit 0
PORTD           0x1008     Port D Data
PORTD.PD5        5   Port D Data Bit 5
PORTD.PD4        4   Port D Data Bit 4
PORTD.PD3        3   Port D Data Bit 3
PORTD.PD2        2   Port D Data Bit 2
PORTD.PD1        1   Port D Data Bit 1
PORTD.PD0        0   Port D Data Bit 0
DDRD            0x1009     Data Direction for Port D
DDRD.DDD5        5   Data Direction for Port D Bit 5
DDRD.DDD4        4   Data Direction for Port D Bit 4
DDRD.DDD3        3   Data Direction for Port D Bit 3
DDRD.DDD2        2   Data Direction for Port D Bit 2
DDRD.DDD1        1   Data Direction for Port D Bit 1
DDRD.DDD0        0   Data Direction for Port D Bit 0
PORTE           0x100A     Port E Data
PORTE.PE7        7   Port E Data Bit 7
PORTE.PE6        6   Port E Data Bit 6
PORTE.PE5        5   Port E Data Bit 5
PORTE.PE4        4   Port E Data Bit 4
PORTE.PE3        3   Port E Data Bit 3
PORTE.PE2        2   Port E Data Bit 2
PORTE.PE1        1   Port E Data Bit 1
PORTE.PE0        0   Port E Data Bit 0
CFORC           0x100B     Timer Compare Force Register
CFORC.FOC1       7   Force Output Comparison Bit 1
CFORC.FOC2       6   Force Output Comparison Bit 2
CFORC.FOC3       5   Force Output Comparison Bit 3
CFORC.FOC4       4   Force Output Comparison Bit 4
CFORC.FOC5       3   Force Output Comparison Bit 5
OC1M            0x100C     Output Compare 1 Mask Register
OC1M.OC1M7       7   Output Compare Masks 7
OC1M.OC1M6       6   Output Compare Masks 6
OC1M.OC1M5       5   Output Compare Masks 5
OC1M.OC1M4       4   Output Compare Masks 4
OC1M.OC1M3       3   Output Compare Masks 3
OC1D            0x100D     Output Compare 1 Data Register
OC1D.OC1D7       7   Output compare data for OC1 bit 7
OC1D.OC1D6       6   Output compare data for OC1 bit 6
OC1D.OC1D5       5   Output compare data for OC1 bit 5
OC1D.OC1D4       4   Output compare data for OC1 bit 4
OC1D.OC1D3       3   Output compare data for OC1 bit 3
TCNTH           0x100E     Timer Counter Register
TCNTL           0x100F     Timer Counter Register
TIC1H           0x1010     Input Capture 1 Register
TIC1L           0x1011     Input Capture 1 Register
TIC2H           0x1012     Input Capture 2 Register
TIC2L           0x1013     Input Capture 2 Register
TIC3H           0x1014     Input Capture 3 Register
TIC3L           0x1015     Input Capture 3 Register
TOC1H           0x1016     Output Compare 1 Register
TOC1L           0x1017     Output Compare 1 Register
TOC2H           0x1018     Output Compare 2 Register
TOC2L           0x1019     Output Compare 2 Register
TOC3H           0x101A     Output Compare 3 Register
TOC3L           0x101B     Output Compare 3 Register
TOC4H           0x101C     Output Compare 4 Register
TOC4L           0x101D     Output Compare 4 Register
TCO5H           0x101E     Output Compare 5 Register
TCO5L           0x101F     Output Compare 5 Register
TCTL1           0x1020     Timer Control Register 1
TCTL1.OM2        7   Output Mode Bits 2
TCTL1.OL2        6   Output Level Bits 2
TCTL1.OM3        5   Output Mode Bits 3
TCTL1.OL3        4   Output Level Bits 3
TCTL1.OM4        3   Output Mode Bits 4
TCTL1.OL4        2   Output Level Bits 4
TCTL1.OM5        1   Output Mode Bits 5
TCTL1.OL5        0   Output Level Bits 5
TCTL2           0x1021     Timer Control Register 2
TCTL2.EDG4B      7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A      6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B      5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A      4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B      3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A      2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B      1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A      0   EDG3A  Input Capture Edge Control Bits
TMSK1           0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I       7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I       6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I       5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I       4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I     3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I       2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I       1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I       0   Input Capture 3 Interrupt Enable Bits
TFLG1           0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F       7   Output Compare 1 Flag
TFLG1.OC2F       6   Output Compare 2 Flag
TFLG1.OC3F       5   Output Compare 3 Flag
TFLG1.OC4F       4   Output Compare 4 Flag
TFLG1.I4_O5F     3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F       2   Input Capture 1 Flag
TFLG1.IC2F       1   Input Capture 2 Flag
TFLG1.IC3F       0   Input Capture 3 Flag
TMSK2           0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI        7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII       6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI      5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII       4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1        1   Timer Prescaler Select Bits 1
TMSK2.PR0        0   Timer Prescaler Select Bits 0
TFLG2           0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF        7   Timer Overflow Interrupt Flag
TFLG2.RTIF       6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF      5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF       4   Pulse Accumulator Input Edge Interrupt Flag
PACTL           0x1026     Pulse Accumulator Control Register
PACTL.DDRA7      7   Data Direction for Port A Bit 7
PACTL.PAEN       6   Pulse Accumulator System Enable Bit
PACTL.PAMOD      5   Pulse Accumulator Mode Bit
PACTL.PEDGE      4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3      3   Data Direction for Port A Bit 3
PACTL.I4_O5      2   Input Capture 4/Output Compare Bit
PACTL.RTR1       1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0       0   RTI Interrupt Rate Select Bits 0
PACNT           0x1027     Pulse Accumulator Count Register
SPCR            0x1028     SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE         6   Serial Peripheral System Enable Bit
SPCR.DWOM        5   Port D Wired-OR Mode Bit
SPCR.MSTR        4   Master Mode Select Bit
SPCR.CPOL        3   Clock Polarity Bit
SPCR.CPHA        2   Clock Phase Bit
SPCR.SPR1        1   SPI Clock Rate Select Bits 1
SPCR.SPR0        0   SPI Clock Rate Select Bits 0
SPSR            0x1029     SPI Status Register
SPSR.SPIF        7   SPI Interrupt Complete Flag
SPSR.WCOL        6   Write Collision Bit
SPSR.MODF        4   Mode Fault Bit
SPDR            0x102A     SPI Data Register
BAUD            0x102B     SCI Baud Rate Control 3
BAUD.TCLR        7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP1        5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0        4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB        3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2        2   SCI Baud Rate Select Bits 2
BAUD.SCR1        1   SCI Baud Rate Select Bits 1
BAUD.SCR0        0   SCI Baud Rate Select Bits 0
SCCR1           0x102C     SCI Control Register 1
SCCR1.R8         7   Receive Data Bit 8
SCCR1.T8         6   Transmit Data Bit 8
SCCR1.M          4   Mode Bit (select character format)
SCCR1.WAKE       3   Wakeup by Address Mark/Idle Bit
SCCR2           0x102D     Serial Communications Control Register 2
SCCR2.TIE        7   Transmit Interrupt Enable Bit
SCCR2.TCIE       6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE        5   Receiver Interrupt Enable Bit
SCCR2.ILIE       4   Idle-Line Interrupt Enable Bit
SCCR2.TE         3   Transmitter Enable Bit
SCCR2.RE         2   Receiver Enable Bit
SCCR2.RWU        1   Receiver Wakeup Control Bit
SCCR2.SBK        0   Send Break
SCSR            0x102E     Serial Communications Status Register
SCSR.TDRE        7   Transmit Data Register Empty Flag
SCSR.TC          6   Transmit Complete Flag
SCSR.RDRF        5   Receive Data Register Full Flag
SCSR.IDLE        4   Idle Line Detected Flag
SCSR.OR          3   Overrun Error Flag
SCSR.NF          2   Noise Error Flag
SCSR.FE          1   Framing Error Flag
SCDR            0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7        7   Receiver/Transmitter Bits 7
SCDR.R6T6        6   Receiver/Transmitter Bits 6
SCDR.R5T5        5   Receiver/Transmitter Bits 5
SCDR.R4T4        4   Receiver/Transmitter Bits 4
SCDR.R3T3        3   Receiver/Transmitter Bits 3
SCDR.R2T2        2   Receiver/Transmitter Bits 2
SCDR.R1T1        1   Receiver/Transmitter Bits 1
SCDR.R0T0        0   Receiver/Transmitter Bits 0
ADCTL           0x1030     A_D Control Register
ADCTL.CCF        7   Conversion Complete Flag
ADCTL.SCAN       5   Continuous Scan Control Bit
ADCTL.MULT       4   Multiple Channel/Single Channel Control Bit
ADCTL.CD         3   Channel Selects D Bits
ADCTL.CC         2   Channel Selects C Bits
ADCTL.CB         1   Channel Selects B Bits
ADCTL.CA         0   Channel Selects A Bits
ADR1            0x1031     A_D Result Register 1
ADR2            0x1032     A_D Result Register 2
ADR3            0x1033     A_D Result Register 3
ADR4            0x1034     A_D Result Register 4
BPROT           0x1035     Block Protect Register
BPROT.PTCON      4   Protect CONFIG Register Bit
BPROT.BPRT3      3   Block Protect Bits for EEPROM 3
BPROT.BPRT2      2   Block Protect Bits for EEPROM 2
BPROT.BPRT1      1   Block Protect Bits for EEPROM 1
BPROT.BPRT0      0   Block Protect Bits for EEPROM 0
RESERV1036      0x1036     RESERVED
RESERV1037      0x1037     RESERVED
RESERV1038      0x1038     RESERVED
OPTION          0x1039     System Configuration Options
OPTION.ADPU      7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL      6   Clock Select Bit
OPTION.IRQE      5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY       4   Enable Oscillator Startup Delay Bit
OPTION.CME       3   Clock Monitor Enable Bit
OPTION.CR1       1   COP Timer Rate Select Bits 1
OPTION.CR0       0   COP Timer Rate Select Bits 0
COPRST          0x103A     Arm_Reset COP Timer Circuitry
PPROG           0x103B     EEPROM Program Control Register
PPROG.ODD        7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN       6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE       4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW        3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE      2   Erase Mode Select Bit
PPROG.EELAT      1   EEPROM Latch Control Bit
PPROG.EEPGM      0   EPROM/OTPROM/EEPROM Programming
HPRIO           0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT      7   Read Bootstrap ROM Bit
HPRIO.SMOD       6   Special Mode Select
HPRIO.MDA        5   Mode Select A Bits
HPRIO.IRV        4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3      3   Priority Select Bits 3
HPRIO.PSEL2      2   Priority Select Bits 2
HPRIO.PSEL1      1   Priority Select Bits 1
HPRIO.PSEL0      0   Priority Select Bits 0
INIT            0x103D     RAM and I_O Mapping Register
INIT.RAM3        7   RAM Map Position Bits 3
INIT.RAM2        6   RAM Map Position Bits 2
INIT.RAM1        5   RAM Map Position Bits 1
INIT.RAM0        4   RAM Map Position Bits 0
INIT.REG3        3   64-Byte Register Block Position 3
INIT.REG2        2   64-Byte Register Block Position 2
INIT.REG1        1   64-Byte Register Block Position 1
INIT.REG0        0   64-Byte Register Block Position 0
RESERV3E        0x103E     RESERVED
CONFIG          0x103F     System Configuration Register
CONFIG.NOSEC     3   Security Disable Bit
CONFIG.NOCOP     2   COP System Disable Bit
CONFIG.ROMON     1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON      0   EEPROM Enable Bit
RESERVFFC0      0xFFC0     RESERVED
RESERVFFC1      0xFFC1     RESERVED
RESERVFFC2      0xFFC2     RESERVED
RESERVFFC3      0xFFC3     RESERVED
RESERVFFC4      0xFFC4     RESERVED
RESERVFFC5      0xFFC5     RESERVED
RESERVFFC6      0xFFC6     RESERVED
RESERVFFC7      0xFFC7     RESERVED
RESERVFFC8      0xFFC8     RESERVED
RESERVFFC9      0xFFC9     RESERVED
RESERVFFCA      0xFFCA     RESERVED
RESERVFFCB      0xFFCB     RESERVED
RESERVFFCC      0xFFCC     RESERVED
RESERVFFCD      0xFFCD     RESERVED
RESERVFFCE      0xFFCE     RESERVED
RESERVFFCF      0xFFCF     RESERVED
RESERVFFD0      0xFFD0     RESERVED
RESERVFFD1      0xFFD1     RESERVED
RESERVFFD2      0xFFD2     RESERVED
RESERVFFD3      0xFFD3     RESERVED
RESERVFFD4      0xFFD4     RESERVED
RESERVFFD5      0xFFD5     RESERVED


.68HC711G5
; MC68HC11G5/D     http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11G5.pdf
; MC68HC11G5.pdf

; RAM=512
; ROM=0
; EPROM=16K
; EEPROM=0


; MEMORY MAP
area DATA RAM        0x0000:0x0200
area BSS  RESERVED   0x0200:0x1000
area DATA FSR        0x1000:0x1080
area BSS  RESERVED   0x1080:0xC000
area DATA EPROM      0xC000:0xFFC0
area DATA USER_VEC   0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SWI               0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI1              0xFFDE      Timer Overflow 1
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System
interrupt OC6_IC5           0xFFD4      Timer Output Compare 6/Input Capture 5
interrupt OC7_IC6           0xFFD2      Timer Output Compare 7/Input Capture 6
interrupt TO2               0xFFD0      Timer Overflow 2
interrupt Event_1           0xFFCE      Event 1
interrupt Event_2           0xFFCC      Event 2


; INPUT/ OUTPUT PORTS
PORTA           0x1000   PORTA I_O Port A
PORTA.PA7        7   Port A Data Bit 7
PORTA.PA6        6   Port A Data Bit 6
PORTA.PA5        5   Port A Data Bit 5
PORTA.PA4        4   Port A Data Bit 4
PORTA.PA3        3   Port A Data Bit 3
PORTA.PA2        2   Port A Data Bit 2
PORTA.PA1        1   Port A Data Bit 1
PORTA.PA0        0   Port A Data Bit 0
DDRA            0x1001   DDRA Data Direction for Port A
DDRA.DDA7        7   Data Direction for Port A Bit 7
DDRA.DDA6        6   Data Direction for Port A Bit 6
DDRA.DDA5        5   Data Direction for Port A Bit 5
DDRA.DDA4        4   Data Direction for Port A Bit 4
DDRA.DDA3        3   Data Direction for Port A Bit 3
DDRA.DDA2        2   Data Direction for Port A Bit 2
DDRA.DDA1        1   Data Direction for Port A Bit 1
DDRA.DDA0        0   Data Direction for Port A Bit 0
PORTG           0x1002   PORTG I_O Port G
PORTG.PG7        7   Port G Data Bit 7
PORTG.PG6        6   Port G Data Bit 6
PORTG.PG5        5   Port G Data Bit 5
PORTG.PG4        4   Port G Data Bit 4
PORTG.PG3        3   Port G Data Bit 3
PORTG.PG2        2   Port G Data Bit 2
PORTG.PG1        1   Port G Data Bit 1
PORTG.PG0        0   Port G Data Bit 0
DDRG            0x1003   DDRG Data Direction for Port G
DDRG.DDG7        7   Data Direction for Port G Bit 7
DDRG.DDG6        6   Data Direction for Port G Bit 6
DDRG.DDG5        5   Data Direction for Port G Bit 5
DDRG.DDG4        4   Data Direction for Port G Bit 4
DDRG.DDG3        3   Data Direction for Port G Bit 3
DDRG.DDG2        2   Data Direction for Port G Bit 2
DDRG.DDG1        1   Data Direction for Port G Bit 1
DDRG.DDG0        0   Data Direction for Port G Bit 0
PORTB           0x1004   PORTB I_O Port B
PORTB.PB7        7   Port B Data Bit 7
PORTB.PB6        6   Port B Data Bit 6
PORTB.PB5        5   Port B Data Bit 5
PORTB.PB4        4   Port B Data Bit 4
PORTB.PB3        3   Port B Data Bit 3
PORTB.PB2        2   Port B Data Bit 2
PORTB.PB1        1   Port B Data Bit 1
PORTB.PB0        0   Port B Data Bit 0
PORTF           0x1005   PORTF I_O Port F
PORTF.PF7        7   Port F Data Bit 7
PORTF.PF6        6   Port F Data Bit 6
PORTF.PF5        5   Port F Data Bit 5
PORTF.PF4        4   Port F Data Bit 4
PORTF.PF3        3   Port F Data Bit 3
PORTF.PF2        2   Port F Data Bit 2
PORTF.PF1        1   Port F Data Bit 1
PORTF.PF0        0   Port F Data Bit 0
PORTC           0x1006   PORTC I_O Port C
PORTC.PC7        7   Port C Data Bit 7
PORTC.PC6        6   Port C Data Bit 6
PORTC.PC5        5   Port C Data Bit 5
PORTC.PC4        4   Port C Data Bit 4
PORTC.PC3        3   Port C Data Bit 3
PORTC.PC2        2   Port C Data Bit 2
PORTC.PC1        1   Port C Data Bit 1
PORTC.PC0        0   Port C Data Bit 0
DDRC            0x1007   DDRC Data Direction for Port C
DDRC.DDC7        7   Data Direction for Port C Bit 7
DDRC.DDC6        6   Data Direction for Port C Bit 6
DDRC.DDC5        5   Data Direction for Port C Bit 5
DDRC.DDC4        4   Data Direction for Port C Bit 4
DDRC.DDC3        3   Data Direction for Port C Bit 3
DDRC.DDC2        2   Data Direction for Port C Bit 2
DDRC.DDC1        1   Data Direction for Port C Bit 1
DDRC.DDC0        0   Data Direction for Port C Bit 0
PORTD           0x1008   PORTD I_O Port D
PORTD.PD5        5   Port D Data Bit 5
PORTD.PD4        4   Port D Data Bit 4
PORTD.PD3        3   Port D Data Bit 3
PORTD.PD2        2   Port D Data Bit 2
PORTD.PD1        1   Port D Data Bit 1
PORTD.PD0        0   Port D Data Bit 0
DDRD            0x1009   DDRD Data Direction for Port D
DDRD.DDD5        5   Data Direction for Port D Bit 5
DDRD.DDD4        4   Data Direction for Port D Bit 4
DDRD.DDD3        3   Data Direction for Port D Bit 3
DDRD.DDD2        2   Data Direction for Port D Bit 2
DDRD.DDD1        1   Data Direction for Port D Bit 1
DDRD.DDD0        0   Data Direction for Port D Bit 0
PORTE           0x100A   PORTE I_O Port E
PORTE.PE7        7   Port E Data Bit 7
PORTE.PE6        6   Port E Data Bit 6
PORTE.PE5        5   Port E Data Bit 5
PORTE.PE4        4   Port E Data Bit 4
PORTE.PE3        3   Port E Data Bit 3
PORTE.PE2        2   Port E Data Bit 2
PORTE.PE1        1   Port E Data Bit 1
PORTE.PE0        0   Port E Data Bit 0
CFORC           0x100B   CFORC Compare Force Register
CFORC.FOC1       7   Force Output Comparison 1
CFORC.FOC2       6   Force Output Comparison 2
CFORC.FOC3       5   Force Output Comparison 3
CFORC.FOC4       4   Force Output Comparison 4
CFORC.FOC5       3   Force Output Comparison 5
CFORC.FOC6       2   Force Output Comparison 6
CFORC.FOC7       1   Force Output Comparison 7
OC1M            0x100C   OC1M OC1 Action Mask Register
OC1M.OC1M7       7   Output Compare Masks 7
OC1M.OC1M6       6   Output Compare Masks 6
OC1M.OC1M5       5   Output Compare Masks 5
OC1M.OC1M4       4   Output Compare Masks 4
OC1M.OC1M3       3   Output Compare Masks 3
OC1D            0x100D   OC1D OC1 Action Data Register
OC1D.OC1D7       7   Output Compare Data 7
OC1D.OC1D6       6   Output Compare Data 6
OC1D.OC1D5       5   Output Compare Data 5
OC1D.OC1D4       4   Output Compare Data 4
OC1D.OC1D3       3   Output Compare Data 3
TCNT1H          0x100E   TCNT1H Timer Counter Register 1 H
TCNT1L          0x100F   TCNT1L Timer Counter Register 1 L
TIC1H           0x1010   TIC1H Input Capture 1 Register H
TIC1L           0x1011   TIC1L Input Capture 1 Register L
TIC2H           0x1012   TIC2H Input Capture 2 Register H
TIC2L           0x1013   TIC2L Input Capture 2 Register L
TIC3H           0x1014   TIC3H Input Capture 3 Register H
TIC3L           0x1015   TIC3L Input Capture 3 Register L
TOC1H           0x1016   TOC1H Output Compare 1 Register H
TOC1L           0x1017   TOC1L Output Compare 1 Register L
TOC2H           0x1018   TOC2H Output Compare 2 Register H
TOC2L           0x1019   TOC2L Output Compare 2 Register L
TOC3H           0x101A   TOC3H Output Compare 3 Register H
TOC3L           0x101B   TOC3L Output Compare 3 Register L
TOC4H           0x101C   TOC4H Output Compare 4 Register H
TOC4L           0x101D   TOC4L Output Compare 4 Register L
TO5I4H          0x101E   TO5I4H Output Compare 5_Input Capture 4 Register H
TO5I4L          0x101F   TO5I4L Output Compare 5_Input Capture 4 Register L
TCTL1           0x1020   TCTL1 Timer Control Register 1
TCTL1.OM2        7   Output Mode 2
TCTL1.OL2        6   Output Level 2
TCTL1.OM3        5   Output Mode 3
TCTL1.OL3        4   Output Level 3
TCTL1.OM4        3   Output Mode 4
TCTL1.OL4        2   Output Level 4
TCTL1.OM5        1   Output Mode 5
TCTL1.OL5        0   Output Level 5
TCTL2           0x1021   TCTL2 Timer Control Register 2
TCTL2.EDG4B      7   EDG4B Input Capture Edge Control
TCTL2.EDG4A      6   EDG4A Input Capture Edge Control
TCTL2.EDG1B      5   EDG1B Input Capture Edge Control
TCTL2.EDG1A      4   EDG1A Input Capture Edge Control
TCTL2.EDG2B      3   EDG2B Input Capture Edge Control
TCTL2.EDG2A      2   EDG2A Input Capture Edge Control
TCTL2.EDG3B      1   EDG3B Input Capture Edge Control
TCTL2.EDG3A      0   EDG3A Input Capture Edge Control
TMSK1           0x1022   TMSK1 Main Timer Interrupt Mask Register 1
TMSK1.OC1I       7   Output Compare 1 Interrupt Enable
TMSK1.OC2I       6   Output Compare 2 Interrupt Enable
TMSK1.OC3I       5   Output Compare 3 Interrupt Enable
TMSK1.OC4I       4   Output Compare 4 Interrupt Enable
TMSK1.4_5I       3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I       2   Input Capture 1 Interrupt Enable
TMSK1.IC2I       1   Input Capture 2 Interrupt Enable
TMSK1.IC3I       0   Input Capture 3 Interrupt Enable
TFLG1           0x1023   TFLG1 Main Timer Interrupt Flag Register 1
TFLG1.OC1F       7   Output Compare 1 Flag
TFLG1.OC2F       6   Output Compare 2 Flag
TFLG1.OC3F       5   Output Compare 3 Flag
TFLG1.OC4F       4   Output Compare 4 Flag
TFLG1.4_5F       3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F       2   Input Capture 1 Flag
TFLG1.IC2F       1   Input Capture 2 Flag
TFLG1.IC3F       0   Input Capture 3 Flag
TMSK2           0x1024   TMSK2 Misc. Timer Interrupt Mask Register 2
TMSK2.TO1I       7   Timer Overflow 1 Interrupt Enable
TMSK2.RTII       6   RTI Interrupt Enable
TMSK2.PAOVI      5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII       4   Pulse Accumulator Input Interrupt Enable
TMSK2.TO2I       3   Timer Overflow 2 Interrupt Enable
TMSK2.5_6I       2   Input Capture 5/Output Compare 6 Interrupt Enable
TMSK2.6_7I       1   Input Capture 6/Output Compare 7 Interrupt Enable
TFLG2           0x1025   TFLG2 Misc. Timer Interrupt Flag Register 2
TFLG2.TO1F       7   Timer Overflow 1 Flag
TFLG2.RTIF       6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF      5   Pulse Accumulator Overflow Flag
TFLG2.PAIF       4   Pulse Accumulator Input Edge Flag
TFLG2.TO2F       3   Timer Overflow 2 Flag
TFLG2.5_6F       2   Input Capture 5/Output Compare 6 Flag
TFLG2.6_7F       1   Input Capture 6/Output Compare 7 Flag
PACTL           0x1026   PACTL Pulse Accumulator Control Register
PACTL.PAEN       6   Pulse Accumulator System Enable
PACTL.PAMOD      5   Pulse Accumulator Mode
PACTL.PEDGE      4   Pulse Accumulator Edge Control
PACTL.I4_O5      3   Input Capture 4/Output Compare
PACTL.RTR2       2   RTI Interrupt Rate Select 2
PACTL.RTR1       1   RTI Interrupt Rate Select 1
PACTL.RTR0       0   RTI Interrupt Rate Select 0
PACNT           0x1027   PACNT Pulse Accumulator Count Register
SPCR            0x1028   SPCR SPI Control Register
SPCR.SPIE        7   Serial Peripheral Interrupt Enable
SPCR.SPE         6   Serial Peripheral System Enable
SPCR.DWOM        5   Port D Wired-OR Mode
SPCR.MSTR        4   Master Mode Select
SPCR.CPOL        3   Clock Polarity
SPCR.CPHA        2   Clock Phase
SPCR.SPR1        1   SPI Clock Rate Selects 1
SPCR.SPR0        0   SPI Clock Rate Selects 0
SPSR            0x1029   SPSR SPI Status Register
SPSR.SPIF        7   SPI Interrupt Complete Flag
SPSR.WCOL        6   Write Collision
SPSR.MODF        4   Mode Fault
SPDAT           0x102A   SPDAT SPI Data Register
BAUD            0x102B   BAUD SCI Baud Rate Control
BAUD.TCLR        7   Clear Baud Rate Counters (Test)
BAUD.SCP1        5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0        4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB        3   SCI Receive Baud Rate Clock Test
BAUD.SCR2        2   SCI Baud Rate Selects 2
BAUD.SCR1        1   SCI Baud Rate Selects 1
BAUD.SCR0        0   SCI Baud Rate Selects 0
SCCR1           0x102C   SCCR1 SCI Control Register 1
SCCR1.R8         7   Receive Data Bit 8
SCCR1.T8         6   Transmit Data Bit 8
SCCR1.M          4   Mode (Select Character Format)
SCCR1.WAKE       3   Wakeup by Address Mark/Idle
SCCR2           0x102D   SCCR2 SCI Control Register 2
SCCR2.TIE        7   Transmit Interrupt Enable
SCCR2.TCIE       6   Transmit Complete Interrupt Enable
SCCR2.RIE        5   Receiver Interrupt Enable
SCCR2.ILIE       4   Idle-Line Interrupt Enable
SCCR2.TE         3   Transmitter Enable
SCCR2.RE         2   Receiver Enable
SCCR2.RWU        1   Receiver Wakeup Control
SCCR2.SBK        0   Send Break
SCSR            0x102E   SCSR SCI Status Register
SCSR.TDRE        7   Transmit Data Register Empty Flag
SCSR.TC          6   Transmit Complete Flag
SCSR.RDRF        5   Receive Data Register Full Flag
SCSR.IDLE        4   Idle Line Detected Flag
SCSR.OR          3   Overrun Error Flag
SCSR.NF          2   Noise Error Flag
SCSR.FE          1   Framing Error
SCDAT           0x102F   SCDAT SCI Data (Read RDR, Write TDR)
ADCTL           0x1030   ADCTL A_D Control Register
ADCTL.CCF        7   Conversions Complete Flag
ADCTL.CONV8      6   Convert 8/Convert 4 Select Bit
ADCTL.SCAN       5   Continuous Scan Control
ADCTL.MULT       4   Multiple Channel/Single Channel Control
ADCTL.CD         3   Channel Select Bits D
ADCTL.CC         2   Channel Select Bits C
ADCTL.CB         1   Channel Select Bits B
ADCTL.CA         0   Channel Select Bits A
PORTJ           0x1031   PORTJ I_O Port J
PORTJ.PJ3        3   Port J Data Bit 3
PORTJ.PJ2        2   Port J Data Bit 2
PORTJ.PJ1        1   Port J Data Bit 1
PORTJ.PJ0        0   Port J Data Bit 0
DDRJ            0x1032   DDRJ Data Direction for Port J
DDRJ.DDJ3        3   Data Direction for Port J Bit 3
DDRJ.DDJ2        2   Data Direction for Port J Bit 2
DDRJ.DDJ1        1   Data Direction for Port J Bit 1
DDRJ.DDJ0        0   Data Direction for Port J Bit 0
PORTH           0x1033   PORTH I_O Port H
PORTH.PH7        7   Port H Data Bit 7
PORTH.PH6        6   Port H Data Bit 6
PORTH.PH5        5   Port H Data Bit 5
PORTH.PH4        4   Port H Data Bit 4
PORTH.PH3        3   Port H Data Bit 3
PORTH.PH2        2   Port H Data Bit 2
PORTH.PH1        1   Port H Data Bit 1
PORTH.PH0        0   Port H Data Bit 0
DDRH            0x1034   DDRH Data Direction for Port H
DDRH.DDH7        7   Data Direction for Port H Bit 7
DDRH.DDH6        6   Data Direction for Port H Bit 6
DDRH.DDH5        5   Data Direction for Port H Bit 5
DDRH.DDH4        4   Data Direction for Port H Bit 4
DDRH.DDH3        3   Data Direction for Port H Bit 3
DDRH.DDH2        2   Data Direction for Port H Bit 2
DDRH.DDH1        1   Data Direction for Port H Bit 1
DDRH.DDH0        0   Data Direction for Port H Bit 0
RESERV1035      0x1035   RESERVED
RESERV1036      0x1036   RESERVED
RESERV1037      0x1037   RESERVED
OPT2            0x1038   OPT2 System Configuration Options 2 Reg.
OPT2.GWOM        7   Port G Wired-OR Mode
OPT2.CWOM        6   Port C Wired-OR Mode
OPT2.IRV         4   Internal Read Visibility
OPT2.MRDY        1   Memory Ready Enable
OPT2.NHALT       0   Enable Halt Function
OPTION          0x1039   OPTION System Configuration Options
OPTION.ADPU      7   A/D Power Up
OPTION.CSEL      6   Clock Select
OPTION.IRQE      5   IRQ Select Edge Sensitive Only
OPTION.DLY       4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME       3   Clock Monitor Enable
OPTION.CR1       1   COP Timer Rate select bits 1
OPTION.CR0       0   COP Timer Rate select bits 0
COPRST          0x103A   COPRST Arm_Reset COP Timer Circuitry
RESERV103B      0x103B   RESERVED
HPRIO           0x103C   HPRIO Highest Priority I-terrupt and Misc.
HPRIO.RBOOT      7   Read Bootstrap ROM
HPRIO.SMOD       6   Special Mode Select
HPRIO.MDA        5   Mode Select A
HPRIO.PSEL4      4   Priority Select Bits 4
HPRIO.PSEL3      3   Priority Select Bits 3
HPRIO.PSEL2      2   Priority Select Bits 2
HPRIO.PSEL1      1   Priority Select Bits 1
HPRIO.PSEL0      0   Priority Select Bits 0
INIT            0x103D   INIT RAM and I_O Mapping Register
INIT.RAM3        7   RAM Map Position 3
INIT.RAM2        6   RAM Map Position 2
INIT.RAM1        5   RAM Map Position 1
INIT.RAM0        4   RAM Map Position 0
INIT.REG3        3   Register Block Map Position 3
INIT.REG2        2   Register Block Map Position 2
INIT.REG1        1   Register Block Map Position 1
INIT.REG0        0   Register Block Map Position 0
TEST1           0x103E   TEST1 Factory Test Control Register
TEST1.TILOP      7   Test Illegal Opcode
TEST1.TPWSL      6   Pulse Width Modulation Scaled Clock
TEST1.OCCR       5   Output Condition Code Register Status to Timer Port
TEST1.CBYP1      4   Timer Counter 1 Divider Chain By-pass
TEST1.DISR       3   Disable Resets from COP and Clock Monitor
TEST1.FCM        2   Force Clock Monitor Failure
TEST1.FCOP       1   Force COP Watchdog Failure
TEST1.CBYP2      0   Timer Counter 2 Chain By-pass
CONFIG          0x103F   CONFIG COP and ROM Enables
CONFIG.NOCOP     2   COP System Disable
CONFIG.ROMON     1   ROM Enable
ADR1H           0x1040   ADR1H A/D Result Register 1 H
ADR1L           0x1041   ADR1L A/D Result Register 1 L
ADR2H           0x1042   ADR2H A/D Result Register 2 H
ADR2L           0x1043   ADR2L A/D Result Register 2 L
ADR3H           0x1044   ADR3H A/D Result Register 3 H
ADR3L           0x1045   ADR3L A/D Result Register 3 L
ADR4H           0x1046   ADR4H A/D Result Register 4 H
ADR4L           0x1047   ADR4L A/D Result Register 4 L
ADR5H           0x1048   ADR5H A/D Result Register 5 H
ADR5L           0x1049   ADR5L A/D Result Register 5 L
ADR6H           0x104A   ADR6 A/D Result Register 6 H
ADR6L           0x104B   ADR6 A/D Result Register 6 L
ADR7H           0x104C   ADR7H A/D Result Register 7 H
ADR7L           0x104D   ADR7L A/D Result Register 7 L
ADR8H           0x104E   ADR8H A/D Result Register 8 H
ADR8L           0x104F   ADR8L A/D Result Register 8 L
TCTL3           0x1050   TCTL3 Timer Control Register 3
TCTL3.EDG5B      7   Input Capture Edge Control 5B
TCTL3.EDG5A      6   Input Capture Edge Control 5A
TCTL3.EDG6B      5   Input Capture Edge Control 6B
TCTL3.EDG6A      4   Input Capture Edge Control 6A
TCTL3.OM6        3   Output Mode 6
TCTL3.OL6        2   Output Level 6
TCTL3.OM7        1   Output Mode 7
TCTL3.OL7        0   Output Level 7
TCTL4           0x1051   TCTL4 Timer Control Register 4
TCTL4.CT2SP      7   Timer Counter 2 Stop (used to facilitate testing)
TCTL4.CT1SP      6   Timer Counter 1 Stop (used to facilitate testing)
TCTL4.I5_O6      1   Configure TO6I5 Register for Input Capture or Output Compare
TCTL4.I6_O7      0   Configure TO7I6 Register for Input Capture or Output Compare
TCNT2H          0x1052   TCNT2H Timer Counter Register 2 H
TCNT2L          0x1053   TCNT2L Timer Counter Register 2 L
TO6I5H          0x1054   TO6I5H Output Compare 6_Input Capture 5 Register H
TO6I5L          0x1055   TO6I5L Output Compare 6_Input Capture 5 Register L
TO7I6H          0x1056   TO7I6H Output Compare 7_Input Capture 6 Register H
TO7I6L          0x1057   TO7I6L Output Compare 7_Input Capture 6 Register L
TPRE            0x1058   TPRE Timer Prescaler Register
TPRE.TEDGB       7   Timer External Clock Edge Select B
TPRE.TEDGA       6   Timer External Clock Edge Select A
TPRE.PR2B        5   Timer Prescaler Select 2B
TPRE.PR2A        4   Timer Prescaler Select 2A
TPRE.PR1B        1   Timer Prescaler Select 1B
TPRE.PR1A        0   Timer Prescaler Select 1A
RESERV1059      0x1059   RESERVED
RESERV105A      0x105A   RESERVED
RESERV105B      0x105B   RESERVED
RESERV105C      0x105C   RESERVED
RESERV105D      0x105D   RESERVED
RESERV105E      0x105E   RESERVED
RESERV105F      0x105F   RESERVED
PWCLK           0x1060   PWCLK PWM Timer Clock Select
PWCLK.CON34      7   Concatenate channels 3 and 4
PWCLK.CON12      6   Concatenate channels 1 and 2
PWCLK.PCKA2      5   Prescaler for clock A BIT 2
PWCLK.PCKA1      4   Prescaler for clock A BIT 1
PWCLK.PCKB3      2   Prescaler for clock B BIT 3
PWCLK.PCKB2      1   Prescaler for clock B BIT 2
PWCLK.PCKB1      0   Prescaler for clock B BIT 1
PWPOL           0x1061   PWPOL PWM Timer Polarity
PWPOL.PCLK4      7   Pulse Width Channel 4 Clock Select
PWPOL.PCLK3      6   Pulse Width Channel 3 Clock Select
PWPOL.PCLK2      5   Pulse Width Channel 2 Clock Select
PWPOL.PCLK1      4   Pulse Width Channel 1 Clock Select
PWPOL.PPOL4      3   Pulse Width Channel 4 Polarity
PWPOL.PPOL3      2   Pulse Width Channel 3 Polarity
PWPOL.PPOL2      1   Pulse Width Channel 2 Polarity
PWPOL.PPOL1      0   Pulse Width Channel 1 Polarity
PWSCAL          0x1062   PWSCAL PWM Timer Prescaler
PWEN            0x1063   PWEN PWM Timer Enable
PWEN.PWEN4       3   Pulse Width Channel 4 Enable
PWEN.PWEN3       2   Pulse Width Channel 3 Enable
PWEN.PWEN2       1   Pulse Width Channel 2 Enable
PWEN.PWEN1       0   Pulse Width Channel 1 Enable
PWCNT1          0x1064   PWCNT1 PWM Timer Counter 1
PWCNT2          0x1065   PWCNT2 PWM Timer Counter 2
PWCNT3          0x1066   PWCNT3 PWM Timer Counter 3
PWCNT4          0x1067   PWCNT4 PWM Timer Counter 4
PWPER1          0x1068   PWPER1 PWM Timer Period 1
PWPER2          0x1069   PWPER2 PWM Timer Period 2
PWPER3          0x106A   PWPER3 PWM Timer Period 3
PWPER4          0x106B   PWPER4 PWM Timer Period 4
PWDTY1          0x106C   PWDTY1 PWM Timer Duty 1
PWDTY2          0x106D   PWDTY2 PWM Timer Duty 2
PWDTY3          0x106E   PWDTY3 PWM Timer Duty 3
PWDTY4          0x106F   PWDTY4 PWM Timer Duty 4
EVCLK           0x1070   EVCLK Event Counter Clock Select
EVCLK.EVMDB      5   Event Counter Mode bits B
EVCLK.EVMDA      4   Event Counter Mode bits A
EVCLK.EVCKC      2   Event Counter Prescaler bits C
EVCLK.EVCKB      1   Event Counter Prescaler bits B
EVCLK.EVCKA      0   Event Counter Prescaler bits A
EVCTL           0x1071   EVCTL Event Counter Control Register
EVCTL.EVOEN      7   Event Output Enable (Port H, bit 6)
EVCTL.EVPOL      6   Event Output Polarity
EVCTL.EVI2C      5   Event Input Select 2C (EVI2)
EVCTL.EVI2B      4   Event Input Select 2B (EVI2)
EVCTL.EVI2A      3   Event Input Select 2A (EVI2)
EVCTL.EVI1C      2   Event Input Select 1C (EVI1)
EVCTL.EVI1B      1   Event Input Select 1B (EVI1)
EVCTL.EVI1A      0   Event Input Select 1A (EVI1)
EVMSK           0x1072   EVMSK Event Counter Interrupt Mask Register
EVMSK.EVCEN      7   Event Counters Enable
EVMSK.EV2I       1   Event 2 Interrupt Enable
EVMSK.EV1I       0   Event 1 Interrupt Enable
EVFLG           0x1073   EVFLG Event Counter Interrupt Flag Register
EVFLG.EV2F       1   Event Interrupt 2 Flag
EVFLG.EV1F       0   Event Interrupt 1 Flag
EVCNT1          0x1074   EVCNT1 Event Counter Count Register 1
EVCNT2          0x1075   EVCNT2 Event Counter Count Register 2
ECMP1A          0x1076   ECMP1A Event Counter Compare Register 1A
ECMP2A          0x1077   ECMP2A Event Counter Compare Register 2A
ECMP1B          0x1078   ECMP1B Event Counter Compare Register 1B
ECMP2B          0x1079   ECMP2B Event Counter Compare Register 2B
RESERV107A      0x107A   RESERVED
RESERV107B      0x107B   RESERVED
RESERV107C      0x107C   RESERVED
RESERV107D      0x107D   RESERVED
RESERV107E      0x107E   RESERVED
RESERV107F      0x107F   RESERVED
RESERVFFC0      0xFFC0   RESERVED
RESERVFFC1      0xFFC1   RESERVED
RESERVFFC2      0xFFC2   RESERVED
RESERVFFC3      0xFFC3   RESERVED
RESERVFFC4      0xFFC4   RESERVED
RESERVFFC5      0xFFC5   RESERVED
RESERVFFC6      0xFFC6   RESERVED
RESERVFFC7      0xFFC7   RESERVED
RESERVFFC8      0xFFC8   RESERVED
RESERVFFC9      0xFFC9   RESERVED
RESERVFFCA      0xFFCA   RESERVED
RESERVFFCB      0xFFCB   RESERVED
                     

.68HC711J6
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC711K4
; for M68HC711K Family (M68HC11K.pdf) http://
; M68HC11K.pdf

; RAM=768
; ROM=0
; EPROM=24K
; EEPROM=640


; MEMORY MAP
area DATA FSR          0x0000:0x0080
area DATA RAM          0x0080:0x0380
area BSS  RESERVED     0x0380:0x0D80
area DATA EEPROM       0x0D80:0x1000
area BSS  RESERVED     0x1000:0xA000
area DATA EPROM        0xA000:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select Bit 1
TMSK2.PR0       0   Timer Prescaler Select Bit 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
EPROG          0x002B    EPROM Programming Control Register (Present only in EPROM (711) devices)
EPROG.ELAT      5   EPROM Latch Control Bit
EPROG.EXCOL     4   Select Extra Columns Bit
EPROG.EXROW     3   Select Extra Rows Bit
EPROG.EPGM      0   EPROM Programming Enable Bit
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
PGAR           0x002D    Port G Assignment Register
PGAR.PGAR5      5   Port G Pin Assignment Bit 5
PGAR.PGAR4      4   Port G Pin Assignment Bit 4
PGAR.PGAR3      3   Port G Pin Assignment Bit 3
PGAR.PGAR2      2   Port G Pin Assignment Bit 2
PGAR.PGAR1      1   Port G Pin Assignment Bit 1
PGAR.PGAR0      0   Port G Pin Assignment Bit 0
OPT3           0x002E    System Configuration Options 3 Register (Not available on M68HC11K4 devices)
OPT3.SM         6   Slow-Mode Enable Bit
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG Bit
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.STRCH      5   Stretch External Accesses Bit
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode                                
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM Address Mapping Control Bit
CONFIG.CLKX     5   XOUT Clock Enable Bit
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   RAM and EPROM Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/PROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
MMSIZ          0x0056    Memory Mapping Size Register
MMSIZ.MXGS2     7   Memory Expansion Select for GPCS 2 Bit
MMSIZ.MXGS1     6   Memory Expansion Select for GPCS 1 Bit
MMSIZ.W2SZ1     5   Window 2 Size Bit 1
MMSIZ.W2SZ0     4   Window 2 Size Bit 0
MMSIZ.W1SZ1     1   Window 1 Size Bit 1
MMSIZ.W1SZ0     0   Window 1 Size Bit 0
MMWBR          0x0057    Memory Mapping Window Base Register
MMWBR.W2A15     7   Window 2 Base Address Bit 5
MMWBR.W2A14     6   Window 2 Base Address Bit 4
MMWBR.W2A13     5   Window 2 Base Address Bit 3
MMWBR.W1A15     3   Window Base 1 Address Bit 5
MMWBR.W1A14     2   Window Base 1 Address Bit 4
MMWBR.W1A13     1   Window Base 1 Address Bit 3
MM1CR          0x0058    Memory Mapping Window 1 Control Register
MM1CR.X1A18     6   Memory Mapping Window 1 Expansion Address Line Select Bit 18
MM1CR.X1A17     5   Memory Mapping Window 1 Expansion Address Line Select Bit 17
MM1CR.X1A16     4   Memory Mapping Window 1 Expansion Address Line Select Bit 16
MM1CR.X1A15     3   Memory Mapping Window 1 Expansion Address Line Select Bit 15
MM1CR.X1A14     2   Memory Mapping Window 1 Expansion Address Line Select Bit 14
MM1CR.X1A13     1   Memory Mapping Window 1 Expansion Address Line Select Bit 13
MM2CR          0x0059    Memory Mapping Window 2 Control Register
MM2CR.X2A18     6   Memory Mapping Window 2 Expansion Address Line Select Bit 18
MM2CR.X2A17     5   Memory Mapping Window 2 Expansion Address Line Select Bit 17
MM2CR.X2A16     4   Memory Mapping Window 2 Expansion Address Line Select Bit 16
MM2CR.X2A15     3   Memory Mapping Window 2 Expansion Address Line Select Bit 15
MM2CR.X2A14     2   Memory Mapping Window 2 Expansion Address Line Select Bit 14
MM2CR.X2A13     1   Memory Mapping Window 2 Expansion Address Line Select Bit 13
CSCSTR         0x005A    Chip Select Clock Stretch Register
CSCSTR.IOSA     7   CSIO Stretch Select Bit A
CSCSTR.IOSB     6   CSIO Stretch Select Bit B
CSCSTR.GP1SA    5   CSGP1 Stretch Select Bit A
CSCSTR.GP1SB    4   CSGP1 Stretch Select Bit B
CSCSTR.GP2SA    3   CSGP2 Stretch Select Bit A
CSCSTR.GP2SB    2   CSGP2 Stretch Select Bit B
CSCSTR.PCSA     1   CSPROG Stretch Select Bit A
CSCSTR.PCSB     0   CSPROG Stretch Select Bit B
CSCTL          0x005B    Chip Select Control Register
CSCTL.IOEN      7   I/O Chip-Select Enable Bit
CSCTL.IOPL      6   I/O Chip-Select Polarity Select Bit
CSCTL.IOCSA     5   I/O Chip-Select Address Valid Bit
CSCTL.IOSZ      4   I/O Chip-Select Size Select Bit
CSCTL.GCSPR     3   General-Purpose Chip Select Priority Bit
CSCTL.PCSEN     2   Program Chip Select Enable Bit
CSCTL.PCSZA     1   Program Chip Select Size A Bit
CSCTL.PCSZB     0   Program Chip Select Size B Bit
GPCS1A         0x005C    General-Purpose Chip Select 1 Address Register
GPCS1A.G1A18    7   General-Purpose Chip Select 1 Address Bit 18
GPCS1A.G1A17    6   General-Purpose Chip Select 1 Address Bit 17
GPCS1A.G1A16    5   General-Purpose Chip Select 1 Address Bit 16
GPCS1A.G1A15    4   General-Purpose Chip Select 1 Address Bit 15
GPCS1A.G1A14    3   General-Purpose Chip Select 1 Address Bit 14
GPCS1A.G1A13    2   General-Purpose Chip Select 1 Address Bit 13
GPCS1A.G1A12    1   General-Purpose Chip Select 1 Address Bit 12
GPCS1A.G1A11    0   General-Purpose Chip Select 1 Address Bit 11
GPCS1C         0x005D    General-Purpose Chip Select 1 Control Register
GPCS1C.G1DG2    7   GPCS 1 Drives GPCS 2 Bit
GPCS1C.G1DPC    6   General-Purpose Chip Select 1 Drives Program Chip Select Bit
GPCS1C.G1POL    5   General-Purpose Chip Select 1 Polarity Select Bit
GPCS1C.G1AV     4   General-Purpose Chip Select 1 Address Valid Select Bit
GPCS1C.G1SZA    3   General-Purpose Chip Select 1 Size Bit A
GPCS1C.G1SZB    2   General-Purpose Chip Select 1 Size Bit B
GPCS1C.G1SZC    1   General-Purpose Chip Select 1 Size Bit C
GPCS1C.G1SZD    0   General-Purpose Chip Select 1 Size Bit D
GPCS2A         0x005E    General-Purpose Chip Select 2 Address Register
GPCS2A.G2A18    7   General-Purpose Chip Select 2 Address Bit 18
GPCS2A.G2A17    6   General-Purpose Chip Select 2 Address Bit 17
GPCS2A.G2A16    5   General-Purpose Chip Select 2 Address Bit 16
GPCS2A.G2A15    4   General-Purpose Chip Select 2 Address Bit 15
GPCS2A.G2A14    3   General-Purpose Chip Select 2 Address Bit 14
GPCS2A.G2A13    2   General-Purpose Chip Select 2 Address Bit 13
GPCS2A.G2A12    1   General-Purpose Chip Select 2 Address Bit 12
GPCS2A.G2A11    0   General-Purpose Chip Select 2 Address Bit 11
GPCS2C         0x005F    General-Purpose Chip Select 2 Control Register
GPCS2C.G2DPC    6   General-Purpose Chip Select 2 Drives Program Chip Select Bit
GPCS2C.G2POL    5   General-Purpose Chip Select 2 Polarity Select Bit
GPCS2C.G2AV     4   General-Purpose Chip Select 2 Address Valid Select Bit
GPCS2C.G2SZA    3   General-Purpose Chip Select 2 Size Bit A
GPCS2C.G2SZB    2   General-Purpose Chip Select 2 Size Bit B
GPCS2C.G2SZC    1   General-Purpose Chip Select 2 Size Bit C
GPCS2C.G2SZD    0   General-Purpose Chip Select 2 Size Bit D
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH7       7   Port H Data Bit 7
PORTH.PH6       6   Port H Data Bit 6
PORTH.PH5       5   Port H Data Bit 5
PORTH.PH4       4   Port H Data Bit 4
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH7       7   Data Direction for Port H Bit 7
DDRH.DDH6       6   Data Direction for Port H Bit 6
DDRH.DDH5       5   Data Direction for Port H Bit 5
DDRH.DDH4       4   Data Direction for Port H Bit 4
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6
PORTG.PG5       5   Port G Data Bit 5
PORTG.PG4       4   Port G Data Bit 4
PORTG.PG3       3   Port G Data Bit 3
PORTG.PG2       2   Port G Data Bit 2
PORTG.PG1       1   Port G Data Bit 1
PORTG.PG0       0   Port G Data Bit 0
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6
DDRG.DDG5       5   Data Direction for Port G Bit 5
DDRG.DDG4       4   Data Direction for Port G Bit 4
DDRG.DDG3       3   Data Direction for Port G Bit 3
DDRG.DDG2       2   Data Direction for Port G Bit 2
DDRG.DDG1       1   Data Direction for Port G Bit 1
DDRG.DDG0       0   Data Direction for Port G Bit 0
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC711KA2
; for M68HC711K Family (M68HC11K.pdf)  http://
; ka4.pdf

; RAM=1024
; ROM=0
; EPROM=32K
; EEPROM=640


; MEMORY MAP
area DATA FSR		0x0000:0x0080
area DATA RAM		0x0080:0x0480
area BSS  RESERVED      0x0480:0x0D80
area DATA EEPROM	0x0D80:0x1000
area BSS  RESERVED      0x1000:0x8000
area DATA EPROM         0x8000:0xFFC0
area DATA USER_VEC	0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select 1
TMSK2.PR0       0   Timer Prescaler Select 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
RESERV002D     0x002D    RESERVED
RESERV002E     0x002E    RESERVED
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM/EPROM Mapping Control
CONFIG.CLKX     5   XOUT Clock Enable
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/EPROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
RESERV0055     0x0056    RESERVED
RESERV0055     0x0057    RESERVED
RESERV0055     0x0058    RESERVED
RESERV0055     0x0059    RESERVED
RESERV0055     0x005A    RESERVED
RESERV0055     0x005B    RESERVED
RESERV0055     0x005C    RESERVED
RESERV0055     0x005D    RESERVED
RESERV0055     0x005E    RESERVED
RESERV0055     0x005F    RESERVED
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register 
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register 
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register 
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register 
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1                             
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low 
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC711KA4
; for M68HC711K Family (M68HC11K.pdf)  http://
; ka4.pdf

; RAM=768
; ROM=0
; EPROM=24K
; EEPROM=640


; MEMORY MAP
area DATA FSR		0x0000:0x0080
area DATA RAM		0x0080:0x0380
area BSS  RESERVED      0x0380:0x0D80
area DATA EEPROM	0x0D80:0x1000
area BSS  RESERVED      0x1000:0xA000
area DATA EPROM         0xA000:0xFFC0
area DATA USER_VEC	0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET   0xFFFE   Processor reset
interrupt CME       0xFFFC   Clock Monitor Fail
interrupt NOCOP     0xFFFA   COP Failure
interrupt OPC       0xFFF8   Illegal Opcode Trap
interrupt SOFT      0xFFF6   Software Interrupt
interrupt XIRQ      0xFFF4   XIRQ Pin
interrupt IRQ       0xFFF2   IRQ
interrupt RTII      0xFFF0   Real Time Interrupt
interrupt IC1I      0xFFEE   Timer Input Capture 1
interrupt IC2I      0xFFEC   Timer Input Capture 2
interrupt IC3I      0xFFEA   Timer Input Capture 3
interrupt OC1I      0xFFE8   Timer Output Compare 1
interrupt OC2I      0xFFE6   Timer Output Compare 2
interrupt OC3I      0xFFE4   Timer Output Compare 3
interrupt OC4I      0xFFE2   Timer Output Compare 4
interrupt I4_I5     0xFFE0   Timer Input Capture 4 / Output Compare 5
interrupt TOI       0xFFDE   Timer Overflow
interrupt PAOVI     0xFFDC   Pulse Accumulator Overflow
interrupt PAII      0xFFDA   Pulse Accumulator Input Edge
interrupt SPIE      0xFFD8   SPI Serial Transfer Complete
interrupt SCISS     0xFFD6   SCI Serial System



; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer Prescaler Select 1
TMSK2.PR0       0   Timer Prescaler Select 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
RESERV002B     0x002B    RESERVED
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
RESERV002D     0x002D    RESERVED
RESERV002E     0x002E    RESERVED
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4   Protect for CONFIG
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM/EPROM Mapping Control
CONFIG.CLKX     5   XOUT Clock Enable
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/EPROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
RESERV0055     0x0056    RESERVED
RESERV0055     0x0057    RESERVED
RESERV0055     0x0058    RESERVED
RESERV0055     0x0059    RESERVED
RESERV0055     0x005A    RESERVED
RESERV0055     0x005B    RESERVED
RESERV0055     0x005C    RESERVED
RESERV0055     0x005D    RESERVED
RESERV0055     0x005E    RESERVED
RESERV0055     0x005F    RESERVED
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register 
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register 
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register 
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register 
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1                             
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low 
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC711KS2
; for M68HC711K Family (M68HC11K.pdf)  http://
; M68HC11K.pdf

; RAM=1024
; ROM=0
; EPROM=32K
; EEPROM=640


; MEMORY MAP
area DATA FSR         0x0000:0x0080
area DATA RAM         0x0080:0x0480
area BSS  RESERVED    0x0480:0x0D80
area DATA EEPROM      0x0D80:0x1000
area BSS  RESERVED    0x1000:0x8000
area DATA EPROM       0x8000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A Data Register
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Port A Data Direction  Register
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002    Port B Data Direction Register
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003    Port F Data Direction Register
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B Data Register
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F Data Register
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C Data Register
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Port C Data Direction Register
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D Data Register
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Port D Data Direction Register
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E Data Register
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer Compare Force Register
CFORC.FOC1      7   Force Output Comparison Bit 1
CFORC.FOC2      6   Force Output Comparison Bit 2
CFORC.FOC3      5   Force Output Comparison Bit 3
CFORC.FOC4      4   Force Output Comparison Bit 4
CFORC.FOC5      3   Force Output Comparison Bit 5
OC1M           0x000C    Output Compare 1 Mask Register
OC1M.OC1M7      7   Output Compare 1 Masks Bit 7
OC1M.OC1M6      6   Output Compare 1 Masks Bit 6
OC1M.OC1M5      5   Output Compare 1 Masks Bit 5
OC1M.OC1M4      4   Output Compare 1 Masks Bit 4
OC1M.OC1M3      3   Output Compare 1 Masks Bit 3
OC1D           0x000D    Output Compare 1 Data Register
OC1D.OC1D7      7   Output Compare Data Bit 7
OC1D.OC1D6      6   Output Compare Data Bit 6
OC1D.OC1D5      5   Output Compare Data Bit 5
OC1D.OC1D4      4   Output Compare Data Bit 4
OC1D.OC1D3      3   Output Compare Data Bit 3
TCNTH          0x000E    Timer Counter Register High
TCNTL          0x000F    Timer Counter Register Low
TIC1H          0x0010    Timer Input Capture 1 Register High
TIC1L          0x0011    Timer Input Capture 1 Register Low
TIC2H          0x0012    Timer Input Capture 2 Register High
TIC2L          0x0013    Timer Input Capture 2 Register Low
TIC3H          0x0014    Timer Input Capture 3 Register High
TIC3L          0x0015    Timer Input Capture 3 Register Low
TOC1H          0x0016    Timer Output Compare 1 High Register
TOC1L          0x0017    Timer Output Compare 1 Low Register
TOC2H          0x0018    Timer Output Compare 2 High Register
TOC2L          0x0019    Timer Output Compare 2 Low Register
TOC3H          0x001A    Timer Output Compare 3 High Register
TOC3L          0x001B    Timer Output Compare 3 Low Register
TOC4H          0x001C    Timer Output Compare 4 High Register
TOC4L          0x001D    Timer Output Compare 4 Low Register
TI4H_O5H       0x001E    Timer Input Capture 4/ Output Compare 5 Reg. High
TI4L_O5L       0x001F    Timer Input Capture 4/ Output Compare 5 Low Reg.
TCTL1          0x0020    Timer Control 1 Register
TCTL1.OM2       7   Output Mode Bit 2
TCTL1.OL2       6   Output Level Bit 2
TCTL1.OM3       5   Output Mode Bit 3
TCTL1.OL3       4   Output Level Bit 3
TCTL1.OM4       3   Output Mode Bit 4
TCTL1.OL4       2   Output Level Bit 4
TCTL1.OM5       1   Output Mode Bit 5
TCTL1.OL5       0   Output Level Bit 5
TCTL2          0x0021    Timer Control 2 Register
TCTL2.EDG4B     7   Input Capture Edge Control Bit 4B
TCTL2.EDG4A     6   Input Capture Edge Control Bit 4A
TCTL2.EDG1B     5   Input Capture Edge Control Bit 1B
TCTL2.EDG1A     4   Input Capture Edge Control Bit 1A
TCTL2.EDG2B     3   Input Capture Edge Control Bit 2B
TCTL2.EDG2A     2   Input Capture Edge Control Bit 2A
TCTL2.EDG3B     1   Input Capture Edge Control Bit 3B
TCTL2.EDG3A     0   Input Capture Edge Control Bit 3A
TMSK1          0x0022    Timer Interrupt Mask 1 Register
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I    3   Input Capture 4 or Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x0023    Timer Interrupt Flag 1 Register
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x0024    Timer Interrupt Mask 2 Register
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable Bit
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Interrupt Enable   
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025    Timer Interrupt Flag 2
TFLG2.TOF       7   Timer Overflow Flag              
TFLG2.RTIF      6   Real Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Flag    
TFLG2.PAIF      4   Pulse Accumulator Input Edge Flag  
PACTL          0x0026    Pulse Accumulator Control Register
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.I4_O5     2   Input Capture 4/Output Compare
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x0027    Pulse Accumulator Count Register
SPCR           0x0028    Serial Peripheral Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable   
SPCR.DWOM       5   Port D Wired-OR Mode              
SPCR.MSTR       4   Master Mode Select                
SPCR.CPOL       3   Clock Polarity                    
SPCR.CPHA       2   Clock Phase                       
SPCR.SPR1       1   SPI Clock Rate Selects 1          
SPCR.SPR0       0   SPI Clock Rate Selects 0          
SPSR           0x0029    Serial Peripheral Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision Bit
SPSR.MODF       4   Mode Fault Bit
SPDR           0x002A    Serial Peripheral Data Register
EPROG          0x002B    EPROM Programming Control Register (Present only in EPROM (711) devices)
EPROG.ELAT      5   EPROM Latch Control Bit
EPROG.EXCOL     4   Select Extra Columns Bit
EPROG.EXROW     3   Select Extra Rows Bit
EPROG.EPGM      0   EPROM Programming Enable Bit
PPAR           0x002C    Port Pullup Assignment Register
PPAR.HPPUE      3   Port H Pin Pullup Enable Bits
PPAR.GPPUE      2   Port G Pin Pullup Enable Bits
PPAR.FPPUE      1   Port F Pin Pullup Enable Bits
PPAR.BPPUE      0   Port B Pin Pullup Enable Bits
PGAR           0x002D    Port G Assignment Register
PGAR.PGAR5      5   Port G Pin Assignment Bit 5
PGAR.PGAR4      4   Port G Pin Assignment Bit 4
PGAR.PGAR3      3   Port G Pin Assignment Bit 3
PGAR.PGAR2      2   Port G Pin Assignment Bit 2
PGAR.PGAR1      1   Port G Pin Assignment Bit 1
PGAR.PGAR0      0   Port G Pin Assignment Bit 0
OPT3           0x002E    System Configuration Options 3 Register (Not available on M68HC11K4 devices)
OPT3.SM         6   Slow-Mode Enable Bit
RESERV002F     0x002F    RESERVED
ADCTL          0x0030    Analog-to-Digital Control_Status Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control Bit
ADCTL.MULT      4   Multiple Channel/Single Channel Control Bit
ADCTL.CD        3   Channel Selects D Bits
ADCTL.CC        2   Channel Selects C Bits
ADCTL.CB        1   Channel Selects B Bits
ADCTL.CA        0   Channel Selects A Bits
ADR1           0x0031    Analog-to-Digital Results Register 1
ADR2           0x0032    Analog-to-Digital Results Register 2
ADR3           0x0033    Analog-to-Digital Results Register 3
ADR4           0x0034    Analog-to-Digital Results Register 4
BPROT          0x0035    Block Protect Register
BPROT.BULKP     7   Bulk Erase of EEPROM Protect Bit
BPROT.LVPEN     6   Low-Voltage Programming Protect Enable Bit
BPROT.BPRT4     5   Block Protect Bits for EEPROM Bit 4
BPROT.PTCON     4
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
RESERV0036     0x0036    RESERVED
INIT2          0x0037    EEPROM Mapping Register
INIT2.EE3       7   EEPROM Map Position Bit 3
INIT2.EE2       6   EEPROM Map Position Bit 2
INIT2.EE1       5   EEPROM Map Position Bit 1
INIT2.EE0       4   EEPROM Map Position Bit 0
OPT2           0x0038    System Configuration Options 2 Register
OPT2.LIRDV      7   LIR Driven Bit
OPT2.CWOM       6   Port C Wired-OR Mode Bit
OPT2.IRVNE      4   Internal Read Visibility/Not E Bit
OPT2.LSBF       3   Least Significant Bit (LSB) First Enable Bit
OPT2.SPR2       2   SPI Clock Rate Selected Bit
OPT2.XDV1       1   XOUT Clock Divide Select Bit 1
OPT2.XDV0       0   XOUT Clock Divide Select Bit 0
OPTION         0x0039    System Configuration Options Register
OPTION.ADPU     7   A/D Power Up
OPTION.CSEL     6   Clock Select Bit
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Operation Bit
OPTION.DLY      4   Enable Oscillator Start-up delay on exit from STOP
OPTION.CME      3   Clock Monitor Enable Bit
OPTION.FCME     2   Force Clock Monitor Enable Bit
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x003A    Arm_Reset COP Timer Circuitry Register
PPROG          0x003B    EEPROM Programming Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM Bit
PPROG.EVEN      6   Program Even Rows in Half of EEPROM Bit
PPROG.LVPI      5   Low-Voltage Programming Inhibit Bit
PPROG.BYTE      4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW       3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE     2   Erase/Normal Control for EEPROM Bit
PPROG.EELAT     1   EEPROM Latch Control Bit
PPROG.EEPGM     0   EEPROM Program Command Bit
HPRIO          0x003C    Highest Priority I-terrupt and Misc. Register
HPRIO.RBOOT     7   Read Bootstrap ROM Bit
HPRIO.SMOD      6   Special Mode Select Bit
HPRIO.MDA       5   Mode Select A Bit
HPRIO.PSEL4     4   Priority Select Bits 4
HPRIO.PSEL3     3   Priority Select Bits 3
HPRIO.PSEL2     2   Priority Select Bits 2
HPRIO.PSEL1     1   Priority Select Bits 1
HPRIO.PSEL0     0   Priority Select Bits 0
INIT           0x003D    RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position Bit 3
INIT.RAM2       6   RAM Map Position Bit 2
INIT.RAM1       5   RAM Map Position Bit 1
INIT.RAM0       4   RAM Map Position Bit 0
INIT.REG3       3   Register Block Position Bit 3
INIT.REG2       2   Register Block Position Bit 2
INIT.REG1       1   Register Block Position Bit 1
INIT.REG0       0   Register Block Position Bit 0
TEST1          0x003E    Test 1 Register
TEST1.TILOP     7   Test Illegal Opcode                                
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F    System Configuration Register
CONFIG.ROMAD    7   ROM Address Mapping Control Bit
CONFIG.CLKX     5   WCOP system disable
CONFIG.PAREN    4   Pullup Assignment Register Enable Bit
CONFIG.NOSEC    3   RAM and EPROM Security Disabled Bit
CONFIG.NOCOP    2   COP System Disable Bit
CONFIG.ROMON    1   ROM/PROM Enable Bit
CONFIG.EEON     0   EEPROM Enable Bit
RESERV0040     0x0040    RESERVED
RESERV0041     0x0041    RESERVED
RESERV0042     0x0042    RESERVED
RESERV0043     0x0043    RESERVED
RESERV0044     0x0044    RESERVED
RESERV0045     0x0045    RESERVED
RESERV0046     0x0046    RESERVED
RESERV0047     0x0047    RESERVED
RESERV0048     0x0048    RESERVED
RESERV0049     0x0049    RESERVED
RESERV004A     0x004A    RESERVED
RESERV004B     0x004B    RESERVED
RESERV004C     0x004C    RESERVED
RESERV004D     0x004D    RESERVED
RESERV004E     0x004E    RESERVED
RESERV004F     0x004F    RESERVED
RESERV0050     0x0050    RESERVED
RESERV0051     0x0051    RESERVED
RESERV0052     0x0052    RESERVED
RESERV0053     0x0053    RESERVED
RESERV0054     0x0054    RESERVED
RESERV0055     0x0055    RESERVED
RESERV0056     0x0056    RESERVED
RESERV0057     0x0057    RESERVED
RESERV0058     0x0058    RESERVED
RESERV0059     0x0059    RESERVED
RESERV005A     0x005A    RESERVED
RESERV005B     0x005B    RESERVED
RESERV005C     0x005C    RESERVED
RESERV005D     0x005D    RESERVED
RESERV005E     0x005E    RESERVED
RESERV005F     0x005F    RESERVED
PWCLK          0x0060    Pulse Width Modulation Timer Clock Select Register
PWCLK.CON34     7   Concatenate Channels 3 and 4 Bit
PWCLK.CON12     6   Concatenate Channels 1 and 2 Bit
PWCLK.PCKA2     5   Prescaler for Clock A Bit 2
PWCLK.PCKA1     4   Prescaler for Clock A Bit 1
PWCLK.PCKB3     2   Prescaler for Clock B Bit 3
PWCLK.PCKB2     1   Prescaler for Clock B Bit 2
PWCLK.PCKB1     0   Prescaler for Clock B Bit 1
PWPOL          0x0061    Pulse Width Modulation Timer Polarity Register
PWPOL.PCLK4     7   Pulse-Width Channel 4 Clock Select Bits
PWPOL.PCLK3     6   Pulse-Width Channel 3 Clock Select Bits
PWPOL.PCLK2     5   Pulse-Width Channel 2 Clock Select Bits
PWPOL.PCLK1     4   Pulse-Width Channel 1 Clock Select Bits
PWPOL.PPOL4     3   Pulse-Width Channel 4 Polarity Bits
PWPOL.PPOL3     2   Pulse-Width Channel 3 Polarity Bits
PWPOL.PPOL2     1   Pulse-Width Channel 2 Polarity Bits
PWPOL.PPOL1     0   Pulse-Width Channel 1 Polarity Bits
PWSCAL         0x0062    Pulse Width Modulation Timer Prescaler Register
PWEN           0x0063    Pulse Width Modulation Timer Enable Register
PWEN.TPWSL      7   PWM Scaled Clock Test Bit
PWEN.DISCP      6   Disable Compare Scaled E-Clock Bit
PWEN.PWEN4      3   Pulse-Width Enable for Channels 4 Bits
PWEN.PWEN3      2   Pulse-Width Enable for Channels 3 Bits
PWEN.PWEN2      1   Pulse-Width Enable for Channels 2 Bits
PWEN.PWEN1      0   Pulse-Width Enable for Channels 1 Bits
PWCNT1         0x0064    Pulse Width Modulation Timer Counter 1 Register
PWCNT2         0x0065    Pulse Width Modulation Timer Counter 2 Register
PWCNT3         0x0066    Pulse Width Modulation Timer Counter 3 Register
PWCNT4         0x0067    Pulse Width Modulation Timer Counter 4 Register
PWPER1         0x0068    Pulse Width Modulation Timer Period 1 Register
PWPER2         0x0069    Pulse Width Modulation Timer Period 2 Register
PWPER3         0x006A    Pulse Width Modulation Timer Period 3 Register
PWPER4         0x006B    Pulse Width Modulation Timer Period 4 Register
PWDTY1         0x006C    Pulse Width Modulation Timer Duty Cycle 1 Register
PWDTY2         0x006D    Pulse Width Modulation Timer Duty Cycle 2 Register
PWDTY3         0x006E    Pulse Width Modulation Timer Duty Cycle 3 Register
PWDTY4         0x006F    Pulse Width Modulation Timer Duty Cycle 4 Register
SCBDH          0x0070    SCI Baud Rate Control Register High
SCBDH.BTST      7   Baud Register Test Bit
SCBDH.BSPL      6   Baud Rate Counter Split Bit
SCBDH.SBR12     4   SCI Baud Rate Select Bit 12
SCBDH.SBR11     3   SCI Baud Rate Select Bit 11
SCBDH.SBR10     2   SCI Baud Rate Select Bit 10
SCBDH.SBR9      1   SCI Baud Rate Select Bit 9 
SCBDH.SBR8      0   SCI Baud Rate Select Bit 8 
SCBDL          0x0071    SCI Baud Rate Control Register Low
SCBDL.SBR7      7   SCI Baud Rate Select Bit 7
SCBDL.SBR6      6   SCI Baud Rate Select Bit 6
SCBDL.SBR5      5   SCI Baud Rate Select Bit 5
SCBDL.SBR4      4   SCI Baud Rate Select Bit 4
SCBDL.SBR3      3   SCI Baud Rate Select Bit 3
SCBDL.SBR2      2   SCI Baud Rate Select Bit 2
SCBDL.SBR1      1   SCI Baud Rate Select Bit 1
SCBDL.SBR0      0   SCI Baud Rate Select Bit 0
SCCR1          0x0072    SCI Control Register 1
SCCR1.LOOPS     7   SCI Loop Mode Enable Bit
SCCR1.WOMS      6   Wired-OR Mode for SCI Pins PD[1:0] Bits
SCCR1.M         4   Mode (SCI Word Size) Bit
SCCR1.WAKE      3   Wakeup Mode Bit
SCCR1.ILT       2   Idle Line Type Bit
SCCR1.PE        1   Parity Enable Bit
SCCR1.PT        0   Parity Type Bit
SCCR2          0x0073    SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable Bit
SCCR2.TCIE      6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE       5   Receiver Interrupt Enable Bit
SCCR2.ILIE      4   Idle Line Interrupt Enable Bit
SCCR2.TE        3   Transmitter Enable Bit
SCCR2.RE        2   Receiver Enable Bit
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break Bit
SCSR1          0x0074    SCI Status Register 1
SCSR1.TDRE      7   Transmit Data Register Empty Flag
SCSR1.TC        6   Transmit Complete Flag
SCSR1.RDRF      5   Receive Data Register Full Flag
SCSR1.IDLE      4   Idle Line Detected Flag
SCSR1.OR        3   Overrun Error Flag
SCSR1.NF        2   Noise Error Flag
SCSR1.FE        1   Framing Error Flag
SCSR1.PF        0   Parity Error Flag
SCSR2          0x0075    SCI Status Register 2
SCSR2.RAF       0   Receiver Active Flag
SCDRH          0x0076    SCI Data Register high
SCDRH.R8        7   Receiver Bit 8
SCDRH.T8        6   Transmitter Bit 8
SCDRL          0x0077    SCI Data Register low
SCDRL.R7_T7     7   Receiver/Transmitter Bits 7
SCDRL.R6_T6     6   Receiver/Transmitter Bits 6
SCDRL.R5_T5     5   Receiver/Transmitter Bits 5
SCDRL.R4_T4     4   Receiver/Transmitter Bits 4
SCDRL.R3_T3     3   Receiver/Transmitter Bits 3
SCDRL.R2_T2     2   Receiver/Transmitter Bits 2
SCDRL.R1_T1     1   Receiver/Transmitter Bits 1
SCDRL.R0_T0     0   Receiver/Transmitter Bits 0
RESERV0078     0x0078    RESERVED
RESERV0079     0x0079    RESERVED
RESERV007A     0x007A    RESERVED
RESERV007B     0x007B    RESERVED
PORTH          0x007C    Port H Data Register
PORTH.PH3       3   Port H Data Bit 3
PORTH.PH2       2   Port H Data Bit 2
PORTH.PH1       1   Port H Data Bit 1
PORTH.PH0       0   Port H Data Bit 0
DDRH           0x007D    Port H Data Direction Register
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G Data Register
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F    Port G Data Direction Register
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED
RESERVFFD2     0xFFD2    RESERVED
RESERVFFD3     0xFFD3    RESERVED
RESERVFFD4     0xFFD4    RESERVED
RESERVFFD5     0xFFD5    RESERVED


.68HC711L6
; MC68HC711L6/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC711L6.pdf
; MC68HC711L6TS.pdf

; RAM=512
; ROM=0 
; EPROM=16K
; EEPROM=512


; MEMORY MAP
area DATA RAM         0x0000:0x0200
area BSS  RESERVED    0x0200:0x1000
area DATA FSR         0x1000:0x1040
area BSS  RESERVED    0x1040:0xB600
area DATA EEPROM      0xB600:0xB800
area BSS  RESERVED    0xB800:0xC000
area CODE EPROM       0xC000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET   0xFFFE      Processor reset
interrupt CME       0xFFFC      Clock Monitor Fail
interrupt NOCOP     0xFFFA      COP Failure
interrupt OPC       0xFFF8      Illegal Opcode Trap
interrupt SOFT      0xFFF6      Software Interrupt
interrupt XIRQ      0xFFF4      XIRQ Pin
interrupt IRQ       0xFFF2      IRQ
interrupt RTII      0xFFF0      Real Time Interrupt
interrupt IC1I      0xFFEE      Timer Input Capture 1
interrupt IC2I      0xFFEC      Timer Input Capture 2
interrupt IC3I      0xFFEA      Timer Input Capture 3
interrupt OC1I      0xFFE8      Timer Output Compare 1
interrupt OC2I      0xFFE6      Timer Output Compare 2
interrupt OC3I      0xFFE4      Timer Output Compare 3
interrupt OC4I      0xFFE2      Timer Output Compare 4
interrupt I4_I5     0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI       0xFFDE      Timer Overflow
interrupt PAOVI     0xFFDC      Pulse Accumulator Overflow
interrupt PAII      0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE      0xFFD8      SPI Serial Transfer Complete
interrupt SCISS     0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA          0x1000   Port A data
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
RESERVED01     0x1001   RESERVED01
PIOC           0x1002   Parallel I_O Control Register
PIOC.STAF       7   Strobe A Interrupt Status Flag
PIOC.STAI       6   Strobe A Interrupt Enable Mask
PIOC.CWOM       5   Port C Wired-OR Mode (affects all eight port C pins)
PIOC.HNDS       4   Handshake Mode
PIOC.OIN        3   Output or Input Handshake Select
PIOC.PLS        2   Pulsed/Interlocked Handshake Operation
PIOC.EGA        1   Active Edge for Strobe A
PIOC.INVB       0   Invert Strobe B
PORTC          0x1003   I_O Port C
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
PORTB          0x1004   Output Port B
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTCL         0x1005   Alternate Latched Port C
PORTCL.PCL7     7
PORTCL.PCL6     6
PORTCL.PCL5     5
PORTCL.PCL4     4
PORTCL.PCL3     3
PORTCL.PCL2     2
PORTCL.PCL1     1
PORTCL.PCL0     0
RESERVED06     0x1006   RESERVED06
DDRC           0x1007   Data Direction for Port C
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x1008   I_O Port D
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x1009   Data Direction for Port D
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x100A   Input Port E
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x100B   Compare Force Register
CFORC.FOC1      7   Write Ones to Force Compare 1
CFORC.FOC2      6   Write Ones to Force Compare 2
CFORC.FOC3      5   Write Ones to Force Compare 3
CFORC.FOC4      4   Write Ones to Force Compare 4
CFORC.FOC5      3   Write Ones to Force Compare 5
OC1M           0x100C   OC1 Action Mask Register
OC1M.OC1M7      7   Output Compare Masks 7
OC1M.OC1M6      6   Output Compare Masks 6
OC1M.OC1M5      5   Output Compare Masks 5
OC1M.OC1M4      4   Output Compare Masks 4
OC1M.OC1M3      3   Output Compare Masks 3
OC1D           0x100D    OC1 Action Data Register
OC1D.OC1D7      7   Output compare data 7
OC1D.OC1D6      6   Output compare data 6
OC1D.OC1D5      5   Output compare data 5
OC1D.OC1D4      4   Output compare data 4
OC1D.OC1D3      3   Output compare data 3
TCNTH          0x100E   Timer Counter Register (High)
TCNTL          0x100F   Timer Counter Register (Low)
TIC1H          0x1010   Input Capture 1 Register (High)
TIC1L          0x1011   Input Capture 1 Register (Low)
TIC2H          0x1012   Input Capture 2 Register (High)
TIC2L          0x1013   Input Capture 2 Register (Low)
TIC3H          0x1014   Input Capture 3 Register (High)
TIC3L          0x1015   Input Capture 3 Register (Low)
TOC1H          0x1016   Output Compare 1 Register (High)
TOC1L          0x1017   Output Compare 1 Register (Low)
TOC2H          0x1018   Output Compare 2 Register (High)
TOC2L          0x1019   Output Compare 2 Register (Low)
TOC3H          0x101A   Output Compare 3 Register (High)
TOC3L          0x101B   Output Compare 3 Register (Low)
TOC4H          0x101C   Output Compare 4 Register (High)
TOC4L          0x101D   Output Compare 4 Register (Low)
TI4_O5H        0x101E   Timer Input Capture 4/Output Compare 5 (High)
TI4_O5L        0x101F   Timer Input Capture 4/Output Compare 5 (Low)
TCTL1          0x1020   Timer Control Register 1
TCTL1.OM2       7   Output Mode 2
TCTL1.OL2       6   Output Level 2
TCTL1.OM3       5   Output Mode 3
TCTL1.OL3       4   Output Level 3
TCTL1.OM4       3   Output Mode 4
TCTL1.OL4       2   Output Level 4
TCTL1.OM5       1   Output Mode 5
TCTL1.OL5       0   Output Level 5
TCTL2          0x1021   Timer Control Register 2
TCTL2.EDG4B     7   Input Capture Edge Control 4B
TCTL2.EDG4A     6   Input Capture Edge Control 4A
TCTL2.EDG1B     5   Input Capture Edge Control 1B
TCTL2.EDG1A     4   Input Capture Edge Control 1A
TCTL2.EDG2B     3   Input Capture Edge Control 2B
TCTL2.EDG2A     2   Input Capture Edge Control 2A
TCTL2.EDG3B     1   Input Capture Edge Control 3B
TCTL2.EDG3A     0   Input Capture Edge Control 3A
TMSK1          0x1022   Timer Interrupt Mask Register 1
TMSK1.OC1I      7   Output Compare 1 Interrupt Enable
TMSK1.OC2I      6   Output Compare 2 Interrupt Enable
TMSK1.OC3I      5   Output Compare 3 Interrupt Enable
TMSK1.OC4I      4   Output Compare 4 Interrupt Enable
TMSK1.I4_O5I    3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I      2   Input Capture 1 Interrupt Enable
TMSK1.IC2I      1   Input Capture 2 Interrupt Enable
TMSK1.IC3I      0   Input Capture 3 Interrupt Enable
TFLG1          0x1023   Timer Interrupt Flag Register 1
TFLG1.OC1F      7   Output Compare 1 Flag
TFLG1.OC2F      6   Output Compare 2 Flag
TFLG1.OC3F      5   Output Compare 3 Flag
TFLG1.OC4F      4   Output Compare 4 Flag
TFLG1.I4_O5F    3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F      2   Input Capture 1 Flag
TFLG1.IC2F      1   Input Capture 2 Flag
TFLG1.IC3F      0   Input Capture 3 Flag
TMSK2          0x1024   Timer Interrupt Mask Register 2
TMSK2.TOI       7   Timer Overflow Interrupt Enable
TMSK2.RTII      6   Real-time Interrupt Enable
TMSK2.PAOVI     5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII      4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1       1   Timer Prescaler Select 1
TMSK2.PR0       0   Timer Prescaler Select 0
TFLG2          0x1025   Timer Interrupt Flag Register 2
TFLG2.TOF       7   Timer Overflow Interrupt Flag
TFLG2.RTIF      6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF     5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF      4   Pulse Accumulator Input Edge Interrupt Flag
PACTL          0x1026   Pulse Accumulator Control Register
PACTL.DDRA7     7   Data Direction for Port A Bit 7
PACTL.PAEN      6   Pulse Accumulator System Enable
PACTL.PAMOD     5   Pulse Accumulator Mode
PACTL.PEDGE     4   Pulse Accumulator Edge Control
PACTL.DDRA3     3   Data Direction for Port A Bit 3
PACTL.I4_O5     2   Input Capture 4/Output Compare 5
PACTL.RTR1      1   RTI Interrupt Rate Select 1
PACTL.RTR0      0   RTI Interrupt Rate Select 0
PACNT          0x1027   Pulse Accumulator Count Register
SPCR           0x1028   SPI Control Register
SPCR.SPIE       7   Serial Peripheral Interrupt Enable
SPCR.SPE        6   Serial Peripheral System Enable
SPCR.DWOM       5   Port D Wired-OR Mode
SPCR.MSTR       4   Master Mode Select
SPCR.CPOL       3   Clock Polarity
SPCR.CPHA       2   Clock Phase
SPCR.SPR1       1   SPI Clock Rate Selects 1
SPCR.SPR0       0   SPI Clock Rate Selects 0
SPSR           0x1029   SPI Status Register
SPSR.SPIF       7   SPI Transfer Complete Flag
SPSR.WCOL       6   Write Collision
SPSR.MODF       4   Mode Fault
SPDR           0x102A   SPI Data Register
BAUD           0x102B   SCI Baud Rate Control 3
BAUD.TCLR       7   Clear Baud Rate Counters (Test)
BAUD.SCP1       5   SCI Baud Rate Prescaler Selects 1
BAUD.SCP0       4   SCI Baud Rate Prescaler Selects 0
BAUD.RCKB       3   SCI Baud Rate Clock Check (Test)
BAUD.SCR2       2   SCI Baud Rate Selects 2
BAUD.SCR1       1   SCI Baud Rate Selects 1
BAUD.SCR0       0   SCI Baud Rate Selects 0
SCCR1          0x102C   SCI Control Register 1
SCCR1.R8        7   Receive Data Bit 8
SCCR1.T8        6   Transmit Data Bit 8
SCCR1.M         4   Mode (Select Character Format)
SCCR1.WAKE      3   Wakeup by Address Mark/Idle
SCCR2          0x102D   SCI Control Register 2
SCCR2.TIE       7   Transmit Interrupt Enable
SCCR2.TCIE      6   Transmit Complete Interrupt Enable
SCCR2.RIE       5   Receiver Interrupt Enable
SCCR2.ILIE      4   Idle Line Interrupt Enable
SCCR2.TE        3   Transmitter Enable
SCCR2.RE        2   Receiver Enable
SCCR2.RWU       1   Receiver Wakeup Control
SCCR2.SBK       0   Send Break
SCSR           0x102E   SCI Status Register
SCSR.TDRE       7   Transmit Data Register Empty Flag
SCSR.TC         6   Transmit Complete Flag
SCSR.RDRF       5   Receive Data Register Full Flag
SCSR.IDLE       4   Idle Line Detected Flag
SCSR.OR         3   Overrun Error Flag
SCSR.NF         2   Noise Error Flag
SCSR.FE         1   Framing Error
SCDR           0x102F   SCI Data (Read RDR, Write TDR)
SCDR.R7T7       7   Receiver/transmitter data bits 7
SCDR.R6T6       6   Receiver/transmitter data bits 6
SCDR.R5T5       5   Receiver/transmitter data bits 5
SCDR.R4T4       4   Receiver/transmitter data bits 4
SCDR.R3T3       3   Receiver/transmitter data bits 3
SCDR.R2T2       2   Receiver/transmitter data bits 2
SCDR.R1T1       1   Receiver/transmitter data bits 1
SCDR.R0T0       0   Receiver/transmitter data bits 0
ADCTL          0x1030   A_D Control Register
ADCTL.CCF       7   Conversions Complete Flag
ADCTL.SCAN      5   Continuous Scan Control
ADCTL.MULT      4   Multiple-Channel/Single-Channel Control
ADCTL.CD        3   Channel Selects D
ADCTL.CC        2   Channel Selects C
ADCTL.CB        1   Channel Selects B
ADCTL.CA        0   Channel Selects A
ADR1           0x1031   A_D Result Register 1
ADR2           0x1032   A_D Result Register 2
ADR3           0x1033   A_D Result Register 3
ADR4           0x1034   A_D Result Register 4
BPROT          0x1035   Block Protect Register
BPROT.PTCON     4   Protect CONFIG Register
BPROT.BPRT3     3   Block Protect Bits for EEPROM Bit 3
BPROT.BPRT2     2   Block Protect Bits for EEPROM Bit 2
BPROT.BPRT1     1   Block Protect Bits for EEPROM Bit 1
BPROT.BPRT0     0   Block Protect Bits for EEPROM Bit 0
PORTG          0x1036   Port G data
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6
PORTG.PG5       5   Port G Data Bit 5
PORTG.PG4       4   Port G Data Bit 4
PORTG.PG3       3   Port G Data Bit 3
PORTG.PG2       2   Port G Data Bit 2
PORTG.PG1       1   Port G Data Bit 1
PORTG.PG0       0   Port G Data Bit 0
DDRG           0x1037   Data direction G
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6
DDRG.DDG5       5   Data Direction for Port G Bit 5
DDRG.DDG4       4   Data Direction for Port G Bit 4
DDRG.DDG3       3   Data Direction for Port G Bit 3
DDRG.DDG2       2   Data Direction for Port G Bit 2
DDRG.DDG1       1   Data Direction for Port G Bit 1
DDRG.DDG0       0   Data Direction for Port G Bit 0
RESERVED38     0x1038   RESERVED38
OPTION         0x1039   System Configuration Options
OPTION.ADPU     7   Analog-to-Digital Converter Power-Up
OPTION.CSEL     6   Clock Select
OPTION.IRQE     5   Configure IRQ for Edge-Sensitive Only Operation
OPTION.DLY      4   Enable Oscillator Startup Delay
OPTION.CME      3   Clock Monitor Enable
OPTION.CR1      1   COP Timer Rate Select Bit 1
OPTION.CR0      0   COP Timer Rate Select Bit 0
COPRST         0x103A   Arm_Reset COP Timer Circuitry
PPROG          0x103B   EEPROM Program Control Register
PPROG.ODD       7   Program Odd Rows in Half of EEPROM (Test)
PPROG.EVEN      6   Program Even Rows in Half of EEPROM (Test)
PPROG.BYTE      4   Byte/Erase Select
PPROG.ROW       3   Row/All Erase Select
PPROG.ERASE     2   Erase Mode Select
PPROG.EELAT     1   EEPROM Latch Control
PPROG.EEPGM     0   EEPROM Program Command
HPRIO          0x103C   Highest Priority I-Bit Int and Misc
HPRIO.RBOOT     7   Read Bootstrap ROM
HPRIO.SMOD      6   Special Mode Select
HPRIO.MDA       5   Mode Select A
HPRIO.IRV       4   Internal Read Visibility/Not E
HPRIO.PSEL3     3   Priority Select Bit 3
HPRIO.PSEL2     2   Priority Select Bit 2
HPRIO.PSEL1     1   Priority Select Bit 1
HPRIO.PSEL0     0   Priority Select Bit 0
INIT           0x103D   RAM and I_O Mapping Register
INIT.RAM3       7   RAM Map Position 3
INIT.RAM2       6   RAM Map Position 2
INIT.RAM1       5   RAM Map Position 1
INIT.RAM0       4   RAM Map Position 0
INIT.REG3       3   64-Byte Register Block Position 3
INIT.REG2       2   64-Byte Register Block Position 2
INIT.REG1       1   64-Byte Register Block Position 1
INIT.REG0       0   64-Byte Register Block Position 0
TEST1          0x103E   Factory TEST Control Register
TEST1.TILOP     7   Test Illegal Opcode
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2
TEST1.FCOP      1
TEST1.TCON      0
CONFIG         0x103F   COP, ROM, and EEPROM Enables
CONFIG.NOSEC    3   Security Disable
CONFIG.NOCOP    2   COP System Disable
CONFIG.ROMON    1   ROM Enable
CONFIG.EEON     0   EEPROM Enable
RESERVFFC0     0xFFC0   RESERVED
RESERVFFC1     0xFFC1   RESERVED
RESERVFFC2     0xFFC2   RESERVED
RESERVFFC3     0xFFC3   RESERVED
RESERVFFC4     0xFFC4   RESERVED
RESERVFFC5     0xFFC5   RESERVED
RESERVFFC6     0xFFC6   RESERVED
RESERVFFC7     0xFFC7   RESERVED
RESERVFFC8     0xFFC8   RESERVED
RESERVFFC9     0xFFC9   RESERVED
RESERVFFCA     0xFFCA   RESERVED
RESERVFFCB     0xFFCB   RESERVED
RESERVFFCC     0xFFCC   RESERVED
RESERVFFCD     0xFFCD   RESERVED
RESERVFFCE     0xFFCE   RESERVED
RESERVFFCF     0xFFCF   RESERVED
RESERVFFD0     0xFFD0   RESERVED
RESERVFFD1     0xFFD1   RESERVED
RESERVFFD2     0xFFD2   RESERVED
RESERVFFD3     0xFFD3   RESERVED
RESERVFFD4     0xFFD4   RESERVED
RESERVFFD5     0xFFD5   RESERVED


.68HC711M2
; http://

; RAM=1280
; ROM=0
; EPROM=32K
; EEPROM=640

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC711N4
; http://

; RAM=768
; ROM=0
; EPROM=24K
; EEPROM=640

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC711P2
; MC68HC11P2/D  http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=68HC711P2&nodeId=01M98635
; MC68HC11P2.pdf

; ROM=0
; RAM=1K
; EEPROM=640
; EPROM=32K


; MEMORY MAP
area DATA FSR         0x0000:0x0080
area DATA RAM         0x0080:0x0480
area BSS  RESERVED    0x0480:0x0D80
area DATA EEPROM      0x0D80:0x1000
area BSS  RESERVED    0x1000:0x8000
area CODE EPROM       0x8000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET 	0xFFFE       RESET
interrupt CME 		0xFFFC       Clock monitor fail 
interrupt NOCOP 	0xFFFA       COP failure 
interrupt OPCODE 	0xFFF8       Illegal opcode trap 
interrupt SOFT 		0xFFF6       Software interrupt 
interrupt XIRQ 		0xFFF4       XIRQ pin 
interrupt IRQ 		0xFFF2       IRQ pin I None
interrupt RTII 		0xFFF0       Real-time interrupt 
interrupt IC1I 		0xFFEE       Timer input capture 1 
interrupt IC2I 		0xFFEC       Timer input capture 2 
interrupt IC3I 		0xFFEA       Timer input capture 3 
interrupt OC1I 		0xFFE8       Timer output compare 1 
interrupt OC2I 		0xFFE6       Timer output compare 2 
interrupt OC3I 		0xFFE4       Timer output compare 3 
interrupt OC4I 		0xFFE2       Timer output compare 4 
interrupt I4_O5I 	0xFFE0       Timer input capture 4/output compare 5 
interrupt TOI 		0xFFDE       Timer overflow 
interrupt PAOVI 	0xFFDC       Pulse accumulator overflow 
interrupt PAII 		0xFFDA       Pulse accumulator input edge 
interrupt SPIE 		0xFFD8       SPI serial transfer complete 
interrupt SCI1 		0xFFD6       SCI1
interrupt SCI2 		0xFFD4       SCI2
interrupt SCI3 		0xFFD2       SCI3


; INPUT/ OUTPUT PORTS
PORTA          0x0000    Port A data
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001    Data direction A
DDRA.DDRA7      7   Data Direction for Port A Bit 7
DDRA.DDRA6      6   Data Direction for Port A Bit 6
DDRA.DDRA5      5   Data Direction for Port A Bit 5
DDRA.DDRA4      4   Data Direction for Port A Bit 4
DDRA.DDRA3      3   Data Direction for Port A Bit 3
DDRA.DDRA2      2   Data Direction for Port A Bit 2
DDRA.DDRA1      1   Data Direction for Port A Bit 1
DDRA.DDRA0      0   Data Direction for Port A Bit 0
DDRB           0x0002    Data direction B
DDRB.DDRB7      7   Data Direction for Port B Bit 7
DDRB.DDRB6      6   Data Direction for Port B Bit 6
DDRB.DDRB5      5   Data Direction for Port B Bit 5
DDRB.DDRB4      4   Data Direction for Port B Bit 4
DDRB.DDRB3      3   Data Direction for Port B Bit 3
DDRB.DDRB2      2   Data Direction for Port B Bit 2
DDRB.DDRB1      1   Data Direction for Port B Bit 1
DDRB.DDRB0      0   Data Direction for Port B Bit 0
DDRF           0x0003    Data direction F
DDRF.DDRF7      7   Data Direction for Port F Bit 7
DDRF.DDRF6      6   Data Direction for Port F Bit 6
DDRF.DDRF5      5   Data Direction for Port F Bit 5
DDRF.DDRF4      4   Data Direction for Port F Bit 4
DDRF.DDRF3      3   Data Direction for Port F Bit 3
DDRF.DDRF2      2   Data Direction for Port F Bit 2
DDRF.DDRF1      1   Data Direction for Port F Bit 1
DDRF.DDRF0      0   Data Direction for Port F Bit 0
PORTB          0x0004    Port B data
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005    Port F data
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006    Port C data
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007    Data direction C
DDRC.DDRC7      7   Data Direction for Port C Bit 7
DDRC.DDRC6      6   Data Direction for Port C Bit 6
DDRC.DDRC5      5   Data Direction for Port C Bit 5
DDRC.DDRC4      4   Data Direction for Port C Bit 4
DDRC.DDRC3      3   Data Direction for Port C Bit 3
DDRC.DDRC2      2   Data Direction for Port C Bit 2
DDRC.DDRC1      1   Data Direction for Port C Bit 1
DDRC.DDRC0      0   Data Direction for Port C Bit 0
PORTD          0x0008    Port D data
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009    Data direction D
DDRD.DDRD5      5   Data Direction for Port D Bit 5
DDRD.DDRD4      4   Data Direction for Port D Bit 4
DDRD.DDRD3      3   Data Direction for Port D Bit 3
DDRD.DDRD2      2   Data Direction for Port D Bit 2
DDRD.DDRD1      1   Data Direction for Port D Bit 1
DDRD.DDRD0      0   Data Direction for Port D Bit 0
PORTE          0x000A    Port E data
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B    Timer compare force
CFORC.FOC1      7   Force output compares 1
CFORC.FOC2      6   Force output compares 2
CFORC.FOC3      5   Force output compares 3
CFORC.FOC4      4   Force output compares 4
CFORC.FOC5      3   Force output compares 5
OC1M           0x000C    Output compare 1 mask
OC1M.OC1M7      7   Output compare masks for OC1 bit 7
OC1M.OC1M6      6   Output compare masks for OC1 bit 6
OC1M.OC1M5      5   Output compare masks for OC1 bit 5
OC1M.OC1M4      4   Output compare masks for OC1 bit 4
OC1M.OC1M3      3   Output compare masks for OC1 bit 3
OC1D           0x000D    Output compare 1 data
OC1D.OC1D7      7   Output compare data for OC1 bit 7
OC1D.OC1D6      6   Output compare data for OC1 bit 6
OC1D.OC1D5      5   Output compare data for OC1 bit 5
OC1D.OC1D4      4   Output compare data for OC1 bit 4
OC1D.OC1D3      3   Output compare data for OC1 bit 3
TCNTH          0x000E    Timer count HIGH
TCNTL          0x000F    Timer count LOW
TIC1H          0x0010    Timer input capture 1 HIGH
TIC1L          0x0011    Timer input capture 1 LOW
TIC2H          0x0012    Timer input capture 2 HIGH
TIC2L          0x0013    Timer input capture 2 LOW
TIC3H          0x0014    Timer input capture 3 HIGH
TIC3L          0x0015    Timer input capture 3 LOW
TOC1H          0x0016    Timer output compare 1 HIGH
TOC1L          0x0017    Timer output compare 1 LOW
TOC2H          0x0018    Timer output compare 2 HIGH
TOC2L          0x0019    Timer output compare 2 LOW
TOC3H          0x001A    Timer output compare 3 HIGH
TOC3L          0x001B    Timer output compare 3 LOW
TOC4H          0x001C    Timer output compare 4 HIGH
TOC4L          0x001D    Timer output compare 4 LOW
TI4_O5H        0x001E    Capture 4/compare 5 HIGH
TI4_O5L        0x001F    Capture 4/compare 5 LOW
TCTL1          0x0020    Timer control 1
TCTL1.OM2       7   Output mode 2
TCTL1.OL2       6   Output level 2
TCTL1.OM3       5   Output mode 3
TCTL1.OL3       4   Output level 3
TCTL1.OM4       3   Output mode 4
TCTL1.OL4       2   Output level 4
TCTL1.OM5       1   Output mode 5
TCTL1.OL5       0   Output level 5
TCTL2          0x0021    Timer control 2
TCTL2.EDG4B     7   Input capture edge control 4B
TCTL2.EDG4A     6   Input capture edge control 4A
TCTL2.EDG1B     5   Input capture edge control 1B
TCTL2.EDG1A     4   Input capture edge control 1A
TCTL2.EDG2B     3   Input capture edge control 2B
TCTL2.EDG2A     2   Input capture edge control 2A
TCTL2.EDG3B     1   Input capture edge control 3B
TCTL2.EDG3A     0   Input capture edge control 3A
TMSK1          0x0022    Timer interrupt mask 1
TMSK1.OC1I      7   Output compare 1 interrupt enable
TMSK1.OC2I      6   Output compare 2 interrupt enable
TMSK1.OC3I      5   Output compare 3 interrupt enable
TMSK1.OC4I      4   Output compare 4 interrupt enable
TMSK1.I4_O5I    3   Input capture 4/output compare 5 interrupt enable
TMSK1.IC1I      2   Input capture 1 interrupt enable
TMSK1.IC2I      1   Input capture 2 interrupt enable
TMSK1.IC3I      0   Input capture 3 interrupt enable
TFLG1          0x0023    Timer interrupt flag 1
TFLG1.OC1F      7   Output compare 1 flag
TFLG1.OC2F      6   Output compare 2 flag
TFLG1.OC3F      5   Output compare 3 flag
TFLG1.OC4F      4   Output compare 4 flag
TFLG1.I4_O5F    3   Input capture 4/output compare 5 flag
TFLG1.IC1F      2   Input capture 1 flag
TFLG1.IC2F      1   Input capture 2 flag
TFLG1.IC3F      0   Input capture 3 flag
TMSK2          0x0024    Timer interrupt mask 2
TMSK2.TOI       7   Timer overflow interrupt enable
TMSK2.RTII      6   Real-time interrupt enable
TMSK2.PAOVI     5   Pulse accumulator overflow interrupt enable
TMSK2.PALL      4   Pulse accumulator interrupt enable
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025    Timer interrupt flag 2
TFLG2.TOF       7   Timer overflow interrupt flag
TFLG2.RTIF      6   Real time (periodic) interrupt flag
TFLG2.PAOVF     5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF      4   Pulse accumulator input edge interrupt flag
PACTL          0x0026    Pulse accumulator control
PACTL.PAEN      6   Pulse accumulator system enable
PACTL.PAMOD     5   Pulse accumulator mode
PACTL.PEDGE     4   Pulse accumulator edge control
PACTL.I4_O5     2   Input capture 4/output compare
PACTL.RTR1      1   RTI interrupt rate select 1
PACTL.RTR0      0   RTI interrupt rate select 0
PACNT          0x0027    Pulse accumulator count
SPCR           0x0028    SPI control
SPCR.SPIE       7   Serial peripheral interrupt enable
SPCR.SPE        6   Serial peripheral system enable
SPCR.DWON       5   Port D wired-OR mode
SPCR.MSTR       4   Master mode select
SPCR.CPOL       3   Clock polarity
SPCR.CPHA       2   Clock phase
SPCR.SPR1       1   SPI clock rate selects 1
SPCR.SPR0       0   SPI clock rate selects 0
SPSR           0x0029    SPI status
SPSR.SPIF       7   SPI interrupt complete flag
SPSR.WCOL       6   Write collision
SPSR.MODF       4   Mode fault
SPDR           0x002A    SPI data
EPROG          0x002B    EPROM programming
EPROG.MBE       7   Multiple byte program enable
EPROG.ELAT      5   EPROM latch control
EPROG.EXCOL     4   Select extra columns
EPROG.EXROW     3   Select extra rows
EPROG.EPGM      0   EPROM program command
PPAR           0x002C    Port pull-up assignment
PPAR.HPPUE      3   Port H pin pull-up enable
PPAR.GPPUE      2   Port G pin pull-up enable
PPAR.FPPUE      1   Port F pin pull-up enable
PPAR.BPPUE      0   Port B pin pull-up enable
RESERV2D       0x002D    RESERVED
PLLCR          0x002E    PLL control
PLLCR.PLLON     7   PLL on
PLLCR.BCS       6   Bus clock select
PLLCR.AUTO      5   Automatic bandwidth control
PLLCR.BWC       4   Bandwidth control
PLLCR.VCOT      3   VCO test (Test mode only)
PLLCR.MCS       2   Module clock select
PLLCR.LCK       1   Synthesizer lock detect
PLLCR.WEN       0   WAIT enable
SYNR           0x002F    Synthesizer program
SYNR.SYNX1      7
SYNR.SYNX0      6
SYNR.SYN45      5
SYNR.SYNE4      4
SYNR.SYNY3      3
SYNR.SYNY2      2
SYNR.SYNY1      1
SYNR.SYNY0      0
ADCTL          0x0030    A/D control&stattus
ADCTL.CCF       7   Conversions complete flag
ADCTL.SCAN      5   Continuous scan control
ADCTL.MULT      4   Multiple-channel/single-channel control
ADCTL.CD        3   Channel select D
ADCTL.CC        2   Channel select C
ADCTL.CB        1   Channel select B
ADCTL.CA        0   Channel select A
ADR1           0x0031    A/D result 1
ADR2           0x0032    A/D result 2
ADR3           0x0033    A/D result 3
ADR4           0x0034    A/D result 4
BPROT          0x0035    Blok protect
BPROT.BULKP     7   Bulk erase of EEPROM protect
BPROT.BPRT4     5   Block protect bit for top 128 bytes of EEPROM
BPROT.PTCON     4   Protect for CONFIG register
BPROT.BPRT3     3   Block protect bit 3 for EEPROM
BPROT.BPRT2     2   Block protect bit 2 for EEPROM
BPROT.BPRT1     1   Block protect bit 1 for EEPROM
BPROT.BPRT0     0   Block protect bit 0 for EEPROM
RESERV36       0x0036    Reserved
INIT2          0x0037    EEPROM mapping
INIT2.EE3       7   EEPROM map position 3
INIT2.EE2       6   EEPROM map position 2
INIT2.EE1       5   EEPROM map position 1
INIT2.EE0       4   EEPROM map position 0
INIT2.M3DL1     3   M3DL1 MI BUS delay select
INIT2.M3DL0     2   M3DL0 MI BUS delay select
INIT2.M2DL1     1   M2DL1 MI BUS delay select
INIT2.M2DL0     0   M2DL0 MI BUS delay select
OPT2           0x0038    System config options 2
OPT2.LIRDV      7   LIR driven
OPT2.CWOM       6   Port C wired-OR mode
OPT2.STRCH      5   Stretch external accesses
OPT2.IRVNE      4   Internal read visibility/not E
OPT2.LSBF       3   LSB-first enable
OPT2.SPR2       2   SPI clock rate select
OPTION         0x0039    System config option 1
OPTION.ADPU     7   A/D power-up
OPTION.CSEL     6   Clock select
OPTION.IRQE     5   Configure IRQ for falling edge sensitive operation
OPTION.DLY      4   Enable oscillator start-up delay
OPTION.CME      3   Clock monitor enable
OPTION.FCME     2   Force clock monitor enable
OPTION.CR1      1   COP timer rate select bits 1
OPTION.CR0      0   COP timer rate select bits 0
COPRST         0x003A    COP timer arm/reset
PPROG          0x003B    EEPROM programming
PPROG.ODD       7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN      6   Program even rows in half of EEPROM (Test)
PPROG.BYTE      4   EEPROM byte erase mode
PPROG.ROW       3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE     2   Erase/normal control for EEPROM
PPROG.EELAT     1   EEPROM latch control
PPROG.EEPGM     0   EEPROM program command
HPRIO          0x003C    Highest priority interrupt
HPRIO.RBOOT     7   Read bootstrap ROM
HPRIO.SMOD      6   Special mode select
HPRIO.MDA       5   Mode select A
HPRIO.PSEL4     4   Priority select bits 4
HPRIO.PSEL3     3   Priority select bits 3
HPRIO.PSEL2     2   Priority select bits 2
HPRIO.PSEL1     1   Priority select bits 1
HPRIO.PSEL0     0   Priority select bits 0
INIT           0x003D    RAM&I/O mapping
INIT.RAM3       7   RAM map position 3
INIT.RAM2       6   RAM map position 2
INIT.RAM1       5   RAM map position 1
INIT.RAM0       4   RAM map position 0
INIT.REG3       3   128-byte register block position 3
INIT.REG2       2   128-byte register block position 2
INIT.REG1       1   128-byte register block position 1
INIT.REG0       0   128-byte register block position 0
TEST1          0x003E    Factori test
TEST1.TILOP     7   Test Illegal Opcode
TEST1.PLTST     6   
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
TEST1.MIDLY     0                                                      
CONFIG         0x003F    Configuration
CONFIG.ROMAD    7   ROM mapping control
CONFIG.PAREN    4   Pull-up assignment register enable
CONFIG.NOSEC    3   EEPROM security disabled
CONFIG.NOCOP    2   COP system disable
CONFIG.ROMON    1   ROM enable
CONFIG.EEON     0   EEPROM enable
RESERV40       0x0040    Reserved
RESERV41       0x0041    Reserved
RESERV42       0x0042    Reserved
RESERV43       0x0043    Reserved
RESERV44       0x0044    Reserved
RESERV45       0x0045    Reserved
RESERV46       0x0046    Reserved
RESERV47       0x0047    Reserved
RESERV48       0x0048    Reserved
RESERV49       0x0049    Reserved
RESERV4A       0x004A    Reserved
RESERV4B       0x004B    Reserved
RESERV4C       0x004C    Reserved
RESERV4D       0x004D    Reserved
RESERV4E       0x004E    Reserved
RESERV4F       0x004F    Reserved
S2BDH          0x0050    SCI/MI 2/3 baud HIGH
S2BDH.B2TST     7   Baud register test (Test mode only)     
S2BDH.B2SPL     6   Baud rate counter split (Test mode only)
S2BDH.S2B12     4   SCI baud rate/ MI BUS clock rate selects
S2BDH.S2B11     3   SCI baud rate/ MI BUS clock rate selects
S2BDH.S2B10     2   SCI baud rate/ MI BUS clock rate selects
S2BDH.S2B9      1   SCI baud rate/ MI BUS clock rate selects
S2BDH.S2B8      0   SCI baud rate/ MI BUS clock rate selects
S2BDL          0x0051    SCI/MI 2/3 baud LOW
S2BDL.S2B7      7   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B6      6   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B5      5   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B4      4   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B3      3   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B2      2   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B1      1   SCI baud rate/ MI BUS clock rate selects
S2BDL.S2B0      0   SCI baud rate/ MI BUS clock rate selects
S2CR1          0x0052    SCO/MI 2 control 1
S2CR1.LOPS2     7   SCI loop mode enable
S2CR1.WOMS2     6   Wired-OR mode for MI BUS2 pins (PH6, PH7)
S2CR1.MIE2      5   Motorola interface bus enable 2
S2CR1.M2        4   Mode (select character format)
S2CR1.WAKE2     3   Wakeup by address mark/idle
S2CR1.ILT2      2   Idle line type
S2CR1.PE2       1   Parity enable
S2CR1.PT2       0   MI BUS TX polarity
S2CR2          0x0053    SCO/MI 2 control 2
S2CR2.TIE2      7   Transmit interrupt enable         
S2CR2.TCIE2     6   Transmit complete interrupt enable
S2CR2.RIE2      5   Receiver interrupt enable         
S2CR2.ILIE2     4   Idle line interrupt enable        
S2CR2.TE2       3   Transmitter enable                
S2CR2.RE2       2   Receiver enable                   
S2CR2.RWU2      1   Receiver wakeup control           
S2CR2.SBK2      0   Send break                        
S2SR1          0x0054    SCI/MI 2 status 1
S2SR1.TDRE2     7   Transmit data register empty flag
S2SR1.TC2       6   Transmit complete flag           
S2SR1.RDRF2     5   Receive data register full flag 2
S2SR1.IDLE2     4   Idle line detected flag          
S2SR1.OR2       3   Bit error 2
S2SR1.NF2       2   Noise error flag                 
S2SR1.FE2       1   Framing error                    
S2SR1.PF2       0   Parity error flag                
S2SR2          0x0055    SCI/MI 2 status 2
S2SR2.RAF2      0   Receiver active flag (read only)
S2DRH          0x0056    SCI/MI 2 data HIGH
S2DRH.R8B       7   Receiver bit 8   
S2DRH.T8B       6   Transmitter bit 8
S2DRL          0x0057    SCI/MI 2 data LOW
S2DRL.R7T7B     7   Receiver/transmitter data bit 7
S2DRL.R6T6B     6   Receiver/transmitter data bit 6
S2DRL.R5T5B     5   Receiver/transmitter data bit 5
S2DRL.R4T4B     4   Receiver/transmitter data bit 4
S2DRL.R3T3B     3   Receiver/transmitter data bit 3
S2DRL.R2T2B     2   Receiver/transmitter data bit 2
S2DRL.R1T1B     1   Receiver/transmitter data bit 1
S2DRL.R0T0B     0   Receiver/transmitter data bit 0
RESERV58       0x0058    Reserved
RESERV59       0x0059    Reserved
S3CR1          0x005A    SCO/MI 3 control 1
S3CR1.LOPS3     7   SCI loop mode enable                 
S3CR1.WOMS3     6   Wired-OR mode for SCI pins (PD1, PD0)
S3CR1.MIE3      5   Motorola Interface Bus Enable 3
S3CR1.M3        4   Mode (select character format)       
S3CR1.WAKE3     3   Wakeup by address mark/idle          
S3CR1.ILT3      2   Idle line type                       
S3CR1.PE3       1   Parity enable                        
S3CR1.PT3       0   Parity type                          
S3CR2          0x005B    SCO/MI 3 control 2
S3CR2.TIE3      7   Transmit interrupt enable         
S3CR2.TCIE3     6   Transmit complete interrupt enable
S3CR2.RIE3      5   Receiver interrupt enable         
S3CR2.ILIE3     4   Idle line interrupt enable        
S3CR2.TE3       3   Transmitter enable                
S3CR2.RE3       2   Receiver enable                   
S3CR2.RWU3      1   Receiver wakeup control           
S3CR2.SBK3      0   Send break                        
S3SR1          0x005C    SCI/MI 3 status 1
S3SR1.TDRE3     7   Transmit data register empty flag
S3SR1.TC3       6   Transmit complete flag           
S3SR1.RDRF3     5   Receive data register full flag  
S3SR1.IDLE3     4   Idle line detected flag          
S3SR1.OR3       3   Overrun error flag               
S3SR1.NF3       2   Noise error flag                 
S3SR1.FE3       1   Framing error                    
S3SR1.PF3       0   Parity error flag                
S3SR2          0x005D    SCI/MI 3 status 2
S3SR2.RAF3      0   Receiver active flag (read only)
S3DRH          0x005E    SCI/MI 3 data HIGH
S3DRH.R8C       7   Receiver bit 8
S3DRH.T8C       6   Transmitter bit 8
S3DRL          0x005F    SCI/MI 3 data LOW
S3DRL.R7T7C     7   Receiver/transmitter data bit 7
S3DRL.R6T6C     6   Receiver/transmitter data bit 6
S3DRL.R5T5C     5   Receiver/transmitter data bit 5
S3DRL.R4T4C     4   Receiver/transmitter data bit 4
S3DRL.R3T3C     3   Receiver/transmitter data bit 3
S3DRL.R2T2C     2   Receiver/transmitter data bit 2
S3DRL.R1T1C     1   Receiver/transmitter data bit 1
S3DRL.R0T0C     0   Receiver/transmitter data bit 0
PWCLK          0x0060    Pulse width clock select
PWCLK.CON34     7   Concatenate channels 3 and 4
PWCLK.CON12     6   Concatenate Channels 1 and 2
PWCLK.PCKA2     5   Prescaler for clock A 2
PWCLK.PCKA1     4   Prescaler for clock A 1
PWCLK.PCKB3     2   Prescaler for clock B 3
PWCLK.PCKB2     1   Prescaler for clock B 2
PWCLK.PCKB1     0   Prescaler for clock B 1
PWPOL          0x0061    Pulse width polarity select
PWPOL.PCLK4     7   Pulse width channel 4 clock select
PWPOL.PCLK3     6   Pulse width channel 3 clock select
PWPOL.PCLK2     5   Pulse width channel 2 clock select
PWPOL.PCLK1     4   Pulse width channel 1 clock select
PWPOL.PPOL4     3   Pulse width channel 4 polarity
PWPOL.PPOL3     2   Pulse width channel 3 polarity
PWPOL.PPOL2     1   Pulse width channel 2 polarity
PWPOL.PPOL1     0   Pulse width channel 1 polarity
PWSCAL         0x0062    Pulse width scale
PWEN           0x0063    Pulse width enable
PWEN.TPWSL      7   PWM scaled clock test bit (Test mode only)
PWEN.DISCP      6   Disable compare scaled E clock (Test mode only)
PWEN.PWEN4      3   Pulse width channel 4
PWEN.PWEN3      2   Pulse width channel 3
PWEN.PWEN2      1   Pulse width channel 2
PWEN.PWEN1      0   Pulse width channel 1
PWCNT1         0x0064    Pulse width count 1
PWCNT2         0x0065    Pulse width count 2
PWCNT3         0x0066    Pulse width count 3
PWCNT4         0x0067    Pulse width count 4
PWPER1         0x0068    Pulse width period 1
PWPER2         0x0069    Pulse width period 2
PWPER3         0x006A    Pulse width period 3
PWPER4         0x006B    Pulse width period 4
PWDTY1         0x006C    Pulse width duty 1
PWDTY2         0x006D    Pulse width duty 2
PWDTY3         0x006E    Pulse width duty 3
PWDTY4         0x006F    Pulse width duty 4
SCBDH          0x0070    SCI 1 baud rate HIGH
SCBDH.BTST      7   Baud register test (Test mode only)
SCBDH.BSPL      6   Baud rate counter split (Test mode only)
SCBDH.SBR12     4   SCI baud rate selects 12
SCBDH.SBR11     3   SCI baud rate selects 11
SCBDH.SBR10     2   SCI baud rate selects 10
SCBDH.SBR9      1   SCI baud rate selects 9 
SCBDH.SBR8      0   SCI baud rate selects 8 
SCBDL          0x0071    SCI 1 baud rate LOW
SCBDL.SBR7      7   SCI baud rate selects 7
SCBDL.SBR6      6   SCI baud rate selects 6
SCBDL.SBR5      5   SCI baud rate selects 5
SCBDL.SBR4      4   SCI baud rate selects 4
SCBDL.SBR3      3   SCI baud rate selects 3
SCBDL.SBR2      2   SCI baud rate selects 2
SCBDL.SBR1      1   SCI baud rate selects 1
SCBDL.SBR0      0   SCI baud rate selects 0
SCCR1          0x0072    SCI 1 control 1
SCCR1.LOOPS     7   SCI loop mode enable
SCCR1.WOMS      6   Wired-OR mode for SCI pins (PD1, PD0)
SCCR1.M         4   Mode (select character format)
SCCR1.WAKE      3   Wakeup by address mark/idle
SCCR1.ILT       2   Idle line type
SCCR1.PE        1   Parity enable
SCCR1.PT        0   Parity type
SCCR2          0x0073    SCI 1 control 2
SCCR2.TIE       7   Transmit interrupt enable
SCCR2.TCIE      6   Transmit complete interrupt enable
SCCR2.RIE       5   Receiver interrupt enable
SCCR2.ILIE      4   Idle line interrupt enable
SCCR2.TE        3   Transmitter enable
SCCR2.RE        2   Receiver enable
SCCR2.RWU       1   Receiver wakeup control
SCCR2.SBK       0   Send break
SCSR1          0x0074    SCI 1 status 1
SCSR1.TDRE      7   Transmit data register empty flag
SCSR1.TC        6   Transmit complete flag
SCSR1.RDRF      5   Receive data register full flag
SCSR1.IDLE      4   Idle line detected flag
SCSR1.OR        3   Overrun error flag
SCSR1.NF        2   Noise error flag
SCSR1.FE        1   Framing error
SCSR1.PF        0   Parity error flag
SCSR2          0x0075    SCI 1 status 2
SCSR2.RAF       0   Receiver active flag (read only)
SCDRH          0x0076    SCI 1 data HIGH
SCDRH.R8        7   Receiver bit 8
SCDRH.T8        6   Transmitter bit 8
SCDRL          0x0077    SCI 1 data LOW
SCDRL.R7T7      7   Receiver/transmitter data bit 7
SCDRL.R6T6      6   Receiver/transmitter data bit 6
SCDRL.R5T5      5   Receiver/transmitter data bit 5
SCDRL.R4T4      4   Receiver/transmitter data bit 4
SCDRL.R3T3      3   Receiver/transmitter data bit 3
SCDRL.R2T2      2   Receiver/transmitter data bit 2
SCDRL.R1T1      1   Receiver/transmitter data bit 1
SCDRL.R0T0      0   Receiver/transmitter data bit 0
RESERV78       0x0078    Reserved
RESERV79       0x0079    Reserved
RESERV7A       0x007A    Reserved
RESERV7B       0x007B    Reserved
PORTH          0x007C    Port H data
PORTH.PH7       7    Port H Data Bit 7
PORTH.PH6       6    Port H Data Bit 6
PORTH.PH5       5    Port H Data Bit 5
PORTH.PH4       4    Port H Data Bit 4
PORTH.PH3       3    Port H Data Bit 3
PORTH.PH2       2    Port H Data Bit 2
PORTH.PH1       1    Port H Data Bit 1
PORTH.PH0       0    Port H Data Bit 0
DDRH           0x007D    Data direction H
DDRH.DDH7       7   Data Direction for Port H Bit 7
DDRH.DDH6       6   Data Direction for Port H Bit 6
DDRH.DDH5       5   Data Direction for Port H Bit 5
DDRH.DDH4       4   Data Direction for Port H Bit 4
DDRH.DDH3       3   Data Direction for Port H Bit 3
DDRH.DDH2       2   Data Direction for Port H Bit 2
DDRH.DDH1       1   Data Direction for Port H Bit 1
DDRH.DDH0       0   Data Direction for Port H Bit 0
PORTG          0x007E    Port G data
PORTG.PG7       7   Port G Data Bit 7
PORTG.PG6       6   Port G Data Bit 6
PORTG.PG5       5   Port G Data Bit 5
PORTG.PG4       4   Port G Data Bit 4
PORTG.PG3       3   Port G Data Bit 3
PORTG.PG2       2   Port G Data Bit 2
PORTG.PG1       1   Port G Data Bit 1
PORTG.PG0       0   Port G Data Bit 0
DDRG           0x007F    Data direction G
DDRG.DDG7       7   Data Direction for Port G Bit 7
DDRG.DDG6       6   Data Direction for Port G Bit 6
DDRG.DDG5       5   Data Direction for Port G Bit 5
DDRG.DDG4       4   Data Direction for Port G Bit 4
DDRG.DDG3       3   Data Direction for Port G Bit 3
DDRG.DDG2       2   Data Direction for Port G Bit 2
DDRG.DDG1       1   Data Direction for Port G Bit 1
DDRG.DDG0       0   Data Direction for Port G Bit 0
RESERVFFC0     0xFFC0    RESERVED
RESERVFFC1     0xFFC1    RESERVED
RESERVFFC2     0xFFC2    RESERVED
RESERVFFC3     0xFFC3    RESERVED
RESERVFFC4     0xFFC4    RESERVED
RESERVFFC5     0xFFC5    RESERVED
RESERVFFC6     0xFFC6    RESERVED
RESERVFFC7     0xFFC7    RESERVED
RESERVFFC8     0xFFC8    RESERVED
RESERVFFC9     0xFFC9    RESERVED
RESERVFFCA     0xFFCA    RESERVED
RESERVFFCB     0xFFCB    RESERVED
RESERVFFCC     0xFFCC    RESERVED
RESERVFFCD     0xFFCD    RESERVED
RESERVFFCE     0xFFCE    RESERVED
RESERVFFCF     0xFFCF    RESERVED
RESERVFFD0     0xFFD0    RESERVED
RESERVFFD1     0xFFD1    RESERVED


.68HC711PH8
; http://
; MC68HC11PH8.pdf

; RAM=2K
; ROM=0
; EPROM=48K
; EEPROM=768


; MEMORY MAP
area DATA FSR        0x0000:0x0080
area DATA RAM        0x0080:0x0880
area BSS  RESERVED   0x0880:0x0D00
area DATA EEPROM     0x0D00:0x1000
area BSS  RESERVED   0x1000:0x4000
area CODE EPROM      0x4000:0xFFC0
area DATA USER_VEC   0xFFC0:0x1000


; Interrupt and reset vector assignments
interrupt __RESET     0xFFFE   Processor reset
interrupt CME         0xFFFC   Clock Monitor Fail
interrupt NOCOP       0xFFFA   COP Failure
interrupt OPC         0xFFF8   Illegal Opcode Trap
interrupt SOFT        0xFFF6   Software Interrupt
interrupt XIRQ        0xFFF4   XIRQ Pin
interrupt IRQ         0xFFF2   IRQ
interrupt RTII        0xFFF0   Real Time Interrupt
interrupt IC1I        0xFFEE   Timer Input Capture 1
interrupt IC2I        0xFFEC   Timer Input Capture 2
interrupt IC3I        0xFFEA   Timer Input Capture 3
interrupt OC1I        0xFFE8   Timer Output Compare 1
interrupt OC2I        0xFFE6   Timer Output Compare 2
interrupt OC3I        0xFFE4   Timer Output Compare 3
interrupt OC4I        0xFFE2   Timer Output Compare 4
interrupt I4_I5       0xFFE0   Timer Input Capture 4 / Output Compare 5
interrupt TOI         0xFFDE   Timer Overflow
interrupt PAOVI       0xFFDC   Pulse Accumulator Overflow
interrupt PAII        0xFFDA   Pulse Accumulator Input Edge
interrupt SPIE        0xFFD8   SPI1 Serial Transfer Complete
interrupt SCI1        0xFFD6   SCI1
interrupt SPI2E       0xFFD4   SPI2 Serial Transfer Complete
interrupt SCI12       0xFFD2   SCI2
interrupt T8A_B_C_I   0xFFD0   8-bit modulus timer A/B/C underflow
interrupt IEH         0xFFCE   Wired-OR port H


; INPUT/ OUTPUT PORTS
PORTA         0x0000  Port A data
PORTA.PA7      7   Port A Data Bit 7
PORTA.PA6      6   Port A Data Bit 6
PORTA.PA5      5   Port A Data Bit 5
PORTA.PA4      4   Port A Data Bit 4
PORTA.PA3      3   Port A Data Bit 3
PORTA.PA2      2   Port A Data Bit 2
PORTA.PA1      1   Port A Data Bit 1
PORTA.PA0      0   Port A Data Bit 0
DDRA          0x0001  Data direction A
DDRA.DDA7      7   Data Direction for Port A Bit 7
DDRA.DDA6      6   Data Direction for Port A Bit 6
DDRA.DDA5      5   Data Direction for Port A Bit 5
DDRA.DDA4      4   Data Direction for Port A Bit 4
DDRA.DDA3      3   Data Direction for Port A Bit 3
DDRA.DDA2      2   Data Direction for Port A Bit 2
DDRA.DDA1      1   Data Direction for Port A Bit 1
DDRA.DDA0      0   Data Direction for Port A Bit 0
DDRB          0x0002  Data direction B
DDRB.DDB7      7   Data Direction for Port B Bit 7
DDRB.DDB6      6   Data Direction for Port B Bit 6
DDRB.DDB5      5   Data Direction for Port B Bit 5
DDRB.DDB4      4   Data Direction for Port B Bit 4
DDRB.DDB3      3   Data Direction for Port B Bit 3
DDRB.DDB2      2   Data Direction for Port B Bit 2
DDRB.DDB1      1   Data Direction for Port B Bit 1
DDRB.DDB0      0   Data Direction for Port B Bit 0
DDRF          0x0003  Data direction F
DDRF.DDF7      7   Data Direction for Port F Bit 7
DDRF.DDF6      6   Data Direction for Port F Bit 6
DDRF.DDF5      5   Data Direction for Port F Bit 5
DDRF.DDF4      4   Data Direction for Port F Bit 4
DDRF.DDF3      3   Data Direction for Port F Bit 3
DDRF.DDF2      2   Data Direction for Port F Bit 2
DDRF.DDF1      1   Data Direction for Port F Bit 1
DDRF.DDF0      0   Data Direction for Port F Bit 0
PORTB         0x0004  Port B data
PORTB.PB7      7   Port B Data Bit 7
PORTB.PB6      6   Port B Data Bit 6
PORTB.PB5      5   Port B Data Bit 5
PORTB.PB4      4   Port B Data Bit 4
PORTB.PB3      3   Port B Data Bit 3
PORTB.PB2      2   Port B Data Bit 2
PORTB.PB1      1   Port B Data Bit 1
PORTB.PB0      0   Port B Data Bit 0
PORTF         0x0005  Port F data
PORTF.PF7      7   Port F Data Bit 7
PORTF.PF6      6   Port F Data Bit 6
PORTF.PF5      5   Port F Data Bit 5
PORTF.PF4      4   Port F Data Bit 4
PORTF.PF3      3   Port F Data Bit 3
PORTF.PF2      2   Port F Data Bit 2
PORTF.PF1      1   Port F Data Bit 1
PORTF.PF0      0   Port F Data Bit 0
PORTC         0x0006  Port C data
PORTC.PC7      7   Port C Data Bit 7
PORTC.PC6      6   Port C Data Bit 6
PORTC.PC5      5   Port C Data Bit 5
PORTC.PC4      4   Port C Data Bit 4
PORTC.PC3      3   Port C Data Bit 3
PORTC.PC2      2   Port C Data Bit 2
PORTC.PC1      1   Port C Data Bit 1
PORTC.PC0      0   Port C Data Bit 0
DDRC          0x0007  Data direction C
DDRC.DDC7      7   Data Direction for Port C Bit 7
DDRC.DDC6      6   Data Direction for Port C Bit 6
DDRC.DDC5      5   Data Direction for Port C Bit 5
DDRC.DDC4      4   Data Direction for Port C Bit 4
DDRC.DDC3      3   Data Direction for Port C Bit 3
DDRC.DDC2      2   Data Direction for Port C Bit 2
DDRC.DDC1      1   Data Direction for Port C Bit 1
DDRC.DDC0      0   Data Direction for Port C Bit 0
PORTD         0x0008  Port D data
PORTD.PD5      5   Port D Data Bit 5
PORTD.PD4      4   Port D Data Bit 4
PORTD.PD3      3   Port D Data Bit 3
PORTD.PD2      2   Port D Data Bit 2
PORTD.PD1      1   Port D Data Bit 1
PORTD.PD0      0   Port D Data Bit 0
DDRD          0x0009  Data direction D
DDRD.DDD5      5   Data Direction for Port D Bit 5
DDRD.DDD4      4   Data Direction for Port D Bit 4
DDRD.DDD3      3   Data Direction for Port D Bit 3
DDRD.DDD2      2   Data Direction for Port D Bit 2
DDRD.DDD1      1   Data Direction for Port D Bit 1
DDRD.DDD0      0   Data Direction for Port D Bit 0
PORTE         0x000A  Port E data
PORTE.PE7      7   Port E Data Bit 7
PORTE.PE6      6   Port E Data Bit 6
PORTE.PE5      5   Port E Data Bit 5
PORTE.PE4      4   Port E Data Bit 4
PORTE.PE3      3   Port E Data Bit 3
PORTE.PE2      2   Port E Data Bit 2
PORTE.PE1      1   Port E Data Bit 1
PORTE.PE0      0   Port E Data Bit 0
CFORC         0x000B  Timer compare force
CFORC.FOC1     7   Force output compares 1
CFORC.FOC2     6   Force output compares 2
CFORC.FOC3     5   Force output compares 3
CFORC.FOC4     4   Force output compares 4
CFORC.FOC5     3   Force output compares 5
OC1M          0x000C  Output compare 1 mask
OC1M.OC1M7     7   Output compare masks for OC1 bit 7
OC1M.OC1M6     6   Output compare masks for OC1 bit 6
OC1M.OC1M5     5   Output compare masks for OC1 bit 5
OC1M.OC1M4     4   Output compare masks for OC1 bit 4
OC1M.OC1M3     3   Output compare masks for OC1 bit 3
OC1D          0x000D  Output compare 1 data
OC1D.OC1D7     7   Output compare data for OC1 bit 7
OC1D.OC1D6     6   Output compare data for OC1 bit 6
OC1D.OC1D5     5   Output compare data for OC1 bit 5
OC1D.OC1D4     4   Output compare data for OC1 bit 4
OC1D.OC1D3     3   Output compare data for OC1 bit 3
TCNTH         0x000E  Timer count high
TCNTL         0x000F  Timer count low
TIC1H         0x0010  Timer input capture 1 high
TIC1L         0x0011  Timer input capture 1 low 
TIC2H         0x0012  Timer input capture 2 high
TIC2L         0x0013  Timer input capture 2 low 
TIC3H         0x0014  Timer input capture 3 high
TIC3L         0x0015  Timer input capture 3 low 
TOC1H         0x0016  Timer output compare 1 high
TOC1L         0x0017  Timer output compare 1 low 
TOC2H         0x0018  Timer output compare 2 high
TOC2L         0x0019  Timer output compare 2 low 
TOC3H         0x001A  Timer output compare 3 high
TOC3L         0x001B  Timer output compare 3 low 
TOC4H         0x001C  Timer output compare 4 high
TOC4L         0x001D  Timer output compare 4 low 
TI4_O5H       0x001E  Capture 4_compare 5  high
TI4_O5L       0x001F  Capture 4_compare 5  low 
TCTL1         0x0020  Timer control 1
TCTL1.OM2      7   Output mode 2 
TCTL1.OL2      6   Output level 2
TCTL1.OM3      5   Output mode 3 
TCTL1.OL3      4   Output level 3
TCTL1.OM4      3   Output mode 4 
TCTL1.OL4      2   Output level 4
TCTL1.OM5      1   Output mode 5 
TCTL1.OL5      0   Output level 5
TCTL2         0x0021  Timer control 2
TCTL2.EDG4B    7   Input capture edge control 4B
TCTL2.EDG4A    6   Input capture edge control 4A
TCTL2.EDG1B    5   Input capture edge control 1B
TCTL2.EDG1A    4   Input capture edge control 1A
TCTL2.EDG2B    3   Input capture edge control 2B
TCTL2.EDG2A    2   Input capture edge control 2A
TCTL2.EDG3B    1   Input capture edge control 3B
TCTL2.EDG3A    0   Input capture edge control 3A
TMSK1         0x0022  Timer interrupt mask 1
TMSK1.OC1I     7   Output compare 1 interrupt enable                
TMSK1.OC2I     6   Output compare 2 interrupt enable                
TMSK1.OC3I     5   Output compare 3 interrupt enable                
TMSK1.OC4I     4   Output compare 4 interrupt enable                
TMSK1.I4_O5I   3   Input capture 4 / output compare 5 interrupt enable
TMSK1.IC1I     2   Input capture 1 interrupt enable                 
TMSK1.IC2I     1   Input capture 2 interrupt enable                 
TMSK1.IC3I     0   Input capture 3 interrupt enable                 
TFLG1         0x0023  Timer interrupt flag 1
TFLG1.OC1F     7   Output compare 1 flag
TFLG1.OC2F     6   Output compare 2 flag
TFLG1.OC3F     5   Output compare 3 flag
TFLG1.OC4F     4   Output compare 4 flag
TFLG1.I4_O5F   3   Input capture 4/output compare 5 flag
TFLG1.IC1F     2   Input capture 1 flag
TFLG1.IC2F     1   Input capture 2 flag
TFLG1.IC3F     0   Input capture 3 flag
TMSK2         0x0024  Timer interrupt mask 2
TMSK2.TOI      7   Timer overflow interrupt enable            
TMSK2.RTII     6   Real-time interrupt enable                 
TMSK2.PAOVI    5   Pulse accumulator overflow interrupt enable
TMSK2.PAII     4   Pulse accumulator interrupt enable         
TMSK2.PR1      1   Timer prescaler select 1                   
TMSK2.PR0      0   Timer prescaler select 0                   
TFLG2         0x0025  Timer interrupt flag 2
TFLG2.TOF      7   Timer overflow interrupt flag
TFLG2.RTIF     6   Real time interrupt flag
TFLG2.PAOVF    5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF     4   Pulse accumulator input edge interrupt flag
PACTL         0x0026  Pulse accumulator control
PACTL.PAEN     6   Pulse accumulator system enable
PACTL.PAMOD    5   Pulse accumulator mode
PACTL.PEDGE    4   Pulse accumulator edge control
PACTL.I4_O5    2   Input capture 4/output compare
PACTL.RTR1     1   RTI interrupt rate select 1
PACTL.RTR0     0   RTI interrupt rate select 0
PACNT         0x0027  Pulse accumulator count
SPCR          0x0028  SPI control
SPCR.SPIE      7   Serial peripheral interrupt enable
SPCR.SPE       6   Serial peripheral system enable   
SPCR.DWOM      5   Port D wired-OR mode              
SPCR.MSTR      4   Master mode select                
SPCR.CPOL      3   Clock polarity                    
SPCR.CPHA      2   Clock phase                       
SPCR.SPR1      1   SPI clock rate selects 1          
SPCR.SPR0      0   SPI clock rate selects 0          
SPSR          0x0029  SPI status
SPSR.SPIF      7   SPI interrupt complete flag
SPSR.WCOL      6   Write collision
SPSR.MODF      4   Mode fault
SPDR          0x002A  SPI data
EPROG         0x002B  EPROM programming
EPROG.MBE      7   Multiple byte program enable
EPROG.ELAT     5   EPROM latch control
EPROG.EXCOL    4   Select extra columns
EPROG.EXROW    3   Select extra rows
EPROG.EPGM     0   EPROM program command
PPAR          0x002C  Port pull-up assignment
PPAR.HWOIF     4   Port H wired-OR interrupt flag
PPAR.HPPUE     3   Port H pin pull-up enable
PPAR.GPPUE     2   Port G pin pull-up enable
PPAR.FPPUE     1   Port F pin pull-up enable
PPAR.BPPUE     0   Port B pin pull-up enable
LCDR          0x002D  LCD control and data
LCDR.LCD7      7   LCD segment data 7
LCDR.LCD6      6   LCD segment data 6
LCDR.LCD5      5   LCD segment data 5
LCDR.LCD4      4   LCD segment data 4
LCDR.LCDCK     1   LCD frequency clock select
LCDR.LCDE      0   LCD function enable
PLLCR         0x002E  PLL control
PLLCR.PLLON    7   PLL on
PLLCR.BCS      6   Bus clock select
PLLCR.AUTO     5   Automatic bandwidth control
PLLCR.BWC      4   Bandwidth control
PLLCR.VCOT     3   VCO test
PLLCR.MCS      2   Module clock select
PLLCR.T16EN    1   16-bit timer clock enable
PLLCR.WEN      0   WAIT enable
SYNR          0x002F  Synthesizer program
SYNR.SYNX1     7
SYNR.SYNX0     6
SYNR.SYNY5     5
SYNR.SYNY4     4
SYNR.SYNY3     3
SYNR.SYNY2     2
SYNR.SYNY1     1
SYNR.SYNY0     0
ADCTL         0x0030  A/D control & status
ADCTL.CCF      7   Conversions complete flag
ADCTL.SCAN     5   Continuous scan control
ADCTL.MULT     4   Multiple-channel/single-channel control
ADCTL.CD       3   Channel selects D
ADCTL.CC       2   Channel selects C
ADCTL.CB       1   Channel selects B
ADCTL.CA       0   Channel selects A
ADR1          0x0031  A/D result 1
ADR2          0x0032  A/D result 2
ADR3          0x0033  A/D result 3
ADR4          0x0034  A/D result 4
BPROT         0x0035  Block protect
BPROT.BULKP    7   Bulk erase of EEPROM protect
BPROT.BPRT4    5   Block protect bit for top 256 bytes of EEPROM
BPROT.PTCON    4   Protect for CONFIG register
BPROT.BPRT3    3   Block protect bit 3 for EEPROM
BPROT.BPRT2    2   Block protect bit 2 for EEPROM
BPROT.BPRT1    1   Block protect bit 1 for EEPROM
BPROT.BPRT0    0   Block protect bit 0 for EEPROM
RESERVED36    0x0036  RESERVED36
INIT2         0x0037  EEPROM mapping
INIT2.EE3      7   EEPROM map position 3
INIT2.EE2      6   EEPROM map position 2
INIT2.EE1      5   EEPROM map position 1
INIT2.EE0      4   EEPROM map position 0
INIT2.STRX     3   Stretch extended
INIT2.M2DL1    1   MI BUS delay select 1
INIT2.M2DL0    0   MI BUS delay select 0
OPT2          0x0038  System config. options 2 
OPT2.LIRDV     7   LIR driven
OPT2.CWOM      6   Port C wired-OR mode
OPT2.STRCH     5   Stretch external accesses
OPT2.IRVNE     4   Internal read visibility/not E
OPT2.LSBF      3   LSB-first enable
OPT2.SPR2      2   SPI clock rate select
OPT2.EXT4X     1   4XLCK or EXTAL clock output select
OPT2.DISE      0   E clock output disable
OPTION        0x0039  System config. options 1
OPTION.ADPU    7   A/D power-up
OPTION.CSEL    6   Clock select
OPTION.IRQE    5   Configure IRQ for falling edge sensitive operation
OPTION.DLY     4   Enable oscillator start-up delay
OPTION.CME     3   Clock monitor enable
OPTION.FCME    2   Force clock monitor enable
OPTION.CR1     1   COP timer rate select bit 1
OPTION.CR0     0   COP timer rate select bit 0
COPRST        0x003A  COP timer arm_reset
PPROG         0x003B  EEPROM programming
PPROG.ODD      7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN     6   Program even rows in half of EEPROM (Test)
PPROG.BYTE     4   EEPROM byte erase mode
PPROG.ROW      3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE    2   Erase/normal control for EEPROM
PPROG.EELAT    1   EEPROM latch control
PPROG.EEPGM    0   EEPROM program command
HPRIO         0x003C  Highest priority interrupt
HPRIO.RBOOT    7   Read bootstrap ROM
HPRIO.SMOD     6   Special mode select
HPRIO.MDA      5   Mode select A
HPRIO.PSEL4    4   Priority select bit 4
HPRIO.PSEL3    3   Priority select bit 3
HPRIO.PSEL2    2   Priority select bit 2
HPRIO.PSEL1    1   Priority select bit 1
HPRIO.PSEL0    0   Priority select bit 0
INIT          0x003D  RAM & I_O mapping
INIT.RAM3      7   RAM map position 3
INIT.RAM2      6   RAM map position 2
INIT.RAM1      5   RAM map position 1
INIT.RAM0      4   RAM map position 0
INIT.REG3      3   128-byte register block position 3
INIT.REG2      2   128-byte register block position 2
INIT.REG1      1   128-byte register block position 1
INIT.REG0      0   128-byte register block position 0
TEST1         0x003E  Factory test
TEST1.TILOP    7   Test Illegal Opcode
TEST1.PLTST    6
TEST1.OCCR     5   Output Condition Code Register Status to Timer Port
TEST1.CBYP     4   Timer Counter Divider Chain By-pass
TEST1.DISR     3   Disable Resets from COP and Clock Monitor
TEST1.FCM      2   Force Clock Monitor Failure
TEST1.FCOP     1   Force COP Watchdog Failure
TEST1.MIDLY    0
CONFIG        0x003F  Configuration control
CONFIG.ROMAD   7   ROM mapping control
CONFIG.FREEZ   6   Address bus freeze in expanded user mode
CONFIG.CLK4X   5   4X clock enable
CONFIG.PAREN   4   Pull-up assignment register enable
CONFIG.NOSEC   3   EEPROM security disabled
CONFIG.NOCOP   2   COP system disable
CONFIG.ROMON   1   ROM enable
CONFIG.EEON    0   EEPROM enable
RESERVED40    0x0040  RESERVED40
RESERVED41    0x0041  RESERVED41
RESERVED42    0x0042  RESERVED42
RESERVED43    0x0043  RESERVED43
RESERVED44    0x0044  RESERVED44
RESERVED45    0x0045  RESERVED45
RESERVED46    0x0046  RESERVED46
RESERVED47    0x0047  RESERVED47
RESERVED48    0x0048  RESERVED48
RESERVED49    0x0049  RESERVED49
RESERVED4A    0x004A  RESERVED4A
RESERVED4B    0x004B  RESERVED4B
SP2CR         0x004C  SPI2 control
SP2CR.SP2IE    7   Serial peripheral interrupt enable
SP2CR.SP2E     6   Serial peripheral system enable
SP2CR.GWOM     5   Port D wired-OR mode
SP2CR.MSTR2    4   Master mode select
SP2CR.CPOL2    3   Clock polarity
SP2CR.CPHA2    2   Clock phase
SP2CR.SP2R1    1   SPI clock rate selects 1
SP2CR.SP2R0    0   SPI clock rate selects 0
SP2SR         0x004D  SPI2 status
SP2SR.SP2IF    7   SPI interrupt complete flag
SP2SR.WCOL2    6   Write collision
SP2SR.MODF2    4   Mode fault
SP2DR         0x004E  SPI2 data
SP2OPT        0x004F  SPI2 control options
SP2OPT.LSBF2   3   LSB-first enable
SP2OPT.SP2R2   2   SPI clock rate select
S2BDH         0x0050  SCI2_MI baud high
S2BDH.B2TST    7   Baud register test (Test mode only)
S2BDH.B2SPL    6   Baud rate counter split (Test mode only)
S2BDH.B2RST    5   Baud rate reset (Test mode only)
S2BDH.S2B12    4   SCI baud rate selects 12
S2BDH.S2B11    3   SCI baud rate selects 11
S2BDH.S2B10    2   SCI baud rate selects 10
S2BDH.S2B9     1   SCI baud rate selects 9 
S2BDH.S2B8     0   SCI baud rate selects 8 
S2BDL         0x0051  SCI2_MI baud low
S2BDL.S2B7     7   SCI baud rate selects 7
S2BDL.S2B6     6   SCI baud rate selects 6
S2BDL.S2B5     5   SCI baud rate selects 5
S2BDL.S2B4     4   SCI baud rate selects 4
S2BDL.S2B3     3   SCI baud rate selects 3
S2BDL.S2B2     2   SCI baud rate selects 2
S2BDL.S2B1     1   SCI baud rate selects 1
S2BDL.S2B0     0   SCI baud rate selects 0
S2CR1         0x0052  SCI2_MI control 1
S2CR1.LOPS2    7   SCI loop mode enable
S2CR1.WOMS2    6   Wired-OR mode for SCI pins (PG1, PG0)
S2CR1.MIE2     5   Motorola interface bus enable 2
S2CR1.M2       4   Mode (select character format)
S2CR1.WAKE2    3   Wake-up by address mark/idle
S2CR1.ILT2     2   Idle line type
S2CR1.PE2      1   Parity enable
S2CR1.PT2      0   Parity type
S2CR2         0x0053  SCI2_MI control 2
S2CR2.TIE2     7   Transmit interrupt enable
S2CR2.TCIE2    6   Transmit complete interrupt enable
S2CR2.RIE2     5   Receiver interrupt enable
S2CR2.ILIE2    4   Idle line interrupt enable
S2CR2.TE2      3   Transmitter enable
S2CR2.RE2      2   Receiver enable
S2CR2.RWU2     1   Receiver wake-up control
S2CR2.SBK2     0   Send break
S2SR1         0x0054  SCI2_MI status 1
S2SR1.TDRE2    7   Transmit data register empty flag
S2SR1.TC2      6   Transmit complete flag
S2SR1.RDRF2    5   Receive data register full flag
S2SR1.IDLE2    4   Idle line detected flag
S2SR1.OR2      3   Overrun error flag
S2SR1.NF2      2   Noise error flag
S2SR1.FE2      1   Framing error
S2SR1.PF2      0   Parity error flag
S2SR2         0x0055  SCI2_MI status 2
S2SR2.RAF2     0   Receiver active flag (read only)
S2DRH         0x0056  SCI2_MI data high
S2DRH.R8B      7   Receiver bit 8
S2DRH.T8B      6   Transmitter bit 8
S2DRL         0x0057  SCI2_MI data low
S2DRL.R7T7B    7   Receiver/transmitter data bit 7
S2DRL.R6T6B    6   Receiver/transmitter data bit 6
S2DRL.R5T5B    5   Receiver/transmitter data bit 5
S2DRL.R4T4B    4   Receiver/transmitter data bit 4
S2DRL.R3T3B    3   Receiver/transmitter data bit 3
S2DRL.R2T2B    2   Receiver/transmitter data bit 2
S2DRL.R1T1B    1   Receiver/transmitter data bit 1
S2DRL.R0T0B    0   Receiver/transmitter data bit 0
RESERVED58    0x0058  RESERVED58
T8ADR         0x0059  8-bit modulus timer A data
T8BDR         0x005A  8-bit modulus timer B data
T8CDR         0x005B  8-bit modulus timer C data
RESERVED5C    0x005C  RESERVED5C
T8ACR         0x005D  8-bit modulus timer A control
T8ACR.T8AI     7   8-bit timer A interrupt enable
T8ACR.T8AF     6   8-bit timer A underflow flag
T8ACR.CSA2     2   8-bit timer A clock rate 2
T8ACR.CSA1     1   8-bit timer A clock rate 1
T8ACR.CSA0     0   8-bit timer A clock rate 0
T8BCR         0x005E  8-bit modulus timer B control
T8BCR.T8BI     7   8-bit timer B interrupt enable
T8BCR.T8BF     6   8-bit timer B underflow flag
T8BCR.PRB      3   8-bit timer B preset
T8BCR.CSB2     2   8-bit timer B clock rate 2
T8BCR.CSB1     1   8-bit timer B clock rate 1
T8BCR.CSB0     0   8-bit timer B clock rate 0
T8CCR         0x005F  8-bit modulus timer C control
T8CCR.T8CI     7   bit timer C interrupt enable
T8CCR.T8CF     6   8-bit timer C underflow flag
T8CCR.PRC      3   8-bit timer C preset
T8CCR.CSC2     2   8-bit timer C clock rate 2
T8CCR.CSC1     1   8-bit timer C clock rate 1
T8CCR.CSC0     0   8-bit timer C clock rate 0
PWCLK         0x0060  Pulse width clock select
PWCLK.CON34    7   Concatenate channels 3 and 4
PWCLK.CON12    6   Concatenate channels 1 and 2
PWCLK.PCKA2    5   Prescaler for clock A 2
PWCLK.PCKA1    4   Prescaler for clock A 1
PWCLK.PCKB3    2   Prescaler for clock B 3
PWCLK.PCKB2    1   Prescaler for clock B 2
PWCLK.PCKB1    0   Prescaler for clock B 1
PWPOL         0x0061  Pulse width polarity select
PWPOL.PCLK4    7   Pulse width channel 4 clock select
PWPOL.PCLK3    6   Pulse width channel 3 clock select
PWPOL.PCLK2    5   Pulse width channel 2 clock select
PWPOL.PCLK1    4   Pulse width channel 1 clock select
PWPOL.PPOL4    3   Pulse width channel 4 polarity
PWPOL.PPOL3    2   Pulse width channel 3 polarity
PWPOL.PPOL2    1   Pulse width channel 2 polarity
PWPOL.PPOL1    0   Pulse width channel 1 polarity
PWSCAL        0x0062  Pulse width scale
PWEN          0x0063  Pulse width enable
PWEN.TPWSL     7   PWM scaled clock test bit (Test mode only)
PWEN.DISCP     6   Disable compare scaled E clock (Test mode only)
PWEN.PWEN4     3   Pulse width channel 4
PWEN.PWEN3     2   Pulse width channel 3
PWEN.PWEN2     1   Pulse width channel 2
PWEN.PWEN1     0   Pulse width channel 1
PWCNT1        0x0064  Pulse width count 1
PWCNT2        0x0065  Pulse width count 2
PWCNT3        0x0066  Pulse width count 3
PWCNT4        0x0067  Pulse width count 4
PWPER1        0x0068  Pulse width period 1
PWPER2        0x0069  Pulse width period 2
PWPER3        0x006A  Pulse width period 3
PWPER4        0x006B  Pulse width period 4
PWDTY1        0x006C  Pulse width duty 1
PWDTY2        0x006D  Pulse width duty 2
PWDTY3        0x006E  Pulse width duty 3
PWDTY4        0x006F  Pulse width duty 4
SCBDH         0x0070  SCI1 baud rate high
SCBDH.BTST     7   Baud register test (Test mode only)     
SCBDH.BSPL     6   Baud rate counter split (Test mode only)
SCBDH.BRST     5   Baud rate reset (Test mode only)        
SCBDH.SBR12    4   SCI baud rate selects 12                
SCBDH.SBR11    3   SCI baud rate selects 11                
SCBDH.SBR10    2   SCI baud rate selects 10                
SCBDH.SBR9     1   SCI baud rate selects 9                 
SCBDH.SBR8     0   SCI baud rate selects 8                 
SCBDL         0x0071  SCI1 baud rate low
SCBDL.SBR7     7   SCI baud rate selects 7
SCBDL.SBR6     6   SCI baud rate selects 6
SCBDL.SBR5     5   SCI baud rate selects 5
SCBDL.SBR4     4   SCI baud rate selects 4
SCBDL.SBR3     3   SCI baud rate selects 3
SCBDL.SBR2     2   SCI baud rate selects 2
SCBDL.SBR1     1   SCI baud rate selects 1
SCBDL.SBR0     0   SCI baud rate selects 0
SCCR1         0x0072  SCCR1 SCI1 control 1
SCCR1.LOOPS    7   SCI loop mode enable
SCCR1.WOMS     6   Wired-OR mode for SCI pins (PG1, PG0)
SCCR1.M        4   Mode (select character format)
SCCR1.WAKE     3   Wake-up by address mark/idle
SCCR1.ILT      2   Idle line type
SCCR1.PE       1   Parity enable
SCCR1.PT       0   Parity type
SCCR2         0x0073  SCI1 control 2
SCCR2.TIE      7   Transmit interrupt enable
SCCR2.TCIE     6   Transmit complete interrupt enable
SCCR2.RIE      5   Receiver interrupt enable
SCCR2.ILIE     4   Idle line interrupt enable
SCCR2.TE       3   Transmitter enable
SCCR2.RE       2   Receiver enable
SCCR2.RWU      1   Receiver wake-up control
SCCR2.SBK      0   Send break
SCSR1         0x0074  SCI1 status 1
SCSR1.TDRE     7   Transmit data register empty flag
SCSR1.TC       6   Transmit complete flag
SCSR1.RDRF     5   Receive data register full flag
SCSR1.IDLE     4   Idle line detected flag
SCSR1.OR       3   Overrun error flag
SCSR1.NF       2   Noise error flag
SCSR1.FE       1   Framing error
SCSR1.PF       0   Parity error flag
SCSR2         0x0075  SCI1 status 2
SCSR2.RAF      0   Receiver active flag (read only)
SCDRH         0x0076  SCI1 data high
SCDRH.R8       7   Receiver bit 8   
SCDRH.T8       6   Transmitter bit 8
SCDRL         0x0077  SCI1 data low
SCDRL.R7T7     7   Receiver/transmitter data bit 7
SCDRL.R6T6     6   Receiver/transmitter data bit 6
SCDRL.R5T5     5   Receiver/transmitter data bit 5
SCDRL.R4T4     4   Receiver/transmitter data bit 4
SCDRL.R3T3     3   Receiver/transmitter data bit 3
SCDRL.R2T2     2   Receiver/transmitter data bit 2
SCDRL.R1T1     1   Receiver/transmitter data bit 1
SCDRL.R0T0     0   Receiver/transmitter data bit 0
RESERVED78    0x0078  RESERVED78
RESERVED79    0x0079  RESERVED79
RESERVED7A    0x007A  RESERVED7A
WOIEH         0x007B  Wired-OR interrupt enable
WOIEH.IEH7     7   Port H pin 7 wired-OR interrupt enable
WOIEH.IEH6     6   Port H pin 6 wired-OR interrupt enable
WOIEH.IEH5     5   Port H pin 5 wired-OR interrupt enable
WOIEH.IEH4     4   Port H pin 4 wired-OR interrupt enable
WOIEH.IEH3     3   Port H pin 3 wired-OR interrupt enable
WOIEH.IEH2     2   Port H pin 2 wired-OR interrupt enable
WOIEH.IEH1     1   Port H pin 1 wired-OR interrupt enable
WOIEH.IEH0     0   Port H pin 0 wired-OR interrupt enable
PORTH         0x007C  Port H data
PORTH.PH7      7   Port H Data Bit 7
PORTH.PH6      6   Port H Data Bit 6
PORTH.PH5      5   Port H Data Bit 5
PORTH.PH4      4   Port H Data Bit 4
PORTH.PH3      3   Port H Data Bit 3
PORTH.PH2      2   Port H Data Bit 2
PORTH.PH1      1   Port H Data Bit 1
PORTH.PH0      0   Port H Data Bit 0
DDRH          0x007D  Data direction H
DDRH.DDH7      7   Data Direction for Port H Bit 7
DDRH.DDH6      6   Data Direction for Port H Bit 6
DDRH.DDH5      5   Data Direction for Port H Bit 5
DDRH.DDH4      4   Data Direction for Port H Bit 4
DDRH.DDH3      3   Data Direction for Port H Bit 3
DDRH.DDH2      2   Data Direction for Port H Bit 2
DDRH.DDH1      1   Data Direction for Port H Bit 1
DDRH.DDH0      0   Data Direction for Port H Bit 0
PORTG         0x007E  Port G data
PORTG.PG7      7   Port G Data Bit 7
PORTG.PG6      6   Port G Data Bit 6
PORTG.PG5      5   Port G Data Bit 5
PORTG.PG4      4   Port G Data Bit 4
PORTG.PG3      3   Port G Data Bit 3
PORTG.PG2      2   Port G Data Bit 2
PORTG.PG1      1   Port G Data Bit 1
PORTG.PG0      0   Port G Data Bit 0
DDRG          0x007F  Data direction G
DDRG.DDG7      7   Data Direction for Port G Bit 7
DDRG.DDG6      6   Data Direction for Port G Bit 6
DDRG.DDG5      5   Data Direction for Port G Bit 5
DDRG.DDG4      4   Data Direction for Port G Bit 4
DDRG.DDG3      3   Data Direction for Port G Bit 3
DDRG.DDG2      2   Data Direction for Port G Bit 2
DDRG.DDG1      1   Data Direction for Port G Bit 1
DDRG.DDG0      0   Data Direction for Port G Bit 0
RESERVFFC0    0xFFC0  RESERVED
RESERVFFC1    0xFFC1  RESERVED
RESERVFFC2    0xFFC2  RESERVED
RESERVFFC3    0xFFC3  RESERVED
RESERVFFC4    0xFFC4  RESERVED
RESERVFFC5    0xFFC5  RESERVED
RESERVFFC6    0xFFC6  RESERVED
RESERVFFC7    0xFFC7  RESERVED
RESERVFFC8    0xFFC8  RESERVED
RESERVFFC9    0xFFC9  RESERVED
RESERVFFCA    0xFFCA  RESERVED
RESERVFFCB    0xFFCB  RESERVED
RESERVFFCC    0xFFCC  RESERVED
RESERVFFCD    0xFFCD  RESERVED


.68HC811E2
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP
area DATA RAM          0x0000:0x0100
area BSS  RESERVED     0x0100:0x1000
area DATA FSR          0x1000:0x1040
area BSS  RESERVED     0x1040:0xF800
area DATA EEPROM       0xF800:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET   0xFFFE    Processor reset
interrupt CME       0xFFFC    Clock Monitor Fail
interrupt NOCOP     0xFFFA    COP Failure
interrupt OPC       0xFFF8    Illegal Opcode Trap
interrupt SOFT      0xFFF6    Software Interrupt
interrupt XIRQ      0xFFF4    XIRQ Pin
interrupt IRQ       0xFFF2    IRQ
interrupt RTII      0xFFF0    Real Time Interrupt
interrupt IC1I      0xFFEE    Timer Input Capture 1
interrupt IC2I      0xFFEC    Timer Input Capture 2
interrupt IC3I      0xFFEA    Timer Input Capture 3
interrupt OC1I      0xFFE8    Timer Output Compare 1
interrupt OC2I      0xFFE6    Timer Output Compare 2
interrupt OC3I      0xFFE4    Timer Output Compare 3
interrupt OC4I      0xFFE2    Timer Output Compare 4
interrupt I4_I5     0xFFE0    Timer Input Capture 4 / Output Compare 5
interrupt TOI       0xFFDE    Timer Overflow
interrupt PAOVI     0xFFDC    Pulse Accumulator Overflow
interrupt PAII      0xFFDA    Pulse Accumulator Input Edge
interrupt SPIE      0xFFD8    SPI Serial Transfer Complete
interrupt SCISS     0xFFD6    SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA            0x1000     Port A data
PORTA.PA7     	  7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
RESERV01         0x1001     RESERVED
PIOC             0x1002     Parallel I_O Control Register
PIOC.STAF         7   Strobe A Interrupt Status Flag
PIOC.STAI         6   Strobe A Interrupt Enable Mask Bit
PIOC.CWOM         5   Port C Wired-OR Mode Bit (affects all eight port C pins)
PIOC.HNDS         4   Handshake Mode Bit
PIOC.OIN          3   Output or Input Handshake Select Bit
PIOC.PLS          2   Pulsed/Interlocked Handshake Operation Bit
PIOC.EGA          1   Active Edge for Strobe A Bit
PIOC.INVB         0   Invert Strobe B Bit
PORTC            0x1003      Port C Data
PORTC.PC7         7   Port C Data Bit 7
PORTC.PC6         6   Port C Data Bit 6
PORTC.PC5         5   Port C Data Bit 5
PORTC.PC4         4   Port C Data Bit 4
PORTC.PC3         3   Port C Data Bit 3
PORTC.PC2         2   Port C Data Bit 2
PORTC.PC1         1   Port C Data Bit 1
PORTC.PC0         0   Port C Data Bit 0
PORTB            0x1004     Output Port B
PORTB.PB7         7   Port B Data Bit 7
PORTB.PB6         6   Port B Data Bit 6
PORTB.PB5         5   Port B Data Bit 5
PORTB.PB4         4   Port B Data Bit 4
PORTB.PB3         3   Port B Data Bit 3
PORTB.PB2         2   Port B Data Bit 2
PORTB.PB1         1   Port B Data Bit 1
PORTB.PB0         0   Port B Data Bit 0
PORTCL           0x1005     Alternate Latched Port C
PORTCL.PCL7       7
PORTCL.PCL6       6
PORTCL.PCL5       5
PORTCL.PCL4       4
PORTCL.PCL3       3
PORTCL.PCL2       2
PORTCL.PCL1       1
PORTCL.PCL0       0
RESERV1006       0x1006     RESERVED06
DDRC             0x1007     Data Direction for Port C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x1008     Port D Data
PORTD.PD5         5   Port D Data Bit 5
PORTD.PD4         4   Port D Data Bit 4
PORTD.PD3         3   Port D Data Bit 3
PORTD.PD2         2   Port D Data Bit 2
PORTD.PD1         1   Port D Data Bit 1
PORTD.PD0         0   Port D Data Bit 0
DDRD             0x1009     Data Direction for Port D
DDRD.DDD5         5   Data Direction for Port D Bit 5
DDRD.DDD4         4   Data Direction for Port D Bit 4
DDRD.DDD3         3   Data Direction for Port D Bit 3
DDRD.DDD2         2   Data Direction for Port D Bit 2
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
PORTE            0x100A     Port E Data
PORTE.PE7         7   Port E Data Bit 7
PORTE.PE6         6   Port E Data Bit 6
PORTE.PE5         5   Port E Data Bit 5
PORTE.PE4         4   Port E Data Bit 4
PORTE.PE3         3   Port E Data Bit 3
PORTE.PE2         2   Port E Data Bit 2
PORTE.PE1         1   Port E Data Bit 1
PORTE.PE0         0   Port E Data Bit 0
CFORC            0x100B     Timer Compare Force Register
CFORC.FOC1        7   Force Output Comparison Bit 1
CFORC.FOC2        6   Force Output Comparison Bit 2
CFORC.FOC3        5   Force Output Comparison Bit 3
CFORC.FOC4        4   Force Output Comparison Bit 4
CFORC.FOC5        3   Force Output Comparison Bit 5
OC1M             0x100C     Output Compare 1 Mask Register
OC1M.OC1M7        7   Output Compare Masks 7
OC1M.OC1M6        6   Output Compare Masks 6
OC1M.OC1M5        5   Output Compare Masks 5
OC1M.OC1M4        4   Output Compare Masks 4
OC1M.OC1M3        3   Output Compare Masks 3
OC1D             0x100D     Output Compare 1 Data Register
OC1D.OC1D7        7
OC1D.OC1D6        6
OC1D.OC1D5        5
OC1D.OC1D4        4
OC1D.OC1D3        3
TCNTH            0x100E     Timer Counter Register
TCNTL            0x100F     Timer Counter Register
TIC1H            0x1010     Input Capture 1 Register
TIC1L            0x1011     Input Capture 1 Register
TIC2H            0x1012     Input Capture 2 Register
TIC2L            0x1013     Input Capture 2 Register
TIC3H            0x1014     Input Capture 3 Register
TIC3L            0x1015     Input Capture 3 Register
TOC1H            0x1016     Output Compare 1 Register
TOC1L            0x1017     Output Compare 1 Register
TOC2H            0x1018     Output Compare 2 Register
TOC2L            0x1019     Output Compare 2 Register
TOC3H            0x101A     Output Compare 3 Register
TOC3L            0x101B     Output Compare 3 Register
TOC4H            0x101C     Output Compare 4 Register
TOC4L            0x101D     Output Compare 4 Register
TCO5H            0x101E     Output Compare 5 Register
TCO5L            0x101F     Output Compare 5 Register
TCTL1            0x1020     Timer Control Register 1
TCTL1.OM2         7   Output Mode Bits 2
TCTL1.OL2         6   Output Level Bits 2
TCTL1.OM3         5   Output Mode Bits 3
TCTL1.OL3         4   Output Level Bits 3
TCTL1.OM4         3   Output Mode Bits 4
TCTL1.OL4         2   Output Level Bits 4
TCTL1.OM5         1   Output Mode Bits 5
TCTL1.OL5         0   Output Level Bits 5
TCTL2            0x1021     Timer Control Register 2
TCTL2.EDG4B       7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A       6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B       5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A       4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B       3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A       2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B       1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A       0   EDG3A  Input Capture Edge Control Bits
TMSK1            0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I        7   Output Compare 1 Interrupt Enable Bits
TMSK1.OC2I        6   Output Compare 2 Interrupt Enable Bits
TMSK1.OC3I        5   Output Compare 3 Interrupt Enable Bits
TMSK1.OC4I        4   Output Compare 4 Interrupt Enable Bits
TMSK1.I4_O5I      3   Input Capture 4/Output Compare 5 Interrupt Enable Bit
TMSK1.IC1I        2   Input Capture 1 Interrupt Enable Bits
TMSK1.IC2I        1   Input Capture 2 Interrupt Enable Bits
TMSK1.IC3I        0   Input Capture 3 Interrupt Enable Bits
TFLG1            0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F        7   Output Compare 1 Flag
TFLG1.OC2F        6   Output Compare 2 Flag
TFLG1.OC3F        5   Output Compare 3 Flag
TFLG1.OC4F        4   Output Compare 4 Flag
TFLG1.I4_O5F      3   Input Capture 4/Output Compare 5 Flag
TFLG1.IC1F        2   Input Capture 1 Flag
TFLG1.IC2F        1   Input Capture 2 Flag
TFLG1.IC3F        0   Input Capture 3 Flag
TMSK2            0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable Bit
TMSK2.RTII        6   Real-Time Interrupt Enable Bit
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable Bit
TMSK2.PAII        4   Pulse Accumulator Input Edge Interrupt Enable Bit
TMSK2.PR1         1   Timer Prescaler Select Bits 1
TMSK2.PR0         0   Timer Prescaler Select Bits 0
TFLG2            0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF         7   Timer Overflow Interrupt Flag
TFLG2.RTIF        6   Real-Time (Periodic) Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Interrupt Flag
PACTL            0x1026     Pulse Accumulator Control Register
PACTL.DDRA7       7   Data Direction for Port A Bit 7
PACTL.PAEN        6   Pulse Accumulator System Enable Bit
PACTL.PAMOD       5   Pulse Accumulator Mode Bit
PACTL.PEDGE       4   Pulse Accumulator Edge Control Bit
PACTL.DDRA3       3   Data Direction for Port A Bit 3
PACTL.I4_O5       2   Input Capture 4/Output Compare Bit
PACTL.RTR1        1   RTI Interrupt Rate Select Bits 1
PACTL.RTR0        0   RTI Interrupt Rate Select Bits 0
PACNT            0x1027     Pulse Accumulator Count Register
SPCR             0x1028     SPI Control Register
SPCR.SPIE         7   Serial Peripheral Interrupt Enable Bit
SPCR.SPE          6   Serial Peripheral System Enable Bit
SPCR.DWOM         5   Port D Wired-OR Mode Bit
SPCR.MSTR         4   Master Mode Select Bit
SPCR.CPOL         3   Clock Polarity Bit
SPCR.CPHA         2   Clock Phase Bit
SPCR.SPR1         1   SPI Clock Rate Select Bits 1
SPCR.SPR0         0   SPI Clock Rate Select Bits 0
SPSR             0x1029     SPI Status Register
SPSR.SPIF         7   SPI Interrupt Complete Flag
SPSR.WCOL         6   Write Collision Bit
SPSR.MODF         4   Mode Fault Bit
SPDR             0x102A     SPI Data Register
BAUD             0x102B     SCI Baud Rate Control 3
BAUD.TCLR         7   Clear Baud Rate Counter Bit (Test)
BAUD.SCP1         5   SCI Baud Rate Prescaler Select Bits 1
BAUD.SCP0         4   SCI Baud Rate Prescaler Select Bits 0
BAUD.RCKB         3   SCI Baud Rate Clock Check Bit (Test)
BAUD.SCR2         2   SCI Baud Rate Select Bits 2
BAUD.SCR1         1   SCI Baud Rate Select Bits 1
BAUD.SCR0         0   SCI Baud Rate Select Bits 0
SCCR1            0x102C     SCI Control Register 1
SCCR1.R8          7   Receive Data Bit 8
SCCR1.T8          6   Transmit Data Bit 8
SCCR1.M           4   Mode Bit (select character format)
SCCR1.WAKE        3   Wakeup by Address Mark/Idle Bit
SCCR2            0x102D     Serial Communications Control Register 2
SCCR2.TIE         7   Transmit Interrupt Enable Bit
SCCR2.TCIE        6   Transmit Complete Interrupt Enable Bit
SCCR2.RIE         5   Receiver Interrupt Enable Bit
SCCR2.ILIE        4   Idle-Line Interrupt Enable Bit
SCCR2.TE          3   Transmitter Enable Bit
SCCR2.RE          2   Receiver Enable Bit
SCCR2.RWU         1   Receiver Wakeup Control Bit
SCCR2.SBK         0   Send Break
SCSR             0x102E     Serial Communications Status Register
SCSR.TDRE         7   Transmit Data Register Empty Flag
SCSR.TC           6   Transmit Complete Flag
SCSR.RDRF         5   Receive Data Register Full Flag
SCSR.IDLE         4   Idle Line Detected Flag
SCSR.OR           3   Overrun Error Flag
SCSR.NF           2   Noise Error Flag
SCSR.FE           1   Framing Error Flag
SCDR             0x102F     SCI Data (Read RDR, Write TDR)
SCDR.R7T7         7
SCDR.R6T6         6
SCDR.R5T5         5
SCDR.R4T4         4
SCDR.R3T3         3
SCDR.R2T2         2
SCDR.R1T1         1
SCDR.R0T0         0
ADCTL            0x1030     A_D Control Register
ADCTL.CCF         7   Conversion Complete Flag
ADCTL.SCAN        5   Continuous Scan Control Bit
ADCTL.MULT        4   Multiple Channel/Single Channel Control Bit
ADCTL.CD          3   Channel Selects D Bits
ADCTL.CC          2   Channel Selects C Bits
ADCTL.CB          1   Channel Selects B Bits
ADCTL.CA          0   Channel Selects A Bits
ADR1             0x1031     A_D Result Register 1
ADR2             0x1032     A_D Result Register 2
ADR3             0x1033     A_D Result Register 3
ADR4             0x1034     A_D Result Register 4
BPROT            0x1035     Block Protect Register
BPROT.PTCON       4   Protect CONFIG Register Bit
BPROT.BPRT3       3   Block Protect Bits for EEPROM 3
BPROT.BPRT2       2   Block Protect Bits for EEPROM 2
BPROT.BPRT1       1   Block Protect Bits for EEPROM 1
BPROT.BPRT0       0   Block Protect Bits for EEPROM 0
RESERV1036       0x1036     RESERVED
RESERV1037       0x1037     RESERVED
RESERV1038       0x1038     RESERVED
OPTION           0x1039     System Configuration Options
OPTION.ADPU       7   Analog-to-Digital Converter Power-Up Bit
OPTION.CSEL       6   Clock Select Bit
OPTION.IRQE       5   Configure IRQ for Edge-Sensitive Only Operation Bit
OPTION.DLY        4   Enable Oscillator Startup Delay Bit
OPTION.CME        3   Clock Monitor Enable Bit
OPTION.CR1        1   COP Timer Rate Select Bits 1
OPTION.CR0        0   COP Timer Rate Select Bits 0
COPRST           0x103A     Arm_Reset COP Timer Circuitry
PPROG            0x103B     EEPROM Program Control Register
PPROG.ODD         7   Program Odd Rows in Half of EEPROM (Test) Bit
PPROG.EVEN        6   Program Even Rows in Half of EEPROM (Test) Bit
PPROG.BYTE        4   Byte/Other EEPROM Erase Mode Bit
PPROG.ROW         3   Row/All EEPROM Erase Mode Bit
PPROG.ERASE       2   Erase Mode Select Bit
PPROG.EELAT       1   EEPROM Latch Control Bit
PPROG.EEPGM       0   EPROM/OTPROM/EEPROM Programming
HPRIO            0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT       7   Read Bootstrap ROM Bit
HPRIO.SMOD        6   Special Mode Select
HPRIO.MDA         5   Mode Select A Bits
HPRIO.IRV         4   Internal Read Visibility (Not E) Bit
HPRIO.PSEL3       3   Priority Select Bits 3
HPRIO.PSEL2       2   Priority Select Bits 2
HPRIO.PSEL1       1   Priority Select Bits 1
HPRIO.PSEL0       0   Priority Select Bits 0
INIT             0x103D     RAM and I_O Mapping Register
INIT.RAM3         7   RAM Map Position Bits 3
INIT.RAM2         6   RAM Map Position Bits 2
INIT.RAM1         5   RAM Map Position Bits 1
INIT.RAM0         4   RAM Map Position Bits 0
INIT.REG3         3   64-Byte Register Block Position 3
INIT.REG2         2   64-Byte Register Block Position 2
INIT.REG1         1   64-Byte Register Block Position 1
INIT.REG0         0   64-Byte Register Block Position 0
RESERV3E         0x103E     RESERVED
CONFIG           0x103F     System Configuration Register
CONFIG.EE3        7   EEPROM Mapping Bit 3
CONFIG.EE2        6   EEPROM Mapping Bit 2
CONFIG.EE1        5   EEPROM Mapping Bit 1
CONFIG.EE0        4   EEPROM Mapping Bit 0
CONFIG.NOSEC      3   Security Disable Bit
CONFIG.NOCOP      2   COP System Disable Bit
CONFIG.ROMON      1   ROM/EPROM/OTPROM Enable Bit
CONFIG.EEON       0   EEPROM Enable Bit
RESERVFFC0       0xFFC0     RESERVED
RESERVFFC1       0xFFC1     RESERVED
RESERVFFC2       0xFFC2     RESERVED
RESERVFFC3       0xFFC3     RESERVED
RESERVFFC4       0xFFC4     RESERVED
RESERVFFC5       0xFFC5     RESERVED
RESERVFFC6       0xFFC6     RESERVED
RESERVFFC7       0xFFC7     RESERVED
RESERVFFC8       0xFFC8     RESERVED
RESERVFFC9       0xFFC9     RESERVED
RESERVFFCA       0xFFCA     RESERVED
RESERVFFCB       0xFFCB     RESERVED
RESERVFFCC       0xFFCC     RESERVED
RESERVFFCD       0xFFCD     RESERVED
RESERVFFCE       0xFFCE     RESERVED
RESERVFFCF       0xFFCF     RESERVED
RESERVFFD0       0xFFD0     RESERVED
RESERVFFD1       0xFFD1     RESERVED
RESERVFFD2       0xFFD2     RESERVED
RESERVFFD3       0xFFD3     RESERVED
RESERVFFD4       0xFFD4     RESERVED
RESERVFFD5       0xFFD5     RESERVED


.68HC711EA9
; MC68HC11EA9TS/D  http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC11EA9TS.pdf
; ea9.pdf

; RAM=512
; ROM=0
; EPROM=12K
; EEPROM=512


; MEMORY MAP
area DATA RAM          0x0000:0x0200
area BSS  RESERVED     0x0200:0x1000
area DATA FSR          0x1000:0x1040
area BSS  RESERVED     0x1040:0xB600
area DATA EEPROM       0xB600:0xB800
area BSS  RESERVED     0xB800:0xD000
area DATA EPROM        0xD000:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SCISS             0xFFD6      SCI Serial System


; INPUT/ OUTPUT PORTS
PORTA            0x1000     Port A data
PORTA.PA7     	  7   Port A Data Bit 7
PORTA.PA6         6   Port A Data Bit 6
PORTA.PA5         5   Port A Data Bit 5
PORTA.PA4         4   Port A Data Bit 4
PORTA.PA3         3   Port A Data Bit 3
PORTA.PA2         2   Port A Data Bit 2
PORTA.PA1         1   Port A Data Bit 1
PORTA.PA0         0   Port A Data Bit 0
DDRA             0x1001     Data Direction Port A
DDRA.DDA7         7   Data Direction for Port A Bit 7
DDRA.DDA6         6   Data Direction for Port A Bit 6
DDRA.DDA5         5   Data Direction for Port A Bit 5
DDRA.DDA4         4   Data Direction for Port A Bit 4
DDRA.DDA3         3   Data Direction for Port A Bit 3
DDRA.DDA2         2   Data Direction for Port A Bit 2
DDRA.DDA1         1   Data Direction for Port A Bit 1
DDRA.DDA0         0   Data Direction for Port A Bit 0
PIOC             0x1002     Parallel I_O Control Register
PIOC.STAF         7   Strobe A Interrupt Status Flag
PIOC.STAI         6   Strobe A Interrupt Enable
PIOC.CWOM         5   Strobe A Interrupt Enable
PIOC.HNDS         4   Handshake Mode
PIOC.OIN          3   Output or Input Handshaking
PIOC.PLS          2   Pulse/Interlocked Handshake Operation
PIOC.EGA          1   Active Edge for Strobe A
PIOC.INVB         0   Invert Strobe B
PORTC            0x1003      Port C Data
PORTC.PC7         7   Port C Data Bit 7
PORTC.PC6         6   Port C Data Bit 6
PORTC.PC5         5   Port C Data Bit 5
PORTC.PC4         4   Port C Data Bit 4
PORTC.PC3         3   Port C Data Bit 3
PORTC.PC2         2   Port C Data Bit 2
PORTC.PC1         1   Port C Data Bit 1
PORTC.PC0         0   Port C Data Bit 0
PORTB            0x1004     Port B Data
PORTB.PB7         7   Port B Data Bit 7
PORTB.PB6         6   Port B Data Bit 6
PORTB.PB5         5   Port B Data Bit 5
PORTB.PB4         4   Port B Data Bit 4
PORTB.PB3         3   Port B Data Bit 3
PORTB.PB2         2   Port B Data Bit 2
PORTB.PB1         1   Port B Data Bit 1
PORTB.PB0         0   Port B Data Bit 0
PORTCL           0x1005     Alternate Latched Port C
PORTCL.PCL7       7
PORTCL.PCL6       6
PORTCL.PCL5       5
PORTCL.PCL4       4
PORTCL.PCL3       3
PORTCL.PCL2       2
PORTCL.PCL1       1
PORTCL.PCL0       0
DDRB             0x1006     Data Direction Port B
DDRB.DDB7         7   Data Direction for Port B Bit 7
DDRB.DDB6         6   Data Direction for Port B Bit 6
DDRB.DDB5         5   Data Direction for Port B Bit 5
DDRB.DDB4         4   Data Direction for Port B Bit 4
DDRB.DDB3         3   Data Direction for Port B Bit 3
DDRB.DDB2         2   Data Direction for Port B Bit 2
DDRB.DDB1         1   Data Direction for Port B Bit 1
DDRB.DDB0         0   Data Direction for Port B Bit 0
DDRC             0x1007     Data Direction for Port C
DDRC.DDC7         7   Data Direction for Port C Bit 7
DDRC.DDC6         6   Data Direction for Port C Bit 6
DDRC.DDC5         5   Data Direction for Port C Bit 5
DDRC.DDC4         4   Data Direction for Port C Bit 4
DDRC.DDC3         3   Data Direction for Port C Bit 3
DDRC.DDC2         2   Data Direction for Port C Bit 2
DDRC.DDC1         1   Data Direction for Port C Bit 1
DDRC.DDC0         0   Data Direction for Port C Bit 0
PORTD            0x1008     Port D Data
PORTD.XPIN        7   XIRQ Interrupt Pin Status Flag
PORTD.IPIN        6   IRQ Interrupt Pin Status Flag
PORTD.PD1         1   Port D Data Bit 1
PORTD.PD0         0   Port D Data Bit 0
DDRD             0x1009     Data Direction for Port D
DDRD.DISX         7   Disable XIRQ Pin Interrupts
DDRD.DISI         6   Disable IRQ Pin Interrupts
DDRD.DDD1         1   Data Direction for Port D Bit 1
DDRD.DDD0         0   Data Direction for Port D Bit 0
PORTE            0x100A     Port E Data
PORTE.PE7         7   Port E Data Bit 7
PORTE.PE6         6   Port E Data Bit 6
PORTE.PE5         5   Port E Data Bit 5
PORTE.PE4         4   Port E Data Bit 4
PORTE.PE3         3   Port E Data Bit 3
PORTE.PE2         2   Port E Data Bit 2
PORTE.PE1         1   Port E Data Bit 1
PORTE.PE0         0   Port E Data Bit 0
CFORC            0x100B     Compare Force Register
CFORC.FOC1        7   Force Output Compare 1
CFORC.FOC2        6   Force Output Compare 2
CFORC.FOC3        5   Force Output Compare 3
CFORC.FOC4        4   Force Output Compare 4
CFORC.FOC5        3   Force Output Compare 5
OC1M             0x100C     OC1 Action Mask Register
OC1M.OC1M7        7   Output Compare Masks 7
OC1M.OC1M6        6   Output Compare Masks 6
OC1M.OC1M5        5   Output Compare Masks 5
OC1M.OC1M4        4   Output Compare Masks 4
OC1M.OC1M3        3   Output Compare Masks 3
OC1D             0x100D      OC1 Action Data Register
OC1D.OC1D7        7
OC1D.OC1D6        6
OC1D.OC1D5        5
OC1D.OC1D4        4
OC1D.OC1D3        3
TCNTH            0x100E     Timer Counter Register (HI)
TCNTL            0x100F     Timer Counter Register (LO)
TIC1H            0x1010     Input Capture 1 Register (HI)
TIC1L            0x1011     Input Capture 1 Register (LO)
TIC2H            0x1012     Input Capture 2 Register (HI)
TIC2L            0x1013     Input Capture 2 Register (LO)
TIC3H            0x1014     Input Capture 3 Register (HI)
TIC3L            0x1015     Input Capture 3 Register (LO)
TOC1H            0x1016     Output Compare 1 Register (HI)
TOC1L            0x1017     Output Compare 1 Register (LO)
TOC2H            0x1018     Output Compare 2 Register (HI)
TOC2L            0x1019     Output Compare 2 Register (LO)
TOC3H            0x101A     Output Compare 3 Register (HI)
TOC3L            0x101B     Output Compare 3 Register (LO)
TOC4H            0x101C     Output Compare 4 Register (HI)
TOC4L            0x101D     Output Compare 4 Register (LO)
TCO5H            0x101E     Output Compare 5 Register (HI)
TCO5L            0x101F     Output Compare 5 Register (LO)
TCTL1            0x1020     Timer Control Register 1
TCTL1.OM2         7   Output Mode Bits 2 
TCTL1.OL2         6   Output Level Bits 2
TCTL1.OM3         5   Output Mode Bits 3 
TCTL1.OL3         4   Output Level Bits 3
TCTL1.OM4         3   Output Mode Bits 4 
TCTL1.OL4         2   Output Level Bits 4
TCTL1.OM5         1   Output Mode Bits 5 
TCTL1.OL5         0   Output Level Bits 5
TCTL2            0x1021     Timer Control Register 2
TCTL2.EDG4B       7   EDG4B  Input Capture Edge Control Bits
TCTL2.EDG4A       6   EDG4A  Input Capture Edge Control Bits
TCTL2.EDG1B       5   EDG1B  Input Capture Edge Control Bits
TCTL2.EDG1A       4   EDG1A  Input Capture Edge Control Bits
TCTL2.EDG2B       3   EDG2B  Input Capture Edge Control Bits
TCTL2.EDG2A       2   EDG2A  Input Capture Edge Control Bits
TCTL2.EDG3B       1   EDG3B  Input Capture Edge Control Bits
TCTL2.EDG3A       0   EDG3A  Input Capture Edge Control Bits
TMSK1            0x1022     Timer Interrupt Mask Register 1
TMSK1.OC1I        7   Output Compare (OC1) Interrupt Enable
TMSK1.OC2I        6   Output Compare (OC2) Interrupt Enable
TMSK1.OC3I        5   Output Compare (OC3) Interrupt Enable
TMSK1.OC4I        4   Output Compare (OC4) Interrupt Enable
TMSK1.I4_O5I      3   Input Capture 4/Output Compare 5 Interrupt Enable
TMSK1.IC1I        2   Input Capture (IC1) Interrupt Enable
TMSK1.IC2I        1   Input Capture (IC2) Interrupt Enable
TMSK1.IC3I        0   Input Capture (IC3) Interrupt Enable
TFLG1            0x1023     Timer Interrupt Flag Register 1
TFLG1.OC1F        7   Output Compare (OC1) Interrupt Flag
TFLG1.OC2F        6   Output Compare (OC2) Interrupt Flag
TFLG1.OC3F        5   Output Compare (OC3) Interrupt Flag
TFLG1.OC4F        4   Output Compare (OC4) Interrupt Flag
TFLG1.I4_O5F      3   Input Capture 4/Output Compare 5 Interrupt Enable
TFLG1.IC1F        2   Input Capture (IC1) Interrupt Enable
TFLG1.IC2F        1   Input Capture (IC2) Interrupt Enable
TFLG1.IC3F        0   Input Capture (IC3) Interrupt Enable
TMSK2            0x1024     Timer Interrupt Mask Register 2
TMSK2.TOI         7   Timer Overflow Interrupt Enable
TMSK2.RTII        6   Real-Time Interrupt Enable
TMSK2.PAOVI       5   Pulse Accumulator Overflow Interrupt Enable
TMSK2.PAII        4   Pulse Accumulator Input Edge Interrupt Enable
TMSK2.PR1         1   Timer Prescaler Select 1
TMSK2.PR0         0   Timer Prescaler Select 0
TFLG2            0x1025     Timer Interrupt Flag Register 2
TFLG2.TOF         7   Timer Overflow Interrupt Flag
TFLG2.RTIF        6   Real-Time Interrupt Flag
TFLG2.PAOVF       5   Pulse Accumulator Overflow Interrupt Flag
TFLG2.PAIF        4   Pulse Accumulator Input Edge Interrupt Flag
PACTL            0x1026     Pulse Accumulator Control Register
PACTL.PAEN        6   Pulse Accumulator Enable
PACTL.PAMOD       5   Pulse Accumulator Mode Select
PACTL.PEDGE       4   Pulse Accumulator Input Edge Select
PACTL.I4_O5       2   Input Capture 4/Output Compare 5 Select
PACTL.RTR1        1   Real-Time Interrupt Rate Select 1
PACTL.RTR0        0   Real-Time Interrupt Rate Select 0
PACNT            0x1027     Pulse Accumulator Count Register
SCBDH            0x1028     SCI Baud Rate Select High
SCBDH.BTST        7   Baud Register Test (TEST)
SCBDH.BSPL        6   Baud Rate Counter Split (TEST)
SCBDH.SBR12       4   SCI Baud Rate Select Bits 12
SCBDH.SBR11       3   SCI Baud Rate Select Bits 11
SCBDH.SBR10       2   SCI Baud Rate Select Bits 10
SCBDH.SBR9        1   SCI Baud Rate Select Bits 9
SCBDH.SBR8        0   SCI Baud Rate Select Bits 8
SCBDL            0x1029     SCI Baud Rate Select Low
SCBDL.SBR7        7   SCI Baud Rate Select Bits 7
SCBDL.SBR6        6   SCI Baud Rate Select Bits 6
SCBDL.SBR5        5   SCI Baud Rate Select Bits 5
SCBDL.SBR4        4   SCI Baud Rate Select Bits 4
SCBDL.SBR3        3   SCI Baud Rate Select Bits 3
SCBDL.SBR2        2   SCI Baud Rate Select Bits 2
SCBDL.SBR1        1   SCI Baud Rate Select Bits 1
SCBDL.SBR0        0   SCI Baud Rate Select Bits 0
SCCR1            0x102A     SCI Control Register 1
SCCR1.LOOPS       7   SCI LOOP Mode Enable
SCCR1.WOMS        6   Wired-Or Mode Option for PD[1:0] (See also DWOM bit in SPCR.)
SCCR1.M           4   Mode (Select Character Format)
SCCR1.WAKE        3   Wake-Up by Address Mark/Idle
SCCR1.ILT         2   Idle Line Type
SCCR1.PE          1   Parity Enable
SCCR1.PT          0   Parity Type
SCCR2            0x102B     SCI Control Register 2
SCCR2.TIE         7   Transmit Interrupt Enable
SCCR2.TCIE        6   Transmit Complete Interrupt Enable
SCCR2.RIE         5   Receiver Interrupt Enable
SCCR2.ILIE        4   Idle Line Interrupt Enable
SCCR2.TE          3   Transmitter Enable
SCCR2.RE          2   Receiver Enable
SCCR2.RWU         1   Receiver Wake-Up Control
SCCR2.SBK         0   Send Break
SCSR1            0x102C     SCI Status Register
SCSR1.TDRE        7   Transmit Data Register Empty Flag
SCSR1.TC          6   Transmit Complete Flag
SCSR1.RDRF        5   Receive Data Register Full Flag
SCSR1.IDLE        4   Idle Line Detected Flag
SCSR1.OR          3   Overrun Error Flag
SCSR1.NF          2   Noise Error Flag
SCSR1.FE          1   Framing Error
SCSR1.PF          0   Parity Error Flag
SCSR2            0x102D     SCI Status Register 2
SCSR2.RAF         0   Receiver Active Flag (Read only)
SCDRH            0x102E     SCI Data High
SCDRH.R8          7   Receiver Bit 8
SCDRH.T8          6   Transmitter Bit 8
SCDRL            0x102F     SCI Data Low
SCDRL.R7T7        7   Receiver/Transmitter Data Bits 7
SCDRL.R6T6        6   Receiver/Transmitter Data Bits 6
SCDRL.R5T5        5   Receiver/Transmitter Data Bits 5
SCDRL.R4T4        4   Receiver/Transmitter Data Bits 4
SCDRL.R3T3        3   Receiver/Transmitter Data Bits 3
SCDRL.R2T2        2   Receiver/Transmitter Data Bits 2
SCDRL.R1T1        1   Receiver/Transmitter Data Bits 1
SCDRL.R0T0        0   Receiver/Transmitter Data Bits 0
ADCTL            0x1030     A_D Control Register
ADCTL.CCF         7   Conversions Complete Flag
ADCTL.SCAN        5   Continuous Scan Control
ADCTL.MULT        4   Multiple Channel/Single Channel Control
ADCTL.CD          3   Channel Select D
ADCTL.CC          2   Channel Select C
ADCTL.CB          1   Channel Select B
ADCTL.CA          0   Channel Select A
ADR1             0x1031     A_D Result Register 1
ADR2             0x1032     A_D Result Register 2
ADR3             0x1033     A_D Result Register 3
ADR4             0x1034     A_D Result Register 4
BPROT            0x1035     Block Protect Register
BPROT.PTCON       4   Protect CONFIG Register
BPROT.BPRT3       3   Block Protect Bits for EEPROM 3
BPROT.BPRT2       2   Block Protect Bits for EEPROM 2
BPROT.BPRT1       1   Block Protect Bits for EEPROM 1
BPROT.BPRT0       0   Block Protect Bits for EEPROM 0
PLLCR            0x1036     PLL Control
PLLCR.PLLON       7   PLL System Enable
PLLCR.BCS         6   Bus Clock Select
PLLCR.AUTO        5   Automatic/Manual Loop Filter Bandwidth Control
PLLCR.BWC         4   Loop Filter Bandwidth Control/Status
PLLCR.VCOT        3   Voltage Controlled Oscillator (VCO) Test
PLLCR.MCS         2   Module Clock Select
PLLCR.LCK         1   Synthesizer Lock Detect Flag
PLLCR.WEN         0   WAIT Enable
SYNR             0x1037     Frequency Synthesizer Control
SYNR.SYNX1        7   Binary Tap Select Bits 1
SYNR.SYNX0        6   Binary Tap Select Bits 0
SYNR.SYNY5        5   Modulo Counter Rate Select Bits 5
SYNR.SYNY4        4   Modulo Counter Rate Select Bits 4
SYNR.SYNY3        3   Modulo Counter Rate Select Bits 3
SYNR.SYNY2        2   Modulo Counter Rate Select Bits 2
SYNR.SYNY1        1   Modulo Counter Rate Select Bits 1
SYNR.SYNY0        0   Modulo Counter Rate Select Bits 0
RESERV38         0x1038     RESERVED
OPTION           0x1039     System Configuration Options
OPTION.ADPU       7   A/D Converter Power up
OPTION.CSEL       6   Clock Select
OPTION.IRQE       5   IRQ Select Edge-Sensitive Only
OPTION.DLY        4   Enable Oscillator Start-up Delay
OPTION.CME        3   Clock Monitor Enable
OPTION.CR1        1   COP Timer Rate Select 1
OPTION.CR0        0   COP Timer Rate Select 0
COPRST           0x103A     Arm_Reset COP Timer Circuitry
PPROG            0x103B     EEPROM Program Control Register
PPROG.ODD         7   Program Odd Rows in Half of EEPROM (TEST)
PPROG.EVEN        6   Program Even Rows in Half of EEPROM (TEST)
PPROG.ELAT        5   EPROM/OTPROM Latch Control
PPROG.BYTE        4   Byte/Other EEPROM Erase Mode
PPROG.ROW         3   Row/All EEPROM Erase Mode
PPROG.ERASE       2   Erase/Normal Control for EEPROM
PPROG.EELAT       1   EEPROM Latch Control
PPROG.PGM         0   EPROM/OTPROM/EEPROM Programming Voltage Enable
HPRIO            0x103C     Highest Priority I-Bit Int and Misc
HPRIO.RBOOT       7   Read Bootstrap ROM/EPROM
HPRIO.SMOD        6   Special Mode Select
HPRIO.MDA         5   Mode Select A
HPRIO.IRVNE       4   Internal Read Visibility(Not E)
HPRIO.PSEL3       3   Priority Select Bits 3
HPRIO.PSEL2       2   Priority Select Bits 2
HPRIO.PSEL1       1   Priority Select Bits 1
HPRIO.PSEL0       0   Priority Select Bits 0
INIT             0x103D     RAM and I_O Mapping Register
INIT.RAM3         7   RAM Map Position 3
INIT.RAM2         6   RAM Map Position 2
INIT.RAM1         5   RAM Map Position 1
INIT.RAM0         4   RAM Map Position 0
INIT.REG3         3   64-Byte Register Block Position 3
INIT.REG2         2   64-Byte Register Block Position 2
INIT.REG1         1   64-Byte Register Block Position 1
INIT.REG0         0   64-Byte Register Block Position 0
RESERV103E       0x103E     RESERVED
CONFIG           0x103F     COP, ROM, and EEPROM Enables
CONFIG.NOSEC      3   Security Disable
CONFIG.NOCOP      2   COP System Disable
CONFIG.ROMON      1   ROM/EPROM/OTPROM Enable
CONFIG.EEON       0   EEPROM Enable
RESERVFFC0       0xFFC0     RESERVED
RESERVFFC1       0xFFC1     RESERVED
RESERVFFC2       0xFFC2     RESERVED
RESERVFFC3       0xFFC3     RESERVED
RESERVFFC4       0xFFC4     RESERVED
RESERVFFC5       0xFFC5     RESERVED
RESERVFFC6       0xFFC6     RESERVED
RESERVFFC7       0xFFC7     RESERVED
RESERVFFC8       0xFFC8     RESERVED
RESERVFFC9       0xFFC9     RESERVED
RESERVFFCA       0xFFCA     RESERVED
RESERVFFCB       0xFFCB     RESERVED
RESERVFFCC       0xFFCC     RESERVED
RESERVFFCD       0xFFCD     RESERVED
RESERVFFCE       0xFFCE     RESERVED
RESERVFFCF       0xFFCF     RESERVED
RESERVFFD0       0xFFD0     RESERVED
RESERVFFD1       0xFFD1     RESERVED
RESERVFFD2       0xFFD2     RESERVED
RESERVFFD3       0xFFD3     RESERVED
RESERVFFD4       0xFFD4     RESERVED
RESERVFFD5       0xFFD5     RESERVED
RESERVFFD8       0xFFD8     RESERVED
RESERVFFD9       0xFFD9     RESERVED


.68HC811A2
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68HC11PA8
; http://
; pa8.pdf

; RAM=2K 
; ROM=48K    
; EPROM=0 
; EEPROM=512


; MEMORY MAP
area DATA FSR           0x0000:0x0080 
area DATA RAM           0x0080:0x0880 
area BSS  RESERVED      0x0880:0x0E00 
area DATA EEPROM        0x0E00:0x1000 
area BSS  RESERVED      0x1000:0x4000 
area CODE ROM           0x4000:0xFFC0 
area DATA USER_VEC      0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCI               0xFFD6      SCI
interrupt I2C_bus           0xFFD4      I2C bus


; INPUT/ OUTPUT PORTS
PORTA          0x0000   Port A data
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001   Data direction A
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002   Data direction B
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003   Data direction F
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004   Port B data
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005   Port F data
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006   Port C data
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007   Data direction C
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008   Port D data
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009   Data direction D
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A   Port E data
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B   Timer compare force
CFORC.FOC1      7   Force output compares 1
CFORC.FOC2      6   Force output compares 2
CFORC.FOC3      5   Force output compares 3
CFORC.FOC4      4   Force output compares 4
CFORC.FOC5      3   Force output compares 5
OC1M           0x000C   Output compare 1 mask
OC1M.OC1M7      7   Output compare masks for OC1 bit 7
OC1M.OC1M6      6   Output compare masks for OC1 bit 6
OC1M.OC1M5      5   Output compare masks for OC1 bit 5
OC1M.OC1M4      4   Output compare masks for OC1 bit 4
OC1M.OC1M3      3   Output compare masks for OC1 bit 3
OC1D           0x000D   Output compare 1 data
OC1D.OC1D7      7   Output compare data for OC1 bit 7
OC1D.OC1D6      6   Output compare data for OC1 bit 6
OC1D.OC1D5      5   Output compare data for OC1 bit 5
OC1D.OC1D4      4   Output compare data for OC1 bit 4
OC1D.OC1D3      3   Output compare data for OC1 bit 3
TCNTH          0x000E   Timer count
TCNTL          0x000F   Timer count
TIC1H          0x0010   Timer input capture 1
TIC1L          0x0011   Timer input capture 1
TIC2H          0x0012   Timer input capture 2
TIC2L          0x0013   Timer input capture 2
TIC3H          0x0014   Timer input capture 3
TIC3L          0x0015   Timer input capture 3
TOC1H          0x0016   Timer output compare 1
TOC1L          0x0017   Timer output compare 1
TOC2H          0x0018   Timer output compare 2
TOC2L          0x0019   Timer output compare 2
TOC3H          0x001A   Timer output compare 3
TOC3L          0x001B   Timer output compare 3
TOC4H          0x001C   Timer output compare 4
TOC4L          0x001D   Timer output compare 4
TI4_O5H        0x001E   Capture 4_compare 5
TI4_O5L        0x001F   Capture 4_compare 5
TCTL1          0x0020   Timer control 1
TCTL1.OM2       7   Output mode 2 
TCTL1.OL2       6   Output level 2
TCTL1.OM3       5   Output mode 3 
TCTL1.OL3       4   Output level 3
TCTL1.OM4       3   Output mode 4 
TCTL1.OL4       2   Output level 4
TCTL1.OM5       1   Output mode 5 
TCTL1.OL5       0   Output level 5
TCTL2          0x0021   Timer control 2
TCTL2.EDG4B     7   Input capture edge control 4B
TCTL2.EDG4A     6   Input capture edge control 4A
TCTL2.EDG1B     5   Input capture edge control 1B
TCTL2.EDG1A     4   Input capture edge control 1A
TCTL2.EDG2B     3   Input capture edge control 2B
TCTL2.EDG2A     2   Input capture edge control 2A
TCTL2.EDG3B     1   Input capture edge control 3B
TCTL2.EDG3A     0   Input capture edge control 3A
TMSK1          0x0022   Timer interrupt mask 1
TMSK1.OC1I      7   Output compare 1 interrupt enable
TMSK1.OC2I      6   Output compare 2 interrupt enable
TMSK1.OC3I      5   Output compare 3 interrupt enable
TMSK1.OC4I      4   Output compare 4 interrupt enable
TMSK1.I4_O5I    3   Input capture 4/output compare 5 interrupt enable
TMSK1.IC1I      2   Input capture 1 interrupt enable
TMSK1.IC2I      1   Input capture 2 interrupt enable
TMSK1.IC3I      0   Input capture 3 interrupt enable
TFLG1          0x0023   Timer interrupt flag 1
TFLG1.OC1F      7   Output compare 1 flag
TFLG1.OC2F      6   Output compare 2 flag
TFLG1.OC3F      5   Output compare 3 flag
TFLG1.OC4F      4   Output compare 4 flag
TFLG1.I4_O5F    3   Input capture 4/output compare 5 flag
TFLG1.IC1F      2   Input capture 1 flag
TFLG1.IC2F      1   Input capture 2 flag
TFLG1.IC3F      0   Input capture 3 flag
TMSK2          0x0024   Timer interrupt mask 2
TMSK2.TOI       7   Timer overflow interrupt enable
TMSK2.RTII      6   Real-time interrupt enable
TMSK2.PAOVI     5   Pulse accumulator overflow interrupt enable
TMSK2.PAII      4   Pulse accumulator interrupt enable
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025   Timer interrupt flag 2
TFLG2.TOF       7   Timer overflow interrupt flag
TFLG2.RTIF      6   Real time (periodic) interrupt flag
TFLG2.PAOVF     5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF      4   Pulse accumulator input edge interrupt flag
PACTL          0x0026   Pulse accumulator control
PACTL.PAEN      6   Pulse accumulator system enable
PACTL.PAMOD     5   Pulse accumulator mode         
PACTL.PEDGE     4   Pulse accumulator edge control 
PACTL.I4_O5     2   Input capture 4/output compare 
PACTL.RTR1      1   RTI interrupt rate select 1    
PACTL.RTR0      0   RTI interrupt rate select 0    
PACNT          0x0027   Pulse accumulator count
SPCR           0x0028   SPI control
SPCR.SPIE       7   Serial peripheral interrupt enable
SPCR.SPE        6   Serial peripheral system enable   
SPCR.DWOM       5   Port D wired-OR mode              
SPCR.MSTR       4   Master mode select                
SPCR.CPOL       3   Clock polarity                    
SPCR.CPHA       2   Clock phase                       
SPCR.SPR1       1   SPI clock rate selects 1          
SPCR.SPR0       0   SPI clock rate selects 0          
SPSR           0x0029   SPI status
SPSR.SPIF       7   SPI interrupt complete flag
SPSR.WCOL       6   Write collision            
SPSR.MODF       4   Mode fault                 
SPSR.XPIN       1   XIRQ pin input data bit
SPSR.IPIN       0   IRQ pin input data bit
SPDR           0x002A   SPI data
RESERVED2B     0x002B   RESERVED
; EPROG          0x002B   EPROM programming (only to EPROM devices)
; EPROG.MBE       7   Multiple byte program enable
; EPROG.ELAT      5   EPROM latch control
; EPROG.EXCOL     4   Select extra columns
; EPROG.EXROW     3   Select extra rows
; EPROG.EPGM      0   EPROM program command
PPAR           0x002C   Port pull-up assignment
PPAR.GPPUE      2   Port G pin pull-up enable
PPAR.FPPUE      1   Port F pin pull-up enable
PPAR.BPPUE      0   Port B pin pull-up enable
RESERVED2D     0x002D   RESERVED
PLLCR          0x002E   PLL control
PLLCR.PLLON     7   PLL on                     
PLLCR.BCS       6   Bus clock select           
PLLCR.AUTO      5   Automatic bandwidth control
PLLCR.BWC       4   Bandwidth control          
PLLCR.VCOT      3   VCO test (Test mode only)  
PLLCR.MCS       2   Module clock select        
PLLCR.WEN       0   WAIT enable
SYNR           0x002F   Synthesizer program
SYNR.SYNX1      7
SYNR.SYNX0      6
SYNR.SYNY5      5
SYNR.SYNY4      4
SYNR.SYNY3      3
SYNR.SYNY2      2
SYNR.SYNY1      1
SYNR.SYNY0      0
ADCTL          0x0030   A_D control & status
ADCTL.CCF       7   Conversions complete flag              
ADCTL.SCAN      5   Continuous scan control                
ADCTL.MULT      4   Multiple-channel/single-channel control
ADCTL.CD        3   Channel select D                       
ADCTL.CC        2   Channel select C                       
ADCTL.CB        1   Channel select B                       
ADCTL.CA        0   Channel select A                       
ADR1           0x0031   A_D result 1
ADR2           0x0032   A_D result 2
ADR3           0x0033   A_D result 3
ADR4           0x0034   A_D result 4
BPROT          0x0035   Block protect
BPROT.BULKP     7   Bulk erase of EEPROM protect
BPROT.PTCON     4   Protect for CONFIG register   
BPROT.BPRT3     3   Block protect bit 3 for EEPROM
BPROT.BPRT2     2   Block protect bit 2 for EEPROM
BPROT.BPRT1     1   Block protect bit 1 for EEPROM
BPROT.BPRT0     0   Block protect bit 0 for EEPROM
RESERVED36     0x0036   RESERVED
INIT2          0x0037   EEPROM mapping
INIT2.EE3       7   EEPROM map position 3
INIT2.EE2       6   EEPROM map position 2
INIT2.EE1       5   EEPROM map position 1
INIT2.EE0       4   EEPROM map position 0
OPT2           0x0038   System config. options 2
OPT2.LIRDV      7   LIR driven
OPT2.CWOM       6   Port C wired-OR mode
OPT2.STRCH      5   Stretch external accesses
OPT2.IRVNE      4   Internal read visibility/not E
OPT2.LSBF       3   LSB-first enable
OPT2.SPR2       2   SPI clock rate select
OPT2.EXT4X      1   XOUT clock output select
OPT2.XIRQE      0   Configure XIRQ for falling edge sensitive operation
OPTION         0x0039   System config. options 1
OPTION.ADPU     7   A/D power-up
OPTION.CSEL     6   Clock select
OPTION.IRQE     5   Configure IRQ for falling-edge-sensitive operation
OPTION.DLY      4   Enable oscillator start-up delay
OPTION.CME      3   Clock monitor enable
OPTION.FCME     2   Force clock monitor enable
OPTION.CR1      1   COP timer rate select bit 1
OPTION.CR0      0   COP timer rate select bit 0
COPRST         0x003A   COP timer arm_reset
PPROG          0x003B   EEPROM programming
PPROG.ODD       7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN      6   Program even rows in half of EEPROM (Test)
PPROG.BYTE      4   EEPROM byte erase mode
PPROG.ROW       3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE     2   Erase/normal control for EEPROM
PPROG.EELAT     1   EEPROM latch control
PPROG.EEPGM     0   EEPROM program command
HPRIO          0x003C   Highest priority interrupt
HPRIO.RBOOT     7   Read bootstrap ROM
HPRIO.SMOD      6   Special mode select
HPRIO.MDA       5   Mode select A
HPRIO.PSEL4     4   Priority select bit 4
HPRIO.PSEL3     3   Priority select bit 3
HPRIO.PSEL2     2   Priority select bit 2
HPRIO.PSEL1     1   Priority select bit 1
HPRIO.PSEL0     0   Priority select bit 0
INIT           0x003D   RAM & I_O mapping
INIT.RAM3       7   RAM map position 3
INIT.RAM2       6   RAM map position 2
INIT.RAM1       5   RAM map position 1
INIT.RAM0       4   RAM map position 0
INIT.REG3       3   128-byte register block position 3
INIT.REG2       2   128-byte register block position 2
INIT.REG1       1   128-byte register block position 1
INIT.REG0       0   128-byte register block position 0
TEST1          0x003E   Factory test
TEST1.TILOP     7   Test Illegal Opcode
TEST1.PLTST     6   
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F   Configuration control
CONFIG.ROMAD    7   ROM mapping control
CONFIG.MBSP     6   Synchronous serial interface select
CONFIG.CLK4X    5   4X clock enable
CONFIG.PAREN    4   Pull-up assignment register enable
CONFIG.NOSEC    3   EEPROM security disabled
CONFIG.NOCOP    2   COP system disable
CONFIG.ROMON    1   ROM enable
CONFIG.EEON     0   EEPROM enable
MADR           0x0040   I2C bus address
MADR.MADR7      7   Slave address bit 7
MADR.MADR6      6   Slave address bit 6
MADR.MADR5      5   Slave address bit 5
MADR.MADR4      4   Slave address bit 4
MADR.MADR3      3   Slave address bit 3
MADR.MADR2      2   Slave address bit 2
MADR.MADR1      1   Slave address bit 1
MFDR           0x0041   I2C bus frequency divider
MFDR.MBC4       4   Clock rate select bit 4
MFDR.MBC3       3   Clock rate select bit 3
MFDR.MBC2       2   Clock rate select bit 2
MFDR.MBC1       1   Clock rate select bit 1
MFDR.MBC0       0   Clock rate select bit 0
MCR            0x0042   I2C bus control
MCR.MEN         7   I2C bus enable
MCR.MIEN        6   I2C bus interrupt enable
MCR.MSTA        5   Master/slave mode select
MCR.MTX         4   Transmit/receive mode select
MCR.TXAK        3   Transmit acknowledge bit
MSR            0x0043   I2C bus status register
MSR.MCF         7   Data transferring
MSR.MAAS        6   I2C bus addressed as a slave
MSR.MBB         5   Bus busy
MSR.MAL         4   Arbitration lost
MSR.SRW         2   Read/write command
MSR.MIF         1   I2C bus interrupt flag
MSR.RXAK        0   Received acknowledge bit
MDR            0x0044   I2C bus data register
MDR.TRXD7       7
MDR.TRXD6       6
MDR.TRXD5       5
MDR.TRXD4       4
MDR.TRXD3       3
MDR.TRXD2       2
MDR.TRXD1       1
MDR.TRXD0       0
RESERVED45     0x0045   RESERVED
RESERVED46     0x0046   RESERVED
RESERVED47     0x0047   RESERVED
RESERVED48     0x0048   RESERVED
RESERVED49     0x0049   RESERVED
RESERVED4A     0x004A   RESERVED
RESERVED4B     0x004B   RESERVED
RESERVED4C     0x004C   RESERVED
RESERVED4D     0x004D   RESERVED
RESERVED4E     0x004E   RESERVED
RESERVED4F     0x004F   RESERVED
RESERVED50     0x0050   RESERVED
RESERVED51     0x0051   RESERVED
RESERVED52     0x0052   RESERVED
RESERVED53     0x0053   RESERVED
RESERVED54     0x0054   RESERVED
RESERVED55     0x0055   RESERVED
RESERVED56     0x0056   RESERVED
RESERVED57     0x0057   RESERVED
RESERVED58     0x0058   RESERVED
RESERVED59     0x0059   RESERVED
RESERVED5A     0x005A   RESERVED
RESERVED5B     0x005B   RESERVED
RESERVED5C     0x005C   RESERVED
RESERVED5D     0x005D   RESERVED
RESERVED5E     0x005E   RESERVED
RESERVED5F     0x005F   RESERVED
RESERVED60     0x0060   RESERVED
RESERVED61     0x0061   RESERVED
RESERVED62     0x0062   RESERVED
RESERVED63     0x0063   RESERVED
RESERVED64     0x0064   RESERVED
RESERVED65     0x0065   RESERVED
RESERVED66     0x0066   RESERVED
RESERVED67     0x0067   RESERVED
RESERVED68     0x0068   RESERVED
RESERVED69     0x0069   RESERVED
RESERVED6A     0x006A   RESERVED
RESERVED6B     0x006B   RESERVED
RESERVED6C     0x006C   RESERVED
RESERVED6D     0x006D   RESERVED
RESERVED6E     0x006E   RESERVED
RESERVED6F     0x006F   RESERVED
SCBDH          0x0070   SCI baud rate high
SCBDH.BTST      7   Baud register test (Test mode only)
SCBDH.BSPL      6   Baud rate counter split (Test mode only)
SCBDH.BRST      5   Baud rate reset (Test mode only)
SCBDH.SBR12     4   SCI baud rate selects 12
SCBDH.SBR11     3   SCI baud rate selects 11
SCBDH.SBR10     2   SCI baud rate selects 10
SCBDH.SBR9      1   SCI baud rate selects 9 
SCBDH.SBR8      0   SCI baud rate selects 8 
SCBDL          0x0071   SCI baud rate low
SCBDL.SBR7      7   SCI baud rate selects 7
SCBDL.SBR6      6   SCI baud rate selects 6
SCBDL.SBR5      5   SCI baud rate selects 5
SCBDL.SBR4      4   SCI baud rate selects 4
SCBDL.SBR3      3   SCI baud rate selects 3
SCBDL.SBR2      2   SCI baud rate selects 2
SCBDL.SBR1      1   SCI baud rate selects 1
SCBDL.SBR0      0   SCI baud rate selects 0
SCCR1          0x0072   SCI control 1
SCCR1.LOOPS     7   SCI loop mode enable
SCCR1.WOMS      6   Wired-OR mode for SCI pins (PD1, PD0)
SCCR1.M         4   Mode (select character format)
SCCR1.WAKE      3   Wake-up by address mark/idle
SCCR1.ILT       2   Idle line type
SCCR1.PE        1   Parity enable
SCCR1.PT        0   Parity type
SCCR2          0x0073   SCI control 2
SCCR2.TIE       7   Transmit interrupt enable
SCCR2.TCIE      6   Transmit complete interrupt enable
SCCR2.RIE       5   Receiver interrupt enable
SCCR2.ILIE      4   Idle line interrupt enable
SCCR2.TE        3   Transmitter enable
SCCR2.RE        2   Receiver enable
SCCR2.RWU       1   Receiver wake-up control
SCCR2.SBK       0   Send break
SCSR1          0x0074   SCI status 1
SCSR1.TDRE      7   Transmit data register empty flag
SCSR1.TC        6   Transmit complete flag
SCSR1.RDRF      5   Receive data register full flag
SCSR1.IDLE      4   Idle line detected flag
SCSR1.OR        3   Overrun error flag
SCSR1.NF        2   Noise error flag
SCSR1.FE        1   Framing error
SCSR1.PF        0   Parity error flag
SCSR2          0x0075   SCI status 2
SCSR2.RAF       0   Receiver active flag (read only)
SCDRH          0x0076   SCI data high
SCDRH.R8        7   Receiver bit 8
SCDRH.T8        6   Transmitter bit 8
SCDRL          0x0077   SCI data low
SCDRL.R7T7      7   Receiver/transmitter data bit 7
SCDRL.R6T6      6   Receiver/transmitter data bit 6
SCDRL.R5T5      5   Receiver/transmitter data bit 5
SCDRL.R4T4      4   Receiver/transmitter data bit 4
SCDRL.R3T3      3   Receiver/transmitter data bit 3
SCDRL.R2T2      2   Receiver/transmitter data bit 2
SCDRL.R1T1      1   Receiver/transmitter data bit 1
SCDRL.R0T0      0   Receiver/transmitter data bit 0
RESERVED78     0x0078   RESERVED
RESERVED79     0x0079   RESERVED
RESERVED7A     0x007A   RESERVED
RESERVED7B     0x007B   RESERVED
RESERVED7C     0x007C   RESERVED
RESERVED7D     0x007D   RESERVED
PORTG          0x007E   Port G data
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F   Data direction G
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0   RESERVED
RESERVFFC1     0xFFC1   RESERVED
RESERVFFC2     0xFFC2   RESERVED
RESERVFFC3     0xFFC3   RESERVED
RESERVFFC4     0xFFC4   RESERVED
RESERVFFC5     0xFFC5   RESERVED
RESERVFFC6     0xFFC6   RESERVED
RESERVFFC7     0xFFC7   RESERVED
RESERVFFC8     0xFFC8   RESERVED
RESERVFFC9     0xFFC9   RESERVED
RESERVFFCA     0xFFCA   RESERVED
RESERVFFCB     0xFFCB   RESERVED
RESERVFFCC     0xFFCC   RESERVED
RESERVFFCD     0xFFCD   RESERVED
RESERVFFCE     0xFFCE   RESERVED
RESERVFFCF     0xFFCF   RESERVED
RESERVFFD0     0xFFD0   RESERVED
RESERVFFD1     0xFFD1   RESERVED
RESERVFFD2     0xFFD2   RESERVED
RESERVFFD3     0xFFD3   RESERVED


.68HC11PB8
; http://
; pa8.pdf

; RAM=2K 
; ROM=48K    
; EPROM=0 
; EEPROM=512


; MEMORY MAP
area DATA FSR         0x0000:0x0080
area DATA RAM         0x0080:0x0880
area BSS  RESERVED    0x0880:0x0E00
area DATA EEPROM      0x0E00:0x1000
area BSS  RESERVED    0x1000:0x4000
area CODE ROM         0x4000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System
interrupt I2C_bus           0xFFD4      I2C bus


; INPUT/ OUTPUT PORTS
PORTA          0x0000   Port A data
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001   Data direction A
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002   Data direction B
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003   Data direction F
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004   Port B data
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005   Port F data
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006   Port C data
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007   Data direction C
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008   Port D data
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009   Data direction D
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A   Port E data
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B   Timer compare force
CFORC.FOC1      7   Force output compares 1
CFORC.FOC2      6   Force output compares 2
CFORC.FOC3      5   Force output compares 3
CFORC.FOC4      4   Force output compares 4
CFORC.FOC5      3   Force output compares 5
OC1M           0x000C   Output compare 1 mask
OC1M.OC1M7      7   Output compare masks for OC1 bit 7
OC1M.OC1M6      6   Output compare masks for OC1 bit 6
OC1M.OC1M5      5   Output compare masks for OC1 bit 5
OC1M.OC1M4      4   Output compare masks for OC1 bit 4
OC1M.OC1M3      3   Output compare masks for OC1 bit 3
OC1D           0x000D   Output compare 1 data
OC1D.OC1D7      7   Output compare data for OC1 bit 7
OC1D.OC1D6      6   Output compare data for OC1 bit 6
OC1D.OC1D5      5   Output compare data for OC1 bit 5
OC1D.OC1D4      4   Output compare data for OC1 bit 4
OC1D.OC1D3      3   Output compare data for OC1 bit 3
TCNTH          0x000E   Timer count H
TCNTL          0x000F   Timer count L
TIC1H          0x0010   Timer input capture 1
TIC1L          0x0011   Timer input capture 1
TIC2H          0x0012   Timer input capture 2
TIC2L          0x0013   Timer input capture 2
TIC3H          0x0014   Timer input capture 3
TIC3L          0x0015   Timer input capture 3
TOC1H          0x0016   Timer output compare 1
TOC1L          0x0017   Timer output compare 1
TOC2H          0x0018   Timer output compare 2
TOC2L          0x0019   Timer output compare 2
TOC3H          0x001A   Timer output compare 3
TOC3L          0x001B   Timer output compare 3
TOC4H          0x001C   Timer output compare 4
TOC4L          0x001D   Timer output compare 4
TI4_O5H        0x001E   Capture 4_compare 5
TI4_O5L        0x001F   Capture 4_compare 5
TCTL1          0x0020   Timer control 1
TCTL1.OM2       7   Output mode 2 
TCTL1.OL2       6   Output level 2
TCTL1.OM3       5   Output mode 3 
TCTL1.OL3       4   Output level 3
TCTL1.OM4       3   Output mode 4 
TCTL1.OL4       2   Output level 4
TCTL1.OM5       1   Output mode 5 
TCTL1.OL5       0   Output level 5
TCTL2          0x0021   Timer control 2
TCTL2.EDG4B     7   Input capture edge control 4B
TCTL2.EDG4A     6   Input capture edge control 4A
TCTL2.EDG1B     5   Input capture edge control 1B
TCTL2.EDG1A     4   Input capture edge control 1A
TCTL2.EDG2B     3   Input capture edge control 2B
TCTL2.EDG2A     2   Input capture edge control 2A
TCTL2.EDG3B     1   Input capture edge control 3B
TCTL2.EDG3A     0   Input capture edge control 3A
TMSK1          0x0022   Timer interrupt mask 1
TMSK1.OC1I      7   Output compare 1 interrupt enable
TMSK1.OC2I      6   Output compare 2 interrupt enable
TMSK1.OC3I      5   Output compare 3 interrupt enable
TMSK1.OC4I      4   Output compare 4 interrupt enable
TMSK1.I4_O5I    3   Input capture 4/output compare 5 interrupt enable
TMSK1.IC1I      2   Input capture 1 interrupt enable
TMSK1.IC2I      1   Input capture 2 interrupt enable
TMSK1.IC3I      0   Input capture 3 interrupt enable
TFLG1          0x0023   Timer interrupt flag 1
TFLG1.OC1F      7   Output compare 1 flag
TFLG1.OC2F      6   Output compare 2 flag
TFLG1.OC3F      5   Output compare 3 flag
TFLG1.OC4F      4   Output compare 4 flag
TFLG1.I4_O5F    3   Input capture 4/output compare 5 flag
TFLG1.IC1F      2   Input capture 1 flag
TFLG1.IC2F      1   Input capture 2 flag
TFLG1.IC3F      0   Input capture 3 flag
TMSK2          0x0024   Timer interrupt mask 2
TMSK2.TOI       7   Timer overflow interrupt enable
TMSK2.RTII      6   Real-time interrupt enable
TMSK2.PAOVI     5   Pulse accumulator overflow interrupt enable
TMSK2.PAII      4   Pulse accumulator interrupt enable
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025   Timer interrupt flag 2
TFLG2.TOF       7   Timer overflow interrupt flag
TFLG2.RTIF      6   Real time (periodic) interrupt flag
TFLG2.PAOVF     5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF      4   Pulse accumulator input edge interrupt flag
PACTL          0x0026   Pulse accumulator control
PACTL.PAEN      6   Pulse accumulator system enable
PACTL.PAMOD     5   Pulse accumulator mode         
PACTL.PEDGE     4   Pulse accumulator edge control 
PACTL.I4_O5     2   Input capture 4/output compare 
PACTL.RTR1      1   RTI interrupt rate select 1    
PACTL.RTR0      0   RTI interrupt rate select 0    
PACNT          0x0027   Pulse accumulator count
SPCR           0x0028   SPI control
SPCR.SPIE       7   Serial peripheral interrupt enable
SPCR.SPE        6   Serial peripheral system enable   
SPCR.DWOM       5   Port D wired-OR mode              
SPCR.MSTR       4   Master mode select                
SPCR.CPOL       3   Clock polarity                    
SPCR.CPHA       2   Clock phase                       
SPCR.SPR1       1   SPI clock rate selects 1          
SPCR.SPR0       0   SPI clock rate selects 0          
SPSR           0x0029   SPI status
SPSR.SPIF       7   SPI interrupt complete flag
SPSR.WCOL       6   Write collision            
SPSR.MODF       4   Mode fault                 
SPSR.XPIN       1   XIRQ pin input data bit
SPSR.IPIN       0   IRQ pin input data bit
SPDR           0x002A   SPI data
RESERVED2B     0x002B   RESERVED
; EPROG          0x002B   EPROM programming (only to EPROM devices)
; EPROG.MBE       7   Multiple byte program enable
; EPROG.ELAT      5   EPROM latch control
; EPROG.EXCOL     4   Select extra columns
; EPROG.EXROW     3   Select extra rows
; EPROG.EPGM      0   EPROM program command
PPAR           0x002C   Port pull-up assignment
PPAR.GPPUE      2   Port G pin pull-up enable
PPAR.FPPUE      1   Port F pin pull-up enable
PPAR.BPPUE      0   Port B pin pull-up enable
RESERVED2D     0x002D   RESERVED
PLLCR          0x002E   PLL control
PLLCR.PLLON     7   PLL on                     
PLLCR.BCS       6   Bus clock select           
PLLCR.AUTO      5   Automatic bandwidth control
PLLCR.BWC       4   Bandwidth control          
PLLCR.VCOT      3   VCO test (Test mode only)  
PLLCR.MCS       2   Module clock select        
PLLCR.WEN       0   WAIT enable
SYNR           0x002F   Synthesizer program
SYNR.SYNX1      7
SYNR.SYNX0      6
SYNR.SYNY5      5
SYNR.SYNY4      4
SYNR.SYNY3      3
SYNR.SYNY2      2
SYNR.SYNY1      1
SYNR.SYNY0      0
ADCTL          0x0030   A_D control & status
ADCTL.CCF       7   Conversions complete flag              
ADCTL.SCAN      5   Continuous scan control                
ADCTL.MULT      4   Multiple-channel/single-channel control
ADCTL.CD        3   Channel select D                       
ADCTL.CC        2   Channel select C                       
ADCTL.CB        1   Channel select B                       
ADCTL.CA        0   Channel select A                       
ADR1           0x0031   A_D result 1
ADR2           0x0032   A_D result 2
ADR3           0x0033   A_D result 3
ADR4           0x0034   A_D result 4
BPROT          0x0035   Block protect
BPROT.BULKP     7   Bulk erase of EEPROM protect
BPROT.PTCON     4   Protect for CONFIG register   
BPROT.BPRT3     3   Block protect bit 3 for EEPROM
BPROT.BPRT2     2   Block protect bit 2 for EEPROM
BPROT.BPRT1     1   Block protect bit 1 for EEPROM
BPROT.BPRT0     0   Block protect bit 0 for EEPROM
RESERVED36     0x0036   RESERVED
INIT2          0x0037   EEPROM mapping
INIT2.EE3       7   EEPROM map position 3
INIT2.EE2       6   EEPROM map position 2
INIT2.EE1       5   EEPROM map position 1
INIT2.EE0       4   EEPROM map position 0
OPT2           0x0038   System config. options 2
OPT2.LIRDV      7   LIR driven
OPT2.CWOM       6   Port C wired-OR mode
OPT2.STRCH      5   Stretch external accesses
OPT2.IRVNE      4   Internal read visibility/not E
OPT2.LSBF       3   LSB-first enable
OPT2.SPR2       2   SPI clock rate select
OPT2.EXT4X      1   XOUT clock output select
OPT2.XIRQE      0   Configure XIRQ for falling edge sensitive operation
OPTION         0x0039   System config. options 1
OPTION.ADPU     7   A/D power-up
OPTION.CSEL     6   Clock select
OPTION.IRQE     5   Configure IRQ for falling-edge-sensitive operation
OPTION.DLY      4   Enable oscillator start-up delay
OPTION.CME      3   Clock monitor enable
OPTION.FCME     2   Force clock monitor enable
OPTION.CR1      1   COP timer rate select bit 1
OPTION.CR0      0   COP timer rate select bit 0
COPRST         0x003A   COP timer arm_reset
PPROG          0x003B   EEPROM programming
PPROG.ODD       7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN      6   Program even rows in half of EEPROM (Test)
PPROG.BYTE      4   EEPROM byte erase mode
PPROG.ROW       3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE     2   Erase/normal control for EEPROM
PPROG.EELAT     1   EEPROM latch control
PPROG.EEPGM     0   EEPROM program command
HPRIO          0x003C   Highest priority interrupt
HPRIO.RBOOT     7   Read bootstrap ROM
HPRIO.SMOD      6   Special mode select
HPRIO.MDA       5   Mode select A
HPRIO.PSEL4     4   Priority select bit 4
HPRIO.PSEL3     3   Priority select bit 3
HPRIO.PSEL2     2   Priority select bit 2
HPRIO.PSEL1     1   Priority select bit 1
HPRIO.PSEL0     0   Priority select bit 0
INIT           0x003D   RAM & I_O mapping
INIT.RAM3       7   RAM map position 3
INIT.RAM2       6   RAM map position 2
INIT.RAM1       5   RAM map position 1
INIT.RAM0       4   RAM map position 0
INIT.REG3       3   128-byte register block position 3
INIT.REG2       2   128-byte register block position 2
INIT.REG1       1   128-byte register block position 1
INIT.REG0       0   128-byte register block position 0
TEST1          0x003E   Factory test
TEST1.TILOP     7   Test Illegal Opcode
TEST1.PLTST     6   
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F   Configuration control
CONFIG.ROMAD    7   ROM mapping control
CONFIG.MBSP     6   Synchronous serial interface select
CONFIG.CLK4X    5   4X clock enable
CONFIG.PAREN    4   Pull-up assignment register enable
CONFIG.NOSEC    3   EEPROM security disabled
CONFIG.NOCOP    2   COP system disable
CONFIG.ROMON    1   ROM enable
CONFIG.EEON     0   EEPROM enable
MADR           0x0040   I2C bus address
MADR.MADR7      7   Slave address bit 7
MADR.MADR6      6   Slave address bit 6
MADR.MADR5      5   Slave address bit 5
MADR.MADR4      4   Slave address bit 4
MADR.MADR3      3   Slave address bit 3
MADR.MADR2      2   Slave address bit 2
MADR.MADR1      1   Slave address bit 1
MFDR           0x0041   I2C bus frequency divider
MFDR.MBC4       4   Clock rate select bit 4
MFDR.MBC3       3   Clock rate select bit 3
MFDR.MBC2       2   Clock rate select bit 2
MFDR.MBC1       1   Clock rate select bit 1
MFDR.MBC0       0   Clock rate select bit 0
MCR            0x0042   I2C bus control
MCR.MEN         7   I2C bus enable
MCR.MIEN        6   I2C bus interrupt enable
MCR.MSTA        5   Master/slave mode select
MCR.MTX         4   Transmit/receive mode select
MCR.TXAK        3   Transmit acknowledge bit
MSR            0x0043   I2C bus status register
MSR.MCF         7   Data transferring
MSR.MAAS        6   I2C bus addressed as a slave
MSR.MBB         5   Bus busy
MSR.MAL         4   Arbitration lost
MSR.SRW         2   Read/write command
MSR.MIF         1   I2C bus interrupt flag
MSR.RXAK        0   Received acknowledge bit
MDR            0x0044   I2C bus data register
MDR.TRXD7       7
MDR.TRXD6       6
MDR.TRXD5       5
MDR.TRXD4       4
MDR.TRXD3       3
MDR.TRXD2       2
MDR.TRXD1       1
MDR.TRXD0       0
RESERVED45     0x0045   RESERVED
RESERVED46     0x0046   RESERVED
RESERVED47     0x0047   RESERVED
RESERVED48     0x0048   RESERVED
RESERVED49     0x0049   RESERVED
RESERVED4A     0x004A   RESERVED
RESERVED4B     0x004B   RESERVED
RESERVED4C     0x004C   RESERVED
RESERVED4D     0x004D   RESERVED
RESERVED4E     0x004E   RESERVED
RESERVED4F     0x004F   RESERVED
RESERVED50     0x0050   RESERVED
RESERVED51     0x0051   RESERVED
RESERVED52     0x0052   RESERVED
RESERVED53     0x0053   RESERVED
RESERVED54     0x0054   RESERVED
RESERVED55     0x0055   RESERVED
RESERVED56     0x0056   RESERVED
RESERVED57     0x0057   RESERVED
RESERVED58     0x0058   RESERVED
RESERVED59     0x0059   RESERVED
RESERVED5A     0x005A   RESERVED
RESERVED5B     0x005B   RESERVED
RESERVED5C     0x005C   RESERVED
RESERVED5D     0x005D   RESERVED
RESERVED5E     0x005E   RESERVED
RESERVED5F     0x005F   RESERVED
RESERVED60     0x0060   RESERVED
RESERVED61     0x0061   RESERVED
RESERVED62     0x0062   RESERVED
RESERVED63     0x0063   RESERVED
RESERVED64     0x0064   RESERVED
RESERVED65     0x0065   RESERVED
RESERVED66     0x0066   RESERVED
RESERVED67     0x0067   RESERVED
RESERVED68     0x0068   RESERVED
RESERVED69     0x0069   RESERVED
RESERVED6A     0x006A   RESERVED
RESERVED6B     0x006B   RESERVED
RESERVED6C     0x006C   RESERVED
RESERVED6D     0x006D   RESERVED
RESERVED6E     0x006E   RESERVED
RESERVED6F     0x006F   RESERVED
SCBDH          0x0070   SCI baud rate high
SCBDH.BTST      7   Baud register test (Test mode only)
SCBDH.BSPL      6   Baud rate counter split (Test mode only)
SCBDH.BRST      5   Baud rate reset (Test mode only)
SCBDH.SBR12     4   SCI baud rate selects 12
SCBDH.SBR11     3   SCI baud rate selects 11
SCBDH.SBR10     2   SCI baud rate selects 10
SCBDH.SBR9      1   SCI baud rate selects 9 
SCBDH.SBR8      0   SCI baud rate selects 8 
SCBDL          0x0071   SCI baud rate low
SCBDL.SBR7      7   SCI baud rate selects 7
SCBDL.SBR6      6   SCI baud rate selects 6
SCBDL.SBR5      5   SCI baud rate selects 5
SCBDL.SBR4      4   SCI baud rate selects 4
SCBDL.SBR3      3   SCI baud rate selects 3
SCBDL.SBR2      2   SCI baud rate selects 2
SCBDL.SBR1      1   SCI baud rate selects 1
SCBDL.SBR0      0   SCI baud rate selects 0
SCCR1          0x0072   SCI control 1
SCCR1.LOOPS     7   SCI loop mode enable
SCCR1.WOMS      6   Wired-OR mode for SCI pins (PD1, PD0)
SCCR1.M         4   Mode (select character format)
SCCR1.WAKE      3   Wake-up by address mark/idle
SCCR1.ILT       2   Idle line type
SCCR1.PE        1   Parity enable
SCCR1.PT        0   Parity type
SCCR2          0x0073   SCI control 2
SCCR2.TIE       7   Transmit interrupt enable
SCCR2.TCIE      6   Transmit complete interrupt enable
SCCR2.RIE       5   Receiver interrupt enable
SCCR2.ILIE      4   Idle line interrupt enable
SCCR2.TE        3   Transmitter enable
SCCR2.RE        2   Receiver enable
SCCR2.RWU       1   Receiver wake-up control
SCCR2.SBK       0   Send break
SCSR1          0x0074   SCI status 1
SCSR1.TDRE      7   Transmit data register empty flag
SCSR1.TC        6   Transmit complete flag
SCSR1.RDRF      5   Receive data register full flag
SCSR1.IDLE      4   Idle line detected flag
SCSR1.OR        3   Overrun error flag
SCSR1.NF        2   Noise error flag
SCSR1.FE        1   Framing error
SCSR1.PF        0   Parity error flag
SCSR2          0x0075   SCI status 2
SCSR2.RAF       0   Receiver active flag (read only)
SCDRH          0x0076   SCI data high
SCDRH.R8        7   Receiver bit 8
SCDRH.T8        6   Transmitter bit 8
SCDRL          0x0077   SCI data low
SCDRL.R7T7      7   Receiver/transmitter data bit 7
SCDRL.R6T6      6   Receiver/transmitter data bit 6
SCDRL.R5T5      5   Receiver/transmitter data bit 5
SCDRL.R4T4      4   Receiver/transmitter data bit 4
SCDRL.R3T3      3   Receiver/transmitter data bit 3
SCDRL.R2T2      2   Receiver/transmitter data bit 2
SCDRL.R1T1      1   Receiver/transmitter data bit 1
SCDRL.R0T0      0   Receiver/transmitter data bit 0
RESERVED78     0x0078   RESERVED
RESERVED79     0x0079   RESERVED
RESERVED7A     0x007A   RESERVED
RESERVED7B     0x007B   RESERVED
RESERVED7C     0x007C   RESERVED
RESERVED7D     0x007D   RESERVED
PORTG          0x007E   Port G data
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F   Data direction G
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0   RESERVED
RESERVFFC1     0xFFC1   RESERVED
RESERVFFC2     0xFFC2   RESERVED
RESERVFFC3     0xFFC3   RESERVED
RESERVFFC4     0xFFC4   RESERVED
RESERVFFC5     0xFFC5   RESERVED
RESERVFFC6     0xFFC6   RESERVED
RESERVFFC7     0xFFC7   RESERVED
RESERVFFC8     0xFFC8   RESERVED
RESERVFFC9     0xFFC9   RESERVED
RESERVFFCA     0xFFCA   RESERVED
RESERVFFCB     0xFFCB   RESERVED
RESERVFFCC     0xFFCC   RESERVED
RESERVFFCD     0xFFCD   RESERVED
RESERVFFCE     0xFFCE   RESERVED
RESERVFFCF     0xFFCF   RESERVED
RESERVFFD0     0xFFD0   RESERVED
RESERVFFD1     0xFFD1   RESERVED
RESERVFFD2     0xFFD2   RESERVED
RESERVFFD3     0xFFD3   RESERVED


.68HC711PA8
; MC68HC11PA8/D  http://
; pa8.pdf

; RAM=2K 
; ROM=0    
; EPROM=48K 
; EEPROM=512
         

; MEMORY MAP
area DATA FSR         0x0000:0x0080
area DATA RAM         0x0080:0x0880
area BSS  RESERVED    0x0880:0x0E00
area DATA EEPROM      0x0E00:0x1000
area BSS  RESERVED    0x1000:0x4000
area CODE EPROM       0x4000:0xFFC0
area DATA USER_VEC    0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System
interrupt I2C_bus           0xFFD4      I2C bus


; INPUT/ OUTPUT PORTS
PORTA          0x0000   Port A data
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001   Data direction A
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002   Data direction B
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003   Data direction F
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004   Port B data
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005   Port F data
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006   Port C data
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007   Data direction C
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008   Port D data
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009   Data direction D
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A   Port E data
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B   Timer compare force
CFORC.FOC1      7   Force output compares 1
CFORC.FOC2      6   Force output compares 2
CFORC.FOC3      5   Force output compares 3
CFORC.FOC4      4   Force output compares 4
CFORC.FOC5      3   Force output compares 5
OC1M           0x000C   Output compare 1 mask
OC1M.OC1M7      7   Output compare masks for OC1 bit 7
OC1M.OC1M6      6   Output compare masks for OC1 bit 6
OC1M.OC1M5      5   Output compare masks for OC1 bit 5
OC1M.OC1M4      4   Output compare masks for OC1 bit 4
OC1M.OC1M3      3   Output compare masks for OC1 bit 3
OC1D           0x000D   Output compare 1 data
OC1D.OC1D7      7   Output compare data for OC1 bit 7
OC1D.OC1D6      6   Output compare data for OC1 bit 6
OC1D.OC1D5      5   Output compare data for OC1 bit 5
OC1D.OC1D4      4   Output compare data for OC1 bit 4
OC1D.OC1D3      3   Output compare data for OC1 bit 3
TCNTH          0x000E   Timer count
TCNTL          0x000F   Timer count
TIC1H          0x0010   Timer input capture 1
TIC1L          0x0011   Timer input capture 1
TIC2H          0x0012   Timer input capture 2
TIC2L          0x0013   Timer input capture 2
TIC3H          0x0014   Timer input capture 3
TIC3L          0x0015   Timer input capture 3
TOC1H          0x0016   Timer output compare 1
TOC1L          0x0017   Timer output compare 1
TOC2H          0x0018   Timer output compare 2
TOC2L          0x0019   Timer output compare 2
TOC3H          0x001A   Timer output compare 3
TOC3L          0x001B   Timer output compare 3
TOC4H          0x001C   Timer output compare 4
TOC4L          0x001D   Timer output compare 4
TI4_O5H        0x001E   Capture 4_compare 5
TI4_O5L        0x001F   Capture 4_compare 5
TCTL1          0x0020   Timer control 1
TCTL1.OM2       7   Output mode 2 
TCTL1.OL2       6   Output level 2
TCTL1.OM3       5   Output mode 3 
TCTL1.OL3       4   Output level 3
TCTL1.OM4       3   Output mode 4 
TCTL1.OL4       2   Output level 4
TCTL1.OM5       1   Output mode 5 
TCTL1.OL5       0   Output level 5
TCTL2          0x0021   Timer control 2
TCTL2.EDG4B     7   Input capture edge control 4B
TCTL2.EDG4A     6   Input capture edge control 4A
TCTL2.EDG1B     5   Input capture edge control 1B
TCTL2.EDG1A     4   Input capture edge control 1A
TCTL2.EDG2B     3   Input capture edge control 2B
TCTL2.EDG2A     2   Input capture edge control 2A
TCTL2.EDG3B     1   Input capture edge control 3B
TCTL2.EDG3A     0   Input capture edge control 3A
TMSK1          0x0022   Timer interrupt mask 1
TMSK1.OC1I      7   Output compare 1 interrupt enable
TMSK1.OC2I      6   Output compare 2 interrupt enable
TMSK1.OC3I      5   Output compare 3 interrupt enable
TMSK1.OC4I      4   Output compare 4 interrupt enable
TMSK1.I4_O5I    3   Input capture 4/output compare 5 interrupt enable
TMSK1.IC1I      2   Input capture 1 interrupt enable
TMSK1.IC2I      1   Input capture 2 interrupt enable
TMSK1.IC3I      0   Input capture 3 interrupt enable
TFLG1          0x0023   Timer interrupt flag 1
TFLG1.OC1F      7   Output compare 1 flag
TFLG1.OC2F      6   Output compare 2 flag
TFLG1.OC3F      5   Output compare 3 flag
TFLG1.OC4F      4   Output compare 4 flag
TFLG1.I4_O5F    3   Input capture 4/output compare 5 flag
TFLG1.IC1F      2   Input capture 1 flag
TFLG1.IC2F      1   Input capture 2 flag
TFLG1.IC3F      0   Input capture 3 flag
TMSK2          0x0024   Timer interrupt mask 2
TMSK2.TOI       7   Timer overflow interrupt enable
TMSK2.RTII      6   Real-time interrupt enable
TMSK2.PAOVI     5   Pulse accumulator overflow interrupt enable
TMSK2.PAII      4   Pulse accumulator interrupt enable
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025   Timer interrupt flag 2
TFLG2.TOF       7   Timer overflow interrupt flag
TFLG2.RTIF      6   Real time (periodic) interrupt flag
TFLG2.PAOVF     5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF      4   Pulse accumulator input edge interrupt flag
PACTL          0x0026   Pulse accumulator control
PACTL.PAEN      6   Pulse accumulator system enable
PACTL.PAMOD     5   Pulse accumulator mode         
PACTL.PEDGE     4   Pulse accumulator edge control 
PACTL.I4_O5     2   Input capture 4/output compare 
PACTL.RTR1      1   RTI interrupt rate select 1    
PACTL.RTR0      0   RTI interrupt rate select 0    
PACNT          0x0027   Pulse accumulator count
SPCR           0x0028   SPI control
SPCR.SPIE       7   Serial peripheral interrupt enable
SPCR.SPE        6   Serial peripheral system enable   
SPCR.DWOM       5   Port D wired-OR mode              
SPCR.MSTR       4   Master mode select                
SPCR.CPOL       3   Clock polarity                    
SPCR.CPHA       2   Clock phase                       
SPCR.SPR1       1   SPI clock rate selects 1          
SPCR.SPR0       0   SPI clock rate selects 0          
SPSR           0x0029   SPI status
SPSR.SPIF       7   SPI interrupt complete flag
SPSR.WCOL       6   Write collision            
SPSR.MODF       4   Mode fault                 
SPSR.XPIN       1   XIRQ pin input data bit
SPSR.IPIN       0   IRQ pin input data bit
SPDR           0x002A   SPI data
EPROG          0x002B   EPROM programming (only to EPROM devices)
EPROG.MBE       7   Multiple byte program enable
EPROG.ELAT      5   EPROM latch control
EPROG.EXCOL     4   Select extra columns
EPROG.EXROW     3   Select extra rows
EPROG.EPGM      0   EPROM program command
PPAR           0x002C   Port pull-up assignment
PPAR.GPPUE      2   Port G pin pull-up enable
PPAR.FPPUE      1   Port F pin pull-up enable
PPAR.BPPUE      0   Port B pin pull-up enable
RESERVED2D     0x002D   RESERVED
PLLCR          0x002E   PLL control
PLLCR.PLLON     7   PLL on                     
PLLCR.BCS       6   Bus clock select           
PLLCR.AUTO      5   Automatic bandwidth control
PLLCR.BWC       4   Bandwidth control          
PLLCR.VCOT      3   VCO test (Test mode only)  
PLLCR.MCS       2   Module clock select        
PLLCR.WEN       0   WAIT enable
SYNR           0x002F   Synthesizer program
SYNR.SYNX1      7
SYNR.SYNX0      6
SYNR.SYNY5      5
SYNR.SYNY4      4
SYNR.SYNY3      3
SYNR.SYNY2      2
SYNR.SYNY1      1
SYNR.SYNY0      0
ADCTL          0x0030   A_D control & status
ADCTL.CCF       7   Conversions complete flag              
ADCTL.SCAN      5   Continuous scan control                
ADCTL.MULT      4   Multiple-channel/single-channel control
ADCTL.CD        3   Channel select D                       
ADCTL.CC        2   Channel select C                       
ADCTL.CB        1   Channel select B                       
ADCTL.CA        0   Channel select A                       
ADR1           0x0031   A_D result 1
ADR2           0x0032   A_D result 2
ADR3           0x0033   A_D result 3
ADR4           0x0034   A_D result 4
BPROT          0x0035   Block protect
BPROT.BULKP     7   Bulk erase of EEPROM protect
BPROT.PTCON     4   Protect for CONFIG register   
BPROT.BPRT3     3   Block protect bit 3 for EEPROM
BPROT.BPRT2     2   Block protect bit 2 for EEPROM
BPROT.BPRT1     1   Block protect bit 1 for EEPROM
BPROT.BPRT0     0   Block protect bit 0 for EEPROM
RESERVED36     0x0036   RESERVED
INIT2          0x0037   EEPROM mapping
INIT2.EE3       7   EEPROM map position 3
INIT2.EE2       6   EEPROM map position 2
INIT2.EE1       5   EEPROM map position 1
INIT2.EE0       4   EEPROM map position 0
OPT2           0x0038   System config. options 2
OPT2.LIRDV      7   LIR driven
OPT2.CWOM       6   Port C wired-OR mode
OPT2.STRCH      5   Stretch external accesses
OPT2.IRVNE      4   Internal read visibility/not E
OPT2.LSBF       3   LSB-first enable
OPT2.SPR2       2   SPI clock rate select
OPT2.EXT4X      1   XOUT clock output select
OPT2.XIRQE      0   Configure XIRQ for falling edge sensitive operation
OPTION         0x0039   System config. options 1
OPTION.ADPU     7   A/D power-up
OPTION.CSEL     6   Clock select
OPTION.IRQE     5   Configure IRQ for falling-edge-sensitive operation
OPTION.DLY      4   Enable oscillator start-up delay
OPTION.CME      3   Clock monitor enable
OPTION.FCME     2   Force clock monitor enable
OPTION.CR1      1   COP timer rate select bit 1
OPTION.CR0      0   COP timer rate select bit 0
COPRST         0x003A   COP timer arm_reset
PPROG          0x003B   EEPROM programming
PPROG.ODD       7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN      6   Program even rows in half of EEPROM (Test)
PPROG.BYTE      4   EEPROM byte erase mode
PPROG.ROW       3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE     2   Erase/normal control for EEPROM
PPROG.EELAT     1   EEPROM latch control
PPROG.EEPGM     0   EEPROM program command
HPRIO          0x003C   Highest priority interrupt
HPRIO.RBOOT     7   Read bootstrap ROM
HPRIO.SMOD      6   Special mode select
HPRIO.MDA       5   Mode select A
HPRIO.PSEL4     4   Priority select bit 4
HPRIO.PSEL3     3   Priority select bit 3
HPRIO.PSEL2     2   Priority select bit 2
HPRIO.PSEL1     1   Priority select bit 1
HPRIO.PSEL0     0   Priority select bit 0
INIT           0x003D   RAM & I_O mapping
INIT.RAM3       7   RAM map position 3
INIT.RAM2       6   RAM map position 2
INIT.RAM1       5   RAM map position 1
INIT.RAM0       4   RAM map position 0
INIT.REG3       3   128-byte register block position 3
INIT.REG2       2   128-byte register block position 2
INIT.REG1       1   128-byte register block position 1
INIT.REG0       0   128-byte register block position 0
TEST1          0x003E   Factory test
TEST1.TILOP     7   Test Illegal Opcode
TEST1.PLTST     6   
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F   Configuration control
CONFIG.ROMAD    7   ROM mapping control
CONFIG.MBSP     6   Synchronous serial interface select
CONFIG.CLK4X    5   4X clock enable
CONFIG.PAREN    4   Pull-up assignment register enable
CONFIG.NOSEC    3   EEPROM security disabled
CONFIG.NOCOP    2   COP system disable
CONFIG.ROMON    1   ROM enable
CONFIG.EEON     0   EEPROM enable
MADR           0x0040   I2C bus address
MADR.MADR7      7   Slave address bit 7
MADR.MADR6      6   Slave address bit 6
MADR.MADR5      5   Slave address bit 5
MADR.MADR4      4   Slave address bit 4
MADR.MADR3      3   Slave address bit 3
MADR.MADR2      2   Slave address bit 2
MADR.MADR1      1   Slave address bit 1
MFDR           0x0041   I2C bus frequency divider
MFDR.MBC4       4   Clock rate select bit 4
MFDR.MBC3       3   Clock rate select bit 3
MFDR.MBC2       2   Clock rate select bit 2
MFDR.MBC1       1   Clock rate select bit 1
MFDR.MBC0       0   Clock rate select bit 0
MCR            0x0042   I2C bus control
MCR.MEN         7   I2C bus enable
MCR.MIEN        6   I2C bus interrupt enable
MCR.MSTA        5   Master/slave mode select
MCR.MTX         4   Transmit/receive mode select
MCR.TXAK        3   Transmit acknowledge bit
MSR            0x0043   I2C bus status register
MSR.MCF         7   Data transferring
MSR.MAAS        6   I2C bus addressed as a slave
MSR.MBB         5   Bus busy
MSR.MAL         4   Arbitration lost
MSR.SRW         2   Read/write command
MSR.MIF         1   I2C bus interrupt flag
MSR.RXAK        0   Received acknowledge bit
MDR            0x0044   I2C bus data register
MDR.TRXD7       7
MDR.TRXD6       6
MDR.TRXD5       5
MDR.TRXD4       4
MDR.TRXD3       3
MDR.TRXD2       2
MDR.TRXD1       1
MDR.TRXD0       0
RESERVED45     0x0045   RESERVED
RESERVED46     0x0046   RESERVED
RESERVED47     0x0047   RESERVED
RESERVED48     0x0048   RESERVED
RESERVED49     0x0049   RESERVED
RESERVED4A     0x004A   RESERVED
RESERVED4B     0x004B   RESERVED
RESERVED4C     0x004C   RESERVED
RESERVED4D     0x004D   RESERVED
RESERVED4E     0x004E   RESERVED
RESERVED4F     0x004F   RESERVED
RESERVED50     0x0050   RESERVED
RESERVED51     0x0051   RESERVED
RESERVED52     0x0052   RESERVED
RESERVED53     0x0053   RESERVED
RESERVED54     0x0054   RESERVED
RESERVED55     0x0055   RESERVED
RESERVED56     0x0056   RESERVED
RESERVED57     0x0057   RESERVED
RESERVED58     0x0058   RESERVED
RESERVED59     0x0059   RESERVED
RESERVED5A     0x005A   RESERVED
RESERVED5B     0x005B   RESERVED
RESERVED5C     0x005C   RESERVED
RESERVED5D     0x005D   RESERVED
RESERVED5E     0x005E   RESERVED
RESERVED5F     0x005F   RESERVED
RESERVED60     0x0060   RESERVED
RESERVED61     0x0061   RESERVED
RESERVED62     0x0062   RESERVED
RESERVED63     0x0063   RESERVED
RESERVED64     0x0064   RESERVED
RESERVED65     0x0065   RESERVED
RESERVED66     0x0066   RESERVED
RESERVED67     0x0067   RESERVED
RESERVED68     0x0068   RESERVED
RESERVED69     0x0069   RESERVED
RESERVED6A     0x006A   RESERVED
RESERVED6B     0x006B   RESERVED
RESERVED6C     0x006C   RESERVED
RESERVED6D     0x006D   RESERVED
RESERVED6E     0x006E   RESERVED
RESERVED6F     0x006F   RESERVED
SCBDH          0x0070   SCI baud rate high
SCBDH.BTST      7   Baud register test (Test mode only)
SCBDH.BSPL      6   Baud rate counter split (Test mode only)
SCBDH.BRST      5   Baud rate reset (Test mode only)
SCBDH.SBR12     4   SCI baud rate selects 12
SCBDH.SBR11     3   SCI baud rate selects 11
SCBDH.SBR10     2   SCI baud rate selects 10
SCBDH.SBR9      1   SCI baud rate selects 9 
SCBDH.SBR8      0   SCI baud rate selects 8 
SCBDL          0x0071   SCI baud rate low
SCBDL.SBR7      7   SCI baud rate selects 7
SCBDL.SBR6      6   SCI baud rate selects 6
SCBDL.SBR5      5   SCI baud rate selects 5
SCBDL.SBR4      4   SCI baud rate selects 4
SCBDL.SBR3      3   SCI baud rate selects 3
SCBDL.SBR2      2   SCI baud rate selects 2
SCBDL.SBR1      1   SCI baud rate selects 1
SCBDL.SBR0      0   SCI baud rate selects 0
SCCR1          0x0072   SCI control 1
SCCR1.LOOPS     7   SCI loop mode enable
SCCR1.WOMS      6   Wired-OR mode for SCI pins (PD1, PD0)
SCCR1.M         4   Mode (select character format)
SCCR1.WAKE      3   Wake-up by address mark/idle
SCCR1.ILT       2   Idle line type
SCCR1.PE        1   Parity enable
SCCR1.PT        0   Parity type
SCCR2          0x0073   SCI control 2
SCCR2.TIE       7   Transmit interrupt enable
SCCR2.TCIE      6   Transmit complete interrupt enable
SCCR2.RIE       5   Receiver interrupt enable
SCCR2.ILIE      4   Idle line interrupt enable
SCCR2.TE        3   Transmitter enable
SCCR2.RE        2   Receiver enable
SCCR2.RWU       1   Receiver wake-up control
SCCR2.SBK       0   Send break
SCSR1          0x0074   SCI status 1
SCSR1.TDRE      7   Transmit data register empty flag
SCSR1.TC        6   Transmit complete flag
SCSR1.RDRF      5   Receive data register full flag
SCSR1.IDLE      4   Idle line detected flag
SCSR1.OR        3   Overrun error flag
SCSR1.NF        2   Noise error flag
SCSR1.FE        1   Framing error
SCSR1.PF        0   Parity error flag
SCSR2          0x0075   SCI status 2
SCSR2.RAF       0   Receiver active flag (read only)
SCDRH          0x0076   SCI data high
SCDRH.R8        7   Receiver bit 8
SCDRH.T8        6   Transmitter bit 8
SCDRL          0x0077   SCI data low
SCDRL.R7T7      7   Receiver/transmitter data bit 7
SCDRL.R6T6      6   Receiver/transmitter data bit 6
SCDRL.R5T5      5   Receiver/transmitter data bit 5
SCDRL.R4T4      4   Receiver/transmitter data bit 4
SCDRL.R3T3      3   Receiver/transmitter data bit 3
SCDRL.R2T2      2   Receiver/transmitter data bit 2
SCDRL.R1T1      1   Receiver/transmitter data bit 1
SCDRL.R0T0      0   Receiver/transmitter data bit 0
RESERVED78     0x0078   RESERVED
RESERVED79     0x0079   RESERVED
RESERVED7A     0x007A   RESERVED
RESERVED7B     0x007B   RESERVED
RESERVED7C     0x007C   RESERVED
RESERVED7D     0x007D   RESERVED
PORTG          0x007E   Port G data
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F   Data direction G
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0   RESERVED
RESERVFFC1     0xFFC1   RESERVED
RESERVFFC2     0xFFC2   RESERVED
RESERVFFC3     0xFFC3   RESERVED
RESERVFFC4     0xFFC4   RESERVED
RESERVFFC5     0xFFC5   RESERVED
RESERVFFC6     0xFFC6   RESERVED
RESERVFFC7     0xFFC7   RESERVED
RESERVFFC8     0xFFC8   RESERVED
RESERVFFC9     0xFFC9   RESERVED
RESERVFFCA     0xFFCA   RESERVED
RESERVFFCB     0xFFCB   RESERVED
RESERVFFCC     0xFFCC   RESERVED
RESERVFFCD     0xFFCD   RESERVED
RESERVFFCE     0xFFCE   RESERVED
RESERVFFCF     0xFFCF   RESERVED
RESERVFFD0     0xFFD0   RESERVED
RESERVFFD1     0xFFD1   RESERVED
RESERVFFD2     0xFFD2   RESERVED
RESERVFFD3     0xFFD3   RESERVED


.68HC711PB8
; MC68HC11PA8/D  http://
; pa8.pdf

; RAM=2K 
; ROM=0    
; EPROM=48K 
; EEPROM=512
         

; MEMORY MAP
area DATA FSR          0x0000:0x0080
area DATA RAM          0x0080:0x0880
area BSS  RESERVED     0x0880:0x0E00
area DATA EEPROM       0x0E00:0x1000
area BSS  RESERVED     0x1000:0x4000
area CODE EPROM        0x4000:0xFFC0
area DATA USER_VEC     0xFFC0:0x10000


; Interrupt and reset vector assignments
interrupt __RESET           0xFFFE      Processor reset
interrupt CME               0xFFFC      Clock Monitor Fail
interrupt NOCOP             0xFFFA      COP Failure
interrupt OPC               0xFFF8      Illegal Opcode Trap
interrupt SOFT              0xFFF6      Software Interrupt
interrupt XIRQ              0xFFF4      XIRQ Pin
interrupt IRQ               0xFFF2      IRQ
interrupt RTII              0xFFF0      Real Time Interrupt
interrupt IC1I              0xFFEE      Timer Input Capture 1
interrupt IC2I              0xFFEC      Timer Input Capture 2
interrupt IC3I              0xFFEA      Timer Input Capture 3
interrupt OC1I              0xFFE8      Timer Output Compare 1
interrupt OC2I              0xFFE6      Timer Output Compare 2
interrupt OC3I              0xFFE4      Timer Output Compare 3
interrupt OC4I              0xFFE2      Timer Output Compare 4
interrupt I4_I5             0xFFE0      Timer Input Capture 4 / Output Compare 5
interrupt TOI               0xFFDE      Timer Overflow
interrupt PAOVI             0xFFDC      Pulse Accumulator Overflow
interrupt PAII              0xFFDA      Pulse Accumulator Input Edge
interrupt SPIE              0xFFD8      SPI Serial Transfer Complete
interrupt SCISS             0xFFD6      SCI Serial System
interrupt I2C_bus           0xFFD4      I2C bus


; INPUT/ OUTPUT PORTS
PORTA          0x0000   Port A data
PORTA.PA7       7   Port A Data Bit 7
PORTA.PA6       6   Port A Data Bit 6
PORTA.PA5       5   Port A Data Bit 5
PORTA.PA4       4   Port A Data Bit 4
PORTA.PA3       3   Port A Data Bit 3
PORTA.PA2       2   Port A Data Bit 2
PORTA.PA1       1   Port A Data Bit 1
PORTA.PA0       0   Port A Data Bit 0
DDRA           0x0001   Data direction A
DDRA.DDA7       7   Data Direction for Port A Bit 7
DDRA.DDA6       6   Data Direction for Port A Bit 6
DDRA.DDA5       5   Data Direction for Port A Bit 5
DDRA.DDA4       4   Data Direction for Port A Bit 4
DDRA.DDA3       3   Data Direction for Port A Bit 3
DDRA.DDA2       2   Data Direction for Port A Bit 2
DDRA.DDA1       1   Data Direction for Port A Bit 1
DDRA.DDA0       0   Data Direction for Port A Bit 0
DDRB           0x0002   Data direction B
DDRB.DDB7       7   Data Direction for Port B Bit 7
DDRB.DDB6       6   Data Direction for Port B Bit 6
DDRB.DDB5       5   Data Direction for Port B Bit 5
DDRB.DDB4       4   Data Direction for Port B Bit 4
DDRB.DDB3       3   Data Direction for Port B Bit 3
DDRB.DDB2       2   Data Direction for Port B Bit 2
DDRB.DDB1       1   Data Direction for Port B Bit 1
DDRB.DDB0       0   Data Direction for Port B Bit 0
DDRF           0x0003   Data direction F
DDRF.DDF7       7   Data Direction for Port F Bit 7
DDRF.DDF6       6   Data Direction for Port F Bit 6
DDRF.DDF5       5   Data Direction for Port F Bit 5
DDRF.DDF4       4   Data Direction for Port F Bit 4
DDRF.DDF3       3   Data Direction for Port F Bit 3
DDRF.DDF2       2   Data Direction for Port F Bit 2
DDRF.DDF1       1   Data Direction for Port F Bit 1
DDRF.DDF0       0   Data Direction for Port F Bit 0
PORTB          0x0004   Port B data
PORTB.PB7       7   Port B Data Bit 7
PORTB.PB6       6   Port B Data Bit 6
PORTB.PB5       5   Port B Data Bit 5
PORTB.PB4       4   Port B Data Bit 4
PORTB.PB3       3   Port B Data Bit 3
PORTB.PB2       2   Port B Data Bit 2
PORTB.PB1       1   Port B Data Bit 1
PORTB.PB0       0   Port B Data Bit 0
PORTF          0x0005   Port F data
PORTF.PF7       7   Port F Data Bit 7
PORTF.PF6       6   Port F Data Bit 6
PORTF.PF5       5   Port F Data Bit 5
PORTF.PF4       4   Port F Data Bit 4
PORTF.PF3       3   Port F Data Bit 3
PORTF.PF2       2   Port F Data Bit 2
PORTF.PF1       1   Port F Data Bit 1
PORTF.PF0       0   Port F Data Bit 0
PORTC          0x0006   Port C data
PORTC.PC7       7   Port C Data Bit 7
PORTC.PC6       6   Port C Data Bit 6
PORTC.PC5       5   Port C Data Bit 5
PORTC.PC4       4   Port C Data Bit 4
PORTC.PC3       3   Port C Data Bit 3
PORTC.PC2       2   Port C Data Bit 2
PORTC.PC1       1   Port C Data Bit 1
PORTC.PC0       0   Port C Data Bit 0
DDRC           0x0007   Data direction C
DDRC.DDC7       7   Data Direction for Port C Bit 7
DDRC.DDC6       6   Data Direction for Port C Bit 6
DDRC.DDC5       5   Data Direction for Port C Bit 5
DDRC.DDC4       4   Data Direction for Port C Bit 4
DDRC.DDC3       3   Data Direction for Port C Bit 3
DDRC.DDC2       2   Data Direction for Port C Bit 2
DDRC.DDC1       1   Data Direction for Port C Bit 1
DDRC.DDC0       0   Data Direction for Port C Bit 0
PORTD          0x0008   Port D data
PORTD.PD5       5   Port D Data Bit 5
PORTD.PD4       4   Port D Data Bit 4
PORTD.PD3       3   Port D Data Bit 3
PORTD.PD2       2   Port D Data Bit 2
PORTD.PD1       1   Port D Data Bit 1
PORTD.PD0       0   Port D Data Bit 0
DDRD           0x0009   Data direction D
DDRD.DDD5       5   Data Direction for Port D Bit 5
DDRD.DDD4       4   Data Direction for Port D Bit 4
DDRD.DDD3       3   Data Direction for Port D Bit 3
DDRD.DDD2       2   Data Direction for Port D Bit 2
DDRD.DDD1       1   Data Direction for Port D Bit 1
DDRD.DDD0       0   Data Direction for Port D Bit 0
PORTE          0x000A   Port E data
PORTE.PE7       7   Port E Data Bit 7
PORTE.PE6       6   Port E Data Bit 6
PORTE.PE5       5   Port E Data Bit 5
PORTE.PE4       4   Port E Data Bit 4
PORTE.PE3       3   Port E Data Bit 3
PORTE.PE2       2   Port E Data Bit 2
PORTE.PE1       1   Port E Data Bit 1
PORTE.PE0       0   Port E Data Bit 0
CFORC          0x000B   Timer compare force
CFORC.FOC1      7   Force output compares 1
CFORC.FOC2      6   Force output compares 2
CFORC.FOC3      5   Force output compares 3
CFORC.FOC4      4   Force output compares 4
CFORC.FOC5      3   Force output compares 5
OC1M           0x000C   Output compare 1 mask
OC1M.OC1M7      7   Output compare masks for OC1 bit 7
OC1M.OC1M6      6   Output compare masks for OC1 bit 6
OC1M.OC1M5      5   Output compare masks for OC1 bit 5
OC1M.OC1M4      4   Output compare masks for OC1 bit 4
OC1M.OC1M3      3   Output compare masks for OC1 bit 3
OC1D           0x000D   Output compare 1 data
OC1D.OC1D7      7   Output compare data for OC1 bit 7
OC1D.OC1D6      6   Output compare data for OC1 bit 6
OC1D.OC1D5      5   Output compare data for OC1 bit 5
OC1D.OC1D4      4   Output compare data for OC1 bit 4
OC1D.OC1D3      3   Output compare data for OC1 bit 3
TCNTH          0x000E   Timer count
TCNTL          0x000F   Timer count
TIC1H          0x0010   Timer input capture 1
TIC1L          0x0011   Timer input capture 1
TIC2H          0x0012   Timer input capture 2
TIC2L          0x0013   Timer input capture 2
TIC3H          0x0014   Timer input capture 3
TIC3L          0x0015   Timer input capture 3
TOC1H          0x0016   Timer output compare 1
TOC1L          0x0017   Timer output compare 1
TOC2H          0x0018   Timer output compare 2
TOC2L          0x0019   Timer output compare 2
TOC3H          0x001A   Timer output compare 3
TOC3L          0x001B   Timer output compare 3
TOC4H          0x001C   Timer output compare 4
TOC4L          0x001D   Timer output compare 4
TI4_O5H        0x001E   Capture 4_compare 5
TI4_O5L        0x001F   Capture 4_compare 5
TCTL1          0x0020   Timer control 1
TCTL1.OM2       7   Output mode 2 
TCTL1.OL2       6   Output level 2
TCTL1.OM3       5   Output mode 3 
TCTL1.OL3       4   Output level 3
TCTL1.OM4       3   Output mode 4 
TCTL1.OL4       2   Output level 4
TCTL1.OM5       1   Output mode 5 
TCTL1.OL5       0   Output level 5
TCTL2          0x0021   Timer control 2
TCTL2.EDG4B     7   Input capture edge control 4B
TCTL2.EDG4A     6   Input capture edge control 4A
TCTL2.EDG1B     5   Input capture edge control 1B
TCTL2.EDG1A     4   Input capture edge control 1A
TCTL2.EDG2B     3   Input capture edge control 2B
TCTL2.EDG2A     2   Input capture edge control 2A
TCTL2.EDG3B     1   Input capture edge control 3B
TCTL2.EDG3A     0   Input capture edge control 3A
TMSK1          0x0022   Timer interrupt mask 1
TMSK1.OC1I      7   Output compare 1 interrupt enable
TMSK1.OC2I      6   Output compare 2 interrupt enable
TMSK1.OC3I      5   Output compare 3 interrupt enable
TMSK1.OC4I      4   Output compare 4 interrupt enable
TMSK1.I4_O5I    3   Input capture 4/output compare 5 interrupt enable
TMSK1.IC1I      2   Input capture 1 interrupt enable
TMSK1.IC2I      1   Input capture 2 interrupt enable
TMSK1.IC3I      0   Input capture 3 interrupt enable
TFLG1          0x0023   Timer interrupt flag 1
TFLG1.OC1F      7   Output compare 1 flag
TFLG1.OC2F      6   Output compare 2 flag
TFLG1.OC3F      5   Output compare 3 flag
TFLG1.OC4F      4   Output compare 4 flag
TFLG1.I4_O5F    3   Input capture 4/output compare 5 flag
TFLG1.IC1F      2   Input capture 1 flag
TFLG1.IC2F      1   Input capture 2 flag
TFLG1.IC3F      0   Input capture 3 flag
TMSK2          0x0024   Timer interrupt mask 2
TMSK2.TOI       7   Timer overflow interrupt enable
TMSK2.RTII      6   Real-time interrupt enable
TMSK2.PAOVI     5   Pulse accumulator overflow interrupt enable
TMSK2.PAII      4   Pulse accumulator interrupt enable
TMSK2.PR1       1   Timer prescaler select 1
TMSK2.PR0       0   Timer prescaler select 0
TFLG2          0x0025   Timer interrupt flag 2
TFLG2.TOF       7   Timer overflow interrupt flag
TFLG2.RTIF      6   Real time (periodic) interrupt flag
TFLG2.PAOVF     5   Pulse accumulator overflow interrupt flag
TFLG2.PAIF      4   Pulse accumulator input edge interrupt flag
PACTL          0x0026   Pulse accumulator control
PACTL.PAEN      6   Pulse accumulator system enable
PACTL.PAMOD     5   Pulse accumulator mode         
PACTL.PEDGE     4   Pulse accumulator edge control 
PACTL.I4_O5     2   Input capture 4/output compare 
PACTL.RTR1      1   RTI interrupt rate select 1    
PACTL.RTR0      0   RTI interrupt rate select 0    
PACNT          0x0027   Pulse accumulator count
SPCR           0x0028   SPI control
SPCR.SPIE       7   Serial peripheral interrupt enable
SPCR.SPE        6   Serial peripheral system enable   
SPCR.DWOM       5   Port D wired-OR mode              
SPCR.MSTR       4   Master mode select                
SPCR.CPOL       3   Clock polarity                    
SPCR.CPHA       2   Clock phase                       
SPCR.SPR1       1   SPI clock rate selects 1          
SPCR.SPR0       0   SPI clock rate selects 0          
SPSR           0x0029   SPI status
SPSR.SPIF       7   SPI interrupt complete flag
SPSR.WCOL       6   Write collision            
SPSR.MODF       4   Mode fault                 
SPSR.XPIN       1   XIRQ pin input data bit
SPSR.IPIN       0   IRQ pin input data bit
SPDR           0x002A   SPI data
EPROG          0x002B   EPROM programming (only to EPROM devices)
EPROG.MBE       7   Multiple byte program enable
EPROG.ELAT      5   EPROM latch control
EPROG.EXCOL     4   Select extra columns
EPROG.EXROW     3   Select extra rows
EPROG.EPGM      0   EPROM program command
PPAR           0x002C   Port pull-up assignment
PPAR.GPPUE      2   Port G pin pull-up enable
PPAR.FPPUE      1   Port F pin pull-up enable
PPAR.BPPUE      0   Port B pin pull-up enable
RESERVED2D     0x002D   RESERVED
PLLCR          0x002E   PLL control
PLLCR.PLLON     7   PLL on                     
PLLCR.BCS       6   Bus clock select           
PLLCR.AUTO      5   Automatic bandwidth control
PLLCR.BWC       4   Bandwidth control          
PLLCR.VCOT      3   VCO test (Test mode only)  
PLLCR.MCS       2   Module clock select        
PLLCR.WEN       0   WAIT enable
SYNR           0x002F   Synthesizer program
SYNR.SYNX1      7
SYNR.SYNX0      6
SYNR.SYNY5      5
SYNR.SYNY4      4
SYNR.SYNY3      3
SYNR.SYNY2      2
SYNR.SYNY1      1
SYNR.SYNY0      0
ADCTL          0x0030   A_D control & status
ADCTL.CCF       7   Conversions complete flag              
ADCTL.SCAN      5   Continuous scan control                
ADCTL.MULT      4   Multiple-channel/single-channel control
ADCTL.CD        3   Channel select D                       
ADCTL.CC        2   Channel select C                       
ADCTL.CB        1   Channel select B                       
ADCTL.CA        0   Channel select A                       
ADR1           0x0031   A_D result 1
ADR2           0x0032   A_D result 2
ADR3           0x0033   A_D result 3
ADR4           0x0034   A_D result 4
BPROT          0x0035   Block protect
BPROT.BULKP     7   Bulk erase of EEPROM protect
BPROT.PTCON     4   Protect for CONFIG register   
BPROT.BPRT3     3   Block protect bit 3 for EEPROM
BPROT.BPRT2     2   Block protect bit 2 for EEPROM
BPROT.BPRT1     1   Block protect bit 1 for EEPROM
BPROT.BPRT0     0   Block protect bit 0 for EEPROM
RESERVED36     0x0036   RESERVED
INIT2          0x0037   EEPROM mapping
INIT2.EE3       7   EEPROM map position 3
INIT2.EE2       6   EEPROM map position 2
INIT2.EE1       5   EEPROM map position 1
INIT2.EE0       4   EEPROM map position 0
OPT2           0x0038   System config. options 2
OPT2.LIRDV      7   LIR driven
OPT2.CWOM       6   Port C wired-OR mode
OPT2.STRCH      5   Stretch external accesses
OPT2.IRVNE      4   Internal read visibility/not E
OPT2.LSBF       3   LSB-first enable
OPT2.SPR2       2   SPI clock rate select
OPT2.EXT4X      1   XOUT clock output select
OPT2.XIRQE      0   Configure XIRQ for falling edge sensitive operation
OPTION         0x0039   System config. options 1
OPTION.ADPU     7   A/D power-up
OPTION.CSEL     6   Clock select
OPTION.IRQE     5   Configure IRQ for falling-edge-sensitive operation
OPTION.DLY      4   Enable oscillator start-up delay
OPTION.CME      3   Clock monitor enable
OPTION.FCME     2   Force clock monitor enable
OPTION.CR1      1   COP timer rate select bit 1
OPTION.CR0      0   COP timer rate select bit 0
COPRST         0x003A   COP timer arm_reset
PPROG          0x003B   EEPROM programming
PPROG.ODD       7   Program odd rows in half of EEPROM (Test)
PPROG.EVEN      6   Program even rows in half of EEPROM (Test)
PPROG.BYTE      4   EEPROM byte erase mode
PPROG.ROW       3   EEPROM row/bulk erase mode (only valid when BYTE = 0)
PPROG.ERASE     2   Erase/normal control for EEPROM
PPROG.EELAT     1   EEPROM latch control
PPROG.EEPGM     0   EEPROM program command
HPRIO          0x003C   Highest priority interrupt
HPRIO.RBOOT     7   Read bootstrap ROM
HPRIO.SMOD      6   Special mode select
HPRIO.MDA       5   Mode select A
HPRIO.PSEL4     4   Priority select bit 4
HPRIO.PSEL3     3   Priority select bit 3
HPRIO.PSEL2     2   Priority select bit 2
HPRIO.PSEL1     1   Priority select bit 1
HPRIO.PSEL0     0   Priority select bit 0
INIT           0x003D   RAM & I_O mapping
INIT.RAM3       7   RAM map position 3
INIT.RAM2       6   RAM map position 2
INIT.RAM1       5   RAM map position 1
INIT.RAM0       4   RAM map position 0
INIT.REG3       3   128-byte register block position 3
INIT.REG2       2   128-byte register block position 2
INIT.REG1       1   128-byte register block position 1
INIT.REG0       0   128-byte register block position 0
TEST1          0x003E   Factory test
TEST1.TILOP     7   Test Illegal Opcode
TEST1.PLTST     6   
TEST1.OCCR      5   Output Condition Code Register Status to Timer Port
TEST1.CBYP      4   Timer Counter Divider Chain By-pass
TEST1.DISR      3   Disable Resets from COP and Clock Monitor
TEST1.FCM       2   Force Clock Monitor Failure
TEST1.FCOP      1   Force COP Watchdog Failure
CONFIG         0x003F   Configuration control
CONFIG.ROMAD    7   ROM mapping control
CONFIG.MBSP     6   Synchronous serial interface select
CONFIG.CLK4X    5   4X clock enable
CONFIG.PAREN    4   Pull-up assignment register enable
CONFIG.NOSEC    3   EEPROM security disabled
CONFIG.NOCOP    2   COP system disable
CONFIG.ROMON    1   ROM enable
CONFIG.EEON     0   EEPROM enable
MADR           0x0040   I2C bus address
MADR.MADR7      7   Slave address bit 7
MADR.MADR6      6   Slave address bit 6
MADR.MADR5      5   Slave address bit 5
MADR.MADR4      4   Slave address bit 4
MADR.MADR3      3   Slave address bit 3
MADR.MADR2      2   Slave address bit 2
MADR.MADR1      1   Slave address bit 1
MFDR           0x0041   I2C bus frequency divider
MFDR.MBC4       4   Clock rate select bit 4
MFDR.MBC3       3   Clock rate select bit 3
MFDR.MBC2       2   Clock rate select bit 2
MFDR.MBC1       1   Clock rate select bit 1
MFDR.MBC0       0   Clock rate select bit 0
MCR            0x0042   I2C bus control
MCR.MEN         7   I2C bus enable
MCR.MIEN        6   I2C bus interrupt enable
MCR.MSTA        5   Master/slave mode select
MCR.MTX         4   Transmit/receive mode select
MCR.TXAK        3   Transmit acknowledge bit
MSR            0x0043   I2C bus status register
MSR.MCF         7   Data transferring
MSR.MAAS        6   I2C bus addressed as a slave
MSR.MBB         5   Bus busy
MSR.MAL         4   Arbitration lost
MSR.SRW         2   Read/write command
MSR.MIF         1   I2C bus interrupt flag
MSR.RXAK        0   Received acknowledge bit
MDR            0x0044   I2C bus data register
MDR.TRXD7       7
MDR.TRXD6       6
MDR.TRXD5       5
MDR.TRXD4       4
MDR.TRXD3       3
MDR.TRXD2       2
MDR.TRXD1       1
MDR.TRXD0       0
RESERVED45     0x0045   RESERVED
RESERVED46     0x0046   RESERVED
RESERVED47     0x0047   RESERVED
RESERVED48     0x0048   RESERVED
RESERVED49     0x0049   RESERVED
RESERVED4A     0x004A   RESERVED
RESERVED4B     0x004B   RESERVED
RESERVED4C     0x004C   RESERVED
RESERVED4D     0x004D   RESERVED
RESERVED4E     0x004E   RESERVED
RESERVED4F     0x004F   RESERVED
RESERVED50     0x0050   RESERVED
RESERVED51     0x0051   RESERVED
RESERVED52     0x0052   RESERVED
RESERVED53     0x0053   RESERVED
RESERVED54     0x0054   RESERVED
RESERVED55     0x0055   RESERVED
RESERVED56     0x0056   RESERVED
RESERVED57     0x0057   RESERVED
RESERVED58     0x0058   RESERVED
RESERVED59     0x0059   RESERVED
RESERVED5A     0x005A   RESERVED
RESERVED5B     0x005B   RESERVED
RESERVED5C     0x005C   RESERVED
RESERVED5D     0x005D   RESERVED
RESERVED5E     0x005E   RESERVED
RESERVED5F     0x005F   RESERVED
RESERVED60     0x0060   RESERVED
RESERVED61     0x0061   RESERVED
RESERVED62     0x0062   RESERVED
RESERVED63     0x0063   RESERVED
RESERVED64     0x0064   RESERVED
RESERVED65     0x0065   RESERVED
RESERVED66     0x0066   RESERVED
RESERVED67     0x0067   RESERVED
RESERVED68     0x0068   RESERVED
RESERVED69     0x0069   RESERVED
RESERVED6A     0x006A   RESERVED
RESERVED6B     0x006B   RESERVED
RESERVED6C     0x006C   RESERVED
RESERVED6D     0x006D   RESERVED
RESERVED6E     0x006E   RESERVED
RESERVED6F     0x006F   RESERVED
SCBDH          0x0070   SCI baud rate high
SCBDH.BTST      7   Baud register test (Test mode only)
SCBDH.BSPL      6   Baud rate counter split (Test mode only)
SCBDH.BRST      5   Baud rate reset (Test mode only)
SCBDH.SBR12     4   SCI baud rate selects 12
SCBDH.SBR11     3   SCI baud rate selects 11
SCBDH.SBR10     2   SCI baud rate selects 10
SCBDH.SBR9      1   SCI baud rate selects 9 
SCBDH.SBR8      0   SCI baud rate selects 8 
SCBDL          0x0071   SCI baud rate low
SCBDL.SBR7      7   SCI baud rate selects 7
SCBDL.SBR6      6   SCI baud rate selects 6
SCBDL.SBR5      5   SCI baud rate selects 5
SCBDL.SBR4      4   SCI baud rate selects 4
SCBDL.SBR3      3   SCI baud rate selects 3
SCBDL.SBR2      2   SCI baud rate selects 2
SCBDL.SBR1      1   SCI baud rate selects 1
SCBDL.SBR0      0   SCI baud rate selects 0
SCCR1          0x0072   SCI control 1
SCCR1.LOOPS     7   SCI loop mode enable
SCCR1.WOMS      6   Wired-OR mode for SCI pins (PD1, PD0)
SCCR1.M         4   Mode (select character format)
SCCR1.WAKE      3   Wake-up by address mark/idle
SCCR1.ILT       2   Idle line type
SCCR1.PE        1   Parity enable
SCCR1.PT        0   Parity type
SCCR2          0x0073   SCI control 2
SCCR2.TIE       7   Transmit interrupt enable
SCCR2.TCIE      6   Transmit complete interrupt enable
SCCR2.RIE       5   Receiver interrupt enable
SCCR2.ILIE      4   Idle line interrupt enable
SCCR2.TE        3   Transmitter enable
SCCR2.RE        2   Receiver enable
SCCR2.RWU       1   Receiver wake-up control
SCCR2.SBK       0   Send break
SCSR1          0x0074   SCI status 1
SCSR1.TDRE      7   Transmit data register empty flag
SCSR1.TC        6   Transmit complete flag
SCSR1.RDRF      5   Receive data register full flag
SCSR1.IDLE      4   Idle line detected flag
SCSR1.OR        3   Overrun error flag
SCSR1.NF        2   Noise error flag
SCSR1.FE        1   Framing error
SCSR1.PF        0   Parity error flag
SCSR2          0x0075   SCI status 2
SCSR2.RAF       0   Receiver active flag (read only)
SCDRH          0x0076   SCI data high
SCDRH.R8        7   Receiver bit 8
SCDRH.T8        6   Transmitter bit 8
SCDRL          0x0077   SCI data low
SCDRL.R7T7      7   Receiver/transmitter data bit 7
SCDRL.R6T6      6   Receiver/transmitter data bit 6
SCDRL.R5T5      5   Receiver/transmitter data bit 5
SCDRL.R4T4      4   Receiver/transmitter data bit 4
SCDRL.R3T3      3   Receiver/transmitter data bit 3
SCDRL.R2T2      2   Receiver/transmitter data bit 2
SCDRL.R1T1      1   Receiver/transmitter data bit 1
SCDRL.R0T0      0   Receiver/transmitter data bit 0
RESERVED78     0x0078   RESERVED
RESERVED79     0x0079   RESERVED
RESERVED7A     0x007A   RESERVED
RESERVED7B     0x007B   RESERVED
RESERVED7C     0x007C   RESERVED
RESERVED7D     0x007D   RESERVED
PORTG          0x007E   Port G data
PORTG.PG7       7   Port G Data Bit 7
DDRG           0x007F   Data direction G
DDRG.DDG7       7   Data Direction for Port G Bit 7
RESERVFFC0     0xFFC0   RESERVED
RESERVFFC1     0xFFC1   RESERVED
RESERVFFC2     0xFFC2   RESERVED
RESERVFFC3     0xFFC3   RESERVED
RESERVFFC4     0xFFC4   RESERVED
RESERVFFC5     0xFFC5   RESERVED
RESERVFFC6     0xFFC6   RESERVED
RESERVFFC7     0xFFC7   RESERVED
RESERVFFC8     0xFFC8   RESERVED
RESERVFFC9     0xFFC9   RESERVED
RESERVFFCA     0xFFCA   RESERVED
RESERVFFCB     0xFFCB   RESERVED
RESERVFFCC     0xFFCC   RESERVED
RESERVFFCD     0xFFCD   RESERVED
RESERVFFCE     0xFFCE   RESERVED
RESERVFFCF     0xFFCF   RESERVED
RESERVFFD0     0xFFD0   RESERVED
RESERVFFD1     0xFFD1   RESERVED
RESERVFFD2     0xFFD2   RESERVED
RESERVFFD3     0xFFD3   RESERVED


.68L11D3
; http://

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

.68L11L6
; MC68L11L6/D     http://e-www.motorola.com/brdata/PDFDB/docs/MC68L11L6.pdf

; RAM=
; ROM=
; EPROM=
; EEPROM=

; MEMORY MAP

; Interrupt and reset vector assignments

; INPUT/ OUTPUT PORTS

