;
; This file defines SFR names and bit names for Microchip's PIC processors.
;
; This file can be configured for different devices.
; At the beginning of the file there are definitions common for all devices
; Device-specific definitions are introduced by
;
;       .devicename
;
; line. Also an optional directive
;
;       .default=devicename
;
; designates the default device name.
;
;
; It is allowed to have several mappings for the same port. For example:
;
; STATUS     0x03
; STATUS     0x83
; STATUS     0x103
; STATUS     0x183
;
; In this case IDA will redirect all memory references to the first definition.
; (all references to 0x83, 0x103, 0x183 will be rerouted to 0x03)
;

.default=16C622

INDF       0x00
TMR0       0x01
PCL        0x02
STATUS     0x03
STATUS.IRP          7  ; register bank select (indirect)
STATUS.RP1          6  ; register bank select1 (direct)
STATUS.RP0          5  ; register bank select0 (direct)
STATUS.NOT_TO       4
STATUS.NOT_PD       3
STATUS.Z            2  ; zero
STATUS.DC           1  ; digit carry
STATUS.C            0  ; carry
FSR        0x04
PORTA      0x05
PORTB      0x06
PORTC      0x07
PORTD      0x08
PORTE      0x09
PCLATH     0x0A
INTCON     0x0B
INTCON.GIE          7
INTCON.T0IE         5
INTCON.INTE         4
INTCON.RBIE         3
INTCON.T0IF         2
INTCON.INTF         1
INTCON.RBIF         0
PIR1       0x0C
PIR1.PSPIF          7
PIR1.ADIF           6
PIR1.RBFL           5
PIR1.TXIF           4
PIR1.SSPIF          3
PIR1.CCP1IF         2
PIR1.TMR2IF         1
PIR1.TMR1IF         0
PIR2       0x0D
PIR2.CCP2IF         0
TMR1L      0x0E
TMR1H      0x0F
T1CON      0x10
T1CON.T1CKPS1       5
T1CON.T1CKPS0       4
T1CON.T1OSCEN       3
T1CON.T1INSYNC      2
T1CON.TMR1CS        1
T1CON.TMR1ON        0
TMR2       0x11
T2CON      0x12
T2CON.TOUTPS3       6
T2CON.TOUTPS2       5
T2CON.TOUTPS1       4
T2CON.TOUTPS0       3
T2CON.TMR2ON        2
T2CON.T2CKPS1       1
T2CON.T2CKPS0       0
SSPBUF     0x13
SSPCON     0x14
SSPCON.WCOL         7
SSPCON.SSPOV        6
SSPCON.SSPEN        5
SSPCON.CKP          4
SSPCON.SSPM3        3
SSPCON.SSPM2        2
SSPCON.SSPM1        1
SSPCON.SSPM0        0
CCPR1L     0x15
CCPR1H     0x16
CCP1CON    0x17
CCP1CON.CCP1X       5
CCP1CON.CCP1Y       4
CCP1CON.CCP1M3      3
CCP1CON.CCP1M2      2
CCP1CON.CCP1M1      1
CCP1CON.CCP1M0      0
RCSTA      0x18
RCSTA.SPEN          7
RCSTA.RC9           6
RCSTA.SREN          5
RCSTA.CREN          4
RCSTA.FERR          2
RCSTA.OERR          1
RCSTA.RCD8          0
TXREG      0x19
RCREG      0x1A
CCPR2L     0x1B
CCPR2H     0x1C
CCP2CON    0x1D
CCP2CON.CCP2X       5
CCP2CON.CCP2Y       4
CCP2CON.CCP2M3      3
CCP2CON.CCP2M2      2
CCP2CON.CCP2M1      1
CCP2CON.CCP2M0      0
ADRES      0x1E
ADCON0     0x1F
ADCON0.ADCS1        7
ADCON0.ADCS0        6
ADCON0.CHS1         4
ADCON0.CHS0         3
ADCON0.GO           2
ADCON0.ADON         0

INDF       0x80
OPTION_REG 0x81
OPTION_REG.NOT_RBPU 7
OPTION_REG.INTEDG   6
OPTION_REG.T0CS     5
OPTION_REG.T0SE     4
OPTION_REG.PSA      3
OPTION_REG.PS2      2
OPTION_REG.PS1      1
OPTION_REG.PS0      0
PCL        0x82
STATUS     0x83
FSR        0x84
TRISA      0x85
TRISB      0x86
TRISC      0x87
TRISD      0x88
TRISE      0x89
TRISE.IBF           7
TRISE.OBF           6
TRISE.IBOV          5
TRISE.PSPMODE       4
TRISE.TRISE2        2
TRISE.TRISE1        1
TRISE.TRISE0        0
PCLATH     0x8A
INTCON     0x8B
PIE1       0x8C
PIE1.PSPIE          7
PIE1.ADIE           6
PIE1.RCIE           5
PIE1.TXIE           4
PIE1.SSPIE          3
PIE1.CCP1IE         2
PIE1.TMR2IE         1
PIE1.TMR1IE         0
PIE2       0x8D
PIE2.CCP2IE         0
PCON       0x8E
PCON.NOT_POR        1
PCON.NOT_BO         0
OSCCAL     0x8F
PR2        0x92
SSPADD     0x93
SSPATAT    0x94
TXSTA      0x98
TXSTA.CSRC          7
TXSTA.TX9           6
TXSTA.TXEN          5
TXSTA.SYNC          4
TXSTA.BRGH          2
TXSTA.TRMT          1
TXSTA.TXD8          0
SPBRG      0x99
ADCON1     0x9F
ADCON1.PCFG2        2
ADCON1.PCFG1        1
ADCON1.PCFG0        0

INDF       0x100
TMR0       0x101
PCL        0x102
STATUS     0x103
FSR        0x104
PORTB      0x106
PORTF      0x107
PORTG      0x108
PCLATH     0x10A
INTCON     0x10B

INDF       0x180
OPTION_REG 0x181
PCL        0x182
STATUS     0x183
FSR        0x184
TRISB      0x186
TRISF      0x187
TRISG      0x188
PCLATH     0x18A
INTCON     0x18B

;-------------------------------
; Device specific definitions

.16F84

; insert definitions here

.16C622

; insert definitions here

.16C71

; insert definitions here

