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³   SOLiTUDE PROUDLY PRESENTS:   State Navigator v1.5 (c) TransEDA          ³
ÃÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ´
³ SUPPLiER........     TEAM SLT      ³ OPERATiNG SYSTEM.......   WinNT/2K   ³
³ CRACKER.........     H***      	 ³ RELEASE SiZE...........   xx/04      ³
³ PACKER..........     TEAM SLT      ³ RELEASE DATE...........   05.26.00   ³
³ GENRE...........     Debugger	 ³ PROTECTION.............   FlexLM	    ³
³ TESTED BY.......     F******       ³ CRACK TYPE.............   License    ³
ÃÄÄÄÄÄÄÄÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ
³ RELEASE iNFO ³                                                            
ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ      

			State Navigator v1.5


	Finite State Machine Debug and Verification Environment 

	Finite state machines (FSMs) are one of the most common constructs in IC
	designs. They form the core of many networking, telecommunications and bus
	protocols as well as the heart of most control circuitry. As ICs become
	more complex, the number and size of FSMs grows, and the interaction between
	FSMs becomes increasingly difficult to predict or verify. 

	State Navigator is a finite state machine debug and verification environment
	for Verilog and VHDL designs. State Navigator enables designers to
	simultaneously debug multiple interacting state machines. State Navigator
	provides interactive debug of the state machines' functionality, verifies
	their behavioral specification, performs a static verification of the FSM
	structures, and provides detailed FSM coverage data. 

	Designers will see immediate productivity gains with State Navigator since
	it does not require changes to design style or source code, and has been fully
	tested with industry-leading simulators, including ModelSim, VCS, Affirma-NC
	and Verilog-XL. State Navigator runs on both UNIX and Windows-NT platforms. 

	Interactive FSM Debug 

	State Navigator provides a powerful new way to interact with complex FSM designs
	during the design phase, using simulation results to animate the state diagram
	display. Large amounts of simulation data are presented in an easy-to-interpret
	format, enabling designers to quickly identify unexpected behavior in their design.
	Any number of state machines may be displayed together and complex interactions
	between them are immediately visible as highlighted states and transitions move
	from one FSM to the next. Users can single-step forward or backward in simulation
	time and can jump to any point in time. 

	State Navigator's interactive debug capability enables designers to quickly
	visualize the complex behavior of their finite state machine designs - even those
	with multiple,communicating state machines. 

	Behavioral Verification 

	State Navigator enables users to create and verify a behavioral specification of
	their FSMs in terms of sequences. Sequences allow designers to specify the behavior
	of the FSMs at a level higher than the hardware description language (HDL) source
	code, and then easily check the HDL code against the specified sequences. With this
	capability, design and verification engineers can quickly determine if an FSM
	conforms to the specification. State Navigator analyzes simulation results and
	identifies which sequences have been fully verified and which are still uncovered. 

	Complex sequence definition is supported by the use of nesting, labeling, transition-
	cycle constraints and paired-arc constraints; sequences between multiple FSMs are
	also supported. Prohibited sequences can be defined to detect the occurrence of
	specific unexpected behavior. 

	Static FSM Verification 

	State Navigator provides several static checks of FSM designs before simulation,
	allowing correction of common design mistakes before developing extensive test
	suites. 

	Once the FSM is automatically derived from the Verilog or VHDL source code, State
	Navigator identifies any dead states, unreachable states or overwritten transitions
	and generates a state diagram display. Modifications made to the FSM since the last
	analyses are highlighted in the state diagram, enabling fast inspection of the
	changes. A source code window allows for cross probing between textual and graphical
	displays of the FSM. The state diagram display is fully editable and provides
	PostScript output for graphical documentation of the FSM. 

	State Navigator also displays a complete list of all possible paths through the FSM.
	This list is a measure of the complexity of the FSM and provides an estimate of its
	verification difficulty. Designers can use this information to modify their FSM design
	to reduce the total number of paths, reducing the verification task even before a
	single simulation is run. 

	FSM Coverage 

	Building on TransEDA's strengths in code coverage reporting, State Navigator provides
	additional, valuable insight into the coverage of the FSMs contained within the
	design using Transition Coverage, Expression Coverage and Path Coverage. 

	Transition coverage gives designers quick feedback on the quality of the verification
	test suite by measuring which state transitions have been exercised during simulation.
	Transition coverage is counted only after the new state is clocked in - all glitches
	are suppressed. Transition coverage is reported in textual format, as well as by
	color-coding the arcs in the state diagram display. 

	Expression coverage shows the designer how well the controlling conditions for each
	transition have been covered by simulation. For transition expressions with multiple
	controlling terms, State Navigator will calculate and report which terms actually
	caused the FSM to enter each given state. Results are reported textually and
	graphically on the state diagram, with green arcs representing full expression
	coverage, yellow arcs representing partial expression coverage and red arcs
	indicating the transition has not been exercised at all. 

	Path coverage provides a higher level of verification by measuring the percentage
	possible paths through a state machine have been exercised in simulation. This is
	critical in FSM verification as there can often be very large number of paths
	through a state machine, many of which are difficult-to-identify corner-cases.
	Path coverage enables the designer to quickly identify untested paths in the FSM
	and to generate new tests to cover the missing paths. 


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³ iNSTALL NOTES ³                                                           ³
ÃÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ                                                           ³
³    	1) Unpack & Install 						  	          ³
³	2) Choose site.dat when asked for a license during installation	    ³
³	3) Enjoy :)										    ³
³                                                                           ³
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ÚÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ¿
³ SLT NEWS ³                                                                ³
ÃÄÄÄÄÄÄÄÄÄÄÙ                                                                ³
³ The SLT Crew, is pleased to announce the two new divisions at SLT,        ³
³ SLT LINUX, and SLT SOLARIS - where we will get you the newest and         ³
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³ high quality utils for win9x/NT/win2k.                                    ³
³                                                                           ³
³ Linux & Solaris crackers, testers and suppliers are encouraged to apply   ³
³ for trial membership.                                                     ³
³                                                                           ³
³                                                                           ³
³                                                                           ³
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³ SLT GREETS ³                                                              ³
ÃÄÄÄÄÄÄÄÄÄÄÄÄÙ                                                              ³
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³ JOINING SLT ³                                                             ³
ÃÄÄÄÄÄÄÄÄÄÄÄÄÄÙ                                                             ³
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³  We are seeking people able to:                                           ³
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³  1. Supply unreleased software.                                           ³
³                                                                           ³
³  2. Crackers - We are seeking skilled crackers on WinNT and Linux         ³
³     especially those with FlexLM and dongle experience, our crackers      ³
³     work very close, and if you need to pickup some skills, we can        ³
³     help you gain them.                                                   ³
³                                                                           ³
³  3. Testers, preferably with previous experience.                         ³
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³ CONTACT SLT    ³                                                          ³
ÃÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ                                                          ³
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³                         (c) 1999 SOLiTUDE                                 ³
³                                                                           ³
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