                              DESIGN CENTER - SYSTEM  2
                                    VERSION 5.2 


This file describes the new features and changes for the 5.2 release of
the Design Center programs: PSpice, Probe, the Stimulus Editor, and Parts.  
This file covers new information for the following platforms:

IBM-PC DOS (not including digital simulation)
IBM-PC DOS/16M 
NEC-PC DOS (not including digital simulation)
NEC-PC DOS/16M 

For NEC DOS/16M users, we now support NEC High Color and NEC
High Color (with mouse) display devices.

The documentation referenced in this file consists of the following manuals:

Circuit Analysis System Setup Manual
Circuit Analysis User's Guide
Circuit Analysis Reference Manual

//////////////////////////////////////////////////////////////////////////

                    Notes on Memory Management 

//////////////////////////////////////////////////////////////////////////

If your system hangs or portions of the Design Center program
give "out of memory" type errors every time you use the Design
Center, we suggest that you create a "pure" environment to
determine whether the problem involves a conflict with a memory
manager, a TSR, a device driver, or any add-on hardware you may
have.  To create a "pure" environment use the following
procedure:

1.  Make a DOS boot floppy disk before you start making any
    changes.  To make a DOS boot floppy disk either insert an
    unformatted floppy disk in drive A: and type FORMAT A: /S,
    or insert an already formatted floppy disk into drive A: and
    type SYS A:.    This will ensure that you will be able to
    reboot your system in the event that a change you make to
    your CONFIG.SYS file makes your system unable to boot from
    the hard disk.

2.  Make copies of your current CONFIG.SYS and AUTOEXEC.BAT
    files.  Use names other than CONFIG.BAK and AUTOEXEC.BAK.

3.  Create a new CONFIG.SYS file with the following information:

          FILES=20
          BUFFERS=20

4.  Create a new AUTOEXEC.BAT file containing only PATH=,
    PROMPT=, mouse driver, and, if your system requires them,
    hard disk driver statements.

5.  Reboot your system using the new CONFIG.SYS and AUTOEXEC.BAT
    files that you have just created and see if the problem
    still occurs when running the Design Center.  If it does,
    either your hardware is faulty, or the Design Center
    software is incompatible with your system.  If you suspect
    the problem is with the Design Center software, please
    contact MicroSim Technical Support.  If the problem does not
    occur, go on to the next step.

6.  Add statements that reactivate memory managers, resident
    programs, and drivers one by one, reboot your computer and
    test the Design Center after each new addition.  Start with
    items you feel are most essential to the proper operation of
    your system.  Be patient and systematic.  Once a specific
    item which causes the problem is isolated the problem can be
    fully resolved.

Contact MicroSim Technical Support if the problem seems to
revolve around the Design Center, or you are unable to resolve
the problem using the procedure described above.  Be sure to
clearly and precisely document the findings of your
troubleshooting efforts.  The information you gather will help
our Technical Support personnel to further diagnose your problem. 

If your system hangs or portions of the Design Center program
give "out of memory" type errors occasionally and under certain
conditions (eg. if the program seems to fail only when analyzing
a circuit where a large amount of output data is created),
contact MicroSim Technical Support.  Be sure to clearly and
precisely document the conditions and the exact steps used to
produce the problem.  Be sure to include what type of circuit you
are analyzing and what type of analysis you are attempting.  The
MicroSim Technical Support personnel may ask you send them the
circuit file and the schematic of the circuit that seems to cause
the problem so that they can attempt to duplicate and further
diagnose the problem. 

Please note that in order to track down and correct a problem, we
must be able to duplicate it here.  Please provide an account of
the exact steps used to reproduce your problem.


***************************************************************************

                                 PSPICE

***************************************************************************



1.0  Changes to PSpice Circuit File Commands

.DISTRIBUTION  (page 57 in the Circuit Analysis Reference Manual)

The updated value of a parameter is derived from a combination 
of a random number, the distribution, and the tolerance specified.



.OPTIONS   For DOS/16M Platforms only

(Refer to page 76 in the Circuit Analysis Reference Manual)

There has been a new parameter added:

DIGINITSTATE         sets initial state of all flip-flops                                                     
                     (default=2) and latches in circuit:
                     0=clear, 1=set, 2=X


T    (pages 178-180 in the Circuit Analysis Reference Manual)

New transmission line general form for the:

Ideal Line

T<name>             <A port (+) node>  <A port (-) node>
+                   <B port (+) node>  <B port (-) node>
+                   [model name]
+                   Z0=<value>  [TD=<value>]  [F=<value> [NL=<value>]]

Lossy Line

T<name>             <A port (+) node>  <A port (-) node>
+                   <B port (+) node>  <B port (-) node>
+                   [ <model name> [electrical length value] ]
+                   LEN=<value> R=<value> L=<value>
+                   G=<value> C=<value>


Model Form

.MODEL <model name> TRN [model parameters]

For the case of a line which uses a model, the electrical length 
can be optionally given after the model name.  All of the transmission
line parameters from either the ideal or lossy parameter set can be 
expressions.  In additon, R and G can be general laplace expressions.
This allows the user to model frequency dependent effects, such as skin 
effect and dielectric loss.



3.0  Digital Simulation Additions and Enhancements

There are additions and enhancements to the digital simulation capability.  
These changes can be found in the Circuit Analysis Reference Manual, 
Chapter 5, "Digital Devices and Libraries," and are applicable to the 
DOS/16M platforms only (which support digital simulation). 



3.1  Bidirectional Transfer Gate 

The bidirectional transfer gate is a passive device which 
connects or disconnects two nodes.  The state of the gate input
controls whether the gate connects the two nodes.  The device 
type NBTG connects the nodes if the gate is 1, and disconnects 
the nodes if the gate is 0.  Device type PBTG connects the 
nodes if the gate is 0 and disconnects the nodes if the gate is 1.  
The bidirectional transfer gates have no device line parameters.

The I/O Model DRVH and DRVL parameters are used as a ceiling on 
the strength of a 1 or 0 which is passed through a bidirectional 
transfer gate.  In this release, there is no load independent delay 
or charge storage for bidirectional transfer gates.  This may change
in future releases.  Also, the timing model parameters TON and TOFF
have no effect in Version 5.2 (the device behaves as if TON and TOFF
are zero regardless of the value specified in the model).

Please refer to Section 5.2.1.1.3 (page 220) of the Circuit Analysis 
Reference Manual for information on the device format.



3.2  Flip-Flops and Latches

You can override the X startup state by setting .OPTIONS DIGINITSTATE
to either 0 or 1.  If set to 0, all flip-flops and latches in the 
circuit will be cleared.  Likewise, if set to 1, all such devices 
will be preset.  Any other values will produce the default (X) 
startup state.  The DIGINITSTATE option is useful in situations 
where the initial state of the flip-flop is unimportant to the 
function of the circuit, such as a toggle flip-flop in a frequency 
divider.

It is important to note that if you set the initial state to 0 or 1, 
the device will still output an X at the beginning of the simulation 
if the inputs would normally produce an X on the output.  For example, 
if you set the initial state to 1, but the clock is an X at time zero, 
Q and QBar will both go to X when the simulation begins.



3.3  Behavioral Primitives

The Logic Expression, Pin Delay, and Constraint Check primitives 
are used together to allow efficient modeling of digital 
combinational logic behavior.  Typically, this involves 
extracting information from a manufacturer's data sheet describing
the logical operation of a device, and its timing characteristics.
The Logic Expression primitive, LOGICEXP, allows "free-format" 
logic expressions to describe the state behavior of the modeled 
device.  The timing characteristics are handled by the other 
two primitives: path-specific propagation delays, taken from the 
data sheet, are expressed using the Pin-to-Pin Delay primitive,
PINDLY;  timing rules, such as setup/hold times, etc., are 
modeled using the Constraint Check primitive, CONSTRAINT.

Together, these primitives provide a digital modeling mechanism 
that permits reduced gate-counts, node-counts, and improved efficiency.



3.3.1  Logic Expression

The LOGICEXP primitive allows combinational logic to be expressed
in an equation-like style, using a selection of standard logic 
operators, node names, and temporary variables.

For detailed information on logic expression device format please refer 
to Chapter 5, "Digital Devices and Libraries" of the Circuit Analysis 
Reference Manual, Section 5.2.1.9 (starting on page 242).



3.3.2  Pin-to-Pin Delay

The PINDLY primitive is a general mechanism which allows the 
modeling of complex device timing.  It may be thought of
as a set of delay-lines (paths) and rules describing how 
to associate specific amounts of delay with each path.

The PINDLY primitive is expressed in the circuit as a device.  
It provides a framework for specifying all of the relevant
Propagation Delay characteristics during the development of 
a device model.

PINDLY primitives are intended to replace or augment existing 
device-level timing descriptions.  This is desirable because
the manufacturer's specifications of the timing behavior of a 
device do not always contain complete or detailed enough delay
information to allow a one-to-one association with the primitives 
used to describe the logic level behavior of the device.

PINDLY primitives are inserted directly in the paths they are 
intended to operate on, typically at the output pins of a 
subcircuit definition.  They are evaluated in the same manner 
as other logic devices, and also have the ability to access 
arbitrary reference inputs, to gather additional information 
about logic state and timing.

For more information on pin-to-pin delay and the device format 
please refer to Section 5.2.1.9.2 (page 245 of the Circuit Analysis 
Reference Manual).



3.3.3  Constraint Check

The CONSTRAINT primitive provides a general "constraint checking" mechanism 
to the digital modeler.  Types of constraints include setup time and hold 
time checks, pulse width checks, frequency checks, and a general mechanism 
to allow user-defined constraints to be described.

Timing specifications are usually given at the "device" (i.e., package pin) 
level.  Thus, the "inputs" to the constraint description will typically be 
those of the subcircuit description of the device. CONSTRAINT devices may be 
used in conjunction with any combination of digital primitives, including 
gates, logic expression devices, and pin delay devices.  They do not affect 
propagated or stored logic state, and they do not affect propagation delays.  
See Section 5.2.1.9.3 (page 249 of the Circuit Analysis Reference Manual) 
for the device format.



3.4  Input/Output Model

New UIO model parameter:

DIGPOWER     Name of power supply subcircuit      DIGIFPWR


DIGPOWER specifies the name of the power supply subcircuit
PSpice will call when an AtoD or DtoA interface is created. 
The default value is DIGIFPWR, which is the power supply 
subcircuit used by the TTL and CMOS device libraries.



3.5  Digital Power Supplies

To power the interface subcircuits, PSpice uses the digital power and 
ground nodes which are specified on each digital primitive and stimulus 
device.  PSpice uses these nodes only when an AtoD or DtoA interface 
is created on behalf of a digital device.  Their purpose is to provide 
reference or drive voltage for the "analog side" of the interface.

Note: Digital power and ground nodes play no part when a device is 
connected only by digital nodes.

When PSpice calls one of the AtoD or DtoA subcircuits specified 
in the device's I/O Model, it passes the names of the digital 
power and ground which were stated in the U device call.

For example, if a circuit has a buffer primitive which is driven 
by an analog node named IN,

           U1 BUF DigPower DigGround IN OUT TimingModel IOModel

PSpice will create an instance of the appropriate AtoD subcircuit with 
the following subcircuit call:

           X$IN_AtoD IN IN$AtoD DigPower DigGround AtoD
           +          params: CAPACITANCE=0

Notice that the nodes specified in the U device statement, DigPower 
and DigGround, are passed into the interface subcircuit.

See Sections 4.7.2.1 and 4.7.2.2 in the Circuit Analysis User's Guide 
(starting on page 111) for information on how the digital library uses 
power supplies, and how to specify your own power supply.



4.0  4000-Series CMOS Library

If you do not specify power supply nodes on CD4000 devices in your circuit, 
they will use the default power supply nodes $G_DPWR and $G_DGND, which 
default to 5 volts.  You may create a new power supply yourself, and 
specify the new power supply nodes to the devices in your circuit.  
Output drives and input thresholds are correctly modeled for power 
supplies between 3 and 18 volts.  Currently, propagation delays do not 
vary with supply voltages.  For correct propagation delays at supply 
voltages other than 5 volts, you will need to modify the timing models 
in "dig_5.lib".



5.0  New PSpice Model Libraries 

adv_lin.lib  -   "Advanced Linear Devices" opamp macromodels
comlinr.lib  -   "Comlinear Corporation"  opamp macromodels
elantec.lib  -   "Elantec" opamp macromodels
linear.lib   -   voltage comparators, voltage regulators, opamps
motormos.lib -   "Motorola" power MOSFET
nat_semi.lib -   "National Semiconductor" opamp macromodels
tex_inst.lib -   "Texas Instruments" opamp macromodels
filtsub.lib  -   filter biquad stages and LC ladder branches


5.1  "Texas Instruments" Macromodel Library Updates

The Texas Instruments opamp macromodel library has been updated for 
our 5.2 release of the Design Center.  The names of all the macromodels
are different than they were before, as well as there being several
additions to the libarary.  For those of you who have older circuit 
files, the names referenced will not match those in the 
new library: TEXT_INST.LIB.

For your convenience, we are shipping the old versions of 
this library with our 5.2 release, but they will not be 
shipped in the future.

The old versions is called TEX_OLD.LIB.  TEX_OLD.LIB is not 
referenced in NOM.LIB; the new model library, TEX_INST.LIB, is.  
Therefore, if you have older designs which make use of the 
old/obsolete TI macromodels, you will need to specifically
replace/include references of the old/obsolete macromodel  
library as appropriate.



5.2  "Elantec" Macromodel Library Name Changes

Since our shipment of the Elantec pre-release model libraries
(an offer made to 5.1 customers in our April 1994
Newsletter),  the following Elantec device names have
been changed as indicated:

Was:             Changed to:
EL2006/EL        ELH2006/EL
EL2040/EL        ELA2040/EL
EL2223/EL        EL223/EL
EM400/EL         EL400/EL



**********************************************************************
      
                              PROBE

**********************************************************************



1.0  New Probe Functions 

Analog:

AVGX(x,d)    running average of X (from x-d to x) 
over the range of the X axis variable.
DB(x)        magnitude in decibels of x.


Digital:  (DOS/16M Platforms only)

Add_trace Command

A shorthand notation is available for specifying a set of signals that are 
similarly named.  In a digital trace definition,each substring that is of 
the form sss[xx:yy], where sss represents an alphanumeric string and xx and 
yy represent decimal numbers, is replaced by a string of the form 
sssaa, sssbb ... ssszz, where aa, bb, ... zz are all the decimal values 
from xx through yy.  The order of expansion is determined by the relative 
values of xx and yy.  For example, {DATA[7:0]} is equivalent to {DATA7 
DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0}.  Leading zeroes can be used 
in xx and yy to force a minimum width number.  For example, note that 
DATA[8:11] expands into DATA8 DATA9 DATA10 DATA11, while DATA[08:11] 
expands into DATA08 DATA09 DATA10 DATA11.

To use the "@n" construct (to select one transient analysis out of several) 
with the shorthand notation, place the "@n" immediately following the "]".  
For example, A[20:18]@2 expands into A20@2 A19@2 A18@2.



2.0  Analog/Digital Plot Menu (page 322, Circuit Analysis Reference Manual)

Goal_functions enters the Goal Functions Menu and contains
the following commands:

Exit 
(or pressing <Esc>) exits the Goal Functions 
Menu and returns to the Analog/Digital Plot Menu.

eval_Goal_function (page 348, Circuit Analysis Reference Manual)
allows you to evaluate a Goal Function (or an expression 
of Goal Functions) on a single trace or set of traces 
from a single section of data from the .dat file.

Display_evaluation (page 349, Circuit Analysis Reference Manual)
causes the traces and marked points used 
by eval_Goal_function to be displayed in the currently 
selected plot on the currently selected Y axis.  All 
existing traces and labels in the selected plot are erased 
before displaying the "Goal Function" traces.

Do_not_display_evaluation (page 350, Circuit Analysis Reference Manual)
disables the display of Goal Function expression argument 
traces and marked points, that was enabled by Display_evaluation.  
All plots are restored to show the traces and labels they were 
displaying at the time Display_evaluation was chosen.





******************************************************************************

                             The Stimulus Editor

******************************************************************************



1.0  Additions to the Stimulus Editor Main Menu

Zoom Commands

The Zoom commands found in the main menu are not available for 
this release.


Plot Control Menu

Change_digital_plot_size 
enters the Change Digital Plot Size Menu, which contains
the following commands:

Modify_plot_size 
allows you to specify the percentage of 
the plot that should be for digital traces.  You will be 
prompted to select a percentage between the valid range 
which is displayed.  The default is 33 percent.

Change_display_name_size 
allows you to specify the length of the digital signal's 
display name.



